diff --git a/dts/ti/mspm0/g/mspm0g51xx-pinctrl.dtsi b/dts/ti/mspm0/g/mspm0g51xx-pinctrl.dtsi new file mode 100644 index 0000000..e0b378e --- /dev/null +++ b/dts/ti/mspm0/g/mspm0g51xx-pinctrl.dtsi @@ -0,0 +1,2389 @@ +#include + +/{ + soc { + pinctrl: pin-controller@400a0000 { + /omit-if-no-ref/ gpiob_13_pb13: gpiob_13_pb13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pb13: uc3_sclk_pb13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pb13: uc3_rx_pb13 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_cs0_pb13: uc3_cs0_pb13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pb13: uc3_cts_pb13 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima_fault2_pb13: tima_fault2_pb13 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_cmpl_pb13: tima0_ccp1_cmpl_pb13 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_pb13: tima0_ccp3_pb13 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad1_pb13: i2s0_ad1_pb13 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb14: adc_pb14 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_14_pb14: gpiob_14_pb14 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pb14: uc2_cs3_pb14 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pb14: uc3_poci_pb14 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pb14: uc3_rts_pb14 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pb14: tima0_ccp2_pb14 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_pb14: tima0_ccp0_pb14 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_mclk_pb14: i2s0_mclk_pb14 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb15: adc_pb15 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_15_pb15: gpiob_15_pb15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pb15: uc3_pico_pb15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pb15: uc3_tx_pb15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pb15: uc3_cs0_pb15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pb15: uc3_cts_pb15 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg7_ccp0_pb15: timg7_ccp0_pb15 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb16: adc_pb16 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_16_pb16: gpiob_16_pb16 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pb16: uc3_sclk_pb16 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pb16: uc3_rx_pb16 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_poci_pb16: uc3_poci_pb16 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pb16: uc3_rts_pb16 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp1_pb16: timg7_ccp1_pb16 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa12: adc_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_12_pa12: gpioa_12_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pa12: uc3_cs0_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pa12: uc3_cts_pa12 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_sclk_pa12: uc2_sclk_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa12: comp0_out_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_pa12: tima0_ccp3_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pa12: sysctl_fcc_in_pa12 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg0_ccp0_pa12: timg0_ccp0_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_cts_pa12: uc1_cts_pa12 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ i2s0_bclk_pa12: i2s0_bclk_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rts_pa12: uc0_rts_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs0_pa12: uc2_cs0_pa12 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa13: adc_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_in2_minus_pa13: comp0_in2_minus_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_13_pa13: gpioa_13_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pa13: uc3_poci_pa13 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pa13: uc3_rts_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_poci_pa13: uc2_poci_pa13 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_sclk_pa13: uc3_sclk_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa13: uc3_rx_pa13 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp3_cmpl_pa13: tima0_ccp3_cmpl_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ lfss_rtc_out_pa13: lfss_rtc_out_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pa13: timg0_ccp1_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pa13: uc3_cs0_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pa13: uc3_cts_pa13 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ i2s0_ad0_pa13: i2s0_ad0_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rts_pa13: uc1_rts_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pa13: uc2_cs3_pa13 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa14: adc_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_in2_plus_pa14: comp0_in2_plus_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_14_pa14: gpioa_14_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_cts_pa14: uc0_cts_pa14 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_pico_pa14: uc2_pico_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pa14: uc3_pico_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa14: uc3_tx_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp0_pa14: timg7_ccp0_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pa14: sysctl_clk_out_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp0_pa14: timg6_ccp0_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad1_pa14: i2s0_ad1_pa14 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa15: adc_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_in3_plus_pa15: comp0_in3_plus_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_15_pa15: gpioa_15_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rts_pa15: uc0_rts_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pa15: uc2_cs3_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa15: uc1_scl_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa15: uc1_rx_pa15 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp2_pa15: tima0_ccp2_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa15: comp0_out_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rts_pa15: uc1_rts_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_wclk_pa15: i2s0_wclk_pa15 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa16: adc_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_16_pa16: gpioa_16_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_cts_pa16: uc0_cts_pa16 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_poci_pa16: uc3_poci_pa16 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pa16: uc3_rts_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa16: uc1_sda_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa16: uc1_tx_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pa16: tima0_ccp2_cmpl_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pa16: sysctl_fcc_in_pa16 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_cts_pa16: uc1_cts_pa16 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ comp0_out_pa16: comp0_out_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_mclk_pa16: i2s0_mclk_pa16 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa17: adc_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_in1_minus_pa17: comp0_in1_minus_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_17_pa17: gpioa_17_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa17: uc1_sda_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa17: uc1_tx_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pa17: uc3_sclk_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa17: uc3_rx_pa17 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_scl_pa17: uc1_scl_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa17: uc1_rx_pa17 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp3_pa17: tima0_ccp3_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp0_pa17: timg7_ccp0_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs1_pa17: uc2_cs1_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_wclk_pa17: i2s0_wclk_pa17 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa18: adc_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_in1_plus_pa18: comp0_in1_plus_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_18_pa18: gpioa_18_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa18: uc1_scl_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa18: uc1_rx_pa18 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_pico_pa18: uc3_pico_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa18: uc3_tx_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa18: uc1_sda_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa18: uc1_tx_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_cmpl_pa18: tima0_ccp3_cmpl_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp1_pa18: timg7_ccp1_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs0_pa18: uc2_cs0_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault2_pa18: tima_fault2_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_mclk_pa18: i2s0_mclk_pa18 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_19_pa19: gpioa_19_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ debugss_swdio_pa19: debugss_swdio_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pa19: uc3_poci_pa19 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pa19: uc3_rts_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa19: uc1_sda_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa19: uc1_tx_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pa19: tima0_ccp2_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pa19: timg0_ccp0_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad0_pa19: i2s0_ad0_pa19 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa20: adc_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_20_pa20: gpioa_20_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ debugss_swclk_pa20: debugss_swclk_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pa20: uc3_sclk_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa20: uc3_rx_pa20 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_scl_pa20: uc1_scl_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa20: uc1_rx_pa20 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pa20: tima0_ccp2_cmpl_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pa20: timg0_ccp1_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pa20: uc3_cs0_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pa20: uc3_cts_pa20 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ i2s0_ad1_pa20: i2s0_ad1_pa20 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb17: adc_pb17 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_17_pb17: gpiob_17_pb17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pb17: uc0_scl_pb17 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pb17: uc0_rx_pb17 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_pico_pb17: uc2_pico_pb17 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pb17: timg0_ccp0_pb17 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pb17: tima0_ccp2_pb17 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb18: adc_pb18 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_18_pb18: gpiob_18_pb18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pb18: uc0_sda_pb18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pb18: uc0_tx_pb18 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_sclk_pb18: uc2_sclk_pb18 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pb18: timg0_ccp1_pb18 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pb18: tima0_ccp2_cmpl_pb18 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb19: adc_pb19 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_19_pb19: gpiob_19_pb19 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_cts_pb19: uc0_cts_pb19 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_poci_pb19: uc2_poci_pb19 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg7_ccp1_pb19: timg7_ccp1_pb19 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pb19: comp0_out_pb19 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa21: adc_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ vref_vref_minus_pa21: vref_vref_minus_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_21_pa21: gpioa_21_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pa21: uc3_pico_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa21: uc3_tx_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pa21: uc2_cs3_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_cts_pa21: uc1_cts_pa21 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp0_pa21: tima0_ccp0_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp0_pa21: timg6_ccp0_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa21: comp0_out_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad0_pa21: i2s0_ad0_pa21 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa22: adc_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_22_pa22: gpioa_22_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pa22: uc3_sclk_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa22: uc3_rx_pa22 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs2_pa22: uc2_cs2_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rts_pa22: uc1_rts_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_cmpl_pa22: tima0_ccp0_cmpl_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp1_pa22: timg6_ccp1_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pa22: tima0_ccp1_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_bclk_pa22: i2s0_bclk_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pa22: sysctl_clk_out_pa22 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb20: adc_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_20_pb20: gpiob_20_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pb20: uc0_sda_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pb20: uc0_tx_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pb20: uc3_cs0_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pb20: uc3_cts_pb20 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs2_pb20: uc2_cs2_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pb20: tima0_ccp2_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault1_pb20: tima_fault1_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pb20: tima0_ccp1_pb20 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb21: adc_pb21 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_in0_plus_pb21: comp0_in0_plus_pb21 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_21_pb21: gpiob_21_pb21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pb21: uc0_scl_pb21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pb21: uc0_rx_pb21 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_poci_pb21: uc3_poci_pb21 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pb21: uc3_rts_pb21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pb21: uc1_sda_pb21 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pb21: uc1_tx_pb21 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb22: adc_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_in0_minus_pb22: comp0_in0_minus_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_22_pb22: gpiob_22_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pb22: uc0_sda_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pb22: uc0_tx_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pb22: uc3_pico_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pb22: uc3_tx_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pb22: uc1_scl_pb22 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pb22: uc1_rx_pb22 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ adc_pb23: adc_pb23 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_23_pb23: gpiob_23_pb23 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_cts_pb23: uc1_cts_pb23 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_sclk_pb23: uc3_sclk_pb23 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pb23: uc3_rx_pb23 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima_fault0_pb23: tima_fault0_pb23 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pb23: comp0_out_pb23 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb24: adc_pb24 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_24_pb24: gpiob_24_pb24 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pb24: uc2_cs3_pb24 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs1_pb24: uc2_cs1_pb24 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pb24: uc3_poci_pb24 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pb24: uc3_rts_pb24 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_pb24: tima0_ccp3_pb24 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_cmpl_pb24: tima0_ccp1_cmpl_pb24 { + pinmux = ; + }; + + /omit-if-no-ref/ vref_vref_minus_pa23: vref_vref_minus_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ vref_vref_plus_pa23: vref_vref_plus_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_23_pa23: gpioa_23_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pa23: uc3_pico_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa23: uc3_tx_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pa23: uc2_cs3_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pa23: uc3_cs0_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pa23: uc3_cts_pa23 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp3_pa23: tima0_ccp3_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pa23: timg0_ccp0_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp0_pa23: timg7_ccp0_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_wclk_pa23: i2s0_wclk_pa23 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa24: adc_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_24_pa24: gpioa_24_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pa24: uc3_poci_pa24 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pa24: uc3_rts_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs2_pa24: uc2_cs2_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pa24: uc3_sclk_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa24: uc3_rx_pa24 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp3_cmpl_pa24: tima0_ccp3_cmpl_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pa24: timg0_ccp1_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp1_pa24: timg7_ccp1_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad1_pa24: i2s0_ad1_pa24 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pa25: adc_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_25_pa25: gpioa_25_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pa25: uc3_sclk_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa25: uc3_rx_pa25 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs3_pa25: uc2_cs3_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pa25: uc3_pico_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa25: uc3_tx_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_pa25: tima0_ccp3_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_cmpl_pa25: tima0_ccp1_cmpl_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa25: comp0_out_pa25 { + pinmux = ; + }; + + /omit-if-no-ref/ adc_pb25: adc_pb25 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_25_pb25: gpiob_25_pb25 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_cts_pb25: uc0_cts_pb25 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs0_pb25: uc2_cs0_pb25 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault0_pb25: tima_fault0_pb25 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pb25: comp0_out_pb25 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pb25: sysctl_fcc_in_pb25 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ adc_pb26: adc_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_26_pb26: gpiob_26_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rts_pb26: uc0_rts_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs1_pb26: uc2_cs1_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_pb26: tima0_ccp0_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_pb26: tima0_ccp3_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp0_pb26: timg6_ccp0_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pb26: comp0_out_pb26 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pb26: sysctl_fcc_in_pb26 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ usbfs0_dm_pa26: usbfs0_dm_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_26_pa26: gpioa_26_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pa26: uc0_sda_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pa26: uc0_tx_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa26: uc1_scl_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa26: uc1_rx_pa26 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg7_ccp0_pa26: timg7_ccp0_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pa26: sysctl_fcc_in_pa26 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima_fault0_pa26: tima_fault0_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pa26: uc3_pico_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa26: uc3_tx_pa26 { + pinmux = ; + }; + + /omit-if-no-ref/ usbfs0_dp_pa27: usbfs0_dp_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_27_pa27: gpioa_27_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pa27: uc0_scl_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pa27: uc0_rx_pa27 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_sda_pa27: uc1_sda_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa27: uc1_tx_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp1_pa27: timg7_ccp1_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pa27: sysctl_clk_out_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ lfss_rtc_out_pa27: lfss_rtc_out_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa27: comp0_out_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pa27: uc3_sclk_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa27: uc3_rx_pa27 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima_fault2_pa27: tima_fault2_pa27 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_00_pa0: gpioa_00_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa0: uc1_sda_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa0: uc1_tx_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pa0: sysctl_fcc_in_pa0 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp0_pa0: tima0_ccp0_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pa0: timg0_ccp0_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault1_pa0: tima_fault1_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pa0: uc0_sda_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pa0: uc0_tx_pa0 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_01_pa1: gpioa_01_pa1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa1: uc1_scl_pa1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa1: uc1_rx_pa1 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs3_pa1: uc2_cs3_pa1 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pa1: tima0_ccp1_pa1 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pa1: timg0_ccp1_pa1 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault2_pa1: tima_fault2_pa1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pa1: uc0_scl_pa1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pa1: uc0_rx_pa1 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ gpioa_28_pa28: gpioa_28_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa28: uc1_sda_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa28: uc1_tx_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pa28: tima0_ccp1_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_pa28: tima0_ccp3_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp0_pa28: timg7_ccp0_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault0_pa28: tima_fault0_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pa28: uc0_sda_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pa28: uc0_tx_pa28 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_29_pa29: gpioa_29_pa29 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa29: uc1_scl_pa29 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa29: uc1_rx_pa29 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_cts_pa29: uc1_cts_pa29 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs3_pa29: uc2_cs3_pa29 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp0_pa29: timg6_ccp0_pa29 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_cts_pa29: uc0_cts_pa29 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ gpioa_30_pa30: gpioa_30_pa30 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa30: uc1_sda_pa30 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa30: uc1_tx_pa30 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rts_pa30: uc1_rts_pa30 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs2_pa30: uc2_cs2_pa30 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp1_pa30: timg6_ccp1_pa30 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rts_pa30: uc0_rts_pa30 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_31_pa31: gpioa_31_pa31 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa31: uc1_scl_pa31 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa31: uc1_rx_pa31 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs3_pa31: uc2_cs3_pa31 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_cmpl_pa31: tima0_ccp3_cmpl_pa31 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp1_pa31: timg7_ccp1_pa31 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pa31: sysctl_clk_out_pa31 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pa31: uc0_scl_pa31 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pa31: uc0_rx_pa31 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ sysctl_rosc_pa2: sysctl_rosc_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_02_pa2: gpioa_02_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rts_pa2: uc1_rts_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs1_pa2: uc2_cs1_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp1_pa2: timg7_ccp1_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_pa2: tima0_ccp0_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_cmpl_pa2: tima0_ccp3_cmpl_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pa2: tima0_ccp2_cmpl_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault0_pa2: tima_fault0_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pa2: uc3_cs0_pa2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pa2: uc3_cts_pa2 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ sysctl_lfxin_pa3: sysctl_lfxin_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_03_pa3: gpioa_03_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa3: uc1_sda_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa3: uc1_tx_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs1_pa3: uc2_cs1_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pa3: uc2_cs3_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pa3: tima0_ccp1_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa3: comp0_out_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp0_pa3: timg7_ccp0_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pa3: tima0_ccp2_pa3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_cts_pa3: uc1_cts_pa3 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ sysctl_lfxout_pa4: sysctl_lfxout_pa4 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_04_pa4: gpioa_04_pa4 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa4: uc1_scl_pa4 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa4: uc1_rx_pa4 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_poci_pa4: uc2_poci_pa4 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs0_pa4: uc2_cs0_pa4 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_cmpl_pa4: tima0_ccp1_cmpl_pa4 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_lfclkin_pa4: sysctl_lfclkin_pa4 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg7_ccp1_pa4: timg7_ccp1_pa4 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_pa4: tima0_ccp3_pa4 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_hfxin_pa5: sysctl_hfxin_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_05_pa5: gpioa_05_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa5: uc1_sda_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa5: uc1_tx_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_pico_pa5: uc2_pico_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_cts_pa5: uc0_cts_pa5 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg0_ccp0_pa5: timg0_ccp0_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pa5: sysctl_fcc_in_pa5 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg6_ccp0_pa5: timg6_ccp0_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault1_pa5: tima_fault1_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pa5: uc3_poci_pa5 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pa5: uc3_rts_pa5 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_hfxout_pa6: sysctl_hfxout_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_06_pa6: gpioa_06_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa6: uc1_scl_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa6: uc1_rx_pa6 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_sclk_pa6: uc2_sclk_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rts_pa6: uc0_rts_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pa6: timg0_ccp1_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_hfclkin_pa6: sysctl_hfclkin_pa6 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ timg6_ccp1_pa6: timg6_ccp1_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault0_pa6: tima_fault0_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pa6: tima0_ccp2_cmpl_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pa6: uc3_pico_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa6: uc3_tx_pa6 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_00_pb0: gpiob_00_pb0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pb0: uc0_sda_pb0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pb0: uc0_tx_pb0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pb0: uc2_cs3_pb0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pb0: uc0_scl_pb0 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pb0: uc0_rx_pb0 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp2_pb0: tima0_ccp2_pb0 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pb0: timg0_ccp0_pb0 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_01_pb1: gpiob_01_pb1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pb1: uc0_scl_pb1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pb1: uc0_rx_pb1 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs2_pb1: uc2_cs2_pb1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pb1: uc0_sda_pb1 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pb1: uc0_tx_pb1 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pb1: tima0_ccp2_cmpl_pb1 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pb1: timg0_ccp1_pb1 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_07_pa7: gpioa_07_pa7 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_poci_pa7: uc2_poci_pa7 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs2_pa7: uc2_cs2_pa7 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa7: comp0_out_pa7 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pa7: tima0_ccp2_pa7 { + pinmux = ; + }; + + /omit-if-no-ref/ timg7_ccp1_pa7: timg7_ccp1_pa7 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pa7: sysctl_clk_out_pa7 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pa7: tima0_ccp1_pa7 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_fcc_in_pa7: sysctl_fcc_in_pa7 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ gpiob_02_pb2: gpiob_02_pb2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pb2: uc3_pico_pb2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pb2: uc3_tx_pb2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pb2: uc1_scl_pb2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pb2: uc1_rx_pb2 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_cts_pb2: uc1_cts_pb2 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp3_pb2: tima0_ccp3_pb2 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp0_pb2: timg6_ccp0_pb2 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_pico_pb2: uc2_pico_pb2 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_hfclkin_pb2: sysctl_hfclkin_pb2 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ gpiob_03_pb3: gpiob_03_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pb3: uc3_sclk_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pb3: uc3_rx_pb3 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_sda_pb3: uc1_sda_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pb3: uc1_tx_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rts_pb3: uc1_rts_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp3_cmpl_pb3: tima0_ccp3_cmpl_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp1_pb3: timg6_ccp1_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_sclk_pb3: uc2_sclk_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_pb3: tima0_ccp0_pb3 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_04_pb4: gpiob_04_pb4 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pb4: uc1_sda_pb4 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pb4: uc1_tx_pb4 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pb4: uc3_cs0_pb4 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pb4: uc3_cts_pb4 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp1_pb4: tima0_ccp1_pb4 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pb4: tima0_ccp2_pb4 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pb4: timg0_ccp0_pb4 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_05_pb5: gpiob_05_pb5 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pb5: uc1_scl_pb5 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pb5: uc1_rx_pb5 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_poci_pb5: uc3_poci_pb5 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pb5: uc3_rts_pb5 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_cmpl_pb5: tima0_ccp1_cmpl_pb5 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pb5: tima0_ccp2_cmpl_pb5 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pb5: timg0_ccp1_pb5 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_08_pa8: gpioa_08_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pa8: uc1_sda_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa8: uc1_tx_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs0_pa8: uc2_cs0_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pa8: uc0_sda_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pa8: uc0_tx_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_pa8: tima0_ccp0_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault2_pa8: tima_fault2_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs3_pa8: uc2_cs3_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_wclk_pa8: i2s0_wclk_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rts_pa8: uc0_rts_pa8 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_hfclkin_pa8: sysctl_hfclkin_pa8 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ gpioa_09_pa9: gpioa_09_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa9: uc1_scl_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa9: uc1_rx_pa9 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_pico_pa9: uc2_pico_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pa9: uc0_scl_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pa9: uc0_rx_pa9 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp0_cmpl_pa9: tima0_ccp0_cmpl_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pa9: sysctl_clk_out_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pa9: tima0_ccp1_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ lfss_rtc_out_pa9: lfss_rtc_out_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_bclk_pa9: i2s0_bclk_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pa9: uc3_sclk_pa9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pa9: uc3_rx_pa9 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc0_cts_pa9: uc0_cts_pa9 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ gpioa_10_pa10: gpioa_10_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_sda_pa10: uc0_sda_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_tx_pa10: uc0_tx_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_poci_pa10: uc2_poci_pa10 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc1_sda_pa10: uc1_sda_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pa10: uc1_tx_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pa10: tima0_ccp2_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pa10: sysctl_clk_out_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pa10: timg0_ccp0_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault1_pa10: tima_fault1_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad0_pa10: i2s0_ad0_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pa10: uc3_pico_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pa10: uc3_tx_pa10 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_dac_out_pa11: comp0_dac_out_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ gpioa_11_pa11: gpioa_11_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_scl_pa11: uc0_scl_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ uc0_rx_pa11: uc0_rx_pa11 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_sclk_pa11: uc2_sclk_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pa11: uc1_scl_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pa11: uc1_rx_pa11 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp2_cmpl_pa11: tima0_ccp2_cmpl_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pa11: comp0_out_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pa11: timg0_ccp1_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault0_pa11: tima_fault0_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad1_pa11: i2s0_ad1_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pa11: uc3_poci_pa11 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pa11: uc3_rts_pa11 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_06_pb6: gpiob_06_pb6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_sda_pb6: uc1_sda_pb6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_tx_pb6: uc1_tx_pb6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pb6: uc3_cs0_pb6 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pb6: uc3_cts_pb6 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs1_pb6: uc2_cs1_pb6 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp0_pb6: timg6_ccp0_pb6 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault2_pb6: tima_fault2_pb6 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_07_pb7: gpiob_07_pb7 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_scl_pb7: uc1_scl_pb7 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rx_pb7: uc1_rx_pb7 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_poci_pb7: uc3_poci_pb7 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pb7: uc3_rts_pb7 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs2_pb7: uc2_cs2_pb7 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp1_pb7: timg6_ccp1_pb7 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_08_pb8: gpiob_08_pb8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_cts_pb8: uc1_cts_pb8 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_pico_pb8: uc3_pico_pb8 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pb8: uc3_tx_pb8 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pb8: comp0_out_pb8 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_pb8: tima0_ccp0_pb8 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_09_pb9: gpiob_09_pb9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc1_rts_pb9: uc1_rts_pb9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_sclk_pb9: uc3_sclk_pb9 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_rx_pb9: uc3_rx_pb9 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ tima0_ccp1_pb9: tima0_ccp1_pb9 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp0_cmpl_pb9: tima0_ccp0_cmpl_pb9 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_10_pb10: gpiob_10_pb10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cs0_pb10: uc3_cs0_pb10 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_cts_pb10: uc3_cts_pb10 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc2_cs1_pb10: uc2_cs1_pb10 { + pinmux = ; + }; + + /omit-if-no-ref/ comp0_out_pb10: comp0_out_pb10 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp0_pb10: timg0_ccp0_pb10 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp0_pb10: timg6_ccp0_pb10 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_wclk_pb10: i2s0_wclk_pb10 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_11_pb11: gpiob_11_pb11 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_poci_pb11: uc3_poci_pb11 { + pinmux = ; + input-enable; + }; + + /omit-if-no-ref/ uc3_rts_pb11: uc3_rts_pb11 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs2_pb11: uc2_cs2_pb11 { + pinmux = ; + }; + + /omit-if-no-ref/ sysctl_clk_out_pb11: sysctl_clk_out_pb11 { + pinmux = ; + }; + + /omit-if-no-ref/ timg0_ccp1_pb11: timg0_ccp1_pb11 { + pinmux = ; + }; + + /omit-if-no-ref/ timg6_ccp1_pb11: timg6_ccp1_pb11 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_bclk_pb11: i2s0_bclk_pb11 { + pinmux = ; + }; + + /omit-if-no-ref/ gpiob_12_pb12: gpiob_12_pb12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_pico_pb12: uc3_pico_pb12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc3_tx_pb12: uc3_tx_pb12 { + pinmux = ; + }; + + /omit-if-no-ref/ uc2_cs0_pb12: uc2_cs0_pb12 { + pinmux = ; + }; + + /omit-if-no-ref/ tima_fault1_pb12: tima_fault1_pb12 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp1_pb12: tima0_ccp1_pb12 { + pinmux = ; + }; + + /omit-if-no-ref/ tima0_ccp2_pb12: tima0_ccp2_pb12 { + pinmux = ; + }; + + /omit-if-no-ref/ i2s0_ad0_pb12: i2s0_ad0_pb12 { + pinmux = ; + }; + }; + }; +}; \ No newline at end of file diff --git a/mspm0/CMakeLists.txt b/mspm0/CMakeLists.txt index f3abb96..b335f7a 100644 --- a/mspm0/CMakeLists.txt +++ b/mspm0/CMakeLists.txt @@ -30,6 +30,8 @@ if(CONFIG_HAS_MSPM0_SDK) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_GPAMP source/ti/driverlib/dl_gpamp.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_GPIO source/ti/driverlib/dl_gpio.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_I2C source/ti/driverlib/dl_i2c.c) + zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_UNICOMM_I2CC source/ti/driverlib/dl_unicommi2cc.c) + zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_UNICOMM_I2CT source/ti/driverlib/dl_unicommi2ct.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_IWDT source/ti/driverlib/dl_iwdt.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_KEYSTORECTL source/ti/driverlib/dl_keystorectl.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_LCD source/ti/driverlib/dl_lcd.c) @@ -43,12 +45,14 @@ if(CONFIG_HAS_MSPM0_SDK) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_RTC source/ti/driverlib/dl_rtc.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_SCRATCHPAD source/ti/driverlib/dl_scratchpad.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_SPI source/ti/driverlib/dl_spi.c) + zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_UNICOMM_SPI source/ti/driverlib/dl_unicommspi.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_TAMPERIO source/ti/driverlib/dl_tamperio.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_TIMER source/ti/driverlib/dl_timer.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_TIMER source/ti/driverlib/dl_timera.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_TIMER source/ti/driverlib/dl_timerg.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_TRNG source/ti/driverlib/dl_trng.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_UART source/ti/driverlib/dl_uart.c) + zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_UNICOMM_UART source/ti/driverlib/dl_unicommuart.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_VREF source/ti/driverlib/dl_vref.c) zephyr_library_sources_ifdef(CONFIG_USE_MSPM0_DL_WWDT source/ti/driverlib/dl_wwdt.c) endif() diff --git a/mspm0/source/ti/devices/DeviceFamily.h b/mspm0/source/ti/devices/DeviceFamily.h index 491459e..d8d739b 100644 --- a/mspm0/source/ti/devices/DeviceFamily.h +++ b/mspm0/source/ti/devices/DeviceFamily.h @@ -74,6 +74,12 @@ extern "C" { #define DeviceFamily_ID_MSPM0G351X 13 #define DeviceFamily_ID_MSPM0L111X 14 #define DeviceFamily_ID_MSPM0H321X 15 +#define DeviceFamily_ID_MSPM0C1105_C1106 16 +#define DeviceFamily_ID_MSPM0G511X 17 +#define DeviceFamily_ID_MSPM0G518X 18 +#define DeviceFamily_ID_MSPM0L211X 19 +#define DeviceFamily_ID_MSPM0L112X 20 +#define DeviceFamily_ID_MSPM0G352X 21 /* * DeviceFamily_PARENT_XYZ values. @@ -90,6 +96,11 @@ extern "C" { #define DeviceFamily_PARENT_MSPM0GX51X 6 #define DeviceFamily_PARENT_MSPM0L111X 7 #define DeviceFamily_PARENT_MSPM0H321X 8 +#define DeviceFamily_PARENT_MSPM0C1105_C1106 9 +#define DeviceFamily_PARENT_MSPM0G511X 10 +#define DeviceFamily_PARENT_MSPM0G518X 11 +#define DeviceFamily_PARENT_MSPM0L211X_L112X 12 +#define DeviceFamily_PARENT_MSPM0G352X 13 /* * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and @@ -140,6 +151,7 @@ extern "C" { #define DeviceFamily_ID DeviceFamily_ID_MSPM0G350X #define DeviceFamily_DIRECTORY msp #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0G1X0X_G3X0X + #elif defined(DeviceFamily_MSPM0C110X) || defined(__MSPM0C1104__) \ || defined(__MSPM0C1103__) #define DeviceFamily_ID DeviceFamily_ID_MSPM0C110X @@ -176,6 +188,11 @@ extern "C" { #define DeviceFamily_DIRECTORY msp #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0GX51X +#elif defined(DeviceFamily_MSPM0G352X) || defined(__MSPM0G3529__) + #define DeviceFamily_ID DeviceFamily_ID_MSPM0G352X + #define DeviceFamily_DIRECTORY msp + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0G352X + #elif defined(DeviceFamily_MSPM0L111X) || defined(__MSPM0L1117__) \ || defined(__MSPM0L1116__) #define DeviceFamily_ID DeviceFamily_ID_MSPM0L111X @@ -188,6 +205,36 @@ extern "C" { #define DeviceFamily_DIRECTORY msp #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0H321X +#elif defined(DeviceFamily_MSPM0C1105_C1106) || defined(__MSPM0C1106__) \ + || defined(__MSPM0C1105__) + #define DeviceFamily_ID DeviceFamily_ID_MSPM0C1105_C1106 + #define DeviceFamily_DIRECTORY msp + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0C1105_C1106 + +#elif defined(DeviceFamily_MSPM0G511X) || defined(__MSPM0G5117__) \ + || defined(__MSPM0G5116__) || defined(__MSPM0G5115__) + #define DeviceFamily_ID DeviceFamily_ID_MSPM0G511X + #define DeviceFamily_DIRECTORY msp + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0G511X + +#elif defined(DeviceFamily_MSPM0G518X) || defined(__MSPM0G5187__) + #define DeviceFamily_ID DeviceFamily_ID_MSPM0G518X + #define DeviceFamily_DIRECTORY msp + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0G518X + + +#elif defined(DeviceFamily_MSPM0L211X) || defined(__MSPM0L2117__) \ + || defined(__MSPM0L2116__) + #define DeviceFamily_ID DeviceFamily_ID_MSPM0L211X + #define DeviceFamily_DIRECTORY msp + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0L211X_L112X + +#elif defined(DeviceFamily_MSPM0L112X) || defined(__MSPM0L1127__) \ + || defined(__MSPM0L1126__) + #define DeviceFamily_ID DeviceFamily_ID_MSPM0L112X + #define DeviceFamily_DIRECTORY msp + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSPM0L211X_L112X + #else #error "DeviceFamily_XYZ undefined. You must define a DeviceFamily_XYZ!" @@ -207,8 +254,14 @@ extern "C" { + defined(DeviceFamily_MSPM0L222X) \ + defined(DeviceFamily_MSPM0G151X) \ + defined(DeviceFamily_MSPM0G351X) \ + + defined(DeviceFamily_MSPM0G352X) \ + defined(DeviceFamily_MSPM0L111X) \ + defined(DeviceFamily_MSPM0H321X) \ + + defined(DeviceFamily_MSPM0C1105_C1106) \ + + defined(DeviceFamily_MSPM0G511X) \ + + defined(DeviceFamily_MSPM0G518X) \ + + defined(DeviceFamily_MSPM0L211X) \ + + defined(DeviceFamily_MSPM0L112X) \ ) > 1 #error More then one DeviceFamily has been defined! #endif diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0c1105_c1106.h b/mspm0/source/ti/devices/msp/m0p/mspm0c1105_c1106.h new file mode 100644 index 0000000..f629adb --- /dev/null +++ b/mspm0/source/ti/devices/msp/m0p/mspm0c1105_c1106.h @@ -0,0 +1,1057 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_m0p_mspm0c1105_C1106__include +#define ti_devices_msp_m0p_mspm0c1105_C1106__include + +/* Filename: mspm0c1105_c1106.h */ +/* Revised: 2024-06-21 09:34:50*/ + +/* Use standard integer types with explicit width */ +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup MSPM0C1105_C1106_Definitions MSPM0C1105_C1106 Definitions + This file defines all structures and symbols for MSPM0C1105_C1106 + @{ +*/ + +/** @addtogroup MSPM0C1105_C1106_CMSIS Device CMSIS Definitions + Configuration of the Processor and Core Peripherals + @{ +*/ +/****************************************************************************** +* Interrupt Definitions * +******************************************************************************/ +typedef enum IRQn +{ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + SYSCTL_INT_IRQn = 0, /* 16 SYSCTL_INT Interrupt */ + DEBUGSS_INT_IRQn = 1, /* 17 DEBUGSS_INT Interrupt */ + TIMG8_INT_IRQn = 2, /* 18 TIMG8_INT Interrupt */ + UART1_INT_IRQn = 3, /* 19 UART1_INT Interrupt */ + ADC0_INT_IRQn = 4, /* 20 ADC0_INT Interrupt */ + COMP0_INT_IRQn = 7, /* 23 COMP0_INT Interrupt */ + UART2_INT_IRQn = 8, /* 24 UART2_INT Interrupt */ + SPI0_INT_IRQn = 9, /* 25 SPI0_INT Interrupt */ + UART0_INT_IRQn = 15, /* 31 UART0_INT Interrupt */ + TIMG14_INT_IRQn = 16, /* 32 TIMG14_INT Interrupt */ + TIMG2_INT_IRQn = 17, /* 33 TIMG2_INT Interrupt */ + TIMA0_INT_IRQn = 18, /* 34 TIMA0_INT Interrupt */ + TIMG1_INT_IRQn = 19, /* 35 TIMG1_INT Interrupt */ + GPIOA_INT_IRQn = 22, /* 38 GPIOA_INT Interrupt */ + GPIOB_INT_IRQn = 23, /* 39 GPIOB_INT Interrupt */ + I2C0_INT_IRQn = 24, /* 40 I2C0_INT Interrupt */ + I2C1_INT_IRQn = 25, /* 41 I2C1_INT Interrupt */ + FLASHCTL_INT_IRQn = 27, /* 43 FLASHCTL_INT Interrupt */ + WWDT0_INT_IRQn = 29, /* 45 WWDT0_INT Interrupt */ + LFSS_INT_IRQn = 30, /* 46 LFSS_INT Interrupt */ + RTC_B_INT_IRQn = 30, /* 46 RTC_B_INT Interrupt */ + DMA_INT_IRQn = 31, /* 47 DMA_INT Interrupt */ +} IRQn_Type; + +#define NonMaskableInt_VECn 2 /* Non Maskable Interrupt */ +#define HardFault_VECn 3 /* Hard Fault Interrupt */ +#define SVCall_VECn 11 /* SV Call Interrupt */ +#define PendSV_VECn 14 /* Pend SV Interrupt */ +#define SysTick_VECn 15 /* System Tick Interrupt */ +#define SYSCTL_INT_VECn 16 /* SYSCTL_INT Interrupt */ +#define DEBUGSS_INT_VECn 17 /* DEBUGSS_INT Interrupt */ +#define TIMG8_INT_VECn 18 /* TIMG8_INT Interrupt */ +#define UART1_INT_VECn 19 /* UART1_INT Interrupt */ +#define ADC0_INT_VECn 20 /* ADC0_INT Interrupt */ +#define COMP0_INT_VECn 23 /* COMP0_INT Interrupt */ +#define UART2_INT_VECn 24 /* UART2_INT Interrupt */ +#define SPI0_INT_VECn 25 /* SPI0_INT Interrupt */ +#define UART0_INT_VECn 31 /* UART0_INT Interrupt */ +#define TIMG14_INT_VECn 32 /* TIMG14_INT Interrupt */ +#define TIMG2_INT_VECn 33 /* TIMG2_INT Interrupt */ +#define TIMA0_INT_VECn 34 /* TIMA0_INT Interrupt */ +#define TIMG1_INT_VECn 35 /* TIMG1_INT Interrupt */ +#define GPIOA_INT_VECn 38 /* GPIOA_INT Interrupt */ +#define GPIOB_INT_VECn 39 /* GPIOB_INT Interrupt */ +#define I2C0_INT_VECn 40 /* I2C0_INT Interrupt */ +#define I2C1_INT_VECn 41 /* I2C1_INT Interrupt */ +#define FLASHCTL_INT_VECn 43 /* FLASHCTL_INT Interrupt */ +#define WWDT0_INT_VECn 45 /* WWDT0_INT Interrupt */ +#define LFSS_INT_VECn 46 /* LFSS_INT Interrupt */ +#define RTC_B_INT_VECn 46 /* RTC_B_INT Interrupt */ +#define DMA_INT_VECn 47 /* DMA_INT Interrupt */ + + +/****************************************************************************** +* Ignore unused variables * +******************************************************************************/ + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/****************************************************************************** +* Processor and Core Peripheral Section * +******************************************************************************/ + +#define __CM0PLUS_REV 0x0001U /* Core revision r0p1 */ +#define __MPU_PRESENT 0x0001U /* MPU present */ +#define __VTOR_PRESENT 0x0001U /* VTOR present */ +#define __NVIC_PRIO_BITS 0x0002U /* Number of bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0plus.h" /* Processor and core peripherals */ + +/****************************************************************************** +* Peripheral headers * +******************************************************************************/ +/** @addtogroup MSPM0C1105_C1106_Peripherals MSPM0C1105_C1106 Peripherals + MSPM0C1105_C1106 Peripheral registers structures + @{ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __MSPM0_HAS_ADC12__ +#define __MSPM0_HAS_COMP__ +#define __MSPM0_HAS_CRC__ +#define __MSPM0_HAS_GPIO__ +#define __MSPM0_HAS_TIMER_A__ +#define __MSPM0_HAS_TIMER_G__ +#define __MSPM0_HAS_I2C__ +#define __MSPM0_HAS_LFSS__ +#define __MSPM0_HAS_SPI__ +#define __MSPM0_HAS_UART_EXTD__ +#define __MSPM0_HAS_UART_MAIN__ +#define __MSPM0_HAS_VREF__ +#define __MSPM0_HAS_WWDT__ +#define __MSPM0_HAS_RTC_B__ +#define __MSPM0_HAS_IWDT__ +#define __MSPM0_HAS_ADC12_SH_CAP_DISCH__ + +/*@}*/ /* end of group MSPM0C1105_C1106_Peripherals */ + +/****************************************************************************** +* Device and peripheral memory map * +******************************************************************************/ +/** @addtogroup MSPM0C1105_C1106_MemoryMap MSPM0C1105_C1106 Memory Mapping + @{ +*/ + +#define UART1_BASE (0x40100000U) /*!< Base address of module UART1 */ +#define SPI0_BASE (0x40468000U) /*!< Base address of module SPI0 */ +#define CRC_BASE (0x40440000U) /*!< Base address of module CRC */ +#define TIMA0_BASE (0x40860000U) /*!< Base address of module TIMA0 */ +#define GPIOB_BASE (0x400A2000U) /*!< Base address of module GPIOB */ +#define UART2_BASE (0x40102000U) /*!< Base address of module UART2 */ +#define TIMG1_BASE (0x40086000U) /*!< Base address of module TIMG1 */ +#define TIMG8_BASE (0x40090000U) /*!< Base address of module TIMG8 */ +#define WWDT0_BASE (0x40080000U) /*!< Base address of module WWDT0 */ +#define UART0_BASE (0x40108000U) /*!< Base address of module UART0 */ +#define I2C1_BASE (0x400F2000U) /*!< Base address of module I2C1 */ +#define TIMG2_BASE (0x40088000U) /*!< Base address of module TIMG2 */ +#define DEBUGSS_BASE (0x400C7000U) /*!< Base address of module DEBUGSS */ +#define GPIOA_BASE (0x400A0000U) /*!< Base address of module GPIOA */ +#define FLASHCTL_BASE (0x400CD000U) /*!< Base address of module FLASHCTL */ +#define I2C0_BASE (0x400F0000U) /*!< Base address of module I2C0 */ +#define WUC_BASE (0x40424000U) /*!< Base address of module WUC */ +#define DMA_BASE (0x4042A000U) /*!< Base address of module DMA */ +#define COMP0_BASE (0x40008000U) /*!< Base address of module COMP0 */ +#define CPUSS_BASE (0x40400000U) /*!< Base address of module CPUSS */ +#define SYSCTL_BASE (0x400AF000U) /*!< Base address of module SYSCTL */ +#define IOMUX_BASE (0x40428000U) /*!< Base address of module IOMUX */ +#define TIMG14_BASE (0x40084000U) /*!< Base address of module TIMG14 */ +#define LFSS_BASE (0x40094000U) /*!< Base address of module LFSS */ +#define RTC_B_BASE (0x40094000U) /*!< Base address of module RTC_B */ +#define VREF_BASE (0x40030000U) /*!< Base address of module VREF */ +#define ADC0_BASE (0x40004000U) /*!< Base address of module ADC0 */ +#define ADC0_PERIPHERALREGIONSVT_BASE (0x4055A000U) /*!< Base address of module ADC0_PERIPHERALREGIONSVT */ +#define FACTORYREGION_BASE (0x41C40000U) /*!< Base address of module FACTORYREGION */ + +/*@}*/ /* end of group MSPM0C1105_C1106_MemoryMap */ + +/****************************************************************************** +* Peripheral declarations * +******************************************************************************/ +/** @addtogroup MSPM0C1105_C1106_PeripheralDecl MSPM0C1105_C1106 Peripheral Declaration + @{ +*/ + +static UART_Regs * const UART1 = ((UART_Regs *) UART1_BASE); +static SPI_Regs * const SPI0 = ((SPI_Regs *) SPI0_BASE); +static CRC_Regs * const CRC = ((CRC_Regs *) CRC_BASE); +static GPTIMER_Regs * const TIMA0 = ((GPTIMER_Regs *) TIMA0_BASE); +static GPIO_Regs * const GPIOB = ((GPIO_Regs *) GPIOB_BASE); +static UART_Regs * const UART2 = ((UART_Regs *) UART2_BASE); +static GPTIMER_Regs * const TIMG1 = ((GPTIMER_Regs *) TIMG1_BASE); +static GPTIMER_Regs * const TIMG8 = ((GPTIMER_Regs *) TIMG8_BASE); +static WWDT_Regs * const WWDT0 = ((WWDT_Regs *) WWDT0_BASE); +static UART_Regs * const UART0 = ((UART_Regs *) UART0_BASE); +static I2C_Regs * const I2C1 = ((I2C_Regs *) I2C1_BASE); +static GPTIMER_Regs * const TIMG2 = ((GPTIMER_Regs *) TIMG2_BASE); +static DEBUGSS_Regs * const DEBUGSS = ((DEBUGSS_Regs *) DEBUGSS_BASE); +static GPIO_Regs * const GPIOA = ((GPIO_Regs *) GPIOA_BASE); +static FLASHCTL_Regs * const FLASHCTL = ((FLASHCTL_Regs *) FLASHCTL_BASE); +static I2C_Regs * const I2C0 = ((I2C_Regs *) I2C0_BASE); +static WUC_Regs * const WUC = ((WUC_Regs *) WUC_BASE); +static DMA_Regs * const DMA = ((DMA_Regs *) DMA_BASE); +static COMP_Regs * const COMP0 = ((COMP_Regs *) COMP0_BASE); +static CPUSS_Regs * const CPUSS = ((CPUSS_Regs *) CPUSS_BASE); +static SYSCTL_Regs * const SYSCTL = ((SYSCTL_Regs *) SYSCTL_BASE); +static IOMUX_Regs * const IOMUX = ((IOMUX_Regs *) IOMUX_BASE); +static GPTIMER_Regs * const TIMG14 = ((GPTIMER_Regs *) TIMG14_BASE); +static LFSS_Regs * const LFSS = ((LFSS_Regs *) LFSS_BASE); +static RTC_Regs * const RTC_B = ((RTC_Regs *) RTC_B_BASE); +static VREF_Regs * const VREF = ((VREF_Regs *) VREF_BASE); +static ADC12_Regs * const ADC0 = ((ADC12_Regs *) ADC0_BASE); +static ADC12_PERIPHERALREGIONSVT_Regs * const ADC0_PERIPHERALREGIONSVT = ((ADC12_PERIPHERALREGIONSVT_Regs *) ADC0_PERIPHERALREGIONSVT_BASE); +static FACTORYREGION_OPEN_Regs * const FACTORYREGION = ((FACTORYREGION_OPEN_Regs *) FACTORYREGION_BASE); + +/****************************************************************************** +* SYS parameters * +******************************************************************************/ + +#define UART1_SYS_FENTRIES (4) /* !< Number of FIFO entries */ +#define SPI0_SYS_FENTRIES (4) /* !< The number of entries in RX and TX FIFO */ +#define CRC_SYS_CRC32_ENABLE (0) /* !< Parameter to exclude or include 32-bit CRC. This is added for + Lego_N1 products where 32-bit CRC can be excluded in order to save + gates. */ +#define UART2_SYS_FENTRIES (4) /* !< Number of FIFO entries */ +#define UART0_SYS_FENTRIES (4) /* !< Number of FIFO entries */ +#define I2C_SYS_FENTRIES (4) /* !< Parameter for number of FIFO entries */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word: Minimum: 64 Maximum: + 128 */ +#define FLASHCTL_SYS_WEPROTBWIDTH (8) /* !< Bit width of WEPROTB register. */ +#define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register. */ +#define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register. */ +#define DMA_SYS_N_DMA_CHANNEL (3) /* !< Number of DMA channels implemented in DMA. */ +#define DMA_SYS_N_DMA_FULL_CHANNEL (2) /* !< Number of FULL-DMA channels implemented in DMA. If + SYS_N_DMA_CHANNEL is larger than SYS_N_DMA_FULL_CHANNEL, the + remaining channel will be BASIC channel with limited functionality. */ +#define DMA_SYS_MMR_AUTO (1) /* !< Boolean for if auto enable channels implemented in DMA. */ +#define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ +#define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ +#define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ +#define ADC_SYS_NUM_ANALOG_CHAN (32) /* !< Number of analog channels. */ +#define COMP_SYS_DACOUT_EN (1) /* !< Boolean for if 8-bit DAC output to pin is available */ + +/****************************************************************************** +* DMA Triggers * +******************************************************************************/ + +/* External DMA Triggers */ +#define DMA_SOFTWARE_TRIG (0) +#define DMA_GENERIC_SUB0_TRIG (1) +#define DMA_GENERIC_SUB1_TRIG (2) +#define DMA_I2C0_TX_TRIG (3) +#define DMA_I2C0_RX_TRIG (4) +#define DMA_I2C1_TX_TRIG (5) +#define DMA_I2C1_RX_TRIG (6) +#define DMA_SPI0_RX_TRIG (7) +#define DMA_SPI0_TX_TRIG (8) +#define DMA_UART0_RX_TRIG (9) +#define DMA_UART0_TX_TRIG (10) +#define DMA_UART1_RX_TRIG (11) +#define DMA_UART1_TX_TRIG (12) +#define DMA_UART2_RX_TRIG (13) +#define DMA_UART2_TX_TRIG (14) +#define DMA_ADC0_EVT_GEN_BD_TRIG (15) + +/* Internal DMA Triggers */ +#define DMA_CH_0_TRIG (0) +#define DMA_CH_1_TRIG (1) +#define DMA_CH_2_TRIG (2) + + +/****************************************************************************** +* IOMUX Pin Definitions * +******************************************************************************/ + +typedef enum IOMUX_PINCM +{ + IOMUX_PINCM1 = (0), + IOMUX_PINCM2 = (1), + IOMUX_PINCM3 = (2), + IOMUX_PINCM4 = (3), + IOMUX_PINCM5 = (4), + IOMUX_PINCM6 = (5), + IOMUX_PINCM7 = (6), + IOMUX_PINCM8 = (7), + IOMUX_PINCM9 = (8), + IOMUX_PINCM10 = (9), + IOMUX_PINCM11 = (10), + IOMUX_PINCM12 = (11), + IOMUX_PINCM13 = (12), + IOMUX_PINCM14 = (13), + IOMUX_PINCM15 = (14), + IOMUX_PINCM16 = (15), + IOMUX_PINCM17 = (16), + IOMUX_PINCM18 = (17), + IOMUX_PINCM19 = (18), + IOMUX_PINCM20 = (19), + IOMUX_PINCM21 = (20), + IOMUX_PINCM22 = (21), + IOMUX_PINCM23 = (22), + IOMUX_PINCM24 = (23), + IOMUX_PINCM25 = (24), + IOMUX_PINCM26 = (25), + IOMUX_PINCM27 = (26), + IOMUX_PINCM28 = (27), + IOMUX_PINCM29 = (28), + IOMUX_PINCM30 = (29), + IOMUX_PINCM31 = (30), + IOMUX_PINCM32 = (31), + IOMUX_PINCM33 = (32), + IOMUX_PINCM34 = (33), + IOMUX_PINCM35 = (34), + IOMUX_PINCM36 = (35), + IOMUX_PINCM37 = (36), + IOMUX_PINCM38 = (37), + IOMUX_PINCM39 = (38), + IOMUX_PINCM40 = (39), + IOMUX_PINCM41 = (40), + IOMUX_PINCM42 = (41), + IOMUX_PINCM43 = (42), + IOMUX_PINCM44 = (43), + IOMUX_PINCM45 = (44), + IOMUX_PINCM46 = (45), +} IOMUX_PINCM; + + +/* IOMUX_PINCM1[PF] Bits */ +#define IOMUX_PINCM1_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM1_PF_GPIOA_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM1_PF_UART0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_I2C0_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM1_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM1_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM1_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM1_PF_TIMG8_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM1_PF_SYSCTL_BEEPER ((uint32_t)0X00000008) +#define IOMUX_PINCM1_PF_TIMG14_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM1_PF_SPI0_CS1_POCI1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM1_PF_LFSS_RTC_OUT ((uint32_t)0X0000000C) + +/* IOMUX_PINCM2[PF] Bits */ +#define IOMUX_PINCM2_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM2_PF_GPIOA_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM2_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_I2C0_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM2_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM2_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM2_PF_TIMG8_IDX ((uint32_t)0X00000006) +#define IOMUX_PINCM2_PF_TIMG8_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM2_PF_TIMG14_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM2_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X0000000A) +#define IOMUX_PINCM2_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000B) +#define IOMUX_PINCM2_PF_UART0_TX ((uint32_t)0X0000000C) +#define IOMUX_PINCM2_PF_UART1_RTS ((uint32_t)0X0000000D) +#define IOMUX_PINCM2_PF_I2C0_SDA ((uint32_t)0X0000000E) + +/* IOMUX_PINCM3[PF] Bits */ +#define IOMUX_PINCM3_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM3_PF_GPIOA_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM3_PF_UART0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_I2C0_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM3_PF_TIMA0_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM3_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM3_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM3_PF_TIMA0_CCP1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM4[PF] Bits */ +#define IOMUX_PINCM4_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM4_PF_GPIOA_DIO31 ((uint32_t)0X00000001) +#define IOMUX_PINCM4_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_I2C0_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM4_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM4_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) + +/* IOMUX_PINCM5[PF] Bits */ +#define IOMUX_PINCM5_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM5_PF_GPIOA_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM5_PF_TIMG8_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_SPI0_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM5_PF_TIMG2_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM5_PF_TIMG8_IDX ((uint32_t)0X00000005) +#define IOMUX_PINCM5_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM5_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM5_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM5_PF_TIMA_FAULT1 ((uint32_t)0X00000009) +#define IOMUX_PINCM5_PF_TIMA0_CCP0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM5_PF_I2C0_SCL ((uint32_t)0X0000000C) + +/* IOMUX_PINCM6[PF] Bits */ +#define IOMUX_PINCM6_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM6_PF_GPIOA_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM6_PF_TIMG8_CCP0 ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM6_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM6_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM6_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM6_PF_TIMA0_CCP2 ((uint32_t)0X00000008) +#define IOMUX_PINCM6_PF_UART2_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM6_PF_UART1_TX ((uint32_t)0X0000000A) +#define IOMUX_PINCM6_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X0000000B) +#define IOMUX_PINCM6_PF_I2C0_SDA ((uint32_t)0X0000000C) +#define IOMUX_PINCM6_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM7[PF] Bits */ +#define IOMUX_PINCM7_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM7_PF_GPIOA_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM7_PF_TIMG8_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM7_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM7_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM7_PF_SYSCTL_LFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM7_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM7_PF_TIMA0_CCP3 ((uint32_t)0X00000008) +#define IOMUX_PINCM7_PF_UART2_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM7_PF_UART1_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM7_PF_SPI0_CS0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM7_PF_TIMA0_CCP0_CMPL ((uint32_t)0X0000000C) +#define IOMUX_PINCM7_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000D) + +/* IOMUX_PINCM8[PF] Bits */ +#define IOMUX_PINCM8_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM8_PF_GPIOA_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM8_PF_TIMG8_CCP0 ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM8_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM8_PF_TIMG14_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM8_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM8_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM8_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM8_PF_UART0_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM8_PF_UART1_TX ((uint32_t)0X0000000B) +#define IOMUX_PINCM8_PF_TIMA0_CCP1 ((uint32_t)0X0000000C) + +/* IOMUX_PINCM9[PF] Bits */ +#define IOMUX_PINCM9_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM9_PF_GPIOA_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM9_PF_TIMG8_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM9_PF_TIMG14_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM9_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM9_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM9_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM9_PF_UART0_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM9_PF_TIMA0_CCP2_CMPL ((uint32_t)0X0000000A) +#define IOMUX_PINCM9_PF_UART1_RX ((uint32_t)0X0000000B) +#define IOMUX_PINCM9_PF_TIMA0_CCP2 ((uint32_t)0X0000000C) +#define IOMUX_PINCM9_PF_I2C0_SDA ((uint32_t)0X0000000D) +#define IOMUX_PINCM9_PF_SYSCTL_BEEPER ((uint32_t)0X0000000E) + +/* IOMUX_PINCM10[PF] Bits */ +#define IOMUX_PINCM10_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM10_PF_GPIOA_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM10_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_TIMG8_CCP0 ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_TIMA0_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM10_PF_TIMG8_IDX ((uint32_t)0X00000005) +#define IOMUX_PINCM10_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM10_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM10_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000008) +#define IOMUX_PINCM10_PF_SYSCTL_FCC_IN ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_SPI0_POCI ((uint32_t)0X0000000A) +#define IOMUX_PINCM10_PF_SPI0_PICO ((uint32_t)0X0000000B) +#define IOMUX_PINCM10_PF_UART1_TX ((uint32_t)0X0000000C) +#define IOMUX_PINCM10_PF_TIMG1_CCP0 ((uint32_t)0X0000000D) +#define IOMUX_PINCM10_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM11[PF] Bits */ +#define IOMUX_PINCM11_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM11_PF_GPIOB_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM11_PF_UART2_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM11_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM11_PF_UART1_CTS ((uint32_t)0X00000006) +#define IOMUX_PINCM11_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM11_PF_UART2_TX ((uint32_t)0X00000008) +#define IOMUX_PINCM11_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM11_PF_SPI0_PICO ((uint32_t)0X0000000B) +#define IOMUX_PINCM11_PF_UART1_RX ((uint32_t)0X0000000C) +#define IOMUX_PINCM11_PF_TIMA0_CCP1_CMPL ((uint32_t)0X0000000D) + +/* IOMUX_PINCM12[PF] Bits */ +#define IOMUX_PINCM12_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM12_PF_GPIOB_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM12_PF_TIMA_FAULT0 ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UART2_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM12_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM12_PF_UART1_RTS ((uint32_t)0X00000006) +#define IOMUX_PINCM12_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM12_PF_UART2_RX ((uint32_t)0X00000008) +#define IOMUX_PINCM12_PF_TIMG2_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM12_PF_TIMA0_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM12_PF_SPI0_SCLK ((uint32_t)0X0000000B) +#define IOMUX_PINCM12_PF_SPI0_CS0 ((uint32_t)0X0000000C) +#define IOMUX_PINCM12_PF_UART1_TX ((uint32_t)0X0000000D) +#define IOMUX_PINCM12_PF_LFSS_RTC_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM13[PF] Bits */ +#define IOMUX_PINCM13_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM13_PF_GPIOA_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM13_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_SPI0_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM13_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM13_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM13_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM13_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000008) +#define IOMUX_PINCM13_PF_TIMG2_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM13_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM13_PF_UART0_RTS ((uint32_t)0X0000000B) +#define IOMUX_PINCM13_PF_SPI0_SCLK ((uint32_t)0X0000000C) +#define IOMUX_PINCM13_PF_UART1_RX ((uint32_t)0X0000000D) +#define IOMUX_PINCM13_PF_TIMA0_CCP3_CMPL ((uint32_t)0X0000000E) + +/* IOMUX_PINCM14[PF] Bits */ +#define IOMUX_PINCM14_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM14_PF_GPIOA_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM14_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM14_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM14_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM14_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM14_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM14_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM14_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM14_PF_TIMG2_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM14_PF_SPI0_POCI ((uint32_t)0X0000000A) +#define IOMUX_PINCM14_PF_UART0_CTS ((uint32_t)0X0000000B) +#define IOMUX_PINCM14_PF_TIMA_FAULT1 ((uint32_t)0X0000000C) +#define IOMUX_PINCM14_PF_TIMG1_CCP1 ((uint32_t)0X0000000D) + +/* IOMUX_PINCM15[PF] Bits */ +#define IOMUX_PINCM15_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM15_PF_GPIOA_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM15_PF_UART0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM15_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM15_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM15_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM15_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM15_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM15_PF_I2C1_SDA ((uint32_t)0X00000008) +#define IOMUX_PINCM15_PF_TIMA_FAULT1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM15_PF_TIMG2_CCP1 ((uint32_t)0X0000000B) +#define IOMUX_PINCM15_PF_TIMA0_CCP1_CMPL ((uint32_t)0X0000000C) +#define IOMUX_PINCM15_PF_TIMG8_CCP1 ((uint32_t)0X0000000D) +#define IOMUX_PINCM15_PF_SPI0_PICO ((uint32_t)0X0000000E) + +/* IOMUX_PINCM16[PF] Bits */ +#define IOMUX_PINCM16_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM16_PF_GPIOA_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM16_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM16_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM16_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM16_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM16_PF_UART1_RX ((uint32_t)0X00000006) +#define IOMUX_PINCM16_PF_TIMG14_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM16_PF_I2C1_SCL ((uint32_t)0X00000008) +#define IOMUX_PINCM16_PF_TIMA_FAULT0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM16_PF_SPI0_CS0 ((uint32_t)0X0000000C) +#define IOMUX_PINCM16_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM17[PF] Bits */ +#define IOMUX_PINCM17_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM17_PF_GPIOB_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM17_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_TIMG8_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM17_PF_UART2_CTS ((uint32_t)0X00000006) +#define IOMUX_PINCM17_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM17_PF_TIMA_FAULT2 ((uint32_t)0X00000008) +#define IOMUX_PINCM17_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000009) +#define IOMUX_PINCM17_PF_TIMA0_CCP3_CMPL ((uint32_t)0X0000000B) +#define IOMUX_PINCM17_PF_TIMG8_CCP1 ((uint32_t)0X0000000C) +#define IOMUX_PINCM17_PF_TIMA0_CCP2_CMPL ((uint32_t)0X0000000D) +#define IOMUX_PINCM17_PF_UART0_TX ((uint32_t)0X0000000E) + +/* IOMUX_PINCM18[PF] Bits */ +#define IOMUX_PINCM18_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM18_PF_GPIOB_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM18_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_TIMG8_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM18_PF_UART2_RTS ((uint32_t)0X00000006) +#define IOMUX_PINCM18_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM18_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000009) +#define IOMUX_PINCM18_PF_SYSCTL_BEEPER ((uint32_t)0X0000000C) +#define IOMUX_PINCM18_PF_SPI0_SCLK ((uint32_t)0X0000000D) +#define IOMUX_PINCM18_PF_UART0_RX ((uint32_t)0X0000000E) + +/* IOMUX_PINCM19[PF] Bits */ +#define IOMUX_PINCM19_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM19_PF_GPIOB_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM19_PF_UART1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_TIMA0_CCP0 ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_TIMG1_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM19_PF_SPI0_SCLK ((uint32_t)0X00000007) +#define IOMUX_PINCM19_PF_SYSCTL_BEEPER ((uint32_t)0X00000008) +#define IOMUX_PINCM19_PF_TIMG8_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM19_PF_UART0_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM19_PF_SPI0_POCI ((uint32_t)0X0000000B) +#define IOMUX_PINCM19_PF_I2C0_SCL ((uint32_t)0X0000000C) +#define IOMUX_PINCM19_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM20[PF] Bits */ +#define IOMUX_PINCM20_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM20_PF_GPIOB_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM20_PF_UART1_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM20_PF_TIMA0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM20_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM20_PF_TIMG2_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM20_PF_SPI0_POCI ((uint32_t)0X0000000A) +#define IOMUX_PINCM20_PF_UART0_RX ((uint32_t)0X0000000B) +#define IOMUX_PINCM20_PF_I2C0_SCL ((uint32_t)0X0000000C) +#define IOMUX_PINCM20_PF_UART0_TX ((uint32_t)0X0000000D) +#define IOMUX_PINCM20_PF_I2C0_SDA ((uint32_t)0X0000000E) + +/* IOMUX_PINCM21[PF] Bits */ +#define IOMUX_PINCM21_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM21_PF_GPIOB_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM21_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM21_PF_TIMG8_IDX ((uint32_t)0X00000006) +#define IOMUX_PINCM21_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000007) +#define IOMUX_PINCM21_PF_TIMG2_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM21_PF_I2C0_SDA ((uint32_t)0X00000009) +#define IOMUX_PINCM21_PF_SPI0_PICO ((uint32_t)0X0000000A) +#define IOMUX_PINCM21_PF_UART0_TX ((uint32_t)0X0000000B) +#define IOMUX_PINCM21_PF_TIMA_FAULT2 ((uint32_t)0X0000000C) +#define IOMUX_PINCM21_PF_TIMA_FAULT0 ((uint32_t)0X0000000D) +#define IOMUX_PINCM21_PF_TIMG14_CCP2 ((uint32_t)0X0000000E) + +/* IOMUX_PINCM22[PF] Bits */ +#define IOMUX_PINCM22_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM22_PF_GPIOB_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM22_PF_UART2_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_TIMG8_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM22_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM22_PF_TIMA0_CCP1_CMPL ((uint32_t)0X0000000C) +#define IOMUX_PINCM22_PF_UART1_TX ((uint32_t)0X0000000D) +#define IOMUX_PINCM22_PF_TIMG2_CCP1 ((uint32_t)0X0000000E) + +/* IOMUX_PINCM23[PF] Bits */ +#define IOMUX_PINCM23_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM23_PF_GPIOB_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM23_PF_UART2_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_TIMG8_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM23_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM23_PF_TIMA0_CCP2_CMPL ((uint32_t)0X0000000C) +#define IOMUX_PINCM23_PF_UART1_RX ((uint32_t)0X0000000D) +#define IOMUX_PINCM23_PF_I2C1_SDA ((uint32_t)0X0000000E) + +/* IOMUX_PINCM24[PF] Bits */ +#define IOMUX_PINCM24_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM24_PF_GPIOA_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM24_PF_SPI0_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_TIMA0_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM24_PF_SYSCTL_FCC_IN ((uint32_t)0X00000005) +#define IOMUX_PINCM24_PF_TIMG14_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM24_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000008) +#define IOMUX_PINCM24_PF_UART2_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM24_PF_UART1_CTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM24_PF_TIMA0_CCP3_CMPL ((uint32_t)0X0000000B) +#define IOMUX_PINCM24_PF_I2C1_SCL ((uint32_t)0X0000000C) +#define IOMUX_PINCM24_PF_TIMG2_CCP1 ((uint32_t)0X0000000D) +#define IOMUX_PINCM24_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM25[PF] Bits */ +#define IOMUX_PINCM25_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM25_PF_GPIOA_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM25_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM25_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM25_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM25_PF_LFSS_RTC_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM25_PF_TIMG14_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM25_PF_TIMG14_CCP3 ((uint32_t)0X00000008) +#define IOMUX_PINCM25_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000009) +#define IOMUX_PINCM25_PF_UART2_TX ((uint32_t)0X0000000A) +#define IOMUX_PINCM25_PF_UART1_RTS ((uint32_t)0X0000000B) +#define IOMUX_PINCM25_PF_SPI0_CS0 ((uint32_t)0X0000000C) +#define IOMUX_PINCM25_PF_TIMG8_CCP1 ((uint32_t)0X0000000D) +#define IOMUX_PINCM25_PF_TIMA0_CCP1 ((uint32_t)0X0000000E) + +/* IOMUX_PINCM26[PF] Bits */ +#define IOMUX_PINCM26_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM26_PF_GPIOA_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM26_PF_UART0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM26_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_TIMG1_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM26_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM26_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000009) +#define IOMUX_PINCM26_PF_UART2_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM26_PF_I2C0_SCL ((uint32_t)0X0000000C) +#define IOMUX_PINCM26_PF_UART0_TX ((uint32_t)0X0000000D) +#define IOMUX_PINCM26_PF_TIMA0_CCP2 ((uint32_t)0X0000000E) + +/* IOMUX_PINCM27[PF] Bits */ +#define IOMUX_PINCM27_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM27_PF_GPIOA_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM27_PF_UART0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM27_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM27_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM27_PF_TIMG8_IDX ((uint32_t)0X00000007) +#define IOMUX_PINCM27_PF_UART2_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM27_PF_TIMG14_CCP1 ((uint32_t)0X0000000C) + +/* IOMUX_PINCM28[PF] Bits */ +#define IOMUX_PINCM28_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM28_PF_GPIOA_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM28_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM28_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM28_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM28_PF_SYSCTL_FCC_IN ((uint32_t)0X00000007) +#define IOMUX_PINCM28_PF_UART2_CTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM28_PF_TIMG14_CCP2 ((uint32_t)0X0000000C) +#define IOMUX_PINCM28_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM29[PF] Bits */ +#define IOMUX_PINCM29_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM29_PF_GPIOA_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM29_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM29_PF_TIMA0_CCP2 ((uint32_t)0X00000003) +#define IOMUX_PINCM29_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM29_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM29_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM29_PF_TIMG8_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM29_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000008) +#define IOMUX_PINCM29_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000009) +#define IOMUX_PINCM29_PF_SPI0_SCLK ((uint32_t)0X0000000A) +#define IOMUX_PINCM29_PF_I2C0_SDA ((uint32_t)0X0000000B) +#define IOMUX_PINCM29_PF_UART0_RX ((uint32_t)0X0000000C) + +/* IOMUX_PINCM30[PF] Bits */ +#define IOMUX_PINCM30_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM30_PF_GPIOA_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM30_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM30_PF_UART1_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM30_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM30_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM30_PF_TIMG8_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM30_PF_SPI0_PICO ((uint32_t)0X00000008) +#define IOMUX_PINCM30_PF_SPI0_CS0 ((uint32_t)0X00000009) +#define IOMUX_PINCM30_PF_TIMA0_CCP1_CMPL ((uint32_t)0X0000000A) +#define IOMUX_PINCM30_PF_TIMA0_CCP0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM30_PF_SPI0_POCI ((uint32_t)0X0000000C) +#define IOMUX_PINCM30_PF_TIMA_FAULT2 ((uint32_t)0X0000000D) +#define IOMUX_PINCM30_PF_SYSCTL_CLK_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM31[PF] Bits */ +#define IOMUX_PINCM31_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM31_PF_GPIOA_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM31_PF_UART0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_SPI0_PICO ((uint32_t)0X00000003) + +/* IOMUX_PINCM32[PF] Bits */ +#define IOMUX_PINCM32_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM32_PF_GPIOA_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM32_PF_DEBUGSS_SWDIO ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM32_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM32_PF_TIMG14_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM32_PF_SPI0_POCI ((uint32_t)0X00000007) +#define IOMUX_PINCM32_PF_UART0_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM32_PF_UART1_RX ((uint32_t)0X0000000B) +#define IOMUX_PINCM32_PF_SPI0_PICO ((uint32_t)0X0000000D) + +/* IOMUX_PINCM33[PF] Bits */ +#define IOMUX_PINCM33_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM33_PF_GPIOA_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM33_PF_DEBUGSS_SWCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_TIMA_FAULT1 ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM33_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM33_PF_TIMG14_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM33_PF_SPI0_PICO ((uint32_t)0X00000007) +#define IOMUX_PINCM33_PF_TIMA0_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM33_PF_UART0_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM33_PF_UART1_TX ((uint32_t)0X0000000B) +#define IOMUX_PINCM33_PF_SPI0_CS0 ((uint32_t)0X0000000C) +#define IOMUX_PINCM33_PF_UART1_RX ((uint32_t)0X0000000D) + +/* IOMUX_PINCM34[PF] Bits */ +#define IOMUX_PINCM34_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM34_PF_GPIOB_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM34_PF_UART2_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM34_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM34_PF_TIMG14_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM34_PF_TIMG1_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM34_PF_SPI0_CS0 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM35[PF] Bits */ +#define IOMUX_PINCM35_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM35_PF_GPIOB_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM35_PF_UART2_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM35_PF_TIMG14_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM35_PF_SPI0_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM35_PF_TIMG1_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM35_PF_TIMA0_CCP1 ((uint32_t)0X0000000C) +#define IOMUX_PINCM35_PF_UART0_RTS ((uint32_t)0X0000000D) + +/* IOMUX_PINCM36[PF] Bits */ +#define IOMUX_PINCM36_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM36_PF_GPIOB_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM36_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_TIMG8_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM36_PF_UART0_CTS ((uint32_t)0X00000005) +#define IOMUX_PINCM36_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM36_PF_TIMG8_IDX ((uint32_t)0X00000007) +#define IOMUX_PINCM36_PF_UART2_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM36_PF_TIMA0_CCP1_CMPL ((uint32_t)0X0000000C) +#define IOMUX_PINCM36_PF_UART2_RX ((uint32_t)0X0000000D) +#define IOMUX_PINCM36_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM37[PF] Bits */ +#define IOMUX_PINCM37_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM37_PF_GPIOA_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM37_PF_UART2_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM37_PF_UART1_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM37_PF_TIMG1_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM37_PF_UART2_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM37_PF_TIMG8_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM37_PF_TIMA0_CCP0_CMPL ((uint32_t)0X0000000C) +#define IOMUX_PINCM37_PF_UART2_RX ((uint32_t)0X0000000D) + +/* IOMUX_PINCM38[PF] Bits */ +#define IOMUX_PINCM38_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM38_PF_GPIOA_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM38_PF_UART2_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM38_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_UART1_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM38_PF_TIMG1_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM38_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM38_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM38_PF_I2C0_SCL ((uint32_t)0X00000009) +#define IOMUX_PINCM38_PF_TIMG8_CCP1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM38_PF_UART1_RX ((uint32_t)0X0000000B) +#define IOMUX_PINCM38_PF_SPI0_POCI ((uint32_t)0X0000000C) +#define IOMUX_PINCM38_PF_UART2_TX ((uint32_t)0X0000000D) + +/* IOMUX_PINCM39[PF] Bits */ +#define IOMUX_PINCM39_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM39_PF_GPIOB_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM39_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM39_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM39_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM39_PF_UART2_RTS ((uint32_t)0X00000008) +#define IOMUX_PINCM39_PF_I2C0_SDA ((uint32_t)0X00000009) +#define IOMUX_PINCM39_PF_UART1_CTS ((uint32_t)0X0000000C) +#define IOMUX_PINCM39_PF_TIMA0_CCP2_CMPL ((uint32_t)0X0000000D) +#define IOMUX_PINCM39_PF_TIMG8_CCP1 ((uint32_t)0X0000000E) + +/* IOMUX_PINCM40[PF] Bits */ +#define IOMUX_PINCM40_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM40_PF_GPIOB_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM40_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM40_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM40_PF_UART2_RTS ((uint32_t)0X00000008) +#define IOMUX_PINCM40_PF_SPI0_SCLK ((uint32_t)0X0000000C) +#define IOMUX_PINCM40_PF_TIMG14_CCP2 ((uint32_t)0X0000000D) +#define IOMUX_PINCM40_PF_UART0_RTS ((uint32_t)0X0000000E) + +/* IOMUX_PINCM41[PF] Bits */ +#define IOMUX_PINCM41_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM41_PF_GPIOA_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM41_PF_UART2_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM41_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM41_PF_TIMG8_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM41_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM41_PF_UART0_TX ((uint32_t)0X00000008) +#define IOMUX_PINCM41_PF_TIMG14_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM41_PF_SPI0_POCI ((uint32_t)0X0000000C) +#define IOMUX_PINCM41_PF_UART0_CTS ((uint32_t)0X0000000D) + +/* IOMUX_PINCM42[PF] Bits */ +#define IOMUX_PINCM42_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM42_PF_GPIOA_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM42_PF_UART2_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM42_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UART0_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM42_PF_TIMG8_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM42_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM42_PF_UART1_RX ((uint32_t)0X00000008) +#define IOMUX_PINCM42_PF_TIMG14_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM42_PF_SPI0_PICO ((uint32_t)0X0000000C) +#define IOMUX_PINCM42_PF_I2C0_SDA ((uint32_t)0X0000000D) + +/* IOMUX_PINCM43[PF] Bits */ +#define IOMUX_PINCM43_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM43_PF_GPIOA_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM43_PF_SPI0_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_SPI0_SCLK ((uint32_t)0X00000004) +#define IOMUX_PINCM43_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM43_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM43_PF_TIMA0_CCP2 ((uint32_t)0X00000007) +#define IOMUX_PINCM43_PF_UART2_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM43_PF_TIMG14_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM43_PF_TIMG1_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM43_PF_I2C0_SDA ((uint32_t)0X0000000B) +#define IOMUX_PINCM43_PF_UART0_TX ((uint32_t)0X0000000C) +#define IOMUX_PINCM43_PF_TIMA_FAULT2 ((uint32_t)0X0000000D) +#define IOMUX_PINCM43_PF_I2C0_SCL ((uint32_t)0X0000000E) + +/* IOMUX_PINCM44[PF] Bits */ +#define IOMUX_PINCM44_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM44_PF_GPIOA_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM44_PF_SYSCTL_BEEPER ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_TIMG8_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM44_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM44_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM44_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM44_PF_UART2_RTS ((uint32_t)0X00000008) +#define IOMUX_PINCM44_PF_I2C0_SCL ((uint32_t)0X00000009) +#define IOMUX_PINCM44_PF_TIMG1_CCP1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM44_PF_UART0_RX ((uint32_t)0X0000000B) +#define IOMUX_PINCM44_PF_TIMA0_CCP0 ((uint32_t)0X0000000C) +#define IOMUX_PINCM44_PF_I2C0_SDA ((uint32_t)0X0000000D) +#define IOMUX_PINCM44_PF_UART1_CTS ((uint32_t)0X0000000E) + +/* IOMUX_PINCM45[PF] Bits */ +#define IOMUX_PINCM45_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM45_PF_GPIOA_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM45_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000002) +#define IOMUX_PINCM45_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_TIMG8_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM45_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM45_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM45_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM45_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM45_PF_UART1_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM45_PF_I2C0_SCL ((uint32_t)0X0000000A) +#define IOMUX_PINCM45_PF_UART0_TX ((uint32_t)0X0000000B) +#define IOMUX_PINCM45_PF_SPI0_POCI ((uint32_t)0X0000000C) +#define IOMUX_PINCM45_PF_COMP0_OUT ((uint32_t)0X0000000E) + +/* IOMUX_PINCM46[PF] Bits */ +#define IOMUX_PINCM46_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM46_PF_GPIOA_DIO30 ((uint32_t)0X00000001) +#define IOMUX_PINCM46_PF_UART0_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM46_PF_TIMG8_IDX ((uint32_t)0X00000005) +#define IOMUX_PINCM46_PF_TIMA0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM46_PF_UART1_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM46_PF_TIMG2_CCP1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM46_PF_TIMG14_CCP2 ((uint32_t)0X0000000B) +#define IOMUX_PINCM46_PF_I2C0_SDA ((uint32_t)0X0000000C) + + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*@}*/ /* end of group MSPM0C1105_C1106_PeripheralDecl */ + +/*@}*/ /* end of group MSPM0C1105_C1106_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_m0p_mspm0c1105_C1106__include */ + diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g110x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g110x.h index 93dd082..c1eb0eb 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0g110x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g110x.h @@ -311,6 +311,7 @@ static DEBUGSS_Regs * const DEBUGSS #define FLASHCTL_SYS_WEPROTAWIDTH (32) /* !< Bit width of WEPROTA register */ #define FLASHCTL_SYS_WEPROTBWIDTH (12) /* !< Bit width of WEPROTB register */ #define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ +#define GPAMP_SYS_ADC_CHOPPING (1) /* !< GPAMP supports ADC assited chopping */ /****************************************************************************** * DMA Triggers * diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g150x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g150x.h index 46a3e43..f10c040 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0g150x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g150x.h @@ -356,6 +356,7 @@ static DEBUGSS_Regs * const DEBUGSS #define FLASHCTL_SYS_WEPROTAWIDTH (32) /* !< Bit width of WEPROTA register */ #define FLASHCTL_SYS_WEPROTBWIDTH (12) /* !< Bit width of WEPROTB register */ #define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ +#define GPAMP_SYS_ADC_CHOPPING (1) /* !< GPAMP supports ADC assited chopping */ /****************************************************************************** * DMA Triggers * diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g151x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g151x.h index 477a20e..466ff93 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0g151x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g151x.h @@ -104,6 +104,7 @@ typedef enum IRQn AESADV_INT_IRQn = 28, /* 44 AESADV_INT Interrupt */ UART6_INT_IRQn = 29, /* 45 UART6_INT Interrupt */ LFSS_INT_IRQn = 30, /* 46 LFSS_INT Interrupt */ + RTC_B_INT_IRQn = 30, /* 46 RTC_B_INT Interrupt */ DMA_INT_IRQn = 31, /* 47 DMA_INT Interrupt */ } IRQn_Type; @@ -151,6 +152,7 @@ typedef enum IRQn #define AESADV_INT_VECn 44 /* AESADV_INT Interrupt */ #define UART6_INT_VECn 45 /* UART6_INT Interrupt */ #define LFSS_INT_VECn 46 /* LFSS_INT Interrupt */ +#define RTC_B_INT_VECn 46 /* RTC_B_INT Interrupt */ #define DMA_INT_VECn 47 /* DMA_INT Interrupt */ @@ -214,6 +216,7 @@ typedef enum IRQn #include #include #include +#include #include #include #include @@ -237,6 +240,7 @@ typedef enum IRQn #define __MSPM0_HAS_KEYSTORE_CTL__ #define __MSPM0_HAS_MATHACL__ #define __MSPM0_HAS_LFSS__ +#define __MSPM0_HAS_RTC_B__ #define __MSPM0_HAS_SPI__ #define __MSPM0_HAS_TRNG__ #define __MSPM0_HAS_UART_EXTD__ @@ -308,6 +312,7 @@ typedef enum IRQn #define UART6_BASE (0x40506000U) /*!< Base address of module UART6 */ #define FLASHCTL_BASE (0x400CD000U) /*!< Base address of module FLASHCTL */ #define LFSS_BASE (0x40094000U) /*!< Base address of module LFSS */ +#define RTC_B_BASE (0x40094000U) /*!< Base address of module RTC_B */ #define I2C1_BASE (0x400F2000U) /*!< Base address of module I2C1 */ #define I2C2_BASE (0x400F4000U) /*!< Base address of module I2C2 */ #define FACTORYREGION_BASE (0x41C40000U) /*!< Base address of module FACTORYREGION */ @@ -370,6 +375,7 @@ static UART_Regs * const UART5 static UART_Regs * const UART6 = ((UART_Regs *) UART6_BASE); static FLASHCTL_Regs * const FLASHCTL = ((FLASHCTL_Regs *) FLASHCTL_BASE); static LFSS_Regs * const LFSS = ((LFSS_Regs *) LFSS_BASE); +static RTC_Regs * const RTC_B = ((RTC_Regs *) RTC_B_BASE); static I2C_Regs * const I2C1 = ((I2C_Regs *) I2C1_BASE); static I2C_Regs * const I2C2 = ((I2C_Regs *) I2C2_BASE); static FACTORYREGION_OPEN_Regs * const FACTORYREGION = ((FACTORYREGION_OPEN_Regs *) FACTORYREGION_BASE); @@ -385,7 +391,7 @@ static FACTORYREGION_OPEN_Regs * const FACTORYREGION #define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ #define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ #define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ -#define FLASHCTL_SYS_DATAWIDTH (128) /* !< Data bit width of a single flash word. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word. */ #define ADC_SYS_NUM_ANALOG_CHAN (16) /* !< Number of analog channels. */ #define I2C_SYS_FENTRIES (8) /* !< Number of FIFO entries */ #define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register */ diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g310x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g310x.h index 0ab27f3..33a1723 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0g310x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g310x.h @@ -330,6 +330,7 @@ static DEBUGSS_Regs * const DEBUGSS #define FLASHCTL_SYS_WEPROTAWIDTH (32) /* !< Bit width of WEPROTA register */ #define FLASHCTL_SYS_WEPROTBWIDTH (12) /* !< Bit width of WEPROTB register */ #define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ +#define GPAMP_SYS_ADC_CHOPPING (1) /* !< GPAMP supports ADC assited chopping */ /****************************************************************************** * DMA Triggers * diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g350x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g350x.h index 0e9d246..b2e1e8f 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0g350x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g350x.h @@ -368,6 +368,7 @@ static DEBUGSS_Regs * const DEBUGSS #define FLASHCTL_SYS_WEPROTAWIDTH (32) /* !< Bit width of WEPROTA register */ #define FLASHCTL_SYS_WEPROTBWIDTH (12) /* !< Bit width of WEPROTB register */ #define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ +#define GPAMP_SYS_ADC_CHOPPING (1) /* !< GPAMP supports ADC assited chopping */ /****************************************************************************** * DMA Triggers * diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g351x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g351x.h index b54838c..120ac66 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0g351x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g351x.h @@ -404,7 +404,7 @@ static FACTORYREGION_OPEN_Regs * const FACTORYREGION #define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ #define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ #define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ -#define FLASHCTL_SYS_DATAWIDTH (128) /* !< Data bit width of a single flash word. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word. */ #define ADC_SYS_NUM_ANALOG_CHAN (16) /* !< Number of analog channels. */ #define I2C_SYS_FENTRIES (8) /* !< Number of FIFO entries */ #define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register */ diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g352x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g352x.h new file mode 100644 index 0000000..a63200f --- /dev/null +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g352x.h @@ -0,0 +1,1600 @@ +/***************************************************************************** + + Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_m0p_mspm0g352x__include +#define ti_devices_msp_m0p_mspm0g352x__include + +/* Filename: mspm0g352x.h */ +/* Revised: 2024-05-27 03:28:21*/ + +/* Use standard integer types with explicit width */ +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup MSPM0G352X_Definitions MSPM0G352X Definitions + This file defines all structures and symbols for MSPM0G352X + @{ +*/ + +/** @addtogroup MSPM0G352X_CMSIS Device CMSIS Definitions + Configuration of the Processor and Core Peripherals + @{ +*/ +/****************************************************************************** +* Interrupt Definitions * +******************************************************************************/ +typedef enum IRQn +{ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + WWDT0_INT_IRQn = 0, /* 16 WWDT0_INT Interrupt */ + DEBUGSS_INT_IRQn = 0, /* 16 DEBUGSS_INT Interrupt */ + WWDT1_INT_IRQn = 0, /* 16 WWDT1_INT Interrupt */ + SYSCTL_INT_IRQn = 0, /* 16 SYSCTL_INT Interrupt */ + FLASHCTL_INT_IRQn = 0, /* 16 FLASHCTL_INT Interrupt */ + COMP2_INT_IRQn = 1, /* 17 COMP2_INT Interrupt */ + GPIOA_INT_IRQn = 1, /* 17 GPIOA_INT Interrupt */ + GPIOB_INT_IRQn = 1, /* 17 GPIOB_INT Interrupt */ + COMP1_INT_IRQn = 1, /* 17 COMP1_INT Interrupt */ + COMP0_INT_IRQn = 1, /* 17 COMP0_INT Interrupt */ + TRNG_INT_IRQn = 1, /* 17 TRNG_INT Interrupt */ + GPIOC_INT_IRQn = 1, /* 17 GPIOC_INT Interrupt */ + TIMG8_INT_IRQn = 2, /* 18 TIMG8_INT Interrupt */ + UART3_INT_IRQn = 3, /* 19 UART3_INT Interrupt */ + ADC0_INT_IRQn = 4, /* 20 ADC0_INT Interrupt */ + ADC1_INT_IRQn = 5, /* 21 ADC1_INT Interrupt */ + CANFD0_INT_IRQn = 6, /* 22 CANFD0_INT Interrupt */ + DAC0_INT_IRQn = 7, /* 23 DAC0_INT Interrupt */ + TIMG9_INT_IRQn = 8, /* 24 TIMG9_INT Interrupt */ + SPI0_INT_IRQn = 9, /* 25 SPI0_INT Interrupt */ + SPI1_INT_IRQn = 10, /* 26 SPI1_INT Interrupt */ + SPI2_INT_IRQn = 11, /* 27 SPI2_INT Interrupt */ + CANFD1_INT_IRQn = 12, /* 28 CANFD1_INT Interrupt */ + UART1_INT_IRQn = 13, /* 29 UART1_INT Interrupt */ + UART4_INT_IRQn = 14, /* 30 UART4_INT Interrupt */ + UART0_INT_IRQn = 15, /* 31 UART0_INT Interrupt */ + TIMG0_INT_IRQn = 16, /* 32 TIMG0_INT Interrupt */ + TIMG6_INT_IRQn = 17, /* 33 TIMG6_INT Interrupt */ + TIMA0_INT_IRQn = 18, /* 34 TIMA0_INT Interrupt */ + TIMA1_INT_IRQn = 19, /* 35 TIMA1_INT Interrupt */ + TIMG7_INT_IRQn = 20, /* 36 TIMG7_INT Interrupt */ + TIMG12_INT_IRQn = 21, /* 37 TIMG12_INT Interrupt */ + TIMG14_INT_IRQn = 22, /* 38 TIMG14_INT Interrupt */ + UART5_INT_IRQn = 23, /* 39 UART5_INT Interrupt */ + I2C0_INT_IRQn = 24, /* 40 I2C0_INT Interrupt */ + I2C1_INT_IRQn = 25, /* 41 I2C1_INT Interrupt */ + I2C2_INT_IRQn = 26, /* 42 I2C2_INT Interrupt */ + UART7_INT_IRQn = 27, /* 43 UART7_INT Interrupt */ + AESADV_INT_IRQn = 28, /* 44 AESADV_INT Interrupt */ + UART6_INT_IRQn = 29, /* 45 UART6_INT Interrupt */ + LFSS_INT_IRQn = 30, /* 46 LFSS_INT Interrupt */ + RTC_B_INT_IRQn = 30, /* 46 RTC_B_INT Interrupt */ + DMA_INT_IRQn = 31, /* 47 DMA_INT Interrupt */ +} IRQn_Type; + +#define NonMaskableInt_VECn 2 /* Non Maskable Interrupt */ +#define HardFault_VECn 3 /* Hard Fault Interrupt */ +#define SVCall_VECn 11 /* SV Call Interrupt */ +#define PendSV_VECn 14 /* Pend SV Interrupt */ +#define SysTick_VECn 15 /* System Tick Interrupt */ +#define WWDT0_INT_VECn 16 /* WWDT0_INT Interrupt */ +#define DEBUGSS_INT_VECn 16 /* DEBUGSS_INT Interrupt */ +#define WWDT1_INT_VECn 16 /* WWDT1_INT Interrupt */ +#define SYSCTL_INT_VECn 16 /* SYSCTL_INT Interrupt */ +#define FLASHCTL_INT_VECn 16 /* FLASHCTL_INT Interrupt */ +#define COMP2_INT_VECn 17 /* COMP2_INT Interrupt */ +#define GPIOA_INT_VECn 17 /* GPIOA_INT Interrupt */ +#define GPIOB_INT_VECn 17 /* GPIOB_INT Interrupt */ +#define COMP1_INT_VECn 17 /* COMP1_INT Interrupt */ +#define COMP0_INT_VECn 17 /* COMP0_INT Interrupt */ +#define TRNG_INT_VECn 17 /* TRNG_INT Interrupt */ +#define GPIOC_INT_VECn 17 /* GPIOC_INT Interrupt */ +#define TIMG8_INT_VECn 18 /* TIMG8_INT Interrupt */ +#define UART3_INT_VECn 19 /* UART3_INT Interrupt */ +#define ADC0_INT_VECn 20 /* ADC0_INT Interrupt */ +#define ADC1_INT_VECn 21 /* ADC1_INT Interrupt */ +#define CANFD0_INT_VECn 22 /* CANFD0_INT Interrupt */ +#define DAC0_INT_VECn 23 /* DAC0_INT Interrupt */ +#define TIMG9_INT_VECn 24 /* TIMG9_INT Interrupt */ +#define SPI0_INT_VECn 25 /* SPI0_INT Interrupt */ +#define SPI1_INT_VECn 26 /* SPI1_INT Interrupt */ +#define SPI2_INT_VECn 27 /* SPI2_INT Interrupt */ +#define CANFD1_INT_VECn 28 /* CANFD1_INT Interrupt */ +#define UART1_INT_VECn 29 /* UART1_INT Interrupt */ +#define UART4_INT_VECn 30 /* UART4_INT Interrupt */ +#define UART0_INT_VECn 31 /* UART0_INT Interrupt */ +#define TIMG0_INT_VECn 32 /* TIMG0_INT Interrupt */ +#define TIMG6_INT_VECn 33 /* TIMG6_INT Interrupt */ +#define TIMA0_INT_VECn 34 /* TIMA0_INT Interrupt */ +#define TIMA1_INT_VECn 35 /* TIMA1_INT Interrupt */ +#define TIMG7_INT_VECn 36 /* TIMG7_INT Interrupt */ +#define TIMG12_INT_VECn 37 /* TIMG12_INT Interrupt */ +#define TIMG14_INT_VECn 38 /* TIMG14_INT Interrupt */ +#define UART5_INT_VECn 39 /* UART5_INT Interrupt */ +#define I2C0_INT_VECn 40 /* I2C0_INT Interrupt */ +#define I2C1_INT_VECn 41 /* I2C1_INT Interrupt */ +#define I2C2_INT_VECn 42 /* I2C2_INT Interrupt */ +#define UART7_INT_VECn 43 /* UART7_INT Interrupt */ +#define AESADV_INT_VECn 44 /* AESADV_INT Interrupt */ +#define UART6_INT_VECn 45 /* UART6_INT Interrupt */ +#define LFSS_INT_VECn 46 /* LFSS_INT Interrupt */ +#define RTC_B_INT_VECn 46 /* RTC_B_INT Interrupt */ +#define DMA_INT_VECn 47 /* DMA_INT Interrupt */ + + +/****************************************************************************** +* Ignore unused variables * +******************************************************************************/ + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/****************************************************************************** +* Processor and Core Peripheral Section * +******************************************************************************/ + +#define __CM0PLUS_REV 0x0001U /* Core revision r0p1 */ +#define __MPU_PRESENT 0x0001U /* MPU present */ +#define __VTOR_PRESENT 0x0001U /* VTOR present */ +#define __NVIC_PRIO_BITS 0x0002U /* Number of bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0plus.h" /* Processor and core peripherals */ + +/****************************************************************************** +* Peripheral headers * +******************************************************************************/ +/** @addtogroup MSPM0G352X_Peripherals MSPM0G352X Peripherals + MSPM0G352X Peripheral registers structures + @{ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __MSPM0_HAS_ADC12__ +#define __MSPM0_HAS_AESADV__ +#define __MSPM0_HAS_COMP__ +#define __MSPM0_HAS_CRCP__ +#define __MSPM0_HAS_DAC12__ +#define __MSPM0_HAS_GPIO__ +#define __MSPM0_HAS_TIMER_A__ +#define __MSPM0_HAS_TIMER_G__ +#define __MSPM0_HAS_I2C__ +#define __MSPM0_HAS_KEYSTORE_CTL__ +#define __MSPM0_HAS_MATHACL__ +#define __MSPM0_HAS_MCAN__ +#define __MSPM0_HAS_LFSS__ +#define __MSPM0_HAS_RTC_B__ +#define __MSPM0_HAS_SPI__ +#define __MSPM0_HAS_TRNG__ +#define __MSPM0_HAS_UART_EXTD__ +#define __MSPM0_HAS_UART_MAIN__ +#define __MSPM0_HAS_VREF__ +#define __MSPM0_HAS_WWDT__ +#define __MSPM0_HAS_IWDT__ +#define __MSPM0_HAS_ECC__ + +/*! @brief Workaround added for bug in sineCosine operation in MATHACL */ +#define _IQMATH_MATHACL_SINCOS_BUG_WORKAROUND_ + +/*! @brief Define for caching trim table values in SRAM*/ +#define __MSPM0GX51X_TRIM_CACHE__ + +/*@}*/ /* end of group MSPM0G352X_Peripherals */ + +/****************************************************************************** +* Device and peripheral memory map * +******************************************************************************/ +/** @addtogroup MSPM0G352X_MemoryMap MSPM0G352X Memory Mapping + @{ +*/ + +#define UART0_BASE (0x40108000U) /*!< Base address of module UART0 */ +#define TIMA0_BASE (0x40860000U) /*!< Base address of module TIMA0 */ +#define MATHACL_BASE (0x40410000U) /*!< Base address of module MATHACL */ +#define TIMG12_BASE (0x40870000U) /*!< Base address of module TIMG12 */ +#define SPI0_BASE (0x40468000U) /*!< Base address of module SPI0 */ +#define WUC_BASE (0x40424000U) /*!< Base address of module WUC */ +#define COMP2_BASE (0x4000C000U) /*!< Base address of module COMP2 */ +#define I2C0_BASE (0x400F0000U) /*!< Base address of module I2C0 */ +#define CPUSS_BASE (0x40400000U) /*!< Base address of module CPUSS */ +#define GPIOA_BASE (0x400A0000U) /*!< Base address of module GPIOA */ +#define GPIOB_BASE (0x400A2000U) /*!< Base address of module GPIOB */ +#define UART1_BASE (0x40100000U) /*!< Base address of module UART1 */ +#define WWDT0_BASE (0x40080000U) /*!< Base address of module WWDT0 */ +#define COMP1_BASE (0x4000A000U) /*!< Base address of module COMP1 */ +#define DAC0_BASE (0x40018000U) /*!< Base address of module DAC0 */ +#define VREF_BASE (0x40030000U) /*!< Base address of module VREF */ +#define TIMG7_BASE (0x4086A000U) /*!< Base address of module TIMG7 */ +#define TIMG6_BASE (0x40868000U) /*!< Base address of module TIMG6 */ +#define SPI1_BASE (0x4046A000U) /*!< Base address of module SPI1 */ +#define DMA_BASE (0x4042A000U) /*!< Base address of module DMA */ +#define COMP0_BASE (0x40008000U) /*!< Base address of module COMP0 */ +#define TRNG_BASE (0x40444000U) /*!< Base address of module TRNG */ +#define UART3_BASE (0x40500000U) /*!< Base address of module UART3 */ +#define TIMG0_BASE (0x40084000U) /*!< Base address of module TIMG0 */ +#define TIMA1_BASE (0x40862000U) /*!< Base address of module TIMA1 */ +#define IOMUX_BASE (0x40428000U) /*!< Base address of module IOMUX */ +#define DEBUGSS_BASE (0x400C7000U) /*!< Base address of module DEBUGSS */ +#define CANFD0_BASE (0x40508000U) /*!< Base address of module CANFD0 */ +#define CANFD0_SRAM_BASE (0x40508000U) /*!< Base address of memory CANFD0_SRAM */ +#define SPI2_BASE (0x4046C000U) /*!< Base address of module SPI2 */ +#define UART7_BASE (0x4010A000U) /*!< Base address of module UART7 */ +#define UART4_BASE (0x40502000U) /*!< Base address of module UART4 */ +#define GPIOC_BASE (0x400A4000U) /*!< Base address of module GPIOC */ +#define KEYSTORECTL_BASE (0x400AC000U) /*!< Base address of module KEYSTORECTL */ +#define WWDT1_BASE (0x40082000U) /*!< Base address of module WWDT1 */ +#define CANFD1_BASE (0x40510000U) /*!< Base address of module CANFD1 */ +#define CANFD1_SRAM_BASE (0x40510000U) /*!< Base address of memory CANFD1_SRAM */ +#define AESADV_BASE (0x40442000U) /*!< Base address of module AESADV */ +#define SYSCTL_BASE (0x400AF000U) /*!< Base address of module SYSCTL */ +#define ADC0_BASE (0x40000000U) /*!< Base address of module ADC0 */ +#define ADC0_PERIPHERALREGIONSVT_BASE (0x40556000U) /*!< Base address of module ADC0_PERIPHERALREGIONSVT */ +#define ADC1_BASE (0x40002000U) /*!< Base address of module ADC1 */ +#define ADC1_PERIPHERALREGIONSVT_BASE (0x40558000U) /*!< Base address of module ADC1_PERIPHERALREGIONSVT */ +#define CRCP0_BASE (0x40440000U) /*!< Base address of module CRCP0 */ +#define TIMG8_BASE (0x40090000U) /*!< Base address of module TIMG8 */ +#define TIMG9_BASE (0x40092000U) /*!< Base address of module TIMG9 */ +#define TIMG14_BASE (0x40096000U) /*!< Base address of module TIMG14 */ +#define UART5_BASE (0x40504000U) /*!< Base address of module UART5 */ +#define UART6_BASE (0x40506000U) /*!< Base address of module UART6 */ +#define FLASHCTL_BASE (0x400CD000U) /*!< Base address of module FLASHCTL */ +#define LFSS_BASE (0x40094000U) /*!< Base address of module LFSS */ +#define RTC_B_BASE (0x40094000U) /*!< Base address of module RTC_B */ +#define I2C1_BASE (0x400F2000U) /*!< Base address of module I2C1 */ +#define I2C2_BASE (0x400F4000U) /*!< Base address of module I2C2 */ +#define FACTORYREGION_BASE (0x41C40000U) /*!< Base address of module FACTORYREGION */ + + +/*@}*/ /* end of group MSPM0G352X_MemoryMap */ + +/****************************************************************************** +* Peripheral declarations * +******************************************************************************/ +/** @addtogroup MSPM0G352X_PeripheralDecl MSPM0G352X Peripheral Declaration + @{ +*/ + +static UART_Regs * const UART0 = ((UART_Regs *) UART0_BASE); +static GPTIMER_Regs * const TIMA0 = ((GPTIMER_Regs *) TIMA0_BASE); +static MATHACL_Regs * const MATHACL = ((MATHACL_Regs *) MATHACL_BASE); +static GPTIMER_Regs * const TIMG12 = ((GPTIMER_Regs *) TIMG12_BASE); +static SPI_Regs * const SPI0 = ((SPI_Regs *) SPI0_BASE); +static WUC_Regs * const WUC = ((WUC_Regs *) WUC_BASE); +static COMP_Regs * const COMP2 = ((COMP_Regs *) COMP2_BASE); +static I2C_Regs * const I2C0 = ((I2C_Regs *) I2C0_BASE); +static CPUSS_Regs * const CPUSS = ((CPUSS_Regs *) CPUSS_BASE); +static GPIO_Regs * const GPIOA = ((GPIO_Regs *) GPIOA_BASE); +static GPIO_Regs * const GPIOB = ((GPIO_Regs *) GPIOB_BASE); +static UART_Regs * const UART1 = ((UART_Regs *) UART1_BASE); +static WWDT_Regs * const WWDT0 = ((WWDT_Regs *) WWDT0_BASE); +static COMP_Regs * const COMP1 = ((COMP_Regs *) COMP1_BASE); +static DAC12_Regs * const DAC0 = ((DAC12_Regs *) DAC0_BASE); +static VREF_Regs * const VREF = ((VREF_Regs *) VREF_BASE); +static GPTIMER_Regs * const TIMG7 = ((GPTIMER_Regs *) TIMG7_BASE); +static GPTIMER_Regs * const TIMG6 = ((GPTIMER_Regs *) TIMG6_BASE); +static SPI_Regs * const SPI1 = ((SPI_Regs *) SPI1_BASE); +static DMA_Regs * const DMA = ((DMA_Regs *) DMA_BASE); +static COMP_Regs * const COMP0 = ((COMP_Regs *) COMP0_BASE); +static TRNG_Regs * const TRNG = ((TRNG_Regs *) TRNG_BASE); +static UART_Regs * const UART3 = ((UART_Regs *) UART3_BASE); +static GPTIMER_Regs * const TIMG0 = ((GPTIMER_Regs *) TIMG0_BASE); +static GPTIMER_Regs * const TIMA1 = ((GPTIMER_Regs *) TIMA1_BASE); +static IOMUX_Regs * const IOMUX = ((IOMUX_Regs *) IOMUX_BASE); +static DEBUGSS_Regs * const DEBUGSS = ((DEBUGSS_Regs *) DEBUGSS_BASE); +static MCAN_Regs * const CANFD0 = ((MCAN_Regs *) CANFD0_BASE); +static SPI_Regs * const SPI2 = ((SPI_Regs *) SPI2_BASE); +static UART_Regs * const UART7 = ((UART_Regs *) UART7_BASE); +static UART_Regs * const UART4 = ((UART_Regs *) UART4_BASE); +static GPIO_Regs * const GPIOC = ((GPIO_Regs *) GPIOC_BASE); +static KEYSTORECTL_Regs * const KEYSTORECTL = ((KEYSTORECTL_Regs *) KEYSTORECTL_BASE); +static WWDT_Regs * const WWDT1 = ((WWDT_Regs *) WWDT1_BASE); +static MCAN_Regs * const CANFD1 = ((MCAN_Regs *) CANFD1_BASE); +static AESADV_Regs * const AESADV = ((AESADV_Regs *) AESADV_BASE); +static SYSCTL_Regs * const SYSCTL = ((SYSCTL_Regs *) SYSCTL_BASE); +static ADC12_Regs * const ADC0 = ((ADC12_Regs *) ADC0_BASE); +static ADC12_PERIPHERALREGIONSVT_Regs * const ADC0_PERIPHERALREGIONSVT = ((ADC12_PERIPHERALREGIONSVT_Regs *) ADC0_PERIPHERALREGIONSVT_BASE); +static ADC12_Regs * const ADC1 = ((ADC12_Regs *) ADC1_BASE); +static ADC12_PERIPHERALREGIONSVT_Regs * const ADC1_PERIPHERALREGIONSVT = ((ADC12_PERIPHERALREGIONSVT_Regs *) ADC1_PERIPHERALREGIONSVT_BASE); +static CRCP_Regs * const CRCP0 = ((CRCP_Regs *) CRCP0_BASE); +static CRCP_Regs * const CRC0 = ((CRCP_Regs *) CRCP0_BASE); +static CRCP_Regs * const CRC = ((CRCP_Regs *) CRCP0_BASE); +static GPTIMER_Regs * const TIMG8 = ((GPTIMER_Regs *) TIMG8_BASE); +static GPTIMER_Regs * const TIMG9 = ((GPTIMER_Regs *) TIMG9_BASE); +static GPTIMER_Regs * const TIMG14 = ((GPTIMER_Regs *) TIMG14_BASE); +static UART_Regs * const UART5 = ((UART_Regs *) UART5_BASE); +static UART_Regs * const UART6 = ((UART_Regs *) UART6_BASE); +static FLASHCTL_Regs * const FLASHCTL = ((FLASHCTL_Regs *) FLASHCTL_BASE); +static LFSS_Regs * const LFSS = ((LFSS_Regs *) LFSS_BASE); +static RTC_Regs * const RTC_B = ((RTC_Regs *) RTC_B_BASE); +static I2C_Regs * const I2C1 = ((I2C_Regs *) I2C1_BASE); +static I2C_Regs * const I2C2 = ((I2C_Regs *) I2C2_BASE); +static FACTORYREGION_OPEN_Regs * const FACTORYREGION = ((FACTORYREGION_OPEN_Regs *) FACTORYREGION_BASE); + + +/****************************************************************************** +* SYS parameters * +******************************************************************************/ + +#define DMA_SYS_N_DMA_CHANNEL (12) /* !< Number of DMA channels implemented in DMA. */ +#define DMA_SYS_N_DMA_FULL_CHANNEL (6) /* !< Number of FULL-DMA channels implemented in DMA. */ +#define DMA_SYS_MMR_AUTO (1) /* !< Boolean for if auto enable channels implemented in DMA. */ +#define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ +#define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ +#define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word. */ +#define ADC_SYS_NUM_ANALOG_CHAN (16) /* !< Number of analog channels. */ +#define I2C_SYS_FENTRIES (8) /* !< Number of FIFO entries */ +#define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register */ +#define FLASHCTL_SYS_WEPROTBWIDTH (32) /* !< Bit width of WEPROTB register */ +#define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ + +/****************************************************************************** +* DMA Triggers * +******************************************************************************/ + +/* External DMA Triggers */ +#define DMA_SOFTWARE_TRIG (0) +#define DMA_GENERIC_SUB0_TRIG (1) +#define DMA_GENERIC_SUB1_TRIG (2) +#define DMA_AESADV_AES_0_TRIG (3) +#define DMA_AESADV_AES_1_TRIG (4) +#define DMA_DAC0_EVT_BD_1_TRIG (5) +#define DMA_I2C0_TX_TRIG (6) +#define DMA_I2C0_RX_TRIG (7) +#define DMA_I2C1_TX_TRIG (8) +#define DMA_I2C1_RX_TRIG (9) +#define DMA_I2C2_TX_TRIG (10) +#define DMA_I2C2_RX_TRIG (11) +#define DMA_SPI0_RX_TRIG (12) +#define DMA_SPI0_TX_TRIG (13) +#define DMA_SPI1_RX_TRIG (14) +#define DMA_SPI1_TX_TRIG (15) +#define DMA_SPI2_RX_TRIG (16) +#define DMA_SPI2_TX_TRIG (17) +#define DMA_UART3_RX_TRIG (18) +#define DMA_UART3_TX_TRIG (19) +#define DMA_UART4_RX_TRIG (20) +#define DMA_UART4_TX_TRIG (21) +#define DMA_UART5_RX_TRIG (22) +#define DMA_UART5_TX_TRIG (23) +#define DMA_UART6_RX_TRIG (24) +#define DMA_UART6_TX_TRIG (25) +#define DMA_UART0_RX_TRIG (26) +#define DMA_UART0_TX_TRIG (27) +#define DMA_UART7_RX_TRIG (28) +#define DMA_UART7_TX_TRIG (29) +#define DMA_UART1_RX_TRIG (30) +#define DMA_UART1_TX_TRIG (31) +#define DMA_ADC0_EVT_GEN_BD_TRIG (32) +#define DMA_ADC1_EVT_GEN_BD_TRIG (33) + +/* Internal DMA Triggers */ +#define DMA_CH_0_TRIG (0) +#define DMA_CH_1_TRIG (1) +#define DMA_CH_2_TRIG (2) +#define DMA_CH_3_TRIG (3) +#define DMA_CH_4_TRIG (4) +#define DMA_CH_5_TRIG (5) +#define DMA_CH_6_TRIG (6) +#define DMA_CH_7_TRIG (7) +#define DMA_CH_8_TRIG (8) +#define DMA_CH_9_TRIG (9) +#define DMA_CH_10_TRIG (10) +#define DMA_CH_11_TRIG (11) + + +/****************************************************************************** +* IOMUX Pin Definitions * +******************************************************************************/ + +typedef enum IOMUX_PINCM +{ + IOMUX_PINCM1 = (0), + IOMUX_PINCM2 = (1), + IOMUX_PINCM3 = (2), + IOMUX_PINCM4 = (3), + IOMUX_PINCM5 = (4), + IOMUX_PINCM6 = (5), + IOMUX_PINCM7 = (6), + IOMUX_PINCM8 = (7), + IOMUX_PINCM9 = (8), + IOMUX_PINCM10 = (9), + IOMUX_PINCM11 = (10), + IOMUX_PINCM12 = (11), + IOMUX_PINCM13 = (12), + IOMUX_PINCM14 = (13), + IOMUX_PINCM15 = (14), + IOMUX_PINCM16 = (15), + IOMUX_PINCM17 = (16), + IOMUX_PINCM18 = (17), + IOMUX_PINCM19 = (18), + IOMUX_PINCM20 = (19), + IOMUX_PINCM21 = (20), + IOMUX_PINCM22 = (21), + IOMUX_PINCM23 = (22), + IOMUX_PINCM24 = (23), + IOMUX_PINCM25 = (24), + IOMUX_PINCM26 = (25), + IOMUX_PINCM27 = (26), + IOMUX_PINCM28 = (27), + IOMUX_PINCM29 = (28), + IOMUX_PINCM30 = (29), + IOMUX_PINCM31 = (30), + IOMUX_PINCM32 = (31), + IOMUX_PINCM33 = (32), + IOMUX_PINCM34 = (33), + IOMUX_PINCM35 = (34), + IOMUX_PINCM36 = (35), + IOMUX_PINCM37 = (36), + IOMUX_PINCM38 = (37), + IOMUX_PINCM39 = (38), + IOMUX_PINCM40 = (39), + IOMUX_PINCM41 = (40), + IOMUX_PINCM42 = (41), + IOMUX_PINCM43 = (42), + IOMUX_PINCM44 = (43), + IOMUX_PINCM45 = (44), + IOMUX_PINCM46 = (45), + IOMUX_PINCM47 = (46), + IOMUX_PINCM48 = (47), + IOMUX_PINCM49 = (48), + IOMUX_PINCM50 = (49), + IOMUX_PINCM51 = (50), + IOMUX_PINCM52 = (51), + IOMUX_PINCM53 = (52), + IOMUX_PINCM54 = (53), + IOMUX_PINCM55 = (54), + IOMUX_PINCM56 = (55), + IOMUX_PINCM57 = (56), + IOMUX_PINCM58 = (57), + IOMUX_PINCM59 = (58), + IOMUX_PINCM60 = (59), + IOMUX_PINCM61 = (60), + IOMUX_PINCM62 = (61), + IOMUX_PINCM63 = (62), + IOMUX_PINCM64 = (63), + IOMUX_PINCM65 = (64), + IOMUX_PINCM66 = (65), + IOMUX_PINCM67 = (66), + IOMUX_PINCM68 = (67), + IOMUX_PINCM69 = (68), + IOMUX_PINCM70 = (69), + IOMUX_PINCM71 = (70), + IOMUX_PINCM72 = (71), + IOMUX_PINCM73 = (72), + IOMUX_PINCM74 = (73), + IOMUX_PINCM75 = (74), + IOMUX_PINCM76 = (75), + IOMUX_PINCM77 = (76), + IOMUX_PINCM78 = (77), + IOMUX_PINCM79 = (78), + IOMUX_PINCM80 = (79), + IOMUX_PINCM81 = (80), + IOMUX_PINCM82 = (81), + IOMUX_PINCM83 = (82), + IOMUX_PINCM84 = (83), + IOMUX_PINCM85 = (84), + IOMUX_PINCM86 = (85), + IOMUX_PINCM87 = (86), + IOMUX_PINCM88 = (87), + IOMUX_PINCM89 = (88), + IOMUX_PINCM90 = (89), + IOMUX_PINCM91 = (90), + IOMUX_PINCM92 = (91), + IOMUX_PINCM93 = (92), + IOMUX_PINCM94 = (93), +} IOMUX_PINCM; + + +/* IOMUX_PINCM1[PF] Bits */ +#define IOMUX_PINCM1_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM1_PF_GPIOA_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM1_PF_UART0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_I2C0_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM1_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM1_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM1_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM1_PF_TIMG8_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM1_PF_TIMG12_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM1_PF_TIMG0_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM1_PF_UART5_RX ((uint32_t)0X0000000C) + +/* IOMUX_PINCM2[PF] Bits */ +#define IOMUX_PINCM2_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM2_PF_GPIOA_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM2_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_I2C0_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM2_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM2_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM2_PF_TIMG8_IDX ((uint32_t)0X00000006) +#define IOMUX_PINCM2_PF_TIMG8_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM2_PF_TIMG12_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM2_PF_TIMG0_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM2_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X0000000A) +#define IOMUX_PINCM2_PF_UART5_TX ((uint32_t)0X0000000C) + +/* IOMUX_PINCM3[PF] Bits */ +#define IOMUX_PINCM3_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM3_PF_GPIOA_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM3_PF_UART0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_I2C0_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM3_PF_TIMA0_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM3_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM3_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM3_PF_TIMA1_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM3_PF_TIMG14_CCP2 ((uint32_t)0X0000000A) +#define IOMUX_PINCM3_PF_TIMG7_CCP0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM3_PF_UART5_CTS ((uint32_t)0X0000000C) + +/* IOMUX_PINCM4[PF] Bits */ +#define IOMUX_PINCM4_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM4_PF_GPIOA_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM4_PF_I2C1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_UART7_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM4_PF_TIMG8_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM4_PF_I2C2_SCL ((uint32_t)0X00000006) +#define IOMUX_PINCM4_PF_UART0_CTS ((uint32_t)0X00000007) +#define IOMUX_PINCM4_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000008) +#define IOMUX_PINCM4_PF_TIMG6_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM4_PF_TIMG14_CCP3 ((uint32_t)0X0000000A) +#define IOMUX_PINCM4_PF_TIMG14_CCP0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM4_PF_UART5_RTS ((uint32_t)0X0000000C) + +/* IOMUX_PINCM5[PF] Bits */ +#define IOMUX_PINCM5_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM5_PF_GPIOA_DIO30 ((uint32_t)0X00000001) +#define IOMUX_PINCM5_PF_I2C1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_UART7_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM5_PF_TIMG8_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM5_PF_I2C2_SDA ((uint32_t)0X00000006) +#define IOMUX_PINCM5_PF_UART0_RTS ((uint32_t)0X00000007) +#define IOMUX_PINCM5_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000008) +#define IOMUX_PINCM5_PF_TIMG6_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM5_PF_TIMG14_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM6[PF] Bits */ +#define IOMUX_PINCM6_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM6_PF_GPIOA_DIO31 ((uint32_t)0X00000001) +#define IOMUX_PINCM6_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_I2C0_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM6_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM6_PF_TIMG12_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM6_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM6_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000008) +#define IOMUX_PINCM6_PF_TIMG7_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM6_PF_TIMA1_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM7[PF] Bits */ +#define IOMUX_PINCM7_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM7_PF_GPIOA_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM7_PF_TIMG8_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM7_PF_SPI0_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_TIMG7_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM7_PF_SPI1_CS0 ((uint32_t)0X00000005) +#define IOMUX_PINCM7_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM7_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM7_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM7_PF_TIMA_FAULT1 ((uint32_t)0X00000009) +#define IOMUX_PINCM7_PF_UART4_CTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM7_PF_TIMA0_CCP0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM7_PF_SPI2_POCI ((uint32_t)0X0000000C) +#define IOMUX_PINCM7_PF_TIMG9_CCP1 ((uint32_t)0X0000000D) + +/* IOMUX_PINCM8[PF] Bits */ +#define IOMUX_PINCM8_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM8_PF_GPIOA_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM8_PF_TIMG8_CCP0 ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM8_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM8_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM8_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM8_PF_TIMG9_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM8_PF_TIMA0_CCP2 ((uint32_t)0X00000008) +#define IOMUX_PINCM8_PF_UART7_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM8_PF_UART1_TX ((uint32_t)0X0000000A) +#define IOMUX_PINCM8_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X0000000B) +#define IOMUX_PINCM8_PF_COMP1_OUT ((uint32_t)0X0000000C) +#define IOMUX_PINCM8_PF_TIMG7_CCP0 ((uint32_t)0X0000000D) + +/* IOMUX_PINCM9[PF] Bits */ +#define IOMUX_PINCM9_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM9_PF_GPIOA_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM9_PF_TIMG8_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM9_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM9_PF_SYSCTL_LFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM9_PF_TIMG9_IDX ((uint32_t)0X00000007) +#define IOMUX_PINCM9_PF_TIMA0_CCP3 ((uint32_t)0X00000008) +#define IOMUX_PINCM9_PF_UART7_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM9_PF_UART1_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM9_PF_SPI0_CS0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM9_PF_SPI2_CS0 ((uint32_t)0X0000000C) +#define IOMUX_PINCM9_PF_TIMG7_CCP1 ((uint32_t)0X0000000D) + +/* IOMUX_PINCM10[PF] Bits */ +#define IOMUX_PINCM10_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM10_PF_GPIOA_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM10_PF_TIMG8_CCP0 ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM10_PF_TIMG0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM10_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM10_PF_TIMG6_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM10_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM10_PF_UART0_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_UART4_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM10_PF_UART1_TX ((uint32_t)0X0000000B) +#define IOMUX_PINCM10_PF_SPI2_CS1_POCI1 ((uint32_t)0X0000000C) + +/* IOMUX_PINCM11[PF] Bits */ +#define IOMUX_PINCM11_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM11_PF_GPIOA_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM11_PF_TIMG8_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM11_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM11_PF_TIMG0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM11_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM11_PF_TIMG6_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM11_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM11_PF_UART0_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM11_PF_TIMA0_CCP2_CMPL ((uint32_t)0X0000000A) +#define IOMUX_PINCM11_PF_UART1_RX ((uint32_t)0X0000000B) +#define IOMUX_PINCM11_PF_SPI2_CS2_POCI2 ((uint32_t)0X0000000C) + +/* IOMUX_PINCM12[PF] Bits */ +#define IOMUX_PINCM12_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM12_PF_GPIOB_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM12_PF_UART0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM12_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM12_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM12_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000007) +#define IOMUX_PINCM12_PF_TIMA1_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM12_PF_TIMG14_CCP2 ((uint32_t)0X00000009) +#define IOMUX_PINCM12_PF_SPI2_CS3_CD_POCI3 ((uint32_t)0X0000000C) + +/* IOMUX_PINCM13[PF] Bits */ +#define IOMUX_PINCM13_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM13_PF_GPIOB_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM13_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_SPI1_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM13_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM13_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM13_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000007) +#define IOMUX_PINCM13_PF_TIMA1_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM13_PF_TIMG14_CCP3 ((uint32_t)0X00000009) + +/* IOMUX_PINCM14[PF] Bits */ +#define IOMUX_PINCM14_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM14_PF_GPIOA_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM14_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM14_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000003) +#define IOMUX_PINCM14_PF_TIMG8_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM14_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM14_PF_TIMG8_IDX ((uint32_t)0X00000006) +#define IOMUX_PINCM14_PF_TIMG7_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM14_PF_TIMA0_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM14_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000009) +#define IOMUX_PINCM14_PF_SYSCTL_FCC_IN ((uint32_t)0X0000000A) +#define IOMUX_PINCM14_PF_SPI0_POCI ((uint32_t)0X0000000B) + +/* IOMUX_PINCM15[PF] Bits */ +#define IOMUX_PINCM15_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM15_PF_GPIOB_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM15_PF_UART3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM15_PF_UART7_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM15_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM15_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM15_PF_UART1_CTS ((uint32_t)0X00000006) +#define IOMUX_PINCM15_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM15_PF_UART7_TX ((uint32_t)0X00000008) +#define IOMUX_PINCM15_PF_TIMG12_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM15_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM15_PF_SPI0_PICO ((uint32_t)0X0000000B) +#define IOMUX_PINCM15_PF_TIMA1_CCP0 ((uint32_t)0X0000000C) +#define IOMUX_PINCM15_PF_TIMG6_CCP0 ((uint32_t)0X0000000D) + +/* IOMUX_PINCM16[PF] Bits */ +#define IOMUX_PINCM16_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM16_PF_GPIOB_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM16_PF_UART3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM16_PF_UART7_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM16_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM16_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM16_PF_UART1_RTS ((uint32_t)0X00000006) +#define IOMUX_PINCM16_PF_TIMG14_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM16_PF_UART7_RX ((uint32_t)0X00000008) +#define IOMUX_PINCM16_PF_TIMG12_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM16_PF_TIMA0_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM16_PF_SPI0_SCLK ((uint32_t)0X0000000B) +#define IOMUX_PINCM16_PF_TIMA1_CCP1 ((uint32_t)0X0000000C) +#define IOMUX_PINCM16_PF_TIMG6_CCP1 ((uint32_t)0X0000000D) + +/* IOMUX_PINCM17[PF] Bits */ +#define IOMUX_PINCM17_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM17_PF_GPIOB_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM17_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_UART3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM17_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM17_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM17_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM17_PF_TIMA1_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM17_PF_TIMA1_CCP0_CMPL ((uint32_t)0X0000000B) +#define IOMUX_PINCM17_PF_SPI2_PICO ((uint32_t)0X0000000C) + +/* IOMUX_PINCM18[PF] Bits */ +#define IOMUX_PINCM18_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM18_PF_GPIOB_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM18_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_UART3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM18_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM18_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM18_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM18_PF_TIMA1_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM18_PF_TIMA1_CCP1_CMPL ((uint32_t)0X0000000B) +#define IOMUX_PINCM18_PF_SPI2_POCI ((uint32_t)0X0000000C) + +/* IOMUX_PINCM19[PF] Bits */ +#define IOMUX_PINCM19_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM19_PF_GPIOA_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM19_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_SPI0_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM19_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM19_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM19_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM19_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000008) +#define IOMUX_PINCM19_PF_TIMG14_CCP2 ((uint32_t)0X00000009) +#define IOMUX_PINCM19_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM19_PF_UART0_RTS ((uint32_t)0X0000000B) +#define IOMUX_PINCM19_PF_TIMA1_CCP0_CMPL ((uint32_t)0X0000000C) + +/* IOMUX_PINCM20[PF] Bits */ +#define IOMUX_PINCM20_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM20_PF_GPIOA_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM20_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM20_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM20_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM20_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM20_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM20_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM20_PF_TIMG14_CCP3 ((uint32_t)0X00000009) +#define IOMUX_PINCM20_PF_UART4_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM20_PF_UART0_CTS ((uint32_t)0X0000000B) +#define IOMUX_PINCM20_PF_TIMA1_CCP1_CMPL ((uint32_t)0X0000000C) + +/* IOMUX_PINCM21[PF] Bits */ +#define IOMUX_PINCM21_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM21_PF_GPIOA_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM21_PF_UART0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM21_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM21_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM21_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM21_PF_TIMG0_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM21_PF_I2C1_SDA ((uint32_t)0X00000008) +#define IOMUX_PINCM21_PF_TIMG12_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM21_PF_TIMA_FAULT1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM21_PF_TIMA1_CCP0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM21_PF_SPI2_SCLK ((uint32_t)0X0000000C) + +/* IOMUX_PINCM22[PF] Bits */ +#define IOMUX_PINCM22_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM22_PF_GPIOA_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM22_PF_UART0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM22_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM22_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM22_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM22_PF_TIMG0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM22_PF_I2C1_SCL ((uint32_t)0X00000008) +#define IOMUX_PINCM22_PF_TIMG12_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM22_PF_TIMA_FAULT0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM22_PF_TIMA1_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM23[PF] Bits */ +#define IOMUX_PINCM23_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM23_PF_GPIOB_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM23_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_SPI1_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM23_PF_I2C2_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM23_PF_TIMG8_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM23_PF_UART7_CTS ((uint32_t)0X00000006) +#define IOMUX_PINCM23_PF_TIMG14_CCP3 ((uint32_t)0X00000007) +#define IOMUX_PINCM23_PF_TIMA_FAULT2 ((uint32_t)0X00000008) +#define IOMUX_PINCM23_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000009) +#define IOMUX_PINCM23_PF_TIMG12_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM23_PF_TIMG6_CCP0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM23_PF_TIMA1_CCP0_CMPL ((uint32_t)0X0000000C) + +/* IOMUX_PINCM24[PF] Bits */ +#define IOMUX_PINCM24_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM24_PF_GPIOB_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM24_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_SPI1_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM24_PF_I2C2_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM24_PF_TIMG8_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM24_PF_UART7_RTS ((uint32_t)0X00000006) +#define IOMUX_PINCM24_PF_TIMG9_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM24_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000009) +#define IOMUX_PINCM24_PF_TIMG12_CCP1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM24_PF_TIMG6_CCP1 ((uint32_t)0X0000000B) +#define IOMUX_PINCM24_PF_TIMA1_CCP1_CMPL ((uint32_t)0X0000000C) + +/* IOMUX_PINCM25[PF] Bits */ +#define IOMUX_PINCM25_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM25_PF_GPIOB_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM25_PF_UART1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM25_PF_SPI1_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_I2C2_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM25_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM25_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM25_PF_TIMG9_IDX ((uint32_t)0X00000007) +#define IOMUX_PINCM25_PF_COMP1_OUT ((uint32_t)0X00000008) + +/* IOMUX_PINCM26[PF] Bits */ +#define IOMUX_PINCM26_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM26_PF_GPIOB_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM26_PF_UART1_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM26_PF_SPI1_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_I2C2_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM26_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM26_PF_TIMA0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM26_PF_TIMG9_CCP1 ((uint32_t)0X0000000D) + +/* IOMUX_PINCM27[PF] Bits */ +#define IOMUX_PINCM27_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM27_PF_GPIOB_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM27_PF_TIMG0_CCP0 ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_TIMG8_CCP0 ((uint32_t)0X00000003) +#define IOMUX_PINCM27_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM27_PF_UART4_TX ((uint32_t)0X00000006) +#define IOMUX_PINCM27_PF_SPI1_CS3_CD_POCI3 ((uint32_t)0X00000007) +#define IOMUX_PINCM27_PF_TIMG6_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM27_PF_COMP1_OUT ((uint32_t)0X0000000B) + +/* IOMUX_PINCM28[PF] Bits */ +#define IOMUX_PINCM28_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM28_PF_GPIOB_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM28_PF_TIMG0_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM28_PF_TIMG8_CCP1 ((uint32_t)0X00000003) +#define IOMUX_PINCM28_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM28_PF_UART4_RX ((uint32_t)0X00000006) +#define IOMUX_PINCM28_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000007) +#define IOMUX_PINCM28_PF_TIMG6_CCP1 ((uint32_t)0X00000009) + +/* IOMUX_PINCM29[PF] Bits */ +#define IOMUX_PINCM29_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM29_PF_GPIOB_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM29_PF_UART3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM29_PF_TIMA0_CCP2 ((uint32_t)0X00000003) +#define IOMUX_PINCM29_PF_TIMA_FAULT1 ((uint32_t)0X00000004) +#define IOMUX_PINCM29_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM29_PF_UART4_CTS ((uint32_t)0X00000006) +#define IOMUX_PINCM29_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000007) +#define IOMUX_PINCM29_PF_TIMG14_CCP0 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM30[PF] Bits */ +#define IOMUX_PINCM30_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM30_PF_GPIOB_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM30_PF_UART3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM30_PF_TIMA0_CCP3 ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_TIMG12_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM30_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM30_PF_UART4_RTS ((uint32_t)0X00000006) +#define IOMUX_PINCM30_PF_SPI1_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM30_PF_TIMG14_CCP1 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM31[PF] Bits */ +#define IOMUX_PINCM31_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM31_PF_GPIOB_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM31_PF_SPI1_CS3_CD_POCI3 ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_SPI1_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM31_PF_TIMG12_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM31_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM31_PF_TIMG8_IDX ((uint32_t)0X00000006) +#define IOMUX_PINCM31_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000007) + +/* IOMUX_PINCM32[PF] Bits */ +#define IOMUX_PINCM32_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM32_PF_GPIOB_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM32_PF_UART7_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_SPI1_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_UART3_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM32_PF_TIMG8_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM32_PF_I2C2_SCL ((uint32_t)0X00000007) +#define IOMUX_PINCM32_PF_TIMG7_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM33[PF] Bits */ +#define IOMUX_PINCM33_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM33_PF_GPIOB_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM33_PF_UART7_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_SPI1_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_UART3_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM33_PF_TIMG8_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM33_PF_I2C2_SDA ((uint32_t)0X00000007) +#define IOMUX_PINCM33_PF_TIMG7_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM34[PF] Bits */ +#define IOMUX_PINCM34_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM34_PF_GPIOA_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM34_PF_UART3_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM34_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM34_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM34_PF_TIMG0_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM34_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000008) +#define IOMUX_PINCM34_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000009) +#define IOMUX_PINCM34_PF_UART7_CTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM34_PF_UART1_CTS ((uint32_t)0X0000000B) +#define IOMUX_PINCM34_PF_CANFD0_CANTX ((uint32_t)0X0000000C) + +/* IOMUX_PINCM35[PF] Bits */ +#define IOMUX_PINCM35_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM35_PF_GPIOA_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM35_PF_UART3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_UART3_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM35_PF_LFSS_RTC_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM35_PF_TIMG0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM35_PF_SPI1_CS0 ((uint32_t)0X00000008) +#define IOMUX_PINCM35_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000009) +#define IOMUX_PINCM35_PF_UART7_TX ((uint32_t)0X0000000A) +#define IOMUX_PINCM35_PF_UART1_RTS ((uint32_t)0X0000000B) +#define IOMUX_PINCM35_PF_CANFD0_CANRX ((uint32_t)0X0000000C) + +/* IOMUX_PINCM36[PF] Bits */ +#define IOMUX_PINCM36_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM36_PF_GPIOA_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM36_PF_UART0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM36_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_UART3_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM36_PF_TIMG12_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM36_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM36_PF_TIMG12_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM36_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000008) +#define IOMUX_PINCM36_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000009) +#define IOMUX_PINCM36_PF_UART7_RX ((uint32_t)0X0000000A) + +/* IOMUX_PINCM37[PF] Bits */ +#define IOMUX_PINCM37_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM37_PF_GPIOA_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM37_PF_UART0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM37_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM37_PF_I2C2_SCL ((uint32_t)0X00000006) +#define IOMUX_PINCM37_PF_TIMG8_IDX ((uint32_t)0X00000007) +#define IOMUX_PINCM37_PF_TIMG12_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM37_PF_TIMA1_CCP0_CMPL ((uint32_t)0X00000009) +#define IOMUX_PINCM37_PF_UART7_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM37_PF_TIMA1_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM38[PF] Bits */ +#define IOMUX_PINCM38_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM38_PF_GPIOA_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM38_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM38_PF_SPI1_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM38_PF_I2C2_SDA ((uint32_t)0X00000006) +#define IOMUX_PINCM38_PF_SYSCTL_FCC_IN ((uint32_t)0X00000007) +#define IOMUX_PINCM38_PF_TIMG12_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM38_PF_COMP2_OUT ((uint32_t)0X00000009) +#define IOMUX_PINCM38_PF_UART7_CTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM38_PF_TIMA1_CCP1 ((uint32_t)0X0000000B) +#define IOMUX_PINCM38_PF_TIMA1_CCP1_CMPL ((uint32_t)0X0000000C) + +/* IOMUX_PINCM39[PF] Bits */ +#define IOMUX_PINCM39_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM39_PF_GPIOA_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM39_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_SPI1_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM39_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM39_PF_TIMG8_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM39_PF_TIMG12_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM39_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000009) +#define IOMUX_PINCM39_PF_TIMA1_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM39_PF_TIMG7_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM40[PF] Bits */ +#define IOMUX_PINCM40_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM40_PF_GPIOA_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM40_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_SPI1_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM40_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM40_PF_TIMG8_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM40_PF_TIMG12_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM40_PF_SPI0_CS0 ((uint32_t)0X00000009) +#define IOMUX_PINCM40_PF_TIMA1_CCP1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM40_PF_TIMG7_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM41[PF] Bits */ +#define IOMUX_PINCM41_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM41_PF_GPIOA_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM41_PF_DEBUGSS_SWDIO ((uint32_t)0X00000002) +#define IOMUX_PINCM41_PF_SPI1_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_I2C1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM41_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM41_PF_TIMG0_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM42[PF] Bits */ +#define IOMUX_PINCM42_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM42_PF_GPIOA_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM42_PF_DEBUGSS_SWCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM42_PF_SPI1_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_I2C1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM42_PF_TIMG0_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM43[PF] Bits */ +#define IOMUX_PINCM43_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM43_PF_GPIOB_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM43_PF_UART7_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_SPI0_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM43_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM43_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM43_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000007) +#define IOMUX_PINCM43_PF_UART4_TX ((uint32_t)0X00000008) +#define IOMUX_PINCM43_PF_TIMG14_CCP2 ((uint32_t)0X00000009) +#define IOMUX_PINCM43_PF_TIMA1_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM44[PF] Bits */ +#define IOMUX_PINCM44_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM44_PF_GPIOB_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM44_PF_UART7_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_SPI0_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM44_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM44_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM44_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000007) +#define IOMUX_PINCM44_PF_UART4_RX ((uint32_t)0X00000008) +#define IOMUX_PINCM44_PF_TIMG14_CCP3 ((uint32_t)0X00000009) +#define IOMUX_PINCM44_PF_TIMA1_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM45[PF] Bits */ +#define IOMUX_PINCM45_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM45_PF_GPIOB_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM45_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM45_PF_SPI0_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_TIMG8_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM45_PF_UART0_CTS ((uint32_t)0X00000005) +#define IOMUX_PINCM45_PF_COMP2_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM45_PF_TIMG8_IDX ((uint32_t)0X00000007) +#define IOMUX_PINCM45_PF_UART7_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM45_PF_UART4_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM45_PF_SPI1_CS3_CD_POCI3 ((uint32_t)0X0000000A) +#define IOMUX_PINCM45_PF_TIMG7_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM46[PF] Bits */ +#define IOMUX_PINCM46_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM46_PF_GPIOA_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM46_PF_UART7_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM46_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM46_PF_UART1_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM46_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM46_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000007) +#define IOMUX_PINCM46_PF_UART7_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM46_PF_UART4_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM46_PF_TIMG8_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM46_PF_TIMG6_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM47[PF] Bits */ +#define IOMUX_PINCM47_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM47_PF_GPIOA_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM47_PF_UART7_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM47_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM47_PF_UART1_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM47_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM47_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM47_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM47_PF_I2C0_SCL ((uint32_t)0X00000009) +#define IOMUX_PINCM47_PF_TIMG8_CCP1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM47_PF_TIMG6_CCP1 ((uint32_t)0X0000000C) + +/* IOMUX_PINCM48[PF] Bits */ +#define IOMUX_PINCM48_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM48_PF_GPIOB_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM48_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000002) +#define IOMUX_PINCM48_PF_SPI1_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM48_PF_TIMG12_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM48_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM48_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM48_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM48_PF_UART7_RTS ((uint32_t)0X00000008) +#define IOMUX_PINCM48_PF_I2C0_SDA ((uint32_t)0X00000009) +#define IOMUX_PINCM48_PF_TIMA1_CCP1_CMPL ((uint32_t)0X0000000A) + +/* IOMUX_PINCM49[PF] Bits */ +#define IOMUX_PINCM49_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM49_PF_GPIOB_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM49_PF_UART4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM49_PF_SPI1_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM49_PF_I2C0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM49_PF_TIMG8_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM49_PF_UART1_TX ((uint32_t)0X00000006) +#define IOMUX_PINCM49_PF_CANFD1_CANTX ((uint32_t)0X00000007) +#define IOMUX_PINCM49_PF_UART6_RX ((uint32_t)0X00000009) + +/* IOMUX_PINCM50[PF] Bits */ +#define IOMUX_PINCM50_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM50_PF_GPIOB_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM50_PF_UART4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM50_PF_SPI1_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_I2C0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM50_PF_TIMG8_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM50_PF_UART1_RX ((uint32_t)0X00000006) +#define IOMUX_PINCM50_PF_CANFD1_CANRX ((uint32_t)0X00000007) +#define IOMUX_PINCM50_PF_UART6_TX ((uint32_t)0X00000009) + +/* IOMUX_PINCM51[PF] Bits */ +#define IOMUX_PINCM51_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM51_PF_GPIOB_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM51_PF_UART1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM51_PF_SPI1_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM51_PF_COMP0_OUT ((uint32_t)0X00000005) +#define IOMUX_PINCM51_PF_UART6_CTS ((uint32_t)0X00000009) + +/* IOMUX_PINCM52[PF] Bits */ +#define IOMUX_PINCM52_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM52_PF_GPIOB_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM52_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000002) +#define IOMUX_PINCM52_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM52_PF_TIMG12_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM52_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM52_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM52_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000007) +#define IOMUX_PINCM52_PF_UART7_RTS ((uint32_t)0X00000008) +#define IOMUX_PINCM52_PF_UART6_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM52_PF_TIMA1_CCP0_CMPL ((uint32_t)0X0000000A) + +/* IOMUX_PINCM53[PF] Bits */ +#define IOMUX_PINCM53_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM53_PF_GPIOA_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM53_PF_UART7_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM53_PF_SPI0_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM53_PF_I2C2_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM53_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM53_PF_TIMG8_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM53_PF_UART3_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM53_PF_TIMG0_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM53_PF_SPI1_CS1_POCI1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM53_PF_TIMG7_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM54[PF] Bits */ +#define IOMUX_PINCM54_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM54_PF_GPIOA_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM54_PF_UART7_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM54_PF_SPI0_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM54_PF_I2C2_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM54_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM54_PF_TIMG8_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM54_PF_TIMA1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM54_PF_UART3_RTS ((uint32_t)0X00000008) +#define IOMUX_PINCM54_PF_TIMG0_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM54_PF_SPI1_CS2_POCI2 ((uint32_t)0X0000000A) +#define IOMUX_PINCM54_PF_TIMG7_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM55[PF] Bits */ +#define IOMUX_PINCM55_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM55_PF_GPIOA_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM55_PF_UART3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM55_PF_SPI1_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM55_PF_TIMG12_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM55_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM55_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM55_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM55_PF_UART7_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM55_PF_UART3_TX ((uint32_t)0X00000009) + +/* IOMUX_PINCM56[PF] Bits */ +#define IOMUX_PINCM56_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM56_PF_GPIOB_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM56_PF_UART0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM56_PF_SPI0_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM56_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM56_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM56_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM56_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM56_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/* IOMUX_PINCM57[PF] Bits */ +#define IOMUX_PINCM57_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM57_PF_GPIOB_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM57_PF_UART0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM57_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM57_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM57_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM57_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM57_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) +#define IOMUX_PINCM57_PF_TIMA1_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM57_PF_TIMG6_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM58[PF] Bits */ +#define IOMUX_PINCM58_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM58_PF_GPIOB_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM58_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM58_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM58_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM58_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM58_PF_COMP2_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM58_PF_TIMA1_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM58_PF_TIMG6_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM59[PF] Bits */ +#define IOMUX_PINCM59_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM59_PF_GPIOA_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM59_PF_UART3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM59_PF_SPI1_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM59_PF_TIMG8_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM59_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM59_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM59_PF_UART7_RTS ((uint32_t)0X00000008) +#define IOMUX_PINCM59_PF_UART3_RX ((uint32_t)0X00000009) +#define IOMUX_PINCM59_PF_CANFD0_CANTX ((uint32_t)0X0000000A) +#define IOMUX_PINCM59_PF_TIMG7_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM60[PF] Bits */ +#define IOMUX_PINCM60_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM60_PF_GPIOA_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM60_PF_UART3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM60_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM60_PF_TIMG8_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM60_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM60_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM60_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM60_PF_COMP0_OUT ((uint32_t)0X00000009) +#define IOMUX_PINCM60_PF_CANFD0_CANRX ((uint32_t)0X0000000A) +#define IOMUX_PINCM60_PF_TIMG7_CCP1 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM61[PF] Bits */ +#define IOMUX_PINCM61_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM61_PF_GPIOC_DIO12 ((uint32_t)0X00000001) + +/* IOMUX_PINCM62[PF] Bits */ +#define IOMUX_PINCM62_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM62_PF_GPIOC_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM62_PF_SPI2_PICO ((uint32_t)0X0000000C) + +/* IOMUX_PINCM63[PF] Bits */ +#define IOMUX_PINCM63_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM63_PF_GPIOC_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM63_PF_TIMG9_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM63_PF_SPI2_SCLK ((uint32_t)0X0000000C) + +/* IOMUX_PINCM64[PF] Bits */ +#define IOMUX_PINCM64_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM64_PF_GPIOC_DIO15 ((uint32_t)0X00000001) + +/* IOMUX_PINCM65[PF] Bits */ +#define IOMUX_PINCM65_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM65_PF_GPIOB_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM65_PF_I2C2_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM65_PF_SPI1_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM65_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM65_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM65_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM65_PF_UART5_RX ((uint32_t)0X00000007) +#define IOMUX_PINCM65_PF_TIMG14_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM65_PF_UART6_RX ((uint32_t)0X0000000C) + +/* IOMUX_PINCM66[PF] Bits */ +#define IOMUX_PINCM66_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM66_PF_GPIOB_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM66_PF_I2C2_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM66_PF_SPI1_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM66_PF_TIMA_FAULT1 ((uint32_t)0X00000004) +#define IOMUX_PINCM66_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM66_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM66_PF_UART5_TX ((uint32_t)0X00000007) +#define IOMUX_PINCM66_PF_TIMG9_CCP0 ((uint32_t)0X00000008) +#define IOMUX_PINCM66_PF_TIMG14_CCP1 ((uint32_t)0X0000000A) +#define IOMUX_PINCM66_PF_UART6_TX ((uint32_t)0X0000000C) + +/* IOMUX_PINCM67[PF] Bits */ +#define IOMUX_PINCM67_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM67_PF_GPIOB_DIO30 ((uint32_t)0X00000001) +#define IOMUX_PINCM67_PF_UART1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM67_PF_SPI1_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM67_PF_TIMA_FAULT2 ((uint32_t)0X00000004) +#define IOMUX_PINCM67_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM67_PF_UART5_CTS ((uint32_t)0X00000007) +#define IOMUX_PINCM67_PF_TIMG9_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM67_PF_TIMG14_CCP2 ((uint32_t)0X00000009) +#define IOMUX_PINCM67_PF_UART6_CTS ((uint32_t)0X0000000C) + +/* IOMUX_PINCM68[PF] Bits */ +#define IOMUX_PINCM68_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM68_PF_GPIOB_DIO31 ((uint32_t)0X00000001) +#define IOMUX_PINCM68_PF_UART1_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM68_PF_SPI1_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM68_PF_TIMG8_IDX ((uint32_t)0X00000004) +#define IOMUX_PINCM68_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM68_PF_UART5_RTS ((uint32_t)0X00000007) +#define IOMUX_PINCM68_PF_TIMG9_IDX ((uint32_t)0X00000008) +#define IOMUX_PINCM68_PF_TIMG14_CCP3 ((uint32_t)0X00000009) +#define IOMUX_PINCM68_PF_UART6_RTS ((uint32_t)0X0000000C) + +/* IOMUX_PINCM69[PF] Bits */ +#define IOMUX_PINCM69_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM69_PF_GPIOC_DIO16 ((uint32_t)0X00000001) + +/* IOMUX_PINCM70[PF] Bits */ +#define IOMUX_PINCM70_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM70_PF_GPIOC_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM70_PF_TIMG14_CCP2 ((uint32_t)0X00000007) + +/* IOMUX_PINCM71[PF] Bits */ +#define IOMUX_PINCM71_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM71_PF_GPIOC_DIO18 ((uint32_t)0X00000001) + +/* IOMUX_PINCM72[PF] Bits */ +#define IOMUX_PINCM72_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM72_PF_GPIOC_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM72_PF_TIMG9_CCP1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM73[PF] Bits */ +#define IOMUX_PINCM73_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM73_PF_GPIOC_DIO20 ((uint32_t)0X00000001) + +/* IOMUX_PINCM74[PF] Bits */ +#define IOMUX_PINCM74_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM74_PF_GPIOC_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM74_PF_UART1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM74_PF_SPI1_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM74_PF_TIMG8_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM74_PF_TIMA0_CCP2 ((uint32_t)0X00000005) + +/* IOMUX_PINCM75[PF] Bits */ +#define IOMUX_PINCM75_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM75_PF_GPIOC_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM75_PF_UART1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM75_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM75_PF_TIMG8_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM75_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) + +/* IOMUX_PINCM76[PF] Bits */ +#define IOMUX_PINCM76_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM76_PF_GPIOC_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM76_PF_I2C2_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM76_PF_SPI1_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM76_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM76_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM76_PF_TIMG0_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM77[PF] Bits */ +#define IOMUX_PINCM77_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM77_PF_GPIOC_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM77_PF_I2C2_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM77_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM77_PF_TIMA_FAULT1 ((uint32_t)0X00000004) +#define IOMUX_PINCM77_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM77_PF_TIMG0_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM78[PF] Bits */ +#define IOMUX_PINCM78_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM78_PF_GPIOC_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM78_PF_UART3_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM78_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM78_PF_TIMA_FAULT2 ((uint32_t)0X00000004) +#define IOMUX_PINCM78_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM78_PF_TIMG14_CCP2 ((uint32_t)0X00000007) + +/* IOMUX_PINCM79[PF] Bits */ +#define IOMUX_PINCM79_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM79_PF_GPIOC_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM79_PF_UART3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM79_PF_SPI1_CS3_CD_POCI3 ((uint32_t)0X00000003) +#define IOMUX_PINCM79_PF_TIMG8_IDX ((uint32_t)0X00000004) +#define IOMUX_PINCM79_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM79_PF_TIMG14_CCP3 ((uint32_t)0X00000007) + +/* IOMUX_PINCM80[PF] Bits */ +#define IOMUX_PINCM80_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM80_PF_GPIOC_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM80_PF_CANFD1_CANTX ((uint32_t)0X00000007) + +/* IOMUX_PINCM81[PF] Bits */ +#define IOMUX_PINCM81_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM81_PF_GPIOC_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM81_PF_CANFD1_CANRX ((uint32_t)0X00000007) + +/* IOMUX_PINCM82[PF] Bits */ +#define IOMUX_PINCM82_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM82_PF_GPIOC_DIO23 ((uint32_t)0X00000001) + +/* IOMUX_PINCM83[PF] Bits */ +#define IOMUX_PINCM83_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM83_PF_GPIOC_DIO24 ((uint32_t)0X00000001) + +/* IOMUX_PINCM84[PF] Bits */ +#define IOMUX_PINCM84_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM84_PF_GPIOC_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM84_PF_UART3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM84_PF_SPI0_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM84_PF_TIMG8_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM84_PF_TIMA0_CCP0 ((uint32_t)0X00000005) + +/* IOMUX_PINCM85[PF] Bits */ +#define IOMUX_PINCM85_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM85_PF_GPIOC_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM85_PF_UART3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM85_PF_SPI0_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM85_PF_TIMG8_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM85_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) + +/* IOMUX_PINCM86[PF] Bits */ +#define IOMUX_PINCM86_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM86_PF_GPIOC_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM86_PF_UART3_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM86_PF_SPI1_CS2_POCI2 ((uint32_t)0X00000003) +#define IOMUX_PINCM86_PF_TIMA0_CCP1 ((uint32_t)0X00000005) + +/* IOMUX_PINCM87[PF] Bits */ +#define IOMUX_PINCM87_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM87_PF_GPIOC_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM87_PF_UART3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM87_PF_SPI1_CS1_POCI1 ((uint32_t)0X00000003) +#define IOMUX_PINCM87_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) + +/* IOMUX_PINCM88[PF] Bits */ +#define IOMUX_PINCM88_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM88_PF_GPIOC_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM88_PF_TIMG9_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM88_PF_UART6_RX ((uint32_t)0X00000008) + +/* IOMUX_PINCM89[PF] Bits */ +#define IOMUX_PINCM89_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM89_PF_GPIOC_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM89_PF_TIMG9_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM89_PF_UART6_TX ((uint32_t)0X00000008) + +/* IOMUX_PINCM90[PF] Bits */ +#define IOMUX_PINCM90_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM90_PF_GPIOC_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM90_PF_TIMG9_IDX ((uint32_t)0X00000007) +#define IOMUX_PINCM90_PF_UART6_CTS ((uint32_t)0X00000008) + +/* IOMUX_PINCM91[PF] Bits */ +#define IOMUX_PINCM91_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM91_PF_GPIOC_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM91_PF_CANFD1_CANTX ((uint32_t)0X00000007) +#define IOMUX_PINCM91_PF_UART6_RTS ((uint32_t)0X00000008) + +/* IOMUX_PINCM92[PF] Bits */ +#define IOMUX_PINCM92_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM92_PF_GPIOC_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM92_PF_CANFD1_CANRX ((uint32_t)0X00000007) + +/* IOMUX_PINCM93[PF] Bits */ +#define IOMUX_PINCM93_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM93_PF_GPIOC_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM93_PF_UART5_RX ((uint32_t)0X00000007) + +/* IOMUX_PINCM94[PF] Bits */ +#define IOMUX_PINCM94_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM94_PF_GPIOC_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM94_PF_UART5_TX ((uint32_t)0X00000007) + + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*@}*/ /* end of group MSPM0G352X_PeripheralDecl */ + +/*@}*/ /* end of group MSPM0G352X_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_m0p_mspm0g352x__include */ + diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g511x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g511x.h new file mode 100644 index 0000000..764a4ac --- /dev/null +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g511x.h @@ -0,0 +1,1303 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_m0p_mspm0g511x__include +#define ti_devices_msp_m0p_mspm0g511x__include + +/* Filename: mspm0g511x.h */ +/* Revised: 2024-12-23 19:16:39*/ + +/* Use standard integer types with explicit width */ +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup MSPM0G511X_Definitions MSPM0G511X Definitions + This file defines all structures and symbols for MSPM0G511X + @{ +*/ + +/** @addtogroup MSPM0G511X_CMSIS Device CMSIS Definitions + Configuration of the Processor and Core Peripherals + @{ +*/ +/****************************************************************************** +* Interrupt Definitions * +******************************************************************************/ +typedef enum IRQn +{ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + DEBUGSS_INT_IRQn = 0, /* 16 DEBUGSS_INT Interrupt */ + WWDT0_INT_IRQn = 0, /* 16 WWDT0_INT Interrupt */ + WWDT1_INT_IRQn = 0, /* 16 WWDT1_INT Interrupt */ + SYSCTL_INT_IRQn = 0, /* 16 SYSCTL_INT Interrupt */ + FLASHCTL_INT_IRQn = 0, /* 16 FLASHCTL_INT Interrupt */ + COMP0_INT_IRQn = 1, /* 17 COMP0_INT Interrupt */ + GPIOA_INT_IRQn = 1, /* 17 GPIOA_INT Interrupt */ + GPIOB_INT_IRQn = 1, /* 17 GPIOB_INT Interrupt */ + TIMB0_INT_IRQn = 2, /* 18 TIMB0_INT Interrupt */ + ADC0_INT_IRQn = 4, /* 20 ADC0_INT Interrupt */ + USBFS0_INT_IRQn = 6, /* 22 USBFS0_INT Interrupt */ + UC0_INT_IRQn = 9, /* 25 UC0_INT Interrupt */ + UC1_INT_IRQn = 10, /* 26 UC1_INT Interrupt */ + I2S0_INT_IRQn = 11, /* 27 I2S0_INT Interrupt */ + UC2_INT_IRQn = 13, /* 29 UC2_INT Interrupt */ + UC3_INT_IRQn = 14, /* 30 UC3_INT Interrupt */ + TIMG0_INT_IRQn = 16, /* 32 TIMG0_INT Interrupt */ + TIMG6_INT_IRQn = 17, /* 33 TIMG6_INT Interrupt */ + TIMA0_INT_IRQn = 18, /* 34 TIMA0_INT Interrupt */ + TIMG7_INT_IRQn = 20, /* 36 TIMG7_INT Interrupt */ + AESADV_INT_IRQn = 28, /* 44 AESADV_INT Interrupt */ + LFSS_INT_IRQn = 30, /* 46 LFSS_INT Interrupt */ + RTC_B_INT_IRQn = 30, /* 46 RTC_B_INT Interrupt */ + DMA_INT_IRQn = 31, /* 47 DMA_INT Interrupt */ +} IRQn_Type; + +#define NonMaskableInt_VECn 2 /* Non Maskable Interrupt */ +#define HardFault_VECn 3 /* Hard Fault Interrupt */ +#define SVCall_VECn 11 /* SV Call Interrupt */ +#define PendSV_VECn 14 /* Pend SV Interrupt */ +#define SysTick_VECn 15 /* System Tick Interrupt */ +#define DEBUGSS_INT_VECn 16 /* DEBUGSS_INT Interrupt */ +#define WWDT0_INT_VECn 16 /* WWDT0_INT Interrupt */ +#define WWDT1_INT_VECn 16 /* WWDT1_INT Interrupt */ +#define SYSCTL_INT_VECn 16 /* SYSCTL_INT Interrupt */ +#define FLASHCTL_INT_VECn 16 /* FLASHCTL_INT Interrupt */ +#define COMP0_INT_VECn 17 /* COMP0_INT Interrupt */ +#define GPIOA_INT_VECn 17 /* GPIOA_INT Interrupt */ +#define GPIOB_INT_VECn 17 /* GPIOB_INT Interrupt */ +#define TIMB0_INT_VECn 18 /* TIMB0_INT Interrupt */ +#define ADC0_INT_VECn 20 /* ADC0_INT Interrupt */ +#define USBFS0_INT_VECn 22 /* USBFS0_INT Interrupt */ +#define UC0_INT_VECn 25 /* UC0_INT Interrupt */ +#define UC1_INT_VECn 26 /* UC1_INT Interrupt */ +#define I2S0_INT_VECn 27 /* I2S0_INT Interrupt */ +#define UC2_INT_VECn 29 /* UC2_INT Interrupt */ +#define UC3_INT_VECn 30 /* UC3_INT Interrupt */ +#define TIMG0_INT_VECn 32 /* TIMG0_INT Interrupt */ +#define TIMG6_INT_VECn 33 /* TIMG6_INT Interrupt */ +#define TIMA0_INT_VECn 34 /* TIMA0_INT Interrupt */ +#define TIMG7_INT_VECn 36 /* TIMG7_INT Interrupt */ +#define AESADV_INT_VECn 44 /* AESADV_INT Interrupt */ +#define LFSS_INT_VECn 46 /* LFSS_INT Interrupt */ +#define RTC_B_INT_VECn 46 /* RTC_B_INT Interrupt */ +#define DMA_INT_VECn 47 /* DMA_INT Interrupt */ + + +/****************************************************************************** +* Ignore unused variables * +******************************************************************************/ + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/****************************************************************************** +* Processor and Core Peripheral Section * +******************************************************************************/ + +#define __CM0PLUS_REV 0x0001U /* Core revision */ +#define __MPU_PRESENT 0x0001U /* MPU present */ +#define __VTOR_PRESENT 0x0001U /* VTOR present */ +#define __NVIC_PRIO_BITS 0x0002U /* Number of bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0plus.h" /* Processor and core peripherals */ + +/****************************************************************************** +* Peripheral headers * +******************************************************************************/ +/** @addtogroup MSPM0G511X_Peripherals MSPM0G511X Peripherals + MSPM0G511X Peripheral registers structures + @{ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __MSPM0_HAS_ADC12__ +#define __MSPM0_HAS_AESADV__ +#define __MSPM0_HAS_COMP__ +#define __MSPM0_HAS_CRCP__ +#define __MSPM0_HAS_GPIO__ +#define __MSPM0_HAS_TIMER_A__ +#define __MSPM0_HAS_TIMER_G__ +#define __MSPM0_HAS_TIMER_B__ +#define __MSPM0_HAS_KEYSTORE_CTL__ +#define __MSPM0_HAS_LFSS__ +#define __MSPM0_HAS_RTC_B__ +#define __MSPM0_HAS_IWDT__ +#define __MSPM0_HAS_VREF__ +#define __MSPM0_HAS_WWDT__ + +#define __MSPM0_HAS_I2S__ +#define __MCU_HAS_SPGSS__ +#define __MCU_HAS_UNICOMM__ +#define __MCU_HAS_UNICOMMUART__ +#define __MCU_HAS_UNICOMMI2CC__ +#define __MCU_HAS_UNICOMMI2CT__ +#define __MCU_HAS_UNICOMMSPI__ +#define __MSPM0_HAS_USB__ +#define __MSPM0_HAS_ECC__ + +/*@}*/ /* end of group MSPM0G511X_Peripherals */ + +/****************************************************************************** +* Device and peripheral memory map * +******************************************************************************/ +/** @addtogroup MSPM0G511X_MemoryMap MSPM0G511X Memory Mapping + @{ +*/ + +#define COMP0_BASE (0x40008000U) /*!< Base address of module COMP0 */ +#define VREF_BASE (0x40030000U) /*!< Base address of module VREF */ +#define WWDT0_BASE (0x40080000U) /*!< Base address of module WWDT0 */ +#define WWDT1_BASE (0x40082000U) /*!< Base address of module WWDT1 */ +#define TIMG0_BASE (0x40084000U) /*!< Base address of module TIMG0 */ +#define LFSS_BASE (0x40094000U) /*!< Base address of module LFSS */ +#define RTC_B_BASE (0x40094000U) /*!< Base address of module RTC_B */ +#define IWDT_BASE (0x40094000U) /*!< Base address of module IWDT */ +#define GPIOA_BASE (0x400A0000U) /*!< Base address of module GPIOA */ +#define GPIOB_BASE (0x400A2000U) /*!< Base address of module GPIOB */ +#define KEYSTORECTL_BASE (0x400AC000U) /*!< Base address of module KEYSTORECTL */ +#define SYSCTL_BASE (0x400AF000U) /*!< Base address of module SYSCTL */ +#define TIMB0_BASE (0x400B8000U) /*!< Base address of module TIMB0 */ +#define DEBUGSS_BASE (0x400C7000U) /*!< Base address of module DEBUGSS */ +#define EVENTLP_BASE (0x400C9000U) /*!< Base address of module EVENTLP */ +#define FLASHCTL_BASE (0x400CD000U) /*!< Base address of module FLASHCTL */ +#define CPUSS_BASE (0x40400000U) /*!< Base address of module CPUSS */ +#define WUC_BASE (0x40424000U) /*!< Base address of module WUC */ +#define IOMUX_BASE (0x40428000U) /*!< Base address of module IOMUX */ +#define DMA_BASE (0x4042A000U) /*!< Base address of module DMA */ +#define CRCP0_BASE (0x40440000U) /*!< Base address of module CRCP0 */ +#define AESADV_BASE (0x40442000U) /*!< Base address of module AESADV */ +#define I2S0_BASE (0x4047B000U) /*!< Base address of module I2S0 */ +#define USBFS0_BASE (0x4047F000U) /*!< Base address of module USBFS0 */ +#define ADC0_BASE (0x40004000U) /*!< Base address of module ADC0 */ +#define ADC0_SVT_BASE (0x4055A000U) /*!< Base address of module ADC0_SVT */ +#define TIMA0_BASE (0x40860000U) /*!< Base address of module TIMA0 */ +#define TIMG6_BASE (0x40868000U) /*!< Base address of module TIMG6 */ +#define TIMG7_BASE (0x4086A000U) /*!< Base address of module TIMG7 */ +#define UC0_UART_BASE (0x40A00000U) /*!< Base address of module UC0_UART */ +#define UC1_UART_BASE (0x40A02000U) /*!< Base address of module UC1_UART */ +#define UC0_I2CC_BASE (0x40A20000U) /*!< Base address of module UC0_I2CC */ +#define UC1_I2CC_BASE (0x40A22000U) /*!< Base address of module UC1_I2CC */ +#define UC0_I2CT_BASE (0x40A40000U) /*!< Base address of module UC0_I2CT */ +#define UC1_I2CT_BASE (0x40A42000U) /*!< Base address of module UC1_I2CT */ +#define UC0_BASE (0x40A80000U) /*!< Base address of module UC0 */ +#define UC1_BASE (0x40A82000U) /*!< Base address of module UC1 */ +#define SPG0_BASE (0x40A9F000U) /*!< Base address of module SPG0 */ +#define UC3_UART_BASE (0x40B02000U) /*!< Base address of module UC3_UART */ +#define UC2_SPI_BASE (0x40B60000U) /*!< Base address of module UC2_SPI */ +#define UC3_SPI_BASE (0x40B62000U) /*!< Base address of module UC3_SPI */ +#define UC2_BASE (0x40B80000U) /*!< Base address of module UC2 */ +#define UC3_BASE (0x40B82000U) /*!< Base address of module UC3 */ +#define SPG1_BASE (0x40B9F000U) /*!< Base address of module SPG1 */ +#define FACTORYREGION_BASE (0x41C40000U) /*!< Base address of module FACTORYREGION */ + +#define UC_UART_OFFSET (0x00080000U) /*!< UART address offset relative to UCx base address */ +#define UC_I2CC_OFFSET (0x00060000U) /*!< I2CC address offset relative to UCx base address */ +#define UC_I2CT_OFFSET (0x00040000U) /*!< I2CT address offset relative to UCx base address */ +#define UC_SPI_OFFSET (0x00020000U) /*!< SPI address offset relative to UCx base address */ + +#define UC_UART_BASE(UC_BASE) (UC_BASE - UC_UART_OFFSET) /*!< Macro to calculate base address of UNICOMMUART Regs */ +#define UC_I2CC_BASE(UC_BASE) (UC_BASE - UC_I2CC_OFFSET) /*!< Macro to calculate base address of UNICOMMI2CC Regs */ +#define UC_I2CT_BASE(UC_BASE) (UC_BASE - UC_I2CT_OFFSET) /*!< Macro to calculate base address of UNICOMMI2CT Regs */ +#define UC_SPI_BASE(UC_BASE) (UC_BASE - UC_SPI_OFFSET) /*!< Macro to calculate base address of UNICOMMSPI Regs */ + +typedef struct { + UNICOMM_Regs * const inst; + UNICOMMUART_Regs * const uart; + UNICOMMI2CC_Regs * const i2cc; + UNICOMMI2CT_Regs * const i2ct; + UNICOMMSPI_Regs * const spi; + bool const fixedMode; +} UNICOMM_Inst_Regs; + +static const UNICOMM_Inst_Regs UC0_Inst = { + .inst = ((UNICOMM_Regs *) UC0_BASE), + .uart = ((UNICOMMUART_Regs *) UC_UART_BASE(UC0_BASE)), + .i2cc = ((UNICOMMI2CC_Regs *) UC_I2CC_BASE(UC0_BASE)), + .i2ct = ((UNICOMMI2CT_Regs *) UC_I2CT_BASE(UC0_BASE)), + .fixedMode = false, +}; + +static const UNICOMM_Inst_Regs UC1_Inst = { + .inst = ((UNICOMM_Regs *) UC1_BASE), + .uart = ((UNICOMMUART_Regs *) UC_UART_BASE(UC1_BASE)), + .i2cc = ((UNICOMMI2CC_Regs *) UC_I2CC_BASE(UC1_BASE)), + .i2ct = ((UNICOMMI2CT_Regs *) UC_I2CT_BASE(UC1_BASE)), + .fixedMode = false, +}; + +static const UNICOMM_Inst_Regs UC2_Inst = { + .inst = ((UNICOMM_Regs *) UC2_BASE), + .spi = ((UNICOMMSPI_Regs *) UC_SPI_BASE(UC2_BASE)), + .fixedMode = true, +}; + +static const UNICOMM_Inst_Regs UC3_Inst = { + .inst = ((UNICOMM_Regs *) UC3_BASE), + .uart = ((UNICOMMUART_Regs *) UC_UART_BASE(UC3_BASE)), + .spi = ((UNICOMMSPI_Regs *) UC_SPI_BASE(UC3_BASE)), + .fixedMode = false, +}; + +/*@}*/ /* end of group MSPM0G511X_MemoryMap */ + +/****************************************************************************** +* Peripheral declarations * +******************************************************************************/ +/** @addtogroup MSPM0G511X_PeripheralDecl MSPM0G511X Peripheral Declaration + @{ +*/ + +static LFSS_Regs * const LFSS = ((LFSS_Regs *) LFSS_BASE); +static RTC_Regs * const RTC_B = ((RTC_Regs *) RTC_B_BASE); +static DEBUGSS_Regs * const DEBUGSS = ((DEBUGSS_Regs *) DEBUGSS_BASE); +static KEYSTORECTL_Regs * const KEYSTORECTL = ((KEYSTORECTL_Regs *) KEYSTORECTL_BASE); +static AESADV_Regs * const AESADV = ((AESADV_Regs *) AESADV_BASE); +static WWDT_Regs * const WWDT0 = ((WWDT_Regs *) WWDT0_BASE); +static GPTIMER_Regs * const TIMG0 = ((GPTIMER_Regs *) TIMG0_BASE); +static CRCP_Regs * const CRCP0 = ((CRCP_Regs *) CRCP0_BASE); +static CRCP_Regs * const CRC0 = ((CRCP_Regs *) CRCP0_BASE); +static CRCP_Regs * const CRC = ((CRCP_Regs *) CRCP0_BASE); +static VREF_Regs * const VREF = ((VREF_Regs *) VREF_BASE); +static COMP_Regs * const COMP0 = ((COMP_Regs *) COMP0_BASE); +static GPIO_Regs * const GPIOA = ((GPIO_Regs *) GPIOA_BASE); +static WWDT_Regs * const WWDT1 = ((WWDT_Regs *) WWDT1_BASE); +static GPIO_Regs * const GPIOB = ((GPIO_Regs *) GPIOB_BASE); +static CPUSS_Regs * const CPUSS = ((CPUSS_Regs *) CPUSS_BASE); +static IOMUX_Regs * const IOMUX = ((IOMUX_Regs *) IOMUX_BASE); +static GPTIMER_Regs * const TIMA0 = ((GPTIMER_Regs *) TIMA0_BASE); +static GPTIMER_Regs * const TIMG6 = ((GPTIMER_Regs *) TIMG6_BASE); +static GPTIMER_Regs * const TIMG7 = ((GPTIMER_Regs *) TIMG7_BASE); +static DMA_Regs * const DMA = ((DMA_Regs *) DMA_BASE); +static SYSCTL_Regs * const SYSCTL = ((SYSCTL_Regs *) SYSCTL_BASE); +static WUC_Regs * const WUC = ((WUC_Regs *) WUC_BASE); +static FLASHCTL_Regs * const FLASHCTL = ((FLASHCTL_Regs *) FLASHCTL_BASE); +static I2S_Regs * const I2S0 = ((I2S_Regs *) I2S0_BASE); +static FACTORYREGION_OPEN_Regs * const FACTORYREGION = ((FACTORYREGION_OPEN_Regs *) FACTORYREGION_BASE); +static BTIMER_Regs * const TIMB0 = ((BTIMER_Regs *) TIMB0_BASE); +static USB_Regs * const USBFS0 = ((USB_Regs *) USBFS0_BASE); +static SPGSS_Regs * const SPG1 = ((SPGSS_Regs *) SPG1_BASE); +static ADC12_Regs * const ADC0 = ((ADC12_Regs *) ADC0_BASE); +static ADC12_PERIPHERALREGIONSVT_Regs * const ADC0_SVT = ((ADC12_PERIPHERALREGIONSVT_Regs *) ADC0_SVT_BASE); +static SPGSS_Regs * const SPG0 = ((SPGSS_Regs *) SPG0_BASE); + +static UNICOMM_Inst_Regs * const UC0 = (UNICOMM_Inst_Regs *) &UC0_Inst; +static UNICOMM_Inst_Regs * const UC1 = (UNICOMM_Inst_Regs *) &UC1_Inst; +static UNICOMM_Inst_Regs * const UC2 = (UNICOMM_Inst_Regs *) &UC2_Inst; +static UNICOMM_Inst_Regs * const UC3 = (UNICOMM_Inst_Regs *) &UC3_Inst; + +/****************************************************************************** +* SYS parameters * +******************************************************************************/ + +#define ADC_SYS_NUM_ANALOG_CHAN (16) /* !< Number of analog channels. */ +#define BTIM_SYS_NUM_COUNTERS (4) /* !< Max number of counters. */ +#define CRCP_SYS_CRC32_ENABLE (1) /* !< Parameter to exclude or include 32-bit CRC. */ +#define DMA_SYS_N_DMA_CHANNEL (12) /* !< Number of DMA channels implemented in DMA. */ +#define DMA_SYS_N_DMA_FULL_CHANNEL (6) /* !< Number of FULL-DMA channels implemented in DMA. If + SYS_N_DMA_CHANNEL is larger than SYS_N_DMA_FULL_CHANNEL, the + remaining channel will be BASIC channel with limited functionality. */ +#define DMA_SYS_MMR_AUTO (1) /* !< Boolean for if auto enable channels implemented in DMA. */ +#define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ +#define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ +#define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word: Minimum: 64 Maximum: + 128 */ +#define FLASHCTL_SYS_WEPROTBWIDTH (16) /* !< Bit width of WEPROTB register. */ +#define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register. */ +#define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register. */ +#define I2S0_SYS_FENTRIES (4) /* !< Number of FIFO entries */ +#define I2S0_SYS_SINGLE_PIN (0) /* !< Boolean for if enable single Data Pin configuration. */ +#define SPI0_SYS_FENTRIES (4) /* !< The number of entries in RX and TX FIFO */ +#define SPI1_SYS_FENTRIES (4) /* !< The number of entries in RX and TX FIFO */ +#define SPG0_SYS_FENTRIES (4) /* !< The number of entries in RX and TX FIFO */ +#define COMP_SYS_DACOUT_EN (1) /* !< Boolean for if 8-bit DAC output to pin is available */ +#define VREF_SYS_INT_ADC_REF (1) /* !< Supports internal voltage reference for ADCs. */ + +#define UC0_UART_SYS_GLITCH_FILTER (0) +#define UC0_UART_SYS_HW_FLOW_CONTROL (1) +#define UC0_UART_SYS_9_BIT (1) +#define UC0_UART_SYS_RS485 (1) +#define UC0_UART_SYS_LIN (1) +#define UC0_UART_SYS_DALI (1) +#define UC0_UART_SYS_IRDA (1) +#define UC0_UART_SYS_SMART_CARD (1) +#define UC0_UART_SYS_MANCHESTER_ENCODING (1) +#define UC0_UART_SYS_FIFO_LENGTH (4) + +#define UC1_UART_SYS_GLITCH_FILTER (0) +#define UC1_UART_SYS_HW_FLOW_CONTROL (1) +#define UC1_UART_SYS_9_BIT (1) +#define UC1_UART_SYS_RS485 (1) +#define UC1_UART_SYS_LIN (1) +#define UC1_UART_SYS_DALI (0) +#define UC1_UART_SYS_IRDA (0) +#define UC1_UART_SYS_SMART_CARD (0) +#define UC1_UART_SYS_MANCHESTER_ENCODING (0) +#define UC1_UART_SYS_FIFO_LENGTH (4) + +#define UC3_UART_SYS_GLITCH_FILTER (0) +#define UC3_UART_SYS_HW_FLOW_CONTROL (1) +#define UC3_UART_SYS_9_BIT (1) +#define UC3_UART_SYS_RS485 (1) +#define UC3_UART_SYS_LIN (0) +#define UC3_UART_SYS_DALI (0) +#define UC3_UART_SYS_IRDA (0) +#define UC3_UART_SYS_SMART_CARD (0) +#define UC3_UART_SYS_MANCHESTER_ENCODING (0) +#define UC3_UART_SYS_FIFO_LENGTH (4) + +/* UART driver config settings */ +#define UC_UART_SYS_GLITCH_FILTER (0) +#define UC_UART_SYS_HW_FLOW_CONTROL (1) +#define UC_UART_SYS_9_BIT (1) +#define UC_UART_SYS_RS485 (1) +#define UC_UART_SYS_LIN (1) +#define UC_UART_SYS_DALI (1) +#define UC_UART_SYS_IRDA (1) +#define UC_UART_SYS_SMART_CARD (1) +#define UC_UART_SYS_MANCHESTER_ENCODING (1) +#define UC_UART_SYS_FIFO_LENGTH (4) +#define UC_UART_SYS_BUSCLK (1) +#define UC_UART_SYS_MFCLK (1) +#define UC_UART_SYS_LFCLK (1) +#define UC_UART_SYS_ASYNC_LFCLK (0) +#define UC_UART_SYS_ASYNC_SYSCLK (0) +#define UC_UART_SYS_ASYNC_HFCLK (0) +#define UC_UART_SYS_ASYNC_PLL (0) + +/****************************************************************************** +* DMA Triggers * +******************************************************************************/ + +/* External DMA Triggers */ +#define DMA_SOFTWARE_TRIG (0) +#define DMA_AESADV_AES_0_TRIG (3) +#define DMA_AESADV_AES_1_TRIG (4) +#define DMA_UC0_RX_BD_TRIG (5) +#define DMA_UC0_TX_BD_TRIG (6) +#define DMA_UC1_RX_BD_TRIG (7) +#define DMA_UC1_TX_BD_TRIG (8) +#define DMA_UC2_RX_BD_TRIG (9) +#define DMA_UC2_TX_BD_TRIG (10) +#define DMA_UC3_RX_BD_TRIG (11) +#define DMA_UC3_TX_BD_TRIG (12) +#define DMA_I2S0_RX_TRIG (13) +#define DMA_I2S0_TX_TRIG (14) +#define DMA_USBFS0_EVT_0_TRIG (15) +#define DMA_USBFS0_EVT_1_TRIG (16) +#define DMA_USBFS0_EVT_2_TRIG (17) +#define DMA_USBFS0_EVT_3_TRIG (18) +#define DMA_USBFS0_EVT_4_TRIG (19) +#define DMA_USBFS0_EVT_5_TRIG (20) +#define DMA_USBFS0_EVT_6_TRIG (21) +#define DMA_USBFS0_EVT_7_TRIG (22) +#define DMA_ADC0_EVT_GEN_BD_TRIG (23) + +/* Internal DMA Triggers */ +#define DMA_CH_0_TRIG (0) +#define DMA_CH_1_TRIG (1) +#define DMA_CH_2_TRIG (2) +#define DMA_CH_3_TRIG (3) +#define DMA_CH_4_TRIG (4) +#define DMA_CH_5_TRIG (5) +#define DMA_CH_6_TRIG (6) +#define DMA_CH_7_TRIG (7) +#define DMA_CH_8_TRIG (8) +#define DMA_CH_9_TRIG (9) +#define DMA_CH_10_TRIG (10) +#define DMA_CH_11_TRIG (11) + + +/****************************************************************************** +* IOMUX Pin Definitions * +******************************************************************************/ + +typedef enum IOMUX_PINCM +{ + IOMUX_PINCM1 = (0), + IOMUX_PINCM2 = (1), + IOMUX_PINCM3 = (2), + IOMUX_PINCM4 = (3), + IOMUX_PINCM5 = (4), + IOMUX_PINCM6 = (5), + IOMUX_PINCM7 = (6), + IOMUX_PINCM8 = (7), + IOMUX_PINCM9 = (8), + IOMUX_PINCM10 = (9), + IOMUX_PINCM11 = (10), + IOMUX_PINCM12 = (11), + IOMUX_PINCM13 = (12), + IOMUX_PINCM14 = (13), + IOMUX_PINCM15 = (14), + IOMUX_PINCM16 = (15), + IOMUX_PINCM17 = (16), + IOMUX_PINCM18 = (17), + IOMUX_PINCM19 = (18), + IOMUX_PINCM20 = (19), + IOMUX_PINCM21 = (20), + IOMUX_PINCM22 = (21), + IOMUX_PINCM23 = (22), + IOMUX_PINCM24 = (23), + IOMUX_PINCM25 = (24), + IOMUX_PINCM26 = (25), + IOMUX_PINCM27 = (26), + IOMUX_PINCM28 = (27), + IOMUX_PINCM29 = (28), + IOMUX_PINCM30 = (29), + IOMUX_PINCM31 = (30), + IOMUX_PINCM32 = (31), + IOMUX_PINCM33 = (32), + IOMUX_PINCM34 = (33), + IOMUX_PINCM35 = (34), + IOMUX_PINCM36 = (35), + IOMUX_PINCM37 = (36), + IOMUX_PINCM38 = (37), + IOMUX_PINCM39 = (38), + IOMUX_PINCM40 = (39), + IOMUX_PINCM41 = (40), + IOMUX_PINCM42 = (41), + IOMUX_PINCM43 = (42), + IOMUX_PINCM44 = (43), + IOMUX_PINCM45 = (44), + IOMUX_PINCM46 = (45), + IOMUX_PINCM47 = (46), + IOMUX_PINCM48 = (47), + IOMUX_PINCM49 = (48), + IOMUX_PINCM50 = (49), + IOMUX_PINCM51 = (50), + IOMUX_PINCM52 = (51), + IOMUX_PINCM53 = (52), + IOMUX_PINCM54 = (53), + IOMUX_PINCM55 = (54), + IOMUX_PINCM56 = (55), + IOMUX_PINCM57 = (56), + IOMUX_PINCM58 = (57), + IOMUX_PINCM59 = (58), +} IOMUX_PINCM; + + +/* IOMUX_PINCM1[PF] Bits */ +#define IOMUX_PINCM1_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM1_PF_GPIOA_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM1_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_SYSCTL_FCC_IN ((uint32_t)0X00000003) +#define IOMUX_PINCM1_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM1_PF_TIMG0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM1_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM1_PF_UC0_SDA ((uint32_t)0X00000007) +#define IOMUX_PINCM1_PF_UC0_TX ((uint32_t)0X00000007) + +/* IOMUX_PINCM2[PF] Bits */ +#define IOMUX_PINCM2_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM2_PF_GPIOA_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM2_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM2_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM2_PF_TIMG0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM2_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM2_PF_UC0_SCL ((uint32_t)0X00000007) +#define IOMUX_PINCM2_PF_UC0_RX ((uint32_t)0X00000007) + +/* IOMUX_PINCM3[PF] Bits */ +#define IOMUX_PINCM3_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM3_PF_GPIOA_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM3_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_TIMA0_CCP1 ((uint32_t)0X00000003) +#define IOMUX_PINCM3_PF_TIMA0_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM3_PF_TIMG7_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM3_PF_TIMA_FAULT0 ((uint32_t)0X00000006) +#define IOMUX_PINCM3_PF_UC0_SDA ((uint32_t)0X00000007) +#define IOMUX_PINCM3_PF_UC0_TX ((uint32_t)0X00000007) + +/* IOMUX_PINCM4[PF] Bits */ +#define IOMUX_PINCM4_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM4_PF_GPIOA_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM4_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_UC1_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM4_PF_UC2_CS3 ((uint32_t)0X00000004) +#define IOMUX_PINCM4_PF_TIMG6_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM4_PF_UC0_CTS ((uint32_t)0X00000006) + +/* IOMUX_PINCM5[PF] Bits */ +#define IOMUX_PINCM5_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM5_PF_GPIOA_DIO30 ((uint32_t)0X00000001) +#define IOMUX_PINCM5_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_UC1_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM5_PF_UC2_CS2 ((uint32_t)0X00000004) +#define IOMUX_PINCM5_PF_TIMG6_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM5_PF_UC0_RTS ((uint32_t)0X00000006) + +/* IOMUX_PINCM6[PF] Bits */ +#define IOMUX_PINCM6_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM6_PF_GPIOA_DIO31 ((uint32_t)0X00000001) +#define IOMUX_PINCM6_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM6_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM6_PF_TIMG7_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM6_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM6_PF_UC0_SCL ((uint32_t)0X00000007) +#define IOMUX_PINCM6_PF_UC0_RX ((uint32_t)0X00000007) + +/* IOMUX_PINCM7[PF] Bits */ +#define IOMUX_PINCM7_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM7_PF_GPIOA_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM7_PF_UC1_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM7_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_TIMG7_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM7_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM7_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM7_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM7_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM7_PF_TIMA_FAULT1 ((uint32_t)0X00000009) +#define IOMUX_PINCM7_PF_UC3_CS0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM7_PF_UC3_CTS ((uint32_t)0X0000000A) + +/* IOMUX_PINCM8[PF] Bits */ +#define IOMUX_PINCM8_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM8_PF_GPIOA_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM8_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM8_PF_UC2_CS3 ((uint32_t)0X00000004) +#define IOMUX_PINCM8_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM8_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM8_PF_TIMG7_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM8_PF_TIMA0_CCP2 ((uint32_t)0X00000008) +#define IOMUX_PINCM8_PF_UC1_CTS ((uint32_t)0X00000009) + +/* IOMUX_PINCM9[PF] Bits */ +#define IOMUX_PINCM9_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM9_PF_GPIOA_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM9_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_UC2_CS0 ((uint32_t)0X00000004) +#define IOMUX_PINCM9_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM9_PF_SYSCTL_LFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM9_PF_TIMG7_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM9_PF_TIMA0_CCP3 ((uint32_t)0X00000008) + +/* IOMUX_PINCM10[PF] Bits */ +#define IOMUX_PINCM10_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM10_PF_GPIOA_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM10_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_UC0_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM10_PF_TIMG0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM10_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM10_PF_TIMG6_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM10_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM10_PF_UC3_POCI ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_UC3_RTS ((uint32_t)0X00000009) + +/* IOMUX_PINCM11[PF] Bits */ +#define IOMUX_PINCM11_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM11_PF_GPIOA_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM11_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM11_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM11_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_UC0_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM11_PF_TIMG0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM11_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM11_PF_TIMG6_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM11_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM11_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000009) +#define IOMUX_PINCM11_PF_UC3_PICO ((uint32_t)0X0000000A) +#define IOMUX_PINCM11_PF_UC3_TX ((uint32_t)0X0000000A) + +/* IOMUX_PINCM12[PF] Bits */ +#define IOMUX_PINCM12_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM12_PF_GPIOB_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM12_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM12_PF_UC0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_UC0_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM12_PF_TIMG0_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM13[PF] Bits */ +#define IOMUX_PINCM13_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM13_PF_GPIOB_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM13_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM13_PF_UC0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_UC0_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM13_PF_TIMG0_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM14[PF] Bits */ +#define IOMUX_PINCM14_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM14_PF_GPIOA_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM14_PF_UC2_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM14_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM14_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM14_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM14_PF_TIMG7_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM14_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM14_PF_TIMA0_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM14_PF_SYSCTL_FCC_IN ((uint32_t)0X00000009) + +/* IOMUX_PINCM15[PF] Bits */ +#define IOMUX_PINCM15_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM15_PF_GPIOB_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM15_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM15_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM15_PF_UC1_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM15_PF_UC1_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM15_PF_UC1_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM15_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM15_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM15_PF_UC2_PICO ((uint32_t)0X00000007) +#define IOMUX_PINCM15_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000008) + +/* IOMUX_PINCM16[PF] Bits */ +#define IOMUX_PINCM16_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM16_PF_GPIOB_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM16_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM16_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM16_PF_UC1_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM16_PF_UC1_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM16_PF_UC1_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM16_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM16_PF_TIMG6_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM16_PF_UC2_SCLK ((uint32_t)0X00000007) +#define IOMUX_PINCM16_PF_TIMA0_CCP0 ((uint32_t)0X00000008) + +/* IOMUX_PINCM17[PF] Bits */ +#define IOMUX_PINCM17_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM17_PF_GPIOB_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM17_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM17_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM17_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM17_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM17_PF_TIMG0_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM18[PF] Bits */ +#define IOMUX_PINCM18_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM18_PF_GPIOB_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM18_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM18_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM18_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM18_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM18_PF_TIMG0_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM19[PF] Bits */ +#define IOMUX_PINCM19_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM19_PF_GPIOA_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM19_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC2_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_UC0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM19_PF_UC0_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM19_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM19_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM19_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM19_PF_UC2_CS3 ((uint32_t)0X00000008) +#define IOMUX_PINCM19_PF_I2S0_WCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM19_PF_UC0_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM19_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000B) + +/* IOMUX_PINCM20[PF] Bits */ +#define IOMUX_PINCM20_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM20_PF_GPIOA_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM20_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM20_PF_UC0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM20_PF_UC0_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM20_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM20_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM20_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM20_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM20_PF_I2S0_BCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM20_PF_UC3_SCLK ((uint32_t)0X0000000A) +#define IOMUX_PINCM20_PF_UC3_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM20_PF_UC0_CTS ((uint32_t)0X0000000B) + +/* IOMUX_PINCM21[PF] Bits */ +#define IOMUX_PINCM21_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM21_PF_GPIOA_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM21_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM21_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM21_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM21_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM21_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM21_PF_TIMG0_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM21_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM21_PF_I2S0_AD0 ((uint32_t)0X00000009) +#define IOMUX_PINCM21_PF_UC3_PICO ((uint32_t)0X0000000A) +#define IOMUX_PINCM21_PF_UC3_TX ((uint32_t)0X0000000A) + +/* IOMUX_PINCM22[PF] Bits */ +#define IOMUX_PINCM22_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM22_PF_GPIOA_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM22_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM22_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM22_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM22_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM22_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM22_PF_TIMG0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM22_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM22_PF_I2S0_AD1 ((uint32_t)0X00000009) +#define IOMUX_PINCM22_PF_UC3_POCI ((uint32_t)0X0000000A) +#define IOMUX_PINCM22_PF_UC3_RTS ((uint32_t)0X0000000A) + +/* IOMUX_PINCM23[PF] Bits */ +#define IOMUX_PINCM23_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM23_PF_GPIOB_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM23_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM23_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM23_PF_UC2_CS1 ((uint32_t)0X00000004) +#define IOMUX_PINCM23_PF_TIMG6_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM23_PF_TIMA_FAULT2 ((uint32_t)0X00000006) + +/* IOMUX_PINCM24[PF] Bits */ +#define IOMUX_PINCM24_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM24_PF_GPIOB_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM24_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM24_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM24_PF_UC2_CS2 ((uint32_t)0X00000004) +#define IOMUX_PINCM24_PF_TIMG6_CCP1 ((uint32_t)0X00000005) + +/* IOMUX_PINCM25[PF] Bits */ +#define IOMUX_PINCM25_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM25_PF_GPIOB_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM25_PF_UC1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM25_PF_UC3_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_UC3_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM25_PF_TIMA0_CCP0 ((uint32_t)0X00000005) + +/* IOMUX_PINCM26[PF] Bits */ +#define IOMUX_PINCM26_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM26_PF_GPIOB_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM26_PF_UC1_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM26_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM26_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) + +/* IOMUX_PINCM27[PF] Bits */ +#define IOMUX_PINCM27_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM27_PF_GPIOB_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM27_PF_UC3_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_UC3_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM27_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM27_PF_TIMG0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM27_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM27_PF_I2S0_WCLK ((uint32_t)0X00000007) + +/* IOMUX_PINCM28[PF] Bits */ +#define IOMUX_PINCM28_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM28_PF_GPIOB_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM28_PF_UC3_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM28_PF_UC3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM28_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM28_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM28_PF_TIMG0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM28_PF_TIMG6_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM28_PF_I2S0_BCLK ((uint32_t)0X00000007) + +/* IOMUX_PINCM29[PF] Bits */ +#define IOMUX_PINCM29_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM29_PF_GPIOB_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM29_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM29_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM29_PF_UC2_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM29_PF_TIMA_FAULT1 ((uint32_t)0X00000004) +#define IOMUX_PINCM29_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM29_PF_TIMA0_CCP2 ((uint32_t)0X00000006) +#define IOMUX_PINCM29_PF_I2S0_AD0 ((uint32_t)0X00000007) + +/* IOMUX_PINCM30[PF] Bits */ +#define IOMUX_PINCM30_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM30_PF_GPIOB_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM30_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM30_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM30_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_TIMA_FAULT2 ((uint32_t)0X00000004) +#define IOMUX_PINCM30_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM30_PF_TIMA0_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM30_PF_I2S0_AD1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM31[PF] Bits */ +#define IOMUX_PINCM31_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM31_PF_GPIOB_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM31_PF_UC2_CS3 ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM31_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM31_PF_TIMA0_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM31_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM31_PF_I2S0_MCLK ((uint32_t)0X00000007) + +/* IOMUX_PINCM32[PF] Bits */ +#define IOMUX_PINCM32_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM32_PF_GPIOB_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM32_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_TIMG7_CCP0 ((uint32_t)0X00000004) + +/* IOMUX_PINCM33[PF] Bits */ +#define IOMUX_PINCM33_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM33_PF_GPIOB_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM33_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_TIMG7_CCP1 ((uint32_t)0X00000004) + +/* IOMUX_PINCM34[PF] Bits */ +#define IOMUX_PINCM34_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM34_PF_GPIOA_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM34_PF_UC3_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC3_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM34_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM34_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM34_PF_TIMG0_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM34_PF_UC1_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM34_PF_I2S0_BCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM34_PF_UC0_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM34_PF_UC2_CS0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM35[PF] Bits */ +#define IOMUX_PINCM35_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM35_PF_GPIOA_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM35_PF_UC3_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_UC3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_UC3_SCLK ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_UC3_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM35_PF_LFSS_RTC_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM35_PF_TIMG0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM35_PF_UC3_CS0 ((uint32_t)0X00000008) +#define IOMUX_PINCM35_PF_UC3_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM35_PF_I2S0_AD0 ((uint32_t)0X00000009) +#define IOMUX_PINCM35_PF_UC1_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM35_PF_UC2_CS3 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM36[PF] Bits */ +#define IOMUX_PINCM36_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM36_PF_GPIOA_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM36_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM36_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_UC3_PICO ((uint32_t)0X00000004) +#define IOMUX_PINCM36_PF_UC3_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM36_PF_TIMG7_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM36_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM36_PF_TIMG6_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM36_PF_I2S0_AD1 ((uint32_t)0X00000009) + +/* IOMUX_PINCM37[PF] Bits */ +#define IOMUX_PINCM37_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM37_PF_GPIOA_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM37_PF_UC0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM37_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM37_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM37_PF_UC1_RTS ((uint32_t)0X00000007) +#define IOMUX_PINCM37_PF_I2S0_WCLK ((uint32_t)0X00000008) + +/* IOMUX_PINCM38[PF] Bits */ +#define IOMUX_PINCM38_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM38_PF_GPIOA_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM38_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM38_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM38_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM38_PF_UC1_CTS ((uint32_t)0X00000007) +#define IOMUX_PINCM38_PF_COMP0_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM38_PF_I2S0_MCLK ((uint32_t)0X00000009) + +/* IOMUX_PINCM39[PF] Bits */ +#define IOMUX_PINCM39_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM39_PF_GPIOA_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM39_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM39_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM39_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM39_PF_TIMG7_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM39_PF_UC2_CS1 ((uint32_t)0X00000007) +#define IOMUX_PINCM39_PF_I2S0_WCLK ((uint32_t)0X00000008) + +/* IOMUX_PINCM40[PF] Bits */ +#define IOMUX_PINCM40_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM40_PF_GPIOA_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM40_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC3_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC3_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM40_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM40_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM40_PF_TIMG7_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM40_PF_UC2_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM40_PF_TIMA_FAULT2 ((uint32_t)0X00000008) +#define IOMUX_PINCM40_PF_I2S0_MCLK ((uint32_t)0X00000009) + +/* IOMUX_PINCM41[PF] Bits */ +#define IOMUX_PINCM41_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM41_PF_GPIOA_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM41_PF_DEBUGSS_SWDIO ((uint32_t)0X00000002) +#define IOMUX_PINCM41_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM41_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM41_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM41_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM41_PF_I2S0_AD0 ((uint32_t)0X00000007) + +/* IOMUX_PINCM42[PF] Bits */ +#define IOMUX_PINCM42_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM42_PF_GPIOA_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM42_PF_DEBUGSS_SWCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM42_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM42_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM42_PF_UC3_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM42_PF_UC3_CTS ((uint32_t)0X00000007) +#define IOMUX_PINCM42_PF_I2S0_AD1 ((uint32_t)0X00000008) + +/* IOMUX_PINCM43[PF] Bits */ +#define IOMUX_PINCM43_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM43_PF_GPIOB_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM43_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_TIMG0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM43_PF_TIMA0_CCP2 ((uint32_t)0X00000005) + +/* IOMUX_PINCM44[PF] Bits */ +#define IOMUX_PINCM44_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM44_PF_GPIOB_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM44_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_TIMG0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM44_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) + +/* IOMUX_PINCM45[PF] Bits */ +#define IOMUX_PINCM45_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM45_PF_GPIOB_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM45_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM45_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_TIMG7_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM45_PF_COMP0_OUT ((uint32_t)0X00000005) + +/* IOMUX_PINCM46[PF] Bits */ +#define IOMUX_PINCM46_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM46_PF_GPIOA_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM46_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM46_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM46_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM46_PF_UC1_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM46_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM46_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM46_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM46_PF_I2S0_AD0 ((uint32_t)0X00000008) + +/* IOMUX_PINCM47[PF] Bits */ +#define IOMUX_PINCM47_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM47_PF_GPIOA_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM47_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM47_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM47_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM47_PF_UC1_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM47_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM47_PF_TIMG6_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM47_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM47_PF_I2S0_BCLK ((uint32_t)0X00000008) +#define IOMUX_PINCM47_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000009) + +/* IOMUX_PINCM48[PF] Bits */ +#define IOMUX_PINCM48_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM48_PF_GPIOB_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM48_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM48_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM48_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM48_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM48_PF_UC2_CS2 ((uint32_t)0X00000004) +#define IOMUX_PINCM48_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM48_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM48_PF_TIMA0_CCP1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM49[PF] Bits */ +#define IOMUX_PINCM49_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM49_PF_GPIOB_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM49_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM49_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM49_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM49_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM49_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM49_PF_UC1_TX ((uint32_t)0X00000004) + +/* IOMUX_PINCM50[PF] Bits */ +#define IOMUX_PINCM50_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM50_PF_GPIOB_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM50_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM50_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM50_PF_UC3_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC3_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM50_PF_UC1_RX ((uint32_t)0X00000004) + +/* IOMUX_PINCM51[PF] Bits */ +#define IOMUX_PINCM51_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM51_PF_GPIOB_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM51_PF_UC1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM51_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM51_PF_COMP0_OUT ((uint32_t)0X00000005) + +/* IOMUX_PINCM52[PF] Bits */ +#define IOMUX_PINCM52_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM52_PF_GPIOB_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM52_PF_UC2_CS3 ((uint32_t)0X00000002) +#define IOMUX_PINCM52_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM52_PF_UC3_POCI ((uint32_t)0X00000004) +#define IOMUX_PINCM52_PF_UC3_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM52_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM52_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) + +/* IOMUX_PINCM53[PF] Bits */ +#define IOMUX_PINCM53_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM53_PF_GPIOA_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM53_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM53_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM53_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM53_PF_UC3_CS0 ((uint32_t)0X00000004) +#define IOMUX_PINCM53_PF_UC3_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM53_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM53_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM53_PF_TIMG7_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM53_PF_I2S0_WCLK ((uint32_t)0X00000008) + +/* IOMUX_PINCM54[PF] Bits */ +#define IOMUX_PINCM54_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM54_PF_GPIOA_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM54_PF_UC3_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM54_PF_UC3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM54_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM54_PF_UC3_SCLK ((uint32_t)0X00000004) +#define IOMUX_PINCM54_PF_UC3_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM54_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM54_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM54_PF_TIMG7_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM54_PF_I2S0_AD1 ((uint32_t)0X00000008) + +/* IOMUX_PINCM55[PF] Bits */ +#define IOMUX_PINCM55_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM55_PF_GPIOA_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM55_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM55_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM55_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM55_PF_UC3_PICO ((uint32_t)0X00000004) +#define IOMUX_PINCM55_PF_UC3_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM55_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM55_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM55_PF_COMP0_OUT ((uint32_t)0X00000007) + +/* IOMUX_PINCM56[PF] Bits */ +#define IOMUX_PINCM56_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM56_PF_GPIOB_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM56_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM56_PF_UC2_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM56_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM56_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM56_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM56_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM56_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/* IOMUX_PINCM57[PF] Bits */ +#define IOMUX_PINCM57_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM57_PF_GPIOB_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM57_PF_UC0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM57_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM57_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM57_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM57_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM57_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM57_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/* IOMUX_PINCM58[PF] Bits */ +#define IOMUX_PINCM58_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM58_PF_GPIOA_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM58_PF_UC0_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM58_PF_UC0_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM58_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM58_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM58_PF_TIMG7_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM58_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM58_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM58_PF_UC3_PICO ((uint32_t)0X00000008) +#define IOMUX_PINCM58_PF_UC3_TX ((uint32_t)0X00000008) + +/* IOMUX_PINCM59[PF] Bits */ +#define IOMUX_PINCM59_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM59_PF_GPIOA_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM59_PF_UC0_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM59_PF_UC0_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM59_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM59_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM59_PF_TIMG7_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM59_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM59_PF_LFSS_RTC_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM59_PF_COMP0_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM59_PF_UC3_SCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM59_PF_UC3_RX ((uint32_t)0X00000009) +#define IOMUX_PINCM59_PF_TIMA_FAULT2 ((uint32_t)0X0000000A) + + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*@}*/ /* end of group MSPM0G511X_PeripheralDecl */ + +/*@}*/ /* end of group MSPM0G511X_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_m0p_mspm0g511x__include */ diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0g518x.h b/mspm0/source/ti/devices/msp/m0p/mspm0g518x.h new file mode 100644 index 0000000..5851aa5 --- /dev/null +++ b/mspm0/source/ti/devices/msp/m0p/mspm0g518x.h @@ -0,0 +1,1339 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_m0p_mspm0g518x__include +#define ti_devices_msp_m0p_mspm0g518x__include + +/* Filename: mspm0g518x.h */ +/* Revised: 2024-12-23 19:16:39*/ + +/* Use standard integer types with explicit width */ +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup MSPM0G518X_Definitions MSPM0G518X Definitions + This file defines all structures and symbols for MSPM0G518X + @{ +*/ + +/** @addtogroup MSPM0G518X_CMSIS Device CMSIS Definitions + Configuration of the Processor and Core Peripherals + @{ +*/ +/****************************************************************************** +* Interrupt Definitions * +******************************************************************************/ +typedef enum IRQn +{ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + DEBUGSS_INT_IRQn = 0, /* 16 DEBUGSS_INT Interrupt */ + WWDT0_INT_IRQn = 0, /* 16 WWDT0_INT Interrupt */ + WWDT1_INT_IRQn = 0, /* 16 WWDT1_INT Interrupt */ + SYSCTL_INT_IRQn = 0, /* 16 SYSCTL_INT Interrupt */ + FLASHCTL_INT_IRQn = 0, /* 16 FLASHCTL_INT Interrupt */ + COMP0_INT_IRQn = 1, /* 17 COMP0_INT Interrupt */ + GPIOA_INT_IRQn = 1, /* 17 GPIOA_INT Interrupt */ + GPIOB_INT_IRQn = 1, /* 17 GPIOB_INT Interrupt */ + TIMB0_INT_IRQn = 2, /* 18 TIMB0_INT Interrupt */ + ADC0_INT_IRQn = 4, /* 20 ADC0_INT Interrupt */ + USBFS0_INT_IRQn = 6, /* 22 USBFS0_INT Interrupt */ + UC0_INT_IRQn = 9, /* 25 UC0_INT Interrupt */ + UC1_INT_IRQn = 10, /* 26 UC1_INT Interrupt */ + I2S0_INT_IRQn = 11, /* 27 I2S0_INT Interrupt */ + NPU_INT_IRQn = 12, /* 28 NPU_INT Interrupt */ + UC2_INT_IRQn = 13, /* 29 UC2_INT Interrupt */ + UC3_INT_IRQn = 14, /* 30 UC3_INT Interrupt */ + TIMG0_INT_IRQn = 16, /* 32 TIMG0_INT Interrupt */ + TIMG6_INT_IRQn = 17, /* 33 TIMG6_INT Interrupt */ + TIMA0_INT_IRQn = 18, /* 34 TIMA0_INT Interrupt */ + TIMG7_INT_IRQn = 20, /* 36 TIMG7_INT Interrupt */ + AESADV_INT_IRQn = 28, /* 44 AESADV_INT Interrupt */ + LFSS_INT_IRQn = 30, /* 46 LFSS_INT Interrupt */ + RTC_B_INT_IRQn = 30, /* 46 RTC_B_INT Interrupt */ + DMA_INT_IRQn = 31, /* 47 DMA_INT Interrupt */ +} IRQn_Type; + +#define NonMaskableInt_VECn 2 /* Non Maskable Interrupt */ +#define HardFault_VECn 3 /* Hard Fault Interrupt */ +#define SVCall_VECn 11 /* SV Call Interrupt */ +#define PendSV_VECn 14 /* Pend SV Interrupt */ +#define SysTick_VECn 15 /* System Tick Interrupt */ +#define DEBUGSS_INT_VECn 16 /* DEBUGSS_INT Interrupt */ +#define WWDT0_INT_VECn 16 /* WWDT0_INT Interrupt */ +#define WWDT1_INT_VECn 16 /* WWDT1_INT Interrupt */ +#define SYSCTL_INT_VECn 16 /* SYSCTL_INT Interrupt */ +#define FLASHCTL_INT_VECn 16 /* FLASHCTL_INT Interrupt */ +#define COMP0_INT_VECn 17 /* COMP0_INT Interrupt */ +#define GPIOA_INT_VECn 17 /* GPIOA_INT Interrupt */ +#define GPIOB_INT_VECn 17 /* GPIOB_INT Interrupt */ +#define TIMB0_INT_VECn 18 /* TIMB0_INT Interrupt */ +#define ADC0_INT_VECn 20 /* ADC0_INT Interrupt */ +#define USBFS0_INT_VECn 22 /* USBFS0_INT Interrupt */ +#define UC0_INT_VECn 25 /* UC0_INT Interrupt */ +#define UC1_INT_VECn 26 /* UC1_INT Interrupt */ +#define I2S0_INT_VECn 27 /* I2S0_INT Interrupt */ +#define NPU_INT_VECn 28 /* NPU_INT Interrupt */ +#define UC2_INT_VECn 29 /* UC2_INT Interrupt */ +#define UC3_INT_VECn 30 /* UC3_INT Interrupt */ +#define TIMG0_INT_VECn 32 /* TIMG0_INT Interrupt */ +#define TIMG6_INT_VECn 33 /* TIMG6_INT Interrupt */ +#define TIMA0_INT_VECn 34 /* TIMA0_INT Interrupt */ +#define TIMG7_INT_VECn 36 /* TIMG7_INT Interrupt */ +#define AESADV_INT_VECn 44 /* AESADV_INT Interrupt */ +#define LFSS_INT_VECn 46 /* LFSS_INT Interrupt */ +#define RTC_B_INT_VECn 46 /* RTC_B_INT Interrupt */ +#define DMA_INT_VECn 47 /* DMA_INT Interrupt */ + + +/****************************************************************************** +* Ignore unused variables * +******************************************************************************/ + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/****************************************************************************** +* Processor and Core Peripheral Section * +******************************************************************************/ + +#define __CM0PLUS_REV 0x0001U /* Core revision */ +#define __MPU_PRESENT 0x0001U /* MPU present */ +#define __VTOR_PRESENT 0x0001U /* VTOR present */ +#define __NVIC_PRIO_BITS 0x0002U /* Number of bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0plus.h" /* Processor and core peripherals */ + +/****************************************************************************** +* Peripheral headers * +******************************************************************************/ +/** @addtogroup MSPM0G518X_Peripherals MSPM0G518X Peripherals + MSPM0G518X Peripheral registers structures + @{ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __MSPM0_HAS_ADC12__ +#define __MSPM0_HAS_AESADV__ +#define __MSPM0_HAS_COMP__ +#define __MSPM0_HAS_CRCP__ +#define __MSPM0_HAS_GPIO__ +#define __MSPM0_HAS_TIMER_A__ +#define __MSPM0_HAS_TIMER_G__ +#define __MSPM0_HAS_TIMER_B__ +#define __MSPM0_HAS_KEYSTORE_CTL__ +#define __MSPM0_HAS_LFSS__ +#define __MSPM0_HAS_RTC_B__ +#define __MSPM0_HAS_IWDT__ +#define __MSPM0_HAS_VREF__ +#define __MSPM0_HAS_WWDT__ + +#define __MSPM0_HAS_NPU__ +#define __MSPM0_HAS_I2S__ +#define __MCU_HAS_SPGSS__ +#define __MCU_HAS_UNICOMM__ +#define __MCU_HAS_UNICOMMUART__ +#define __MCU_HAS_UNICOMMI2CC__ +#define __MCU_HAS_UNICOMMI2CT__ +#define __MCU_HAS_UNICOMMSPI__ +#define __MSPM0_HAS_USB__ +#define __MSPM0_HAS_ECC__ + +/*@}*/ /* end of group MSPM0G518X_Peripherals */ + +/****************************************************************************** +* Device and peripheral memory map * +******************************************************************************/ +/** @addtogroup MSPM0G518X_MemoryMap MSPM0G518X Memory Mapping + @{ +*/ + +#define COMP0_BASE (0x40008000U) /*!< Base address of module COMP0 */ +#define VREF_BASE (0x40030000U) /*!< Base address of module VREF */ +#define WWDT0_BASE (0x40080000U) /*!< Base address of module WWDT0 */ +#define WWDT1_BASE (0x40082000U) /*!< Base address of module WWDT1 */ +#define TIMG0_BASE (0x40084000U) /*!< Base address of module TIMG0 */ +#define LFSS_BASE (0x40094000U) /*!< Base address of module LFSS */ +#define RTC_B_BASE (0x40094000U) /*!< Base address of module RTC_B */ +#define IWDT_BASE (0x40094000U) /*!< Base address of module IWDT */ +#define GPIOA_BASE (0x400A0000U) /*!< Base address of module GPIOA */ +#define GPIOB_BASE (0x400A2000U) /*!< Base address of module GPIOB */ +#define KEYSTORECTL_BASE (0x400AC000U) /*!< Base address of module KEYSTORECTL */ +#define SYSCTL_BASE (0x400AF000U) /*!< Base address of module SYSCTL */ +#define TIMB0_BASE (0x400B8000U) /*!< Base address of module TIMB0 */ +#define DEBUGSS_BASE (0x400C7000U) /*!< Base address of module DEBUGSS */ +#define EVENTLP_BASE (0x400C9000U) /*!< Base address of module EVENTLP */ +#define FLASHCTL_BASE (0x400CD000U) /*!< Base address of module FLASHCTL */ +#define CPUSS_BASE (0x40400000U) /*!< Base address of module CPUSS */ +#define WUC_BASE (0x40424000U) /*!< Base address of module WUC */ +#define IOMUX_BASE (0x40428000U) /*!< Base address of module IOMUX */ +#define DMA_BASE (0x4042A000U) /*!< Base address of module DMA */ +#define CRCP0_BASE (0x40440000U) /*!< Base address of module CRCP0 */ +#define AESADV_BASE (0x40442000U) /*!< Base address of module AESADV */ +#define I2S0_BASE (0x4047B000U) /*!< Base address of module I2S0 */ +#define USBFS0_BASE (0x4047F000U) /*!< Base address of module USBFS0 */ +#define ADC0_BASE (0x40004000U) /*!< Base address of module ADC0 */ +#define ADC0_SVT_BASE (0x4055A000U) /*!< Base address of module ADC0_SVT */ +#define TIMA0_BASE (0x40860000U) /*!< Base address of module TIMA0 */ +#define TIMG6_BASE (0x40868000U) /*!< Base address of module TIMG6 */ +#define TIMG7_BASE (0x4086A000U) /*!< Base address of module TIMG7 */ +#define NPU_BASE (0x408FF000U) /*!< Base address of module NPU */ +#define UC0_UART_BASE (0x40A00000U) /*!< Base address of module UC0_UART */ +#define UC1_UART_BASE (0x40A02000U) /*!< Base address of module UC1_UART */ +#define UC0_I2CC_BASE (0x40A20000U) /*!< Base address of module UC0_I2CC */ +#define UC1_I2CC_BASE (0x40A22000U) /*!< Base address of module UC1_I2CC */ +#define UC0_I2CT_BASE (0x40A40000U) /*!< Base address of module UC0_I2CT */ +#define UC1_I2CT_BASE (0x40A42000U) /*!< Base address of module UC1_I2CT */ +#define UC0_BASE (0x40A80000U) /*!< Base address of module UC0 */ +#define UC1_BASE (0x40A82000U) /*!< Base address of module UC1 */ +#define SPG0_BASE (0x40A9F000U) /*!< Base address of module SPG0 */ +#define UC3_UART_BASE (0x40B02000U) /*!< Base address of module UC3_UART */ +#define UC2_SPI_BASE (0x40B60000U) /*!< Base address of module UC2_SPI */ +#define UC3_SPI_BASE (0x40B62000U) /*!< Base address of module UC3_SPI */ +#define UC2_BASE (0x40B80000U) /*!< Base address of module UC2 */ +#define UC3_BASE (0x40B82000U) /*!< Base address of module UC3 */ +#define SPG1_BASE (0x40B9F000U) /*!< Base address of module SPG1 */ +#define FACTORYREGION_BASE (0x41C40000U) /*!< Base address of module FACTORYREGION */ + +#define UC_UART_OFFSET (0x00080000U) /*!< UART address offset relative to UCx base address */ +#define UC_I2CC_OFFSET (0x00060000U) /*!< I2CC address offset relative to UCx base address */ +#define UC_I2CT_OFFSET (0x00040000U) /*!< I2CT address offset relative to UCx base address */ +#define UC_SPI_OFFSET (0x00020000U) /*!< SPI address offset relative to UCx base address */ + +#define UC_UART_BASE(UC_BASE) (UC_BASE - UC_UART_OFFSET) /*!< Macro to calculate base address of UNICOMMUART Regs */ +#define UC_I2CC_BASE(UC_BASE) (UC_BASE - UC_I2CC_OFFSET) /*!< Macro to calculate base address of UNICOMMI2CC Regs */ +#define UC_I2CT_BASE(UC_BASE) (UC_BASE - UC_I2CT_OFFSET) /*!< Macro to calculate base address of UNICOMMI2CT Regs */ +#define UC_SPI_BASE(UC_BASE) (UC_BASE - UC_SPI_OFFSET) /*!< Macro to calculate base address of UNICOMMSPI Regs */ + +typedef struct { + UNICOMM_Regs * const inst; + UNICOMMUART_Regs * const uart; + UNICOMMI2CC_Regs * const i2cc; + UNICOMMI2CT_Regs * const i2ct; + UNICOMMSPI_Regs * const spi; + bool const fixedMode; +} UNICOMM_Inst_Regs; + +static const UNICOMM_Inst_Regs UC0_Inst = { + .inst = ((UNICOMM_Regs *) UC0_BASE), + .uart = ((UNICOMMUART_Regs *) UC_UART_BASE(UC0_BASE)), + .i2cc = ((UNICOMMI2CC_Regs *) UC_I2CC_BASE(UC0_BASE)), + .i2ct = ((UNICOMMI2CT_Regs *) UC_I2CT_BASE(UC0_BASE)), + .fixedMode = false, +}; + +static const UNICOMM_Inst_Regs UC1_Inst = { + .inst = ((UNICOMM_Regs *) UC1_BASE), + .uart = ((UNICOMMUART_Regs *) UC_UART_BASE(UC1_BASE)), + .i2cc = ((UNICOMMI2CC_Regs *) UC_I2CC_BASE(UC1_BASE)), + .i2ct = ((UNICOMMI2CT_Regs *) UC_I2CT_BASE(UC1_BASE)), + .fixedMode = false, +}; + +static const UNICOMM_Inst_Regs UC2_Inst = { + .inst = ((UNICOMM_Regs *) UC2_BASE), + .spi = ((UNICOMMSPI_Regs *) UC_SPI_BASE(UC2_BASE)), + .fixedMode = true, +}; + +static const UNICOMM_Inst_Regs UC3_Inst = { + .inst = ((UNICOMM_Regs *) UC3_BASE), + .uart = ((UNICOMMUART_Regs *) UC_UART_BASE(UC3_BASE)), + .spi = ((UNICOMMSPI_Regs *) UC_SPI_BASE(UC3_BASE)), + .fixedMode = false, +}; + +/*@}*/ /* end of group MSPM0G518X_MemoryMap */ + +/****************************************************************************** +* Peripheral declarations * +******************************************************************************/ +/** @addtogroup MSPM0G518X_PeripheralDecl MSPM0G518X Peripheral Declaration + @{ +*/ + +static LFSS_Regs * const LFSS = ((LFSS_Regs *) LFSS_BASE); +static RTC_Regs * const RTC_B = ((RTC_Regs *) RTC_B_BASE); +static DEBUGSS_Regs * const DEBUGSS = ((DEBUGSS_Regs *) DEBUGSS_BASE); +static KEYSTORECTL_Regs * const KEYSTORECTL = ((KEYSTORECTL_Regs *) KEYSTORECTL_BASE); +static AESADV_Regs * const AESADV = ((AESADV_Regs *) AESADV_BASE); +static WWDT_Regs * const WWDT0 = ((WWDT_Regs *) WWDT0_BASE); +static GPTIMER_Regs * const TIMG0 = ((GPTIMER_Regs *) TIMG0_BASE); +static CRCP_Regs * const CRCP0 = ((CRCP_Regs *) CRCP0_BASE); +static CRCP_Regs * const CRC0 = ((CRCP_Regs *) CRCP0_BASE); +static CRCP_Regs * const CRC = ((CRCP_Regs *) CRCP0_BASE); +static VREF_Regs * const VREF = ((VREF_Regs *) VREF_BASE); +static COMP_Regs * const COMP0 = ((COMP_Regs *) COMP0_BASE); +static GPIO_Regs * const GPIOA = ((GPIO_Regs *) GPIOA_BASE); +static WWDT_Regs * const WWDT1 = ((WWDT_Regs *) WWDT1_BASE); +static GPIO_Regs * const GPIOB = ((GPIO_Regs *) GPIOB_BASE); +static CPUSS_Regs * const CPUSS = ((CPUSS_Regs *) CPUSS_BASE); +static IOMUX_Regs * const IOMUX = ((IOMUX_Regs *) IOMUX_BASE); +static GPTIMER_Regs * const TIMA0 = ((GPTIMER_Regs *) TIMA0_BASE); +static GPTIMER_Regs * const TIMG6 = ((GPTIMER_Regs *) TIMG6_BASE); +static GPTIMER_Regs * const TIMG7 = ((GPTIMER_Regs *) TIMG7_BASE); +static DMA_Regs * const DMA = ((DMA_Regs *) DMA_BASE); +static SYSCTL_Regs * const SYSCTL = ((SYSCTL_Regs *) SYSCTL_BASE); +static WUC_Regs * const WUC = ((WUC_Regs *) WUC_BASE); +static FLASHCTL_Regs * const FLASHCTL = ((FLASHCTL_Regs *) FLASHCTL_BASE); +static I2S_Regs * const I2S0 = ((I2S_Regs *) I2S0_BASE); +static NPU_Regs * const NPU = ((NPU_Regs *) NPU_BASE); +static FACTORYREGION_OPEN_Regs * const FACTORYREGION = ((FACTORYREGION_OPEN_Regs *) FACTORYREGION_BASE); +static BTIMER_Regs * const TIMB0 = ((BTIMER_Regs *) TIMB0_BASE); +static USB_Regs * const USBFS0 = ((USB_Regs *) USBFS0_BASE); +static SPGSS_Regs * const SPG1 = ((SPGSS_Regs *) SPG1_BASE); +static ADC12_Regs * const ADC0 = ((ADC12_Regs *) ADC0_BASE); +static ADC12_PERIPHERALREGIONSVT_Regs * const ADC0_SVT = ((ADC12_PERIPHERALREGIONSVT_Regs *) ADC0_SVT_BASE); +static SPGSS_Regs * const SPG0 = ((SPGSS_Regs *) SPG0_BASE); + +static UNICOMM_Inst_Regs * const UC0 = (UNICOMM_Inst_Regs *) &UC0_Inst; +static UNICOMM_Inst_Regs * const UC1 = (UNICOMM_Inst_Regs *) &UC1_Inst; +static UNICOMM_Inst_Regs * const UC2 = (UNICOMM_Inst_Regs *) &UC2_Inst; +static UNICOMM_Inst_Regs * const UC3 = (UNICOMM_Inst_Regs *) &UC3_Inst; + +/****************************************************************************** +* SYS parameters * +******************************************************************************/ + +#define ADC_SYS_NUM_ANALOG_CHAN (16) /* !< Number of analog channels. */ +#define BTIM_SYS_NUM_COUNTERS (4) /* !< Max number of counters. */ +#define CRCP_SYS_CRC32_ENABLE (1) /* !< Parameter to exclude or include 32-bit CRC. */ +#define DMA_SYS_N_DMA_CHANNEL (12) /* !< Number of DMA channels implemented in DMA. */ +#define DMA_SYS_N_DMA_FULL_CHANNEL (6) /* !< Number of FULL-DMA channels implemented in DMA. If + SYS_N_DMA_CHANNEL is larger than SYS_N_DMA_FULL_CHANNEL, the + remaining channel will be BASIC channel with limited functionality. */ +#define DMA_SYS_MMR_AUTO (1) /* !< Boolean for if auto enable channels implemented in DMA. */ +#define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ +#define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ +#define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ +#define FLASHCTL_SYS_DATAWIDTH (128) /* !< Data bit width of a single flash word: Minimum: 64 Maximum: + 128 */ +#define FLASHCTL_SYS_WEPROTBWIDTH (16) /* !< Bit width of WEPROTB register. */ +#define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register. */ +#define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register. */ +#define I2S0_SYS_FENTRIES (4) /* !< Number of FIFO entries */ +#define I2S0_SYS_SINGLE_PIN (0) /* !< Boolean for if enable single Data Pin configuration. */ +#define SPI0_SYS_FENTRIES (4) /* !< The number of entries in RX and TX FIFO */ +#define SPI1_SYS_FENTRIES (4) /* !< The number of entries in RX and TX FIFO */ +#define SPG0_SYS_FENTRIES (4) /* !< The number of entries in RX and TX FIFO */ +#define COMP_SYS_DACOUT_EN (1) /* !< Boolean for if 8-bit DAC output to pin is available */ +#define VREF_SYS_INT_ADC_REF (1) /* !< Supports internal voltage reference for ADCs. */ + +#define UC0_UART_SYS_GLITCH_FILTER (0) +#define UC0_UART_SYS_HW_FLOW_CONTROL (1) +#define UC0_UART_SYS_9_BIT (1) +#define UC0_UART_SYS_RS485 (1) +#define UC0_UART_SYS_LIN (1) +#define UC0_UART_SYS_DALI (1) +#define UC0_UART_SYS_IRDA (1) +#define UC0_UART_SYS_SMART_CARD (1) +#define UC0_UART_SYS_IDLE_LINE (1) +#define UC0_UART_SYS_MANCHESTER_ENCODING (1) +#define UC0_UART_SYS_FIFO_LENGTH (4) +#define UC0_UART_SYS_RX_TIMEOUT (1) +#define UC0_UART_SYS_DMA (1) +#define UC0_UART_SYS_EXTERNAL_DIRECTION (1) + +#define UC1_UART_SYS_GLITCH_FILTER (0) +#define UC1_UART_SYS_HW_FLOW_CONTROL (1) +#define UC1_UART_SYS_9_BIT (1) +#define UC1_UART_SYS_RS485 (1) +#define UC1_UART_SYS_LIN (1) +#define UC1_UART_SYS_DALI (0) +#define UC1_UART_SYS_IRDA (0) +#define UC1_UART_SYS_SMART_CARD (0) +#define UC1_UART_SYS_IDLE_LINE (1) +#define UC1_UART_SYS_MANCHESTER_ENCODING (0) +#define UC1_UART_SYS_FIFO_LENGTH (4) +#define UC1_UART_SYS_RX_TIMEOUT (1) +#define UC1_UART_SYS_DMA (1) +#define UC1_UART_SYS_EXTERNAL_DIRECTION (1) + +#define UC3_UART_SYS_GLITCH_FILTER (0) +#define UC3_UART_SYS_HW_FLOW_CONTROL (1) +#define UC3_UART_SYS_9_BIT (1) +#define UC3_UART_SYS_RS485 (1) +#define UC3_UART_SYS_LIN (0) +#define UC3_UART_SYS_DALI (0) +#define UC3_UART_SYS_IRDA (0) +#define UC3_UART_SYS_SMART_CARD (1) +#define UC3_UART_SYS_IDLE_LINE (1) +#define UC3_UART_SYS_MANCHESTER_ENCODING (0) +#define UC3_UART_SYS_FIFO_LENGTH (4) +#define UC3_UART_SYS_RX_TIMEOUT (1) +#define UC3_UART_SYS_DMA (1) +#define UC3_UART_SYS_EXTERNAL_DIRECTION (1) + +/* UART driver config settings */ +#define UC_UART_SYS_GLITCH_FILTER (0) +#define UC_UART_SYS_HW_FLOW_CONTROL (1) +#define UC_UART_SYS_9_BIT (1) +#define UC_UART_SYS_RS485 (1) +#define UC_UART_SYS_LIN (1) +#define UC_UART_SYS_DALI (1) +#define UC_UART_SYS_IRDA (1) +#define UC_UART_SYS_SMART_CARD (1) +#define UC_UART_SYS_MANCHESTER_ENCODING (1) +#define UC_UART_SYS_FIFO_LENGTH (4) +#define UC_UART_SYS_BUSCLK (1) +#define UC_UART_SYS_MFCLK (1) +#define UC_UART_SYS_LFCLK (1) +#define UC_UART_SYS_ASYNC_LFCLK (0) +#define UC_UART_SYS_ASYNC_SYSCLK (0) +#define UC_UART_SYS_ASYNC_HFCLK (0) +#define UC_UART_SYS_ASYNC_PLL (0) + +#define UC2_SPI_SYS_EN_REPEAT (1) +#define UC2_SPI_SYS_EN_RTOUT (1) +#define UC2_SPI_SYS_EN_COMMAND_DATA (1) +#define UC2_SPI_SYS_EN_CS_CTL (1) +#define UC2_SPI_SYS_EN_PACKING (0) +#define UC2_SPI_SYS_EN_FENTRIES (1) +#define UC2_SPI_SYS_EN_DMA (1) +#define UC2_SPI_SYS_EN_CLKDIV (1) + +#define UC3_SPI_SYS_EN_REPEAT (0) +#define UC3_SPI_SYS_EN_RTOUT (0) +#define UC3_SPI_SYS_EN_COMMAND_DATA (0) +#define UC3_SPI_SYS_EN_CS_CTL (0) +#define UC3_SPI_SYS_EN_PACKING (0) +#define UC3_SPI_SYS_EN_FENTRIES (1) +#define UC3_SPI_SYS_EN_DMA (0) +#define UC3_SPI_SYS_EN_CLKDIV (1) + +/****************************************************************************** +* DMA Triggers * +******************************************************************************/ + +/* External DMA Triggers */ +#define DMA_SOFTWARE_TRIG (0) +#define DMA_AESADV_AES_0_TRIG (3) +#define DMA_AESADV_AES_1_TRIG (4) +#define DMA_UC0_RX_BD_TRIG (5) +#define DMA_UC0_TX_BD_TRIG (6) +#define DMA_UC1_RX_BD_TRIG (7) +#define DMA_UC1_TX_BD_TRIG (8) +#define DMA_UC2_RX_BD_TRIG (9) +#define DMA_UC2_TX_BD_TRIG (10) +#define DMA_UC3_RX_BD_TRIG (11) +#define DMA_UC3_TX_BD_TRIG (12) +#define DMA_I2S0_RX_TRIG (13) +#define DMA_I2S0_TX_TRIG (14) +#define DMA_USBFS0_EVT_0_TRIG (15) +#define DMA_USBFS0_EVT_1_TRIG (16) +#define DMA_USBFS0_EVT_2_TRIG (17) +#define DMA_USBFS0_EVT_3_TRIG (18) +#define DMA_USBFS0_EVT_4_TRIG (19) +#define DMA_USBFS0_EVT_5_TRIG (20) +#define DMA_USBFS0_EVT_6_TRIG (21) +#define DMA_USBFS0_EVT_7_TRIG (22) +#define DMA_ADC0_EVT_GEN_BD_TRIG (23) + +/* Internal DMA Triggers */ +#define DMA_CH_0_TRIG (0) +#define DMA_CH_1_TRIG (1) +#define DMA_CH_2_TRIG (2) +#define DMA_CH_3_TRIG (3) +#define DMA_CH_4_TRIG (4) +#define DMA_CH_5_TRIG (5) +#define DMA_CH_6_TRIG (6) +#define DMA_CH_7_TRIG (7) +#define DMA_CH_8_TRIG (8) +#define DMA_CH_9_TRIG (9) +#define DMA_CH_10_TRIG (10) +#define DMA_CH_11_TRIG (11) + + +/****************************************************************************** +* IOMUX Pin Definitions * +******************************************************************************/ + +typedef enum IOMUX_PINCM +{ + IOMUX_PINCM1 = (0), + IOMUX_PINCM2 = (1), + IOMUX_PINCM3 = (2), + IOMUX_PINCM4 = (3), + IOMUX_PINCM5 = (4), + IOMUX_PINCM6 = (5), + IOMUX_PINCM7 = (6), + IOMUX_PINCM8 = (7), + IOMUX_PINCM9 = (8), + IOMUX_PINCM10 = (9), + IOMUX_PINCM11 = (10), + IOMUX_PINCM12 = (11), + IOMUX_PINCM13 = (12), + IOMUX_PINCM14 = (13), + IOMUX_PINCM15 = (14), + IOMUX_PINCM16 = (15), + IOMUX_PINCM17 = (16), + IOMUX_PINCM18 = (17), + IOMUX_PINCM19 = (18), + IOMUX_PINCM20 = (19), + IOMUX_PINCM21 = (20), + IOMUX_PINCM22 = (21), + IOMUX_PINCM23 = (22), + IOMUX_PINCM24 = (23), + IOMUX_PINCM25 = (24), + IOMUX_PINCM26 = (25), + IOMUX_PINCM27 = (26), + IOMUX_PINCM28 = (27), + IOMUX_PINCM29 = (28), + IOMUX_PINCM30 = (29), + IOMUX_PINCM31 = (30), + IOMUX_PINCM32 = (31), + IOMUX_PINCM33 = (32), + IOMUX_PINCM34 = (33), + IOMUX_PINCM35 = (34), + IOMUX_PINCM36 = (35), + IOMUX_PINCM37 = (36), + IOMUX_PINCM38 = (37), + IOMUX_PINCM39 = (38), + IOMUX_PINCM40 = (39), + IOMUX_PINCM41 = (40), + IOMUX_PINCM42 = (41), + IOMUX_PINCM43 = (42), + IOMUX_PINCM44 = (43), + IOMUX_PINCM45 = (44), + IOMUX_PINCM46 = (45), + IOMUX_PINCM47 = (46), + IOMUX_PINCM48 = (47), + IOMUX_PINCM49 = (48), + IOMUX_PINCM50 = (49), + IOMUX_PINCM51 = (50), + IOMUX_PINCM52 = (51), + IOMUX_PINCM53 = (52), + IOMUX_PINCM54 = (53), + IOMUX_PINCM55 = (54), + IOMUX_PINCM56 = (55), + IOMUX_PINCM57 = (56), + IOMUX_PINCM58 = (57), + IOMUX_PINCM59 = (58), +} IOMUX_PINCM; + + +/* IOMUX_PINCM1[PF] Bits */ +#define IOMUX_PINCM1_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM1_PF_GPIOA_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM1_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_SYSCTL_FCC_IN ((uint32_t)0X00000003) +#define IOMUX_PINCM1_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM1_PF_TIMG0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM1_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM1_PF_UC0_SDA ((uint32_t)0X00000007) +#define IOMUX_PINCM1_PF_UC0_TX ((uint32_t)0X00000007) + +/* IOMUX_PINCM2[PF] Bits */ +#define IOMUX_PINCM2_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM2_PF_GPIOA_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM2_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM2_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM2_PF_TIMG0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM2_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM2_PF_UC0_SCL ((uint32_t)0X00000007) +#define IOMUX_PINCM2_PF_UC0_RX ((uint32_t)0X00000007) + +/* IOMUX_PINCM3[PF] Bits */ +#define IOMUX_PINCM3_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM3_PF_GPIOA_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM3_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_TIMA0_CCP1 ((uint32_t)0X00000003) +#define IOMUX_PINCM3_PF_TIMA0_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM3_PF_TIMG7_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM3_PF_TIMA_FAULT0 ((uint32_t)0X00000006) +#define IOMUX_PINCM3_PF_UC0_SDA ((uint32_t)0X00000007) +#define IOMUX_PINCM3_PF_UC0_TX ((uint32_t)0X00000007) + +/* IOMUX_PINCM4[PF] Bits */ +#define IOMUX_PINCM4_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM4_PF_GPIOA_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM4_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_UC1_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM4_PF_UC2_CS3 ((uint32_t)0X00000004) +#define IOMUX_PINCM4_PF_TIMG6_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM4_PF_UC0_CTS ((uint32_t)0X00000006) + +/* IOMUX_PINCM5[PF] Bits */ +#define IOMUX_PINCM5_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM5_PF_GPIOA_DIO30 ((uint32_t)0X00000001) +#define IOMUX_PINCM5_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_UC1_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM5_PF_UC2_CS2 ((uint32_t)0X00000004) +#define IOMUX_PINCM5_PF_TIMG6_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM5_PF_UC0_RTS ((uint32_t)0X00000006) + +/* IOMUX_PINCM6[PF] Bits */ +#define IOMUX_PINCM6_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM6_PF_GPIOA_DIO31 ((uint32_t)0X00000001) +#define IOMUX_PINCM6_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM6_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM6_PF_TIMG7_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM6_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM6_PF_UC0_SCL ((uint32_t)0X00000007) +#define IOMUX_PINCM6_PF_UC0_RX ((uint32_t)0X00000007) + +/* IOMUX_PINCM7[PF] Bits */ +#define IOMUX_PINCM7_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM7_PF_GPIOA_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM7_PF_UC1_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM7_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_TIMG7_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM7_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM7_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM7_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM7_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM7_PF_TIMA_FAULT1 ((uint32_t)0X00000009) +#define IOMUX_PINCM7_PF_UC3_CS0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM7_PF_UC3_CTS ((uint32_t)0X0000000A) + +/* IOMUX_PINCM8[PF] Bits */ +#define IOMUX_PINCM8_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM8_PF_GPIOA_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM8_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM8_PF_UC2_CS3 ((uint32_t)0X00000004) +#define IOMUX_PINCM8_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM8_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM8_PF_TIMG7_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM8_PF_TIMA0_CCP2 ((uint32_t)0X00000008) +#define IOMUX_PINCM8_PF_UC1_CTS ((uint32_t)0X00000009) + +/* IOMUX_PINCM9[PF] Bits */ +#define IOMUX_PINCM9_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM9_PF_GPIOA_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM9_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_UC2_CS0 ((uint32_t)0X00000004) +#define IOMUX_PINCM9_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM9_PF_SYSCTL_LFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM9_PF_TIMG7_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM9_PF_TIMA0_CCP3 ((uint32_t)0X00000008) + +/* IOMUX_PINCM10[PF] Bits */ +#define IOMUX_PINCM10_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM10_PF_GPIOA_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM10_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_UC0_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM10_PF_TIMG0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM10_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM10_PF_TIMG6_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM10_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM10_PF_UC3_POCI ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_UC3_RTS ((uint32_t)0X00000009) + +/* IOMUX_PINCM11[PF] Bits */ +#define IOMUX_PINCM11_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM11_PF_GPIOA_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM11_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM11_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM11_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_UC0_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM11_PF_TIMG0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM11_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM11_PF_TIMG6_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM11_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM11_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000009) +#define IOMUX_PINCM11_PF_UC3_PICO ((uint32_t)0X0000000A) +#define IOMUX_PINCM11_PF_UC3_TX ((uint32_t)0X0000000A) + +/* IOMUX_PINCM12[PF] Bits */ +#define IOMUX_PINCM12_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM12_PF_GPIOB_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM12_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM12_PF_UC0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_UC0_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM12_PF_TIMG0_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM13[PF] Bits */ +#define IOMUX_PINCM13_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM13_PF_GPIOB_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM13_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM13_PF_UC0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_UC0_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM13_PF_TIMG0_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM14[PF] Bits */ +#define IOMUX_PINCM14_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM14_PF_GPIOA_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM14_PF_UC2_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM14_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM14_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM14_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM14_PF_TIMG7_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM14_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM14_PF_TIMA0_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM14_PF_SYSCTL_FCC_IN ((uint32_t)0X00000009) + +/* IOMUX_PINCM15[PF] Bits */ +#define IOMUX_PINCM15_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM15_PF_GPIOB_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM15_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM15_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM15_PF_UC1_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM15_PF_UC1_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM15_PF_UC1_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM15_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM15_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM15_PF_UC2_PICO ((uint32_t)0X00000007) +#define IOMUX_PINCM15_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000008) + +/* IOMUX_PINCM16[PF] Bits */ +#define IOMUX_PINCM16_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM16_PF_GPIOB_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM16_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM16_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM16_PF_UC1_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM16_PF_UC1_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM16_PF_UC1_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM16_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM16_PF_TIMG6_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM16_PF_UC2_SCLK ((uint32_t)0X00000007) +#define IOMUX_PINCM16_PF_TIMA0_CCP0 ((uint32_t)0X00000008) + +/* IOMUX_PINCM17[PF] Bits */ +#define IOMUX_PINCM17_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM17_PF_GPIOB_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM17_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM17_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM17_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM17_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM17_PF_TIMG0_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM18[PF] Bits */ +#define IOMUX_PINCM18_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM18_PF_GPIOB_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM18_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM18_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM18_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM18_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM18_PF_TIMG0_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM19[PF] Bits */ +#define IOMUX_PINCM19_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM19_PF_GPIOA_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM19_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC2_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_UC0_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM19_PF_UC0_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM19_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM19_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM19_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM19_PF_UC2_CS3 ((uint32_t)0X00000008) +#define IOMUX_PINCM19_PF_I2S0_WCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM19_PF_UC0_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM19_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000B) + +/* IOMUX_PINCM20[PF] Bits */ +#define IOMUX_PINCM20_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM20_PF_GPIOA_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM20_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM20_PF_UC0_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM20_PF_UC0_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM20_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM20_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM20_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM20_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM20_PF_I2S0_BCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM20_PF_UC3_SCLK ((uint32_t)0X0000000A) +#define IOMUX_PINCM20_PF_UC3_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM20_PF_UC0_CTS ((uint32_t)0X0000000B) + +/* IOMUX_PINCM21[PF] Bits */ +#define IOMUX_PINCM21_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM21_PF_GPIOA_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM21_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM21_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM21_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM21_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM21_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM21_PF_TIMG0_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM21_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM21_PF_I2S0_AD0 ((uint32_t)0X00000009) +#define IOMUX_PINCM21_PF_UC3_PICO ((uint32_t)0X0000000A) +#define IOMUX_PINCM21_PF_UC3_TX ((uint32_t)0X0000000A) + +/* IOMUX_PINCM22[PF] Bits */ +#define IOMUX_PINCM22_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM22_PF_GPIOA_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM22_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM22_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM22_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM22_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM22_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM22_PF_TIMG0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM22_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM22_PF_I2S0_AD1 ((uint32_t)0X00000009) +#define IOMUX_PINCM22_PF_UC3_POCI ((uint32_t)0X0000000A) +#define IOMUX_PINCM22_PF_UC3_RTS ((uint32_t)0X0000000A) + +/* IOMUX_PINCM23[PF] Bits */ +#define IOMUX_PINCM23_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM23_PF_GPIOB_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM23_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM23_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM23_PF_UC2_CS1 ((uint32_t)0X00000004) +#define IOMUX_PINCM23_PF_TIMG6_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM23_PF_TIMA_FAULT2 ((uint32_t)0X00000006) + +/* IOMUX_PINCM24[PF] Bits */ +#define IOMUX_PINCM24_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM24_PF_GPIOB_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM24_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM24_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM24_PF_UC2_CS2 ((uint32_t)0X00000004) +#define IOMUX_PINCM24_PF_TIMG6_CCP1 ((uint32_t)0X00000005) + +/* IOMUX_PINCM25[PF] Bits */ +#define IOMUX_PINCM25_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM25_PF_GPIOB_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM25_PF_UC1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM25_PF_UC3_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_UC3_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM25_PF_TIMA0_CCP0 ((uint32_t)0X00000005) + +/* IOMUX_PINCM26[PF] Bits */ +#define IOMUX_PINCM26_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM26_PF_GPIOB_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM26_PF_UC1_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM26_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM26_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) + +/* IOMUX_PINCM27[PF] Bits */ +#define IOMUX_PINCM27_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM27_PF_GPIOB_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM27_PF_UC3_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_UC3_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM27_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM27_PF_TIMG0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM27_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM27_PF_I2S0_WCLK ((uint32_t)0X00000007) + +/* IOMUX_PINCM28[PF] Bits */ +#define IOMUX_PINCM28_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM28_PF_GPIOB_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM28_PF_UC3_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM28_PF_UC3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM28_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM28_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM28_PF_TIMG0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM28_PF_TIMG6_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM28_PF_I2S0_BCLK ((uint32_t)0X00000007) + +/* IOMUX_PINCM29[PF] Bits */ +#define IOMUX_PINCM29_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM29_PF_GPIOB_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM29_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM29_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM29_PF_UC2_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM29_PF_TIMA_FAULT1 ((uint32_t)0X00000004) +#define IOMUX_PINCM29_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM29_PF_TIMA0_CCP2 ((uint32_t)0X00000006) +#define IOMUX_PINCM29_PF_I2S0_AD0 ((uint32_t)0X00000007) + +/* IOMUX_PINCM30[PF] Bits */ +#define IOMUX_PINCM30_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM30_PF_GPIOB_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM30_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM30_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM30_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_TIMA_FAULT2 ((uint32_t)0X00000004) +#define IOMUX_PINCM30_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM30_PF_TIMA0_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM30_PF_I2S0_AD1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM31[PF] Bits */ +#define IOMUX_PINCM31_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM31_PF_GPIOB_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM31_PF_UC2_CS3 ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM31_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM31_PF_TIMA0_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM31_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM31_PF_I2S0_MCLK ((uint32_t)0X00000007) + +/* IOMUX_PINCM32[PF] Bits */ +#define IOMUX_PINCM32_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM32_PF_GPIOB_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM32_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_TIMG7_CCP0 ((uint32_t)0X00000004) + +/* IOMUX_PINCM33[PF] Bits */ +#define IOMUX_PINCM33_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM33_PF_GPIOB_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM33_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_TIMG7_CCP1 ((uint32_t)0X00000004) + +/* IOMUX_PINCM34[PF] Bits */ +#define IOMUX_PINCM34_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM34_PF_GPIOA_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM34_PF_UC3_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC3_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM34_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM34_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM34_PF_TIMG0_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM34_PF_UC1_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM34_PF_I2S0_BCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM34_PF_UC0_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM34_PF_UC2_CS0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM35[PF] Bits */ +#define IOMUX_PINCM35_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM35_PF_GPIOA_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM35_PF_UC3_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_UC3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_UC3_SCLK ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_UC3_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM35_PF_LFSS_RTC_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM35_PF_TIMG0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM35_PF_UC3_CS0 ((uint32_t)0X00000008) +#define IOMUX_PINCM35_PF_UC3_CTS ((uint32_t)0X00000008) +#define IOMUX_PINCM35_PF_I2S0_AD0 ((uint32_t)0X00000009) +#define IOMUX_PINCM35_PF_UC1_RTS ((uint32_t)0X0000000A) +#define IOMUX_PINCM35_PF_UC2_CS3 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM36[PF] Bits */ +#define IOMUX_PINCM36_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM36_PF_GPIOA_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM36_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM36_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_UC3_PICO ((uint32_t)0X00000004) +#define IOMUX_PINCM36_PF_UC3_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM36_PF_TIMG7_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM36_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM36_PF_TIMG6_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM36_PF_I2S0_AD1 ((uint32_t)0X00000009) + +/* IOMUX_PINCM37[PF] Bits */ +#define IOMUX_PINCM37_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM37_PF_GPIOA_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM37_PF_UC0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM37_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM37_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM37_PF_UC1_RTS ((uint32_t)0X00000007) +#define IOMUX_PINCM37_PF_I2S0_WCLK ((uint32_t)0X00000008) + +/* IOMUX_PINCM38[PF] Bits */ +#define IOMUX_PINCM38_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM38_PF_GPIOA_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM38_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM38_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM38_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM38_PF_UC1_CTS ((uint32_t)0X00000007) +#define IOMUX_PINCM38_PF_COMP0_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM38_PF_I2S0_MCLK ((uint32_t)0X00000009) + +/* IOMUX_PINCM39[PF] Bits */ +#define IOMUX_PINCM39_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM39_PF_GPIOA_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM39_PF_UC1_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC1_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM39_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM39_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM39_PF_TIMG7_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM39_PF_UC2_CS1 ((uint32_t)0X00000007) +#define IOMUX_PINCM39_PF_I2S0_WCLK ((uint32_t)0X00000008) + +/* IOMUX_PINCM40[PF] Bits */ +#define IOMUX_PINCM40_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM40_PF_GPIOA_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM40_PF_UC1_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC1_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC3_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC3_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM40_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM40_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM40_PF_TIMG7_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM40_PF_UC2_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM40_PF_TIMA_FAULT2 ((uint32_t)0X00000008) +#define IOMUX_PINCM40_PF_I2S0_MCLK ((uint32_t)0X00000009) + +/* IOMUX_PINCM41[PF] Bits */ +#define IOMUX_PINCM41_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM41_PF_GPIOA_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM41_PF_DEBUGSS_SWDIO ((uint32_t)0X00000002) +#define IOMUX_PINCM41_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM41_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM41_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM41_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM41_PF_I2S0_AD0 ((uint32_t)0X00000007) + +/* IOMUX_PINCM42[PF] Bits */ +#define IOMUX_PINCM42_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM42_PF_GPIOA_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM42_PF_DEBUGSS_SWCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM42_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM42_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM42_PF_UC3_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM42_PF_UC3_CTS ((uint32_t)0X00000007) +#define IOMUX_PINCM42_PF_I2S0_AD1 ((uint32_t)0X00000008) + +/* IOMUX_PINCM43[PF] Bits */ +#define IOMUX_PINCM43_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM43_PF_GPIOB_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM43_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_UC2_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_TIMG0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM43_PF_TIMA0_CCP2 ((uint32_t)0X00000005) + +/* IOMUX_PINCM44[PF] Bits */ +#define IOMUX_PINCM44_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM44_PF_GPIOB_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM44_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_UC2_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_TIMG0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM44_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) + +/* IOMUX_PINCM45[PF] Bits */ +#define IOMUX_PINCM45_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM45_PF_GPIOB_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM45_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM45_PF_UC2_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_TIMG7_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM45_PF_COMP0_OUT ((uint32_t)0X00000005) + +/* IOMUX_PINCM46[PF] Bits */ +#define IOMUX_PINCM46_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM46_PF_GPIOA_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM46_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM46_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM46_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM46_PF_UC1_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM46_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM46_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM46_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM46_PF_I2S0_AD0 ((uint32_t)0X00000008) + +/* IOMUX_PINCM47[PF] Bits */ +#define IOMUX_PINCM47_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM47_PF_GPIOA_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM47_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM47_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM47_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM47_PF_UC1_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM47_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM47_PF_TIMG6_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM47_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM47_PF_I2S0_BCLK ((uint32_t)0X00000008) +#define IOMUX_PINCM47_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000009) + +/* IOMUX_PINCM48[PF] Bits */ +#define IOMUX_PINCM48_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM48_PF_GPIOB_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM48_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM48_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM48_PF_UC3_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM48_PF_UC3_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM48_PF_UC2_CS2 ((uint32_t)0X00000004) +#define IOMUX_PINCM48_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM48_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM48_PF_TIMA0_CCP1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM49[PF] Bits */ +#define IOMUX_PINCM49_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM49_PF_GPIOB_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM49_PF_UC0_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM49_PF_UC0_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM49_PF_UC3_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM49_PF_UC3_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM49_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM49_PF_UC1_TX ((uint32_t)0X00000004) + +/* IOMUX_PINCM50[PF] Bits */ +#define IOMUX_PINCM50_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM50_PF_GPIOB_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM50_PF_UC0_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM50_PF_UC0_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM50_PF_UC3_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC3_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM50_PF_UC1_RX ((uint32_t)0X00000004) + +/* IOMUX_PINCM51[PF] Bits */ +#define IOMUX_PINCM51_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM51_PF_GPIOB_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM51_PF_UC1_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM51_PF_UC3_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_UC3_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM51_PF_COMP0_OUT ((uint32_t)0X00000005) + +/* IOMUX_PINCM52[PF] Bits */ +#define IOMUX_PINCM52_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM52_PF_GPIOB_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM52_PF_UC2_CS3 ((uint32_t)0X00000002) +#define IOMUX_PINCM52_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM52_PF_UC3_POCI ((uint32_t)0X00000004) +#define IOMUX_PINCM52_PF_UC3_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM52_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM52_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) + +/* IOMUX_PINCM53[PF] Bits */ +#define IOMUX_PINCM53_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM53_PF_GPIOA_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM53_PF_UC3_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM53_PF_UC3_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM53_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM53_PF_UC3_CS0 ((uint32_t)0X00000004) +#define IOMUX_PINCM53_PF_UC3_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM53_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM53_PF_TIMG0_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM53_PF_TIMG7_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM53_PF_I2S0_WCLK ((uint32_t)0X00000008) + +/* IOMUX_PINCM54[PF] Bits */ +#define IOMUX_PINCM54_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM54_PF_GPIOA_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM54_PF_UC3_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM54_PF_UC3_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM54_PF_UC2_CS2 ((uint32_t)0X00000003) +#define IOMUX_PINCM54_PF_UC3_SCLK ((uint32_t)0X00000004) +#define IOMUX_PINCM54_PF_UC3_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM54_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM54_PF_TIMG0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM54_PF_TIMG7_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM54_PF_I2S0_AD1 ((uint32_t)0X00000008) + +/* IOMUX_PINCM55[PF] Bits */ +#define IOMUX_PINCM55_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM55_PF_GPIOA_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM55_PF_UC3_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM55_PF_UC3_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM55_PF_UC2_CS3 ((uint32_t)0X00000003) +#define IOMUX_PINCM55_PF_UC3_PICO ((uint32_t)0X00000004) +#define IOMUX_PINCM55_PF_UC3_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM55_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM55_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM55_PF_COMP0_OUT ((uint32_t)0X00000007) + +/* IOMUX_PINCM56[PF] Bits */ +#define IOMUX_PINCM56_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM56_PF_GPIOB_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM56_PF_UC0_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM56_PF_UC2_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM56_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM56_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM56_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM56_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM56_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/* IOMUX_PINCM57[PF] Bits */ +#define IOMUX_PINCM57_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM57_PF_GPIOB_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM57_PF_UC0_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM57_PF_UC2_CS1 ((uint32_t)0X00000003) +#define IOMUX_PINCM57_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM57_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM57_PF_TIMG6_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM57_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM57_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/* IOMUX_PINCM58[PF] Bits */ +#define IOMUX_PINCM58_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM58_PF_GPIOA_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM58_PF_UC0_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM58_PF_UC0_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM58_PF_UC1_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM58_PF_UC1_RX ((uint32_t)0X00000004) +#define IOMUX_PINCM58_PF_TIMG7_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM58_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM58_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM58_PF_UC3_PICO ((uint32_t)0X00000008) +#define IOMUX_PINCM58_PF_UC3_TX ((uint32_t)0X00000008) + +/* IOMUX_PINCM59[PF] Bits */ +#define IOMUX_PINCM59_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM59_PF_GPIOA_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM59_PF_UC0_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM59_PF_UC0_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM59_PF_UC1_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM59_PF_UC1_TX ((uint32_t)0X00000004) +#define IOMUX_PINCM59_PF_TIMG7_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM59_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM59_PF_LFSS_RTC_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM59_PF_COMP0_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM59_PF_UC3_SCLK ((uint32_t)0X00000009) +#define IOMUX_PINCM59_PF_UC3_RX ((uint32_t)0X00000009) +#define IOMUX_PINCM59_PF_TIMA_FAULT2 ((uint32_t)0X0000000A) + + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*@}*/ /* end of group MSPM0G518X_PeripheralDecl */ + +/*@}*/ /* end of group MSPM0G518X_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_m0p_mspm0g518x__include */ diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0h321x.h b/mspm0/source/ti/devices/msp/m0p/mspm0h321x.h index 8c00703..9e29ab6 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0h321x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0h321x.h @@ -293,7 +293,7 @@ static RTC_Regs * const RTC_B #define CRC_SYS_CRC32_ENABLE (0) /* !< Parameter to exclude or include 32-bit CRC. */ -#define FLASHCTL_SYS_DATAWIDTH (128) /* !< Data bit width of a single flash word. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word. */ #define ADC_SYS_NUM_ANALOG_CHAN (32) /* !< Number of analog channels. */ #define I2C_SYS_FENTRIES (4) /* !< Number of FIFO entries */ #define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register */ diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0l110x.h b/mspm0/source/ti/devices/msp/m0p/mspm0l110x.h index 868857e..c6966db 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0l110x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0l110x.h @@ -259,6 +259,8 @@ static GPTIMER_Regs * const TIMG0 #define FLASHCTL_SYS_WEPROTAWIDTH (32) /* !< Bit width of WEPROTA register */ #define FLASHCTL_SYS_WEPROTBWIDTH (4) /* !< Bit width of WEPROTB register */ #define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ +#define VREF_SYS_INT_COMP_REF (1) /* !< Supports internal voltage reference for comparators. */ + /****************************************************************************** * DMA Triggers * diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0l111x.h b/mspm0/source/ti/devices/msp/m0p/mspm0l111x.h index 9c1b9bf..6ec3adf 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0l111x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0l111x.h @@ -291,7 +291,7 @@ static FACTORYREGION_OPEN_Regs * const FACTORYREGION #define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ #define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ #define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ -#define FLASHCTL_SYS_DATAWIDTH (128) /* !< Data bit width of a single flash word. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word. */ #define ADC_SYS_NUM_ANALOG_CHAN (32) /* !< Number of analog channels. */ #define I2C_SYS_FENTRIES (4) /* !< Number of FIFO entries */ #define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register */ diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0l112x.h b/mspm0/source/ti/devices/msp/m0p/mspm0l112x.h new file mode 100644 index 0000000..19ca3da --- /dev/null +++ b/mspm0/source/ti/devices/msp/m0p/mspm0l112x.h @@ -0,0 +1,1171 @@ +/***************************************************************************** + + Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_m0p_mspm0l112x__include +#define ti_devices_msp_m0p_mspm0l112x__include + +/* Filename: mspm0l112x.h */ +/* Revised: 2025-05-22 14:35:05*/ + +/* Use standard integer types with explicit width */ +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup MSPM0L112X_Definitions MSPM0L112X Definitions + This file defines all structures and symbols for MSPM0L112X + @{ +*/ + +/** @addtogroup MSPM0L112X_CMSIS Device CMSIS Definitions + Configuration of the Processor and Core Peripherals + @{ +*/ +/****************************************************************************** +* Interrupt Definitions * +******************************************************************************/ +typedef enum IRQn +{ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + SYSCTL_INT_IRQn = 0, /* 16 SYSCTL_INT Interrupt */ + DEBUGSS_INT_IRQn = 1, /* 17 DEBUGSS_INT Interrupt */ + UC6_INT_IRQn = 3, /* 19 UC6_INT Interrupt */ + ADC0_INT_IRQn = 4, /* 20 ADC0_INT Interrupt */ + TIMB0_INT_IRQn = 5, /* 21 TIMB0_INT Interrupt */ + TIMB1_INT_IRQn = 6, /* 22 TIMB1_INT Interrupt */ + COMP0_INT_IRQn = 7, /* 23 COMP0_INT Interrupt */ + UC7_INT_IRQn = 8, /* 24 UC7_INT Interrupt */ + UC8_INT_IRQn = 9, /* 25 UC8_INT Interrupt */ + TIMB2_INT_IRQn = 13, /* 29 TIMB2_INT Interrupt */ + TIMB3_INT_IRQn = 14, /* 30 TIMB3_INT Interrupt */ + UC4_INT_IRQn = 15, /* 31 UC4_INT Interrupt */ + TIMG14_INT_IRQn = 16, /* 32 TIMG14_INT Interrupt */ + TIMG2_INT_IRQn = 17, /* 33 TIMG2_INT Interrupt */ + TIMA0_INT_IRQn = 18, /* 34 TIMA0_INT Interrupt */ + TIMG1_INT_IRQn = 19, /* 35 TIMG1_INT Interrupt */ + GPIOA_INT_IRQn = 22, /* 38 GPIOA_INT Interrupt */ + GPIOB_INT_IRQn = 23, /* 39 GPIOB_INT Interrupt */ + UC11_INT_IRQn = 24, /* 40 UC11_INT Interrupt */ + AESADV_INT_IRQn = 26, /* 42 AESADV_INT Interrupt */ + FLASHCTL_INT_IRQn = 27, /* 43 FLASHCTL_INT Interrupt */ + WWDT0_INT_IRQn = 29, /* 45 WWDT0_INT Interrupt */ + LFSS_INT_IRQn = 30, /* 46 LFSS_INT Interrupt */ + RTC_B_INT_IRQn = 30, /* 46 RTC_B_INT Interrupt */ + IWDT_INT_IRQn = 30, /* 46 IWDT_INT Interrupt */ + DMA_INT_IRQn = 31, /* 47 DMA_INT Interrupt */ +} IRQn_Type; + +#define NonMaskableInt_VECn 2 /* Non Maskable Interrupt */ +#define HardFault_VECn 3 /* Hard Fault Interrupt */ +#define SVCall_VECn 11 /* SV Call Interrupt */ +#define PendSV_VECn 14 /* Pend SV Interrupt */ +#define SysTick_VECn 15 /* System Tick Interrupt */ +#define SYSCTL_INT_VECn 16 /* SYSCTL_INT Interrupt */ +#define DEBUGSS_INT_VECn 17 /* DEBUGSS_INT Interrupt */ +#define UC6_INT_VECn 19 /* UC6_INT Interrupt */ +#define ADC0_INT_VECn 20 /* ADC0_INT Interrupt */ +#define TIMB0_INT_VECn 21 /* TIMB0_INT Interrupt */ +#define TIMB1_INT_VECn 22 /* TIMB1_INT Interrupt */ +#define COMP0_INT_VECn 23 /* COMP0_INT Interrupt */ +#define UC7_INT_VECn 24 /* UC7_INT Interrupt */ +#define UC8_INT_VECn 25 /* UC8_INT Interrupt */ +#define TIMB2_INT_VECn 29 /* TIMB2_INT Interrupt */ +#define TIMB3_INT_VECn 30 /* TIMB3_INT Interrupt */ +#define UC4_INT_VECn 31 /* UC4_INT Interrupt */ +#define TIMG14_INT_VECn 32 /* TIMG14_INT Interrupt */ +#define TIMG2_INT_VECn 33 /* TIMG2_INT Interrupt */ +#define TIMA0_INT_VECn 34 /* TIMA0_INT Interrupt */ +#define TIMG1_INT_VECn 35 /* TIMG1_INT Interrupt */ +#define GPIOA_INT_VECn 38 /* GPIOA_INT Interrupt */ +#define GPIOB_INT_VECn 39 /* GPIOB_INT Interrupt */ +#define UC11_INT_VECn 40 /* UC11_INT Interrupt */ +#define AESADV_INT_VECn 42 /* AESADV_INT Interrupt */ +#define FLASHCTL_INT_VECn 43 /* FLASHCTL_INT Interrupt */ +#define WWDT0_INT_VECn 45 /* WWDT0_INT Interrupt */ +#define LFSS_INT_VECn 46 /* LFSS_INT Interrupt */ +#define RTC_B_INT_VECn 46 /* RTC_B_INT Interrupt */ +#define IWDT_INT_VECn 46 /* IWDT_INT Interrupt */ +#define DMA_INT_VECn 47 /* DMA_INT Interrupt */ + + +/****************************************************************************** +* Ignore unused variables * +******************************************************************************/ + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/****************************************************************************** +* Processor and Core Peripheral Section * +******************************************************************************/ + +#define __CM0PLUS_REV 0x0001U /* Core revision */ +#define __MPU_PRESENT 0x0001U /* MPU present */ +#define __VTOR_PRESENT 0x0001U /* VTOR present */ +#define __NVIC_PRIO_BITS 0x0002U /* Number of bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0plus.h" /* Processor and core peripherals */ + +/****************************************************************************** +* Peripheral headers * +******************************************************************************/ +/** @addtogroup MSPM0L112X_Peripherals MSPM0L112X Peripherals + MSPM0L112X Peripheral registers structures + @{ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __MSPM0_HAS_ADC12__ +#define __MSPM0_HAS_AESADV__ +#define __MSPM0_HAS_TIMER_B__ +#define __MSPM0_HAS_COMP__ +#define __MSPM0_HAS_CRC__ +#define __MSPM0_HAS_GPIO__ +#define __MSPM0_HAS_KEYSTORE_CTL__ +#define __MSPM0_HAS_LFSS__ +#define __MSPM0_HAS_RTC_B__ +#define __MSPM0_HAS_IWDT__ +#define __MCU_HAS_SPGSS__ +#define __MCU_HAS_UNICOMMI2CC__ +#define __MCU_HAS_UNICOMMI2CT__ +#define __MCU_HAS_UNICOMMSPI__ +#define __MCU_HAS_UNICOMMUART__ +#define __MCU_HAS_UNICOMM__ +#define __MSPM0_HAS_VREF__ +#define __MSPM0_HAS_WWDT__ +#define __MSPM0_HAS_ECC__ + +/*@}*/ /* end of group MSPM0L112X_Peripherals */ + +/****************************************************************************** +* Device and peripheral memory map * +******************************************************************************/ +/** @addtogroup MSPM0L112X_MemoryMap MSPM0L112X Memory Mapping + @{ +*/ + +#define ADC0_BASE (0x40004000U) /*!< Base address of module ADC0 */ +#define COMP0_BASE (0x40008000U) /*!< Base address of module COMP0 */ +#define VREF_BASE (0x40030000U) /*!< Base address of module VREF */ +#define WWDT0_BASE (0x40080000U) /*!< Base address of module WWDT0 */ +#define TIMG14_BASE (0x40084000U) /*!< Base address of module TIMG14 */ +#define TIMG1_BASE (0x40086000U) /*!< Base address of module TIMG1 */ +#define TIMG2_BASE (0x40088000U) /*!< Base address of module TIMG2 */ +#define LFSS_BASE (0x40094000U) /*!< Base address of module LFSS */ +#define RTC_B_BASE (0x40094000U) /*!< Base address of module RTC_B */ +#define IWDT_BASE (0x40094000U) /*!< Base address of module IWDT */ +#define GPIOA_BASE (0x400A0000U) /*!< Base address of module GPIOA */ +#define GPIOB_BASE (0x400A2000U) /*!< Base address of module GPIOB */ +#define KEYSTORECTL_BASE (0x400AC000U) /*!< Base address of module KEYSTORECTL */ +#define SYSCTL_BASE (0x400AF000U) /*!< Base address of module SYSCTL */ +#define TIMB0_BASE (0x400B8000U) /*!< Base address of module TIMB0 */ +#define TIMB1_BASE (0x400BA000U) /*!< Base address of module TIMB1 */ +#define TIMB2_BASE (0x400BC000U) /*!< Base address of module TIMB2 */ +#define TIMB3_BASE (0x400BE000U) /*!< Base address of module TIMB3 */ +#define DEBUGSS_BASE (0x400C7000U) /*!< Base address of module DEBUGSS */ +#define EVENTLP_BASE (0x400C9000U) /*!< Base address of module EVENTLP */ +#define FLASHCTL_BASE (0x400CD000U) /*!< Base address of module FLASHCTL */ +#define CPUSS_BASE (0x40400000U) /*!< Base address of module CPUSS */ +#define WUC_BASE (0x40424000U) /*!< Base address of module WUC */ +#define IOMUX_BASE (0x40428000U) /*!< Base address of module IOMUX */ +#define DMA_BASE (0x4042A000U) /*!< Base address of module DMA */ +#define CRC0_BASE (0x40440000U) /*!< Base address of module CRC0 */ +#define AESADV_BASE (0x40442000U) /*!< Base address of module AESADV */ +#define ADC0_SVT_BASE (0x4055A000U) /*!< Base address of module ADC0_SVT */ +#define TIMA0_BASE (0x40860000U) /*!< Base address of module TIMA0 */ +#define UC4_UART_BASE (0x40A00000U) /*!< Base address of module UC4_UART */ +#define UC6_I2CC_BASE (0x40A22000U) /*!< Base address of module UC6_I2CC */ +#define UC7_I2CT_BASE (0x40A44000U) /*!< Base address of module UC7_I2CT */ +#define UC4_SPI_BASE (0x40A60000U) /*!< Base address of module UC4_SPI */ +#define UC4_BASE (0x40A80000U) /*!< Base address of module UC4 */ +#define UC6_BASE (0x40A82000U) /*!< Base address of module UC6 */ +#define UC7_BASE (0x40A84000U) /*!< Base address of module UC7 */ +#define SPG0_BASE (0x40A9F000U) /*!< Base address of module SPG0 */ +#define UC8_UART_BASE (0x40B00000U) /*!< Base address of module UC8_UART */ +#define UC11_UART_BASE (0x40B02000U) /*!< Base address of module UC11_UART */ +#define UC8_SPI_BASE (0x40B60000U) /*!< Base address of module UC8_SPI */ +#define UC8_BASE (0x40B80000U) /*!< Base address of module UC8 */ +#define UC11_BASE (0x40B82000U) /*!< Base address of module UC11 */ +#define FACTORYREGION_BASE (0x41C40000U) /*!< Base address of module FACTORYREGION */ + + +typedef struct { + UNICOMM_Regs * const inst; + UNICOMMUART_Regs * const uart; + UNICOMMI2CC_Regs * const i2cc; + UNICOMMI2CT_Regs * const i2ct; + UNICOMMSPI_Regs * const spi; + bool const fixedMode; +} UNICOMM_Inst_Regs; + +static const UNICOMM_Inst_Regs UC4_Inst = { + .inst = (UNICOMM_Regs *) UC4_BASE, + .uart = (UNICOMMUART_Regs *) UC4_UART_BASE, + .spi = (UNICOMMSPI_Regs *) UC4_SPI_BASE, + .fixedMode = false +}; +static const UNICOMM_Inst_Regs UC6_Inst = { + .inst = (UNICOMM_Regs *) UC6_BASE, + .i2cc = (UNICOMMI2CC_Regs *) UC6_I2CC_BASE, + .fixedMode = true +}; +static const UNICOMM_Inst_Regs UC7_Inst = { + .inst = (UNICOMM_Regs *) UC7_BASE, + .i2ct = (UNICOMMI2CT_Regs *) UC7_I2CT_BASE, + .fixedMode = true +}; +static const UNICOMM_Inst_Regs UC8_Inst = { + .inst = (UNICOMM_Regs *) UC8_BASE, + .uart = (UNICOMMUART_Regs *) UC8_UART_BASE, + .spi = (UNICOMMSPI_Regs *) UC8_SPI_BASE, + .fixedMode = false +}; +static const UNICOMM_Inst_Regs UC11_Inst = { + .inst = (UNICOMM_Regs *) UC11_BASE, + .uart = (UNICOMMUART_Regs *) UC11_UART_BASE, + .fixedMode = true +}; + + +/*@}*/ /* end of group MSPM0L112X_MemoryMap */ + +/****************************************************************************** +* Peripheral declarations * +******************************************************************************/ +/** @addtogroup MSPM0L112X_PeripheralDecl MSPM0L112X Peripheral Declaration + @{ +*/ + +static ADC12_Regs * const ADC0 = ((ADC12_Regs *) ADC0_BASE); +static COMP_Regs * const COMP0 = ((COMP_Regs *) COMP0_BASE); +static VREF_Regs * const VREF = ((VREF_Regs *) VREF_BASE); +static WWDT_Regs * const WWDT0 = ((WWDT_Regs *) WWDT0_BASE); +static GPTIMER_Regs * const TIMG14 = ((GPTIMER_Regs *) TIMG14_BASE); +static GPTIMER_Regs * const TIMG1 = ((GPTIMER_Regs *) TIMG1_BASE); +static GPTIMER_Regs * const TIMG2 = ((GPTIMER_Regs *) TIMG2_BASE); +static LFSS_Regs * const LFSS = ((LFSS_Regs *) LFSS_BASE); +static RTC_Regs * const RTC_B = ((RTC_Regs *) RTC_B_BASE); +static GPIO_Regs * const GPIOA = ((GPIO_Regs *) GPIOA_BASE); +static GPIO_Regs * const GPIOB = ((GPIO_Regs *) GPIOB_BASE); +static KEYSTORECTL_Regs * const KEYSTORECTL = ((KEYSTORECTL_Regs *) KEYSTORECTL_BASE); +static SYSCTL_Regs * const SYSCTL = ((SYSCTL_Regs *) SYSCTL_BASE); +static BTIMER_Regs * const TIMB0 = ((BTIMER_Regs *) TIMB0_BASE); +static BTIMER_Regs * const TIMB1 = ((BTIMER_Regs *) TIMB1_BASE); +static BTIMER_Regs * const TIMB2 = ((BTIMER_Regs *) TIMB2_BASE); +static BTIMER_Regs * const TIMB3 = ((BTIMER_Regs *) TIMB3_BASE); +static DEBUGSS_Regs * const DEBUGSS = ((DEBUGSS_Regs *) DEBUGSS_BASE); +static FLASHCTL_Regs * const FLASHCTL = ((FLASHCTL_Regs *) FLASHCTL_BASE); +static CPUSS_Regs * const CPUSS = ((CPUSS_Regs *) CPUSS_BASE); +static WUC_Regs * const WUC = ((WUC_Regs *) WUC_BASE); +static IOMUX_Regs * const IOMUX = ((IOMUX_Regs *) IOMUX_BASE); +static DMA_Regs * const DMA = ((DMA_Regs *) DMA_BASE); +static CRC_Regs * const CRC0 = ((CRC_Regs *) CRC0_BASE); +static AESADV_Regs * const AESADV = ((AESADV_Regs *) AESADV_BASE); +static ADC12_PERIPHERALREGIONSVT_Regs * const ADC0_SVT = ((ADC12_PERIPHERALREGIONSVT_Regs *) ADC0_SVT_BASE); +static GPTIMER_Regs * const TIMA0 = ((GPTIMER_Regs *) TIMA0_BASE); +static UNICOMMUART_Regs * const UC4_UART = ((UNICOMMUART_Regs *) UC4_UART_BASE); +static UNICOMMI2CC_Regs * const UC6_I2CC = ((UNICOMMI2CC_Regs *) UC6_I2CC_BASE); +static UNICOMMI2CT_Regs * const UC7_I2CT = ((UNICOMMI2CT_Regs *) UC7_I2CT_BASE); +static UNICOMMSPI_Regs * const UC4_SPI = ((UNICOMMSPI_Regs *) UC4_SPI_BASE); +static UNICOMM_Inst_Regs * const UC4 = ((UNICOMM_Inst_Regs *) &UC4_Inst); +static UNICOMM_Inst_Regs * const UC6 = ((UNICOMM_Inst_Regs *) &UC6_Inst); +static UNICOMM_Inst_Regs * const UC7 = ((UNICOMM_Inst_Regs *) &UC7_Inst); +static SPGSS_Regs * const SPG0 = ((SPGSS_Regs *) SPG0_BASE); +static UNICOMMUART_Regs * const UC8_UART = ((UNICOMMUART_Regs *) UC8_UART_BASE); +static UNICOMMUART_Regs * const UC11_UART = ((UNICOMMUART_Regs *) UC11_UART_BASE); +static UNICOMMSPI_Regs * const UC8_SPI = ((UNICOMMSPI_Regs *) UC8_SPI_BASE); +static UNICOMM_Inst_Regs * const UC8 = ((UNICOMM_Inst_Regs *) &UC8_Inst); +static UNICOMM_Inst_Regs * const UC11 = ((UNICOMM_Inst_Regs *) &UC11_Inst); +static FACTORYREGION_OPEN_Regs * const FACTORYREGION = ((FACTORYREGION_OPEN_Regs *) FACTORYREGION_BASE); + + +/****************************************************************************** +* SYS parameters * +******************************************************************************/ + +#define ADC_SYS_NUM_ANALOG_CHAN (32) /* !< Number of analog channels. */ +#define CRC0_SYS_CRC32_ENABLE (0) /* !< Parameter to exclude or include 32-bit CRC. */ +#define DMA_SYS_N_DMA_CHANNEL (3) /* !< Number of DMA channels implemented in DMA. */ +#define DMA_SYS_N_DMA_FULL_CHANNEL (2) /* !< Number of FULL-DMA channels implemented in DMA. If + SYS_N_DMA_CHANNEL is larger than SYS_N_DMA_FULL_CHANNEL, the + remaining channel will be BASIC channel with limited functionality. */ +#define DMA_SYS_MMR_AUTO (1) /* !< Boolean for if auto enable channels implemented in DMA. */ +#define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ +#define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ +#define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word: Minimum: 64 Maximum: + 128 */ +#define FLASHCTL_SYS_WEPROTBWIDTH (16) /* !< Bit width of WEPROTB register. */ +#define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register. */ +#define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register. */ +#define COMP_SYS_DACOUT_EN (1) /* !< Boolean for if 8-bit DAC output to pin is available */ + + +/****************************************************************************** +* DMA Triggers * +******************************************************************************/ + +/* External DMA Triggers */ +#define DMA_SOFTWARE_TRIG (0) +#define DMA_AESADV_AES_0_TRIG (3) +#define DMA_AESADV_AES_1_TRIG (4) +#define DMA_UC4_RX_BD_TRIG (5) +#define DMA_UC4_TX_BD_TRIG (6) +#define DMA_UC6_RX_BD_TRIG (7) +#define DMA_UC6_TX_BD_TRIG (8) +#define DMA_UC7_RX_BD_TRIG (9) +#define DMA_UC7_TX_BD_TRIG (10) +#define DMA_UC8_RX_BD_TRIG (11) +#define DMA_UC8_TX_BD_TRIG (12) +#define DMA_ADC0_EVT_GEN_BD_TRIG (13) + +/* Internal DMA Triggers */ +#define DMA_CH_0_TRIG (0) +#define DMA_CH_1_TRIG (1) +#define DMA_CH_2_TRIG (2) + + + +/****************************************************************************** +* IOMUX Pin Definitions * +******************************************************************************/ + +typedef enum IOMUX_PINCM +{ + IOMUX_PINCM1 = (0), + IOMUX_PINCM2 = (1), + IOMUX_PINCM3 = (2), + IOMUX_PINCM4 = (3), + IOMUX_PINCM5 = (4), + IOMUX_PINCM6 = (5), + IOMUX_PINCM7 = (6), + IOMUX_PINCM8 = (7), + IOMUX_PINCM9 = (8), + IOMUX_PINCM10 = (9), + IOMUX_PINCM11 = (10), + IOMUX_PINCM12 = (11), + IOMUX_PINCM13 = (12), + IOMUX_PINCM14 = (13), + IOMUX_PINCM15 = (14), + IOMUX_PINCM16 = (15), + IOMUX_PINCM17 = (16), + IOMUX_PINCM18 = (17), + IOMUX_PINCM19 = (18), + IOMUX_PINCM20 = (19), + IOMUX_PINCM21 = (20), + IOMUX_PINCM22 = (21), + IOMUX_PINCM23 = (22), + IOMUX_PINCM24 = (23), + IOMUX_PINCM25 = (24), + IOMUX_PINCM26 = (25), + IOMUX_PINCM27 = (26), + IOMUX_PINCM28 = (27), + IOMUX_PINCM29 = (28), + IOMUX_PINCM30 = (29), + IOMUX_PINCM31 = (30), + IOMUX_PINCM32 = (31), + IOMUX_PINCM33 = (32), + IOMUX_PINCM34 = (33), + IOMUX_PINCM35 = (34), + IOMUX_PINCM36 = (35), + IOMUX_PINCM37 = (36), + IOMUX_PINCM38 = (37), + IOMUX_PINCM39 = (38), + IOMUX_PINCM40 = (39), + IOMUX_PINCM41 = (40), + IOMUX_PINCM42 = (41), + IOMUX_PINCM43 = (42), + IOMUX_PINCM44 = (43), + IOMUX_PINCM45 = (44), + IOMUX_PINCM46 = (45), + IOMUX_PINCM47 = (46), + IOMUX_PINCM48 = (47), + IOMUX_PINCM49 = (48), + IOMUX_PINCM50 = (49), + IOMUX_PINCM51 = (50), + IOMUX_PINCM52 = (51), + IOMUX_PINCM53 = (52), + IOMUX_PINCM54 = (53), + IOMUX_PINCM55 = (54), + IOMUX_PINCM56 = (55), + IOMUX_PINCM57 = (56), + IOMUX_PINCM58 = (57), + IOMUX_PINCM59 = (58), + IOMUX_PINCM60 = (59), +} IOMUX_PINCM; + + +/* IOMUX_PINCM1[PF] Bits */ +#define IOMUX_PINCM1_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM1_PF_GPIOA_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM1_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_UC6_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM1_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM1_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM1_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM1_PF_SYSCTL_BEEPER ((uint32_t)0X00000008) +#define IOMUX_PINCM1_PF_TIMG14_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM1_PF_UC7_SDA ((uint32_t)0X0000000B) + +/* IOMUX_PINCM2[PF] Bits */ +#define IOMUX_PINCM2_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM2_PF_GPIOA_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM2_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC6_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM2_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM2_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM2_PF_TIMG14_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM2_PF_TIMG14_CCP2 ((uint32_t)0X00000007) +#define IOMUX_PINCM2_PF_TIMG14_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM2_PF_UC7_SCL ((uint32_t)0X0000000B) + +/* IOMUX_PINCM3[PF] Bits */ +#define IOMUX_PINCM3_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM3_PF_GPIOA_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM3_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_UC6_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM3_PF_TIMA0_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM3_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM3_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM3_PF_TIMA0_CCP1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM4[PF] Bits */ +#define IOMUX_PINCM4_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM4_PF_GPIOA_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM4_PF_UC7_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_TIMG14_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM4_PF_TIMG1_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM4_PF_UC4_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM4_PF_UC4_CTS ((uint32_t)0X00000007) + +/* IOMUX_PINCM5[PF] Bits */ +#define IOMUX_PINCM5_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM5_PF_GPIOA_DIO30 ((uint32_t)0X00000001) +#define IOMUX_PINCM5_PF_UC7_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_TIMG14_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM5_PF_TIMG1_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM5_PF_UC4_POCI ((uint32_t)0X00000007) +#define IOMUX_PINCM5_PF_UC4_RTS ((uint32_t)0X00000007) + +/* IOMUX_PINCM6[PF] Bits */ +#define IOMUX_PINCM6_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM6_PF_GPIOA_DIO31 ((uint32_t)0X00000001) +#define IOMUX_PINCM6_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC6_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM6_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM6_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM6_PF_TIMG2_CCP1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM7[PF] Bits */ +#define IOMUX_PINCM7_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM7_PF_GPIOA_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM7_PF_TIMG14_CCP3 ((uint32_t)0X00000002) +#define IOMUX_PINCM7_PF_UC4_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_UC4_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_TIMG2_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM7_PF_UC8_CS0 ((uint32_t)0X00000005) +#define IOMUX_PINCM7_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM7_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM7_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM7_PF_TIMA_FAULT1 ((uint32_t)0X00000009) +#define IOMUX_PINCM7_PF_TIMA0_CCP0 ((uint32_t)0X0000000B) + +/* IOMUX_PINCM8[PF] Bits */ +#define IOMUX_PINCM8_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM8_PF_GPIOA_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM8_PF_TIMG14_CCP2 ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM8_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM8_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM8_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM8_PF_TIMA0_CCP2 ((uint32_t)0X00000008) +#define IOMUX_PINCM8_PF_UC8_PICO ((uint32_t)0X0000000A) +#define IOMUX_PINCM8_PF_UC8_TX ((uint32_t)0X0000000A) + +/* IOMUX_PINCM9[PF] Bits */ +#define IOMUX_PINCM9_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM9_PF_GPIOA_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM9_PF_TIMG14_CCP3 ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM9_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM9_PF_SYSCTL_LFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM9_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM9_PF_TIMA0_CCP3 ((uint32_t)0X00000008) +#define IOMUX_PINCM9_PF_UC8_SCLK ((uint32_t)0X0000000A) +#define IOMUX_PINCM9_PF_UC8_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM9_PF_UC4_CS0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM9_PF_UC4_CTS ((uint32_t)0X0000000B) + +/* IOMUX_PINCM10[PF] Bits */ +#define IOMUX_PINCM10_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM10_PF_GPIOA_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM10_PF_TIMG14_CCP2 ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM10_PF_TIMG14_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM10_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM10_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM10_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM10_PF_UC4_CS0 ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_UC4_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_UC8_PICO ((uint32_t)0X0000000B) +#define IOMUX_PINCM10_PF_UC8_TX ((uint32_t)0X0000000B) + +/* IOMUX_PINCM11[PF] Bits */ +#define IOMUX_PINCM11_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM11_PF_GPIOA_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM11_PF_TIMG14_CCP3 ((uint32_t)0X00000002) +#define IOMUX_PINCM11_PF_UC4_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_UC4_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM11_PF_TIMG14_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM11_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM11_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM11_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM11_PF_UC4_POCI ((uint32_t)0X00000009) +#define IOMUX_PINCM11_PF_UC4_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM11_PF_TIMA0_CCP2_CMPL ((uint32_t)0X0000000A) +#define IOMUX_PINCM11_PF_UC8_SCLK ((uint32_t)0X0000000B) +#define IOMUX_PINCM11_PF_UC8_RX ((uint32_t)0X0000000B) + +/* IOMUX_PINCM12[PF] Bits */ +#define IOMUX_PINCM12_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM12_PF_GPIOB_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM12_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM12_PF_TIMG14_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM13[PF] Bits */ +#define IOMUX_PINCM13_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM13_PF_GPIOB_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM13_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM13_PF_TIMG14_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM14[PF] Bits */ +#define IOMUX_PINCM14_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM14_PF_GPIOA_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM14_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM14_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000003) +#define IOMUX_PINCM14_PF_TIMG14_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM14_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM14_PF_TIMG14_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM14_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM14_PF_TIMA0_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM14_PF_SYSCTL_FCC_IN ((uint32_t)0X0000000A) +#define IOMUX_PINCM14_PF_UC4_POCI ((uint32_t)0X0000000B) +#define IOMUX_PINCM14_PF_UC4_RTS ((uint32_t)0X0000000B) + +/* IOMUX_PINCM15[PF] Bits */ +#define IOMUX_PINCM15_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM15_PF_GPIOB_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM15_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM15_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM15_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM15_PF_UC11_TX ((uint32_t)0X00000008) +#define IOMUX_PINCM15_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM15_PF_UC4_PICO ((uint32_t)0X0000000B) +#define IOMUX_PINCM15_PF_UC4_TX ((uint32_t)0X0000000B) + +/* IOMUX_PINCM16[PF] Bits */ +#define IOMUX_PINCM16_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM16_PF_GPIOB_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM16_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM16_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM16_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM16_PF_UC11_RX ((uint32_t)0X00000008) +#define IOMUX_PINCM16_PF_TIMA0_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM16_PF_UC4_SCLK ((uint32_t)0X0000000B) +#define IOMUX_PINCM16_PF_UC4_RX ((uint32_t)0X0000000B) + +/* IOMUX_PINCM17[PF] Bits */ +#define IOMUX_PINCM17_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM17_PF_GPIOB_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM17_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM17_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM17_PF_TIMG14_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM17_PF_TIMG1_CCP0 ((uint32_t)0X00000007) + +/* IOMUX_PINCM18[PF] Bits */ +#define IOMUX_PINCM18_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM18_PF_GPIOB_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM18_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM18_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM18_PF_TIMG14_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM18_PF_TIMG1_CCP1 ((uint32_t)0X00000007) + +/* IOMUX_PINCM19[PF] Bits */ +#define IOMUX_PINCM19_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM19_PF_GPIOA_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM19_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC4_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_UC4_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM19_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM19_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM19_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM19_PF_TIMG2_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM19_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM19_PF_UC4_POCI ((uint32_t)0X0000000B) +#define IOMUX_PINCM19_PF_UC4_RTS ((uint32_t)0X0000000B) + +/* IOMUX_PINCM20[PF] Bits */ +#define IOMUX_PINCM20_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM20_PF_GPIOA_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM20_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM20_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM20_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM20_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM20_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM20_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM20_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM20_PF_TIMG2_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM20_PF_UC4_CS0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM20_PF_UC4_CTS ((uint32_t)0X0000000B) + +/* IOMUX_PINCM21[PF] Bits */ +#define IOMUX_PINCM21_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM21_PF_GPIOA_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM21_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM21_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM21_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM21_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM21_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM21_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM21_PF_UC7_SDA ((uint32_t)0X00000008) +#define IOMUX_PINCM21_PF_TIMA_FAULT1 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM22[PF] Bits */ +#define IOMUX_PINCM22_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM22_PF_GPIOA_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM22_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM22_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM22_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM22_PF_TIMG14_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM22_PF_UC7_SCL ((uint32_t)0X00000008) +#define IOMUX_PINCM22_PF_TIMA_FAULT0 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM23[PF] Bits */ +#define IOMUX_PINCM23_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM23_PF_GPIOB_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM23_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC8_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM23_PF_TIMG14_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM23_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM23_PF_TIMA_FAULT2 ((uint32_t)0X00000008) + +/* IOMUX_PINCM24[PF] Bits */ +#define IOMUX_PINCM24_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM24_PF_GPIOB_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM24_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM24_PF_TIMG14_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM24_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM24_PF_LCD_LCDLFCLK ((uint32_t)0X00000008) + +/* IOMUX_PINCM25[PF] Bits */ +#define IOMUX_PINCM25_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM25_PF_GPIOB_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM25_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM25_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM25_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM25_PF_LCD_LCDSON ((uint32_t)0X00000008) + +/* IOMUX_PINCM26[PF] Bits */ +#define IOMUX_PINCM26_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM26_PF_GPIOB_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM26_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM26_PF_TIMA0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM26_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM26_PF_LCD_LCDEN ((uint32_t)0X00000008) + +/* IOMUX_PINCM27[PF] Bits */ +#define IOMUX_PINCM27_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM27_PF_GPIOB_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM27_PF_TIMG14_CCP0 ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_TIMG14_CCP2 ((uint32_t)0X00000003) +#define IOMUX_PINCM27_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM27_PF_TIMG1_CCP0 ((uint32_t)0X00000005) + +/* IOMUX_PINCM28[PF] Bits */ +#define IOMUX_PINCM28_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM28_PF_GPIOB_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM28_PF_TIMG14_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM28_PF_TIMG14_CCP3 ((uint32_t)0X00000003) +#define IOMUX_PINCM28_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM28_PF_TIMG1_CCP1 ((uint32_t)0X00000005) + +/* IOMUX_PINCM29[PF] Bits */ +#define IOMUX_PINCM29_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM29_PF_GPIOB_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM29_PF_TIMA0_CCP2 ((uint32_t)0X00000003) +#define IOMUX_PINCM29_PF_TIMA_FAULT1 ((uint32_t)0X00000004) +#define IOMUX_PINCM29_PF_TIMA0_CCP1 ((uint32_t)0X00000005) + +/* IOMUX_PINCM30[PF] Bits */ +#define IOMUX_PINCM30_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM30_PF_GPIOB_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM30_PF_TIMA0_CCP3 ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM30_PF_UC8_CS0 ((uint32_t)0X00000007) + +/* IOMUX_PINCM31[PF] Bits */ +#define IOMUX_PINCM31_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM31_PF_GPIOB_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM31_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM31_PF_SYSCTL_FCC_IN ((uint32_t)0X00000004) +#define IOMUX_PINCM31_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM31_PF_TIMG14_CCP2 ((uint32_t)0X00000006) +#define IOMUX_PINCM31_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM31_PF_COMP0_OUT ((uint32_t)0X0000000A) + +/* IOMUX_PINCM32[PF] Bits */ +#define IOMUX_PINCM32_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM32_PF_GPIOB_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM32_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_UC4_POCI ((uint32_t)0X00000004) +#define IOMUX_PINCM32_PF_UC4_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM32_PF_TIMG14_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM32_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM32_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM32_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM32_PF_TIMG14_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM32_PF_UC8_CS0 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM33[PF] Bits */ +#define IOMUX_PINCM33_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM33_PF_GPIOB_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM33_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_UC4_CS0 ((uint32_t)0X00000004) +#define IOMUX_PINCM33_PF_UC4_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM33_PF_TIMG14_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM33_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM33_PF_UC4_PICO ((uint32_t)0X00000007) +#define IOMUX_PINCM33_PF_UC4_TX ((uint32_t)0X00000007) +#define IOMUX_PINCM33_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000008) + +/* IOMUX_PINCM34[PF] Bits */ +#define IOMUX_PINCM34_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM34_PF_GPIOA_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM34_PF_UC4_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC4_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC4_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_UC4_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM34_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM34_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM34_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM34_PF_UC7_SCL ((uint32_t)0X00000008) +#define IOMUX_PINCM34_PF_TIMA0_CCP2 ((uint32_t)0X00000009) + +/* IOMUX_PINCM35[PF] Bits */ +#define IOMUX_PINCM35_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM35_PF_GPIOA_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM35_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM35_PF_LFSS_RTC_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM35_PF_TIMG14_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM35_PF_UC8_CS0 ((uint32_t)0X00000008) +#define IOMUX_PINCM35_PF_UC8_POCI ((uint32_t)0X00000009) +#define IOMUX_PINCM35_PF_UC11_TX ((uint32_t)0X0000000A) +#define IOMUX_PINCM35_PF_COMP0_OUT ((uint32_t)0X0000000B) + +/* IOMUX_PINCM36[PF] Bits */ +#define IOMUX_PINCM36_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM36_PF_GPIOA_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM36_PF_UC4_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM36_PF_UC4_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM36_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM36_PF_UC11_RX ((uint32_t)0X0000000A) + +/* IOMUX_PINCM37[PF] Bits */ +#define IOMUX_PINCM37_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM37_PF_GPIOA_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM37_PF_UC4_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_UC4_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM37_PF_TIMG14_CCP2 ((uint32_t)0X00000007) +#define IOMUX_PINCM37_PF_LCD_LCDEN ((uint32_t)0X00000009) + +/* IOMUX_PINCM38[PF] Bits */ +#define IOMUX_PINCM38_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM38_PF_GPIOA_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM38_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM38_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM38_PF_SYSCTL_FCC_IN ((uint32_t)0X00000007) +#define IOMUX_PINCM38_PF_LCD_LCDSON ((uint32_t)0X00000009) + +/* IOMUX_PINCM39[PF] Bits */ +#define IOMUX_PINCM39_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM39_PF_GPIOA_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM39_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM39_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM39_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM39_PF_TIMG14_CCP2 ((uint32_t)0X00000007) +#define IOMUX_PINCM39_PF_LCD_LCDLFCLK ((uint32_t)0X0000000A) + +/* IOMUX_PINCM40[PF] Bits */ +#define IOMUX_PINCM40_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM40_PF_GPIOA_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM40_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM40_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM40_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM40_PF_TIMG14_CCP3 ((uint32_t)0X00000007) +#define IOMUX_PINCM40_PF_UC4_CS0 ((uint32_t)0X00000009) +#define IOMUX_PINCM40_PF_UC4_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM40_PF_LCD_LCDEN ((uint32_t)0X0000000A) + +/* IOMUX_PINCM41[PF] Bits */ +#define IOMUX_PINCM41_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM41_PF_GPIOA_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM41_PF_DEBUGSS_SWDIO ((uint32_t)0X00000002) +#define IOMUX_PINCM41_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM41_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM41_PF_TIMG14_CCP0 ((uint32_t)0X00000006) + +/* IOMUX_PINCM42[PF] Bits */ +#define IOMUX_PINCM42_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM42_PF_GPIOA_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM42_PF_DEBUGSS_SWCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM42_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM42_PF_TIMG14_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM43[PF] Bits */ +#define IOMUX_PINCM43_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM43_PF_GPIOB_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM43_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM43_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM43_PF_TIMG14_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM43_PF_TIMG1_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM43_PF_LCD_LCDSON ((uint32_t)0X0000000A) + +/* IOMUX_PINCM44[PF] Bits */ +#define IOMUX_PINCM44_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM44_PF_GPIOB_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM44_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_UC4_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_UC4_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM44_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM44_PF_TIMG14_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM44_PF_TIMG1_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM44_PF_LCD_LCDLFCLK ((uint32_t)0X0000000A) + +/* IOMUX_PINCM45[PF] Bits */ +#define IOMUX_PINCM45_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM45_PF_GPIOB_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM45_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM45_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_UC4_CS0 ((uint32_t)0X00000005) +#define IOMUX_PINCM45_PF_UC4_CTS ((uint32_t)0X00000005) +#define IOMUX_PINCM45_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM45_PF_TIMG14_CCP2 ((uint32_t)0X00000007) + +/* IOMUX_PINCM46[PF] Bits */ +#define IOMUX_PINCM46_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM46_PF_GPIOA_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM46_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM46_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM46_PF_TIMG1_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM46_PF_TIMG14_CCP2 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM47[PF] Bits */ +#define IOMUX_PINCM47_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM47_PF_GPIOA_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM47_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM47_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM47_PF_TIMG1_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM47_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM47_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM47_PF_UC6_SCL ((uint32_t)0X00000009) +#define IOMUX_PINCM47_PF_TIMG14_CCP3 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM48[PF] Bits */ +#define IOMUX_PINCM48_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM48_PF_GPIOB_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM48_PF_UC8_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM48_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM48_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM48_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM48_PF_UC6_SDA ((uint32_t)0X00000009) + +/* IOMUX_PINCM49[PF] Bits */ +#define IOMUX_PINCM49_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM49_PF_GPIOB_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM49_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM49_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM49_PF_TIMG14_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM49_PF_UC8_PICO ((uint32_t)0X00000006) +#define IOMUX_PINCM49_PF_UC8_TX ((uint32_t)0X00000006) + +/* IOMUX_PINCM50[PF] Bits */ +#define IOMUX_PINCM50_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM50_PF_GPIOB_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM50_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM50_PF_TIMG14_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM50_PF_UC8_SCLK ((uint32_t)0X00000006) +#define IOMUX_PINCM50_PF_UC8_RX ((uint32_t)0X00000006) + +/* IOMUX_PINCM51[PF] Bits */ +#define IOMUX_PINCM51_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM51_PF_GPIOB_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM51_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM51_PF_COMP0_OUT ((uint32_t)0X00000005) + +/* IOMUX_PINCM52[PF] Bits */ +#define IOMUX_PINCM52_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM52_PF_GPIOB_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM52_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM52_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) + +/* IOMUX_PINCM53[PF] Bits */ +#define IOMUX_PINCM53_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM53_PF_GPIOA_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM53_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM53_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM53_PF_TIMG14_CCP2 ((uint32_t)0X00000006) +#define IOMUX_PINCM53_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM53_PF_TIMG14_CCP0 ((uint32_t)0X00000009) + +/* IOMUX_PINCM54[PF] Bits */ +#define IOMUX_PINCM54_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM54_PF_GPIOA_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM54_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM54_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM54_PF_TIMG14_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM54_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM54_PF_TIMG14_CCP1 ((uint32_t)0X00000009) + +/* IOMUX_PINCM55[PF] Bits */ +#define IOMUX_PINCM55_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM55_PF_GPIOA_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM55_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM55_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM55_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM55_PF_TIMG1_CCP0 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM56[PF] Bits */ +#define IOMUX_PINCM56_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM56_PF_GPIOB_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM56_PF_UC4_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM56_PF_UC4_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM56_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM56_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM56_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM56_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM56_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/* IOMUX_PINCM57[PF] Bits */ +#define IOMUX_PINCM57_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM57_PF_GPIOB_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM57_PF_UC4_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM57_PF_UC4_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM57_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM57_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM57_PF_TIMG1_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM57_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM57_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/* IOMUX_PINCM58[PF] Bits */ +#define IOMUX_PINCM58_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM58_PF_GPIOB_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM58_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM58_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM58_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM58_PF_TIMG1_CCP1 ((uint32_t)0X00000006) + +/* IOMUX_PINCM59[PF] Bits */ +#define IOMUX_PINCM59_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM59_PF_GPIOA_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM59_PF_UC8_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM59_PF_TIMG14_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM59_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM59_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM59_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM59_PF_TIMG1_CCP1 ((uint32_t)0X0000000A) + +/* IOMUX_PINCM60[PF] Bits */ +#define IOMUX_PINCM60_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM60_PF_GPIOA_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM60_PF_TIMG14_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM60_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM60_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM60_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM60_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM60_PF_COMP0_OUT ((uint32_t)0X00000009) + + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*@}*/ /* end of group MSPM0L112X_PeripheralDecl */ + +/*@}*/ /* end of group MSPM0L112X_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_m0p_mspm0l112x__include */ + diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0l130x.h b/mspm0/source/ti/devices/msp/m0p/mspm0l130x.h index cf12d56..a75c26e 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0l130x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0l130x.h @@ -283,6 +283,7 @@ static FACTORYREGION_OPEN_Regs * const FACTORYREGION #define FLASHCTL_SYS_WEPROTAWIDTH (32) /* !< Bit width of WEPROTA register */ #define FLASHCTL_SYS_WEPROTBWIDTH (4) /* !< Bit width of WEPROTB register */ #define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ +#define VREF_SYS_INT_COMP_REF (1) /* !< Supports internal voltage reference for comparators. */ /****************************************************************************** * DMA Triggers * diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0l134x.h b/mspm0/source/ti/devices/msp/m0p/mspm0l134x.h index e24d60c..5913968 100644 --- a/mspm0/source/ti/devices/msp/m0p/mspm0l134x.h +++ b/mspm0/source/ti/devices/msp/m0p/mspm0l134x.h @@ -276,6 +276,8 @@ static GPTIMER_Regs * const TIMG0 #define FLASHCTL_SYS_WEPROTAWIDTH (32) /* !< Bit width of WEPROTA register */ #define FLASHCTL_SYS_WEPROTBWIDTH (4) /* !< Bit width of WEPROTB register */ #define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register */ +#define VREF_SYS_INT_COMP_REF (1) /* !< Supports internal voltage reference for comparators. */ + /****************************************************************************** * DMA Triggers * diff --git a/mspm0/source/ti/devices/msp/m0p/mspm0l211x.h b/mspm0/source/ti/devices/msp/m0p/mspm0l211x.h new file mode 100644 index 0000000..486168d --- /dev/null +++ b/mspm0/source/ti/devices/msp/m0p/mspm0l211x.h @@ -0,0 +1,1246 @@ +/***************************************************************************** + + Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_m0p_mspm0l211x__include +#define ti_devices_msp_m0p_mspm0l211x__include + +/* Filename: mspm0l211x.h */ +/* Revised: 2025-05-22 14:35:05*/ + +/* Use standard integer types with explicit width */ +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup MSPM0L211X_Definitions MSPM0L211X Definitions + This file defines all structures and symbols for MSPM0L211X + @{ +*/ + +/** @addtogroup MSPM0L211X_CMSIS Device CMSIS Definitions + Configuration of the Processor and Core Peripherals + @{ +*/ +/****************************************************************************** +* Interrupt Definitions * +******************************************************************************/ +typedef enum IRQn +{ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + SYSCTL_INT_IRQn = 0, /* 16 SYSCTL_INT Interrupt */ + DEBUGSS_INT_IRQn = 1, /* 17 DEBUGSS_INT Interrupt */ + UC6_INT_IRQn = 3, /* 19 UC6_INT Interrupt */ + ADC0_INT_IRQn = 4, /* 20 ADC0_INT Interrupt */ + TIMB0_INT_IRQn = 5, /* 21 TIMB0_INT Interrupt */ + TIMB1_INT_IRQn = 6, /* 22 TIMB1_INT Interrupt */ + COMP0_INT_IRQn = 7, /* 23 COMP0_INT Interrupt */ + UC7_INT_IRQn = 8, /* 24 UC7_INT Interrupt */ + UC8_INT_IRQn = 9, /* 25 UC8_INT Interrupt */ + TIMB2_INT_IRQn = 13, /* 29 TIMB2_INT Interrupt */ + TIMB3_INT_IRQn = 14, /* 30 TIMB3_INT Interrupt */ + UC4_INT_IRQn = 15, /* 31 UC4_INT Interrupt */ + TIMG14_INT_IRQn = 16, /* 32 TIMG14_INT Interrupt */ + TIMG2_INT_IRQn = 17, /* 33 TIMG2_INT Interrupt */ + TIMA0_INT_IRQn = 18, /* 34 TIMA0_INT Interrupt */ + TIMG1_INT_IRQn = 19, /* 35 TIMG1_INT Interrupt */ + GPIOA_INT_IRQn = 22, /* 38 GPIOA_INT Interrupt */ + GPIOB_INT_IRQn = 23, /* 39 GPIOB_INT Interrupt */ + UC11_INT_IRQn = 24, /* 40 UC11_INT Interrupt */ + AESADV_INT_IRQn = 26, /* 42 AESADV_INT Interrupt */ + FLASHCTL_INT_IRQn = 27, /* 43 FLASHCTL_INT Interrupt */ + LCD_INT_IRQn = 28, /* 44 LCD_INT Interrupt */ + WWDT0_INT_IRQn = 29, /* 45 WWDT0_INT Interrupt */ + LFSS_INT_IRQn = 30, /* 46 LFSS_INT Interrupt */ + RTC_B_INT_IRQn = 30, /* 46 RTC_B_INT Interrupt */ + IWDT_INT_IRQn = 30, /* 46 IWDT_INT Interrupt */ + DMA_INT_IRQn = 31, /* 47 DMA_INT Interrupt */ +} IRQn_Type; + +#define NonMaskableInt_VECn 2 /* Non Maskable Interrupt */ +#define HardFault_VECn 3 /* Hard Fault Interrupt */ +#define SVCall_VECn 11 /* SV Call Interrupt */ +#define PendSV_VECn 14 /* Pend SV Interrupt */ +#define SysTick_VECn 15 /* System Tick Interrupt */ +#define SYSCTL_INT_VECn 16 /* SYSCTL_INT Interrupt */ +#define DEBUGSS_INT_VECn 17 /* DEBUGSS_INT Interrupt */ +#define UC6_INT_VECn 19 /* UC6_INT Interrupt */ +#define ADC0_INT_VECn 20 /* ADC0_INT Interrupt */ +#define TIMB0_INT_VECn 21 /* TIMB0_INT Interrupt */ +#define TIMB1_INT_VECn 22 /* TIMB1_INT Interrupt */ +#define COMP0_INT_VECn 23 /* COMP0_INT Interrupt */ +#define UC7_INT_VECn 24 /* UC7_INT Interrupt */ +#define UC8_INT_VECn 25 /* UC8_INT Interrupt */ +#define TIMB2_INT_VECn 29 /* TIMB2_INT Interrupt */ +#define TIMB3_INT_VECn 30 /* TIMB3_INT Interrupt */ +#define UC4_INT_VECn 31 /* UC4_INT Interrupt */ +#define TIMG14_INT_VECn 32 /* TIMG14_INT Interrupt */ +#define TIMG2_INT_VECn 33 /* TIMG2_INT Interrupt */ +#define TIMA0_INT_VECn 34 /* TIMA0_INT Interrupt */ +#define TIMG1_INT_VECn 35 /* TIMG1_INT Interrupt */ +#define GPIOA_INT_VECn 38 /* GPIOA_INT Interrupt */ +#define GPIOB_INT_VECn 39 /* GPIOB_INT Interrupt */ +#define UC11_INT_VECn 40 /* UC11_INT Interrupt */ +#define AESADV_INT_VECn 42 /* AESADV_INT Interrupt */ +#define FLASHCTL_INT_VECn 43 /* FLASHCTL_INT Interrupt */ +#define LCD_INT_VECn 44 /* LCD_INT Interrupt */ +#define WWDT0_INT_VECn 45 /* WWDT0_INT Interrupt */ +#define LFSS_INT_VECn 46 /* LFSS_INT Interrupt */ +#define RTC_B_INT_VECn 46 /* RTC_B_INT Interrupt */ +#define IWDT_INT_VECn 46 /* IWDT_INT Interrupt */ +#define DMA_INT_VECn 47 /* DMA_INT Interrupt */ + + +/****************************************************************************** +* Ignore unused variables * +******************************************************************************/ + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/****************************************************************************** +* Processor and Core Peripheral Section * +******************************************************************************/ + +#define __CM0PLUS_REV 0x0001U /* Core revision */ +#define __MPU_PRESENT 0x0001U /* MPU present */ +#define __VTOR_PRESENT 0x0001U /* VTOR present */ +#define __NVIC_PRIO_BITS 0x0002U /* Number of bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0plus.h" /* Processor and core peripherals */ + +/****************************************************************************** +* Peripheral headers * +******************************************************************************/ +/** @addtogroup MSPM0L211X_Peripherals MSPM0L211X Peripherals + MSPM0L211X Peripheral registers structures + @{ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __MSPM0_HAS_ADC12__ +#define __MSPM0_HAS_AESADV__ +#define __MSPM0_HAS_TIMER_B__ +#define __MSPM0_HAS_COMP__ +#define __MSPM0_HAS_CRC__ +#define __MSPM0_HAS_GPIO__ +#define __MSPM0_HAS_TIMER_A__ +#define __MSPM0_HAS_TIMER_G__ +#define __MSPM0_HAS_KEYSTORE_CTL__ +#define __MSPM0_HAS_LCD__ +#define __MSPM0_HAS_LFSS__ +#define __MSPM0_HAS_RTC_B__ +#define __MSPM0_HAS_IWDT__ +#define __MCU_HAS_SPGSS__ +#define __MCU_HAS_UNICOMMI2CC__ +#define __MCU_HAS_UNICOMMI2CT__ +#define __MCU_HAS_UNICOMMSPI__ +#define __MCU_HAS_UNICOMMUART__ +#define __MCU_HAS_UNICOMM__ +#define __MSPM0_HAS_VREF__ +#define __MSPM0_HAS_WWDT__ +#define __MSPM0_HAS_ECC__ + +/*@}*/ /* end of group MSPM0L211X_Peripherals */ + +/****************************************************************************** +* Device and peripheral memory map * +******************************************************************************/ +/** @addtogroup MSPM0L211X_MemoryMap MSPM0L211X Memory Mapping + @{ +*/ + +#define ADC0_BASE (0x40004000U) /*!< Base address of module ADC0 */ +#define COMP0_BASE (0x40008000U) /*!< Base address of module COMP0 */ +#define VREF_BASE (0x40030000U) /*!< Base address of module VREF */ +#define LCD_BASE (0x40070000U) /*!< Base address of module LCD */ +#define WWDT0_BASE (0x40080000U) /*!< Base address of module WWDT0 */ +#define TIMG14_BASE (0x40084000U) /*!< Base address of module TIMG14 */ +#define TIMG1_BASE (0x40086000U) /*!< Base address of module TIMG1 */ +#define TIMG2_BASE (0x40088000U) /*!< Base address of module TIMG2 */ +#define LFSS_BASE (0x40094000U) /*!< Base address of module LFSS */ +#define RTC_B_BASE (0x40094000U) /*!< Base address of module RTC_B */ +#define IWDT_BASE (0x40094000U) /*!< Base address of module IWDT */ +#define GPIOA_BASE (0x400A0000U) /*!< Base address of module GPIOA */ +#define GPIOB_BASE (0x400A2000U) /*!< Base address of module GPIOB */ +#define KEYSTORECTL_BASE (0x400AC000U) /*!< Base address of module KEYSTORECTL */ +#define SYSCTL_BASE (0x400AF000U) /*!< Base address of module SYSCTL */ +#define TIMB0_BASE (0x400B8000U) /*!< Base address of module TIMB0 */ +#define TIMB1_BASE (0x400BA000U) /*!< Base address of module TIMB1 */ +#define TIMB2_BASE (0x400BC000U) /*!< Base address of module TIMB2 */ +#define TIMB3_BASE (0x400BE000U) /*!< Base address of module TIMB3 */ +#define DEBUGSS_BASE (0x400C7000U) /*!< Base address of module DEBUGSS */ +#define EVENTLP_BASE (0x400C9000U) /*!< Base address of module EVENTLP */ +#define FLASHCTL_BASE (0x400CD000U) /*!< Base address of module FLASHCTL */ +#define CPUSS_BASE (0x40400000U) /*!< Base address of module CPUSS */ +#define WUC_BASE (0x40424000U) /*!< Base address of module WUC */ +#define IOMUX_BASE (0x40428000U) /*!< Base address of module IOMUX */ +#define DMA_BASE (0x4042A000U) /*!< Base address of module DMA */ +#define CRC0_BASE (0x40440000U) /*!< Base address of module CRC0 */ +#define AESADV_BASE (0x40442000U) /*!< Base address of module AESADV */ +#define ADC0_SVT_BASE (0x4055A000U) /*!< Base address of module ADC0_SVT */ +#define TIMA0_BASE (0x40860000U) /*!< Base address of module TIMA0 */ +#define UC4_UART_BASE (0x40A00000U) /*!< Base address of module UC4_UART */ +#define UC6_I2CC_BASE (0x40A22000U) /*!< Base address of module UC6_I2CC */ +#define UC7_I2CT_BASE (0x40A44000U) /*!< Base address of module UC7_I2CT */ +#define UC4_SPI_BASE (0x40A60000U) /*!< Base address of module UC4_SPI */ +#define UC4_BASE (0x40A80000U) /*!< Base address of module UC4 */ +#define UC6_BASE (0x40A82000U) /*!< Base address of module UC6 */ +#define UC7_BASE (0x40A84000U) /*!< Base address of module UC7 */ +#define SPG0_BASE (0x40A9F000U) /*!< Base address of module SPG0 */ +#define UC8_UART_BASE (0x40B00000U) /*!< Base address of module UC8_UART */ +#define UC11_UART_BASE (0x40B02000U) /*!< Base address of module UC11_UART */ +#define UC8_SPI_BASE (0x40B60000U) /*!< Base address of module UC8_SPI */ +#define UC8_BASE (0x40B80000U) /*!< Base address of module UC8 */ +#define UC11_BASE (0x40B82000U) /*!< Base address of module UC11 */ +#define FACTORYREGION_BASE (0x41C40000U) /*!< Base address of module FACTORYREGION */ + + +typedef struct { + UNICOMM_Regs * const inst; + UNICOMMUART_Regs * const uart; + UNICOMMI2CC_Regs * const i2cc; + UNICOMMI2CT_Regs * const i2ct; + UNICOMMSPI_Regs * const spi; + bool const fixedMode; +} UNICOMM_Inst_Regs; + +static const UNICOMM_Inst_Regs UC4_Inst = { + .inst = (UNICOMM_Regs *) UC4_BASE, + .uart = (UNICOMMUART_Regs *) UC4_UART_BASE, + .spi = (UNICOMMSPI_Regs *) UC4_SPI_BASE, + .fixedMode = false +}; +static const UNICOMM_Inst_Regs UC6_Inst = { + .inst = (UNICOMM_Regs *) UC6_BASE, + .i2cc = (UNICOMMI2CC_Regs *) UC6_I2CC_BASE, + .fixedMode = true +}; +static const UNICOMM_Inst_Regs UC7_Inst = { + .inst = (UNICOMM_Regs *) UC7_BASE, + .i2ct = (UNICOMMI2CT_Regs *) UC7_I2CT_BASE, + .fixedMode = true +}; +static const UNICOMM_Inst_Regs UC8_Inst = { + .inst = (UNICOMM_Regs *) UC8_BASE, + .uart = (UNICOMMUART_Regs *) UC8_UART_BASE, + .spi = (UNICOMMSPI_Regs *) UC8_SPI_BASE, + .fixedMode = false +}; +static const UNICOMM_Inst_Regs UC11_Inst = { + .inst = (UNICOMM_Regs *) UC11_BASE, + .uart = (UNICOMMUART_Regs *) UC11_UART_BASE, + .fixedMode = true +}; + + +/*@}*/ /* end of group MSPM0L211X_MemoryMap */ + +/****************************************************************************** +* Peripheral declarations * +******************************************************************************/ +/** @addtogroup MSPM0L211X_PeripheralDecl MSPM0L211X Peripheral Declaration + @{ +*/ + +static ADC12_Regs * const ADC0 = ((ADC12_Regs *) ADC0_BASE); +static COMP_Regs * const COMP0 = ((COMP_Regs *) COMP0_BASE); +static VREF_Regs * const VREF = ((VREF_Regs *) VREF_BASE); +static LCD_Regs * const LCD = ((LCD_Regs *) LCD_BASE); +static WWDT_Regs * const WWDT0 = ((WWDT_Regs *) WWDT0_BASE); +static GPTIMER_Regs * const TIMG14 = ((GPTIMER_Regs *) TIMG14_BASE); +static GPTIMER_Regs * const TIMG1 = ((GPTIMER_Regs *) TIMG1_BASE); +static GPTIMER_Regs * const TIMG2 = ((GPTIMER_Regs *) TIMG2_BASE); +static LFSS_Regs * const LFSS = ((LFSS_Regs *) LFSS_BASE); +static RTC_Regs * const RTC_B = ((RTC_Regs *) RTC_B_BASE); +static GPIO_Regs * const GPIOA = ((GPIO_Regs *) GPIOA_BASE); +static GPIO_Regs * const GPIOB = ((GPIO_Regs *) GPIOB_BASE); +static KEYSTORECTL_Regs * const KEYSTORECTL = ((KEYSTORECTL_Regs *) KEYSTORECTL_BASE); +static SYSCTL_Regs * const SYSCTL = ((SYSCTL_Regs *) SYSCTL_BASE); +static BTIMER_Regs * const TIMB0 = ((BTIMER_Regs *) TIMB0_BASE); +static BTIMER_Regs * const TIMB1 = ((BTIMER_Regs *) TIMB1_BASE); +static BTIMER_Regs * const TIMB2 = ((BTIMER_Regs *) TIMB2_BASE); +static BTIMER_Regs * const TIMB3 = ((BTIMER_Regs *) TIMB3_BASE); +static DEBUGSS_Regs * const DEBUGSS = ((DEBUGSS_Regs *) DEBUGSS_BASE); +static FLASHCTL_Regs * const FLASHCTL = ((FLASHCTL_Regs *) FLASHCTL_BASE); +static CPUSS_Regs * const CPUSS = ((CPUSS_Regs *) CPUSS_BASE); +static WUC_Regs * const WUC = ((WUC_Regs *) WUC_BASE); +static IOMUX_Regs * const IOMUX = ((IOMUX_Regs *) IOMUX_BASE); +static DMA_Regs * const DMA = ((DMA_Regs *) DMA_BASE); +static CRC_Regs * const CRC0 = ((CRC_Regs *) CRC0_BASE); +static CRC_Regs * const CRC = ((CRC_Regs *) CRC0_BASE); +static AESADV_Regs * const AESADV = ((AESADV_Regs *) AESADV_BASE); +static ADC12_PERIPHERALREGIONSVT_Regs * const ADC0_SVT = ((ADC12_PERIPHERALREGIONSVT_Regs *) ADC0_SVT_BASE); +static GPTIMER_Regs * const TIMA0 = ((GPTIMER_Regs *) TIMA0_BASE); +static UNICOMMUART_Regs * const UC4_UART = ((UNICOMMUART_Regs *) UC4_UART_BASE); +static UNICOMMI2CC_Regs * const UC6_I2CC = ((UNICOMMI2CC_Regs *) UC6_I2CC_BASE); +static UNICOMMI2CT_Regs * const UC7_I2CT = ((UNICOMMI2CT_Regs *) UC7_I2CT_BASE); +static UNICOMMSPI_Regs * const UC4_SPI = ((UNICOMMSPI_Regs *) UC4_SPI_BASE); +static UNICOMM_Inst_Regs * const UC4 = ((UNICOMM_Inst_Regs *) &UC4_Inst); +static UNICOMM_Inst_Regs * const UC6 = ((UNICOMM_Inst_Regs *) &UC6_Inst); +static UNICOMM_Inst_Regs * const UC7 = ((UNICOMM_Inst_Regs *) &UC7_Inst); +static SPGSS_Regs * const SPG0 = ((SPGSS_Regs *) SPG0_BASE); +static UNICOMMUART_Regs * const UC8_UART = ((UNICOMMUART_Regs *) UC8_UART_BASE); +static UNICOMMUART_Regs * const UC11_UART = ((UNICOMMUART_Regs *) UC11_UART_BASE); +static UNICOMMSPI_Regs * const UC8_SPI = ((UNICOMMSPI_Regs *) UC8_SPI_BASE); +static UNICOMM_Inst_Regs * const UC8 = ((UNICOMM_Inst_Regs *) &UC8_Inst); +static UNICOMM_Inst_Regs * const UC11 = ((UNICOMM_Inst_Regs *) &UC11_Inst); +static FACTORYREGION_OPEN_Regs * const FACTORYREGION = ((FACTORYREGION_OPEN_Regs *) FACTORYREGION_BASE); + + +/****************************************************************************** +* SYS parameters * +******************************************************************************/ + +#define ADC_SYS_NUM_ANALOG_CHAN (32) /* !< Number of analog channels. */ +#define CRC0_SYS_CRC32_ENABLE (0) /* !< Parameter to exclude or include 32-bit CRC. */ +#define DMA_SYS_N_DMA_CHANNEL (3) /* !< Number of DMA channels implemented in DMA. */ +#define DMA_SYS_N_DMA_FULL_CHANNEL (2) /* !< Number of FULL-DMA channels implemented in DMA. If + SYS_N_DMA_CHANNEL is larger than SYS_N_DMA_FULL_CHANNEL, the + remaining channel will be BASIC channel with limited functionality. */ +#define DMA_SYS_MMR_AUTO (1) /* !< Boolean for if auto enable channels implemented in DMA. */ +#define DMA_SYS_MMR_EM (1) /* !< Boolean for if extended mode channels implemented in DMA. */ +#define DMA_SYS_MMR_LLONG (1) /* !< Boolean for if channels implemented in DMA with 128-bit access. */ +#define DMA_SYS_MMR_STRIDE (1) /* !< Boolean for if channels implemented in DMA with stride mode. */ +#define FLASHCTL_SYS_DATAWIDTH (64) /* !< Data bit width of a single flash word: Minimum: 64 Maximum: + 128 */ +#define FLASHCTL_SYS_WEPROTBWIDTH (16) /* !< Bit width of WEPROTB register. */ +#define FLASHCTL_SYS_WEPROTAWIDTH (0) /* !< Bit width of WEPROTA register. */ +#define FLASHCTL_SYS_WEPROTCWIDTH (0) /* !< Bit width of WEPROTC register. */ +#define COMP_SYS_DACOUT_EN (1) /* !< Boolean for if 8-bit DAC output to pin is available */ + + +#define UC4_SPI_SYS_EN_REPEAT (0) +#define UC4_SPI_SYS_EN_RTOUT (0) +#define UC4_SPI_SYS_EN_COMMAND_DATA (0) +#define UC4_SPI_SYS_EN_CS_CTL (0) +#define UC4_SPI_SYS_EN_PACKING (0) +#define UC4_SPI_SYS_EN_FENTRIES (1) +#define UC4_SPI_SYS_EN_DMA (0) +#define UC4_SPI_SYS_EN_CLKDIV (1) + +#define UC8_SPI_SYS_EN_REPEAT (0) +#define UC8_SPI_SYS_EN_RTOUT (0) +#define UC8_SPI_SYS_EN_COMMAND_DATA (0) +#define UC8_SPI_SYS_EN_CS_CTL (0) +#define UC8_SPI_SYS_EN_PACKING (0) +#define UC8_SPI_SYS_EN_FENTRIES (1) +#define UC8_SPI_SYS_EN_DMA (0) +#define UC8_SPI_SYS_EN_CLKDIV (1) + + +#define UC4_UART_SYS_GLITCH_FILTER (0) +#define UC4_UART_SYS_HW_FLOW_CONTROL (1) +#define UC4_UART_SYS_9_BIT (1) +#define UC4_UART_SYS_RS485 (1) +#define UC4_UART_SYS_LIN (1) +#define UC4_UART_SYS_DALI (1) +#define UC4_UART_SYS_IRDA (1) +#define UC4_UART_SYS_SMART_CARD (1) +#define UC4_UART_SYS_IDLE_LINE (1) +#define UC4_UART_SYS_MANCHESTER_ENCODING (1) +#define UC4_UART_SYS_FIFO_LENGTH (4) +#define UC4_UART_SYS_RX_TIMEOUT (1) +#define UC4_UART_SYS_DMA (1) +#define UC4_UART_SYS_EXTERNAL_DIRECTION (1) + +#define UC8_UART_SYS_GLITCH_FILTER (0) +#define UC8_UART_SYS_HW_FLOW_CONTROL (0) +#define UC8_UART_SYS_9_BIT (0) +#define UC8_UART_SYS_RS485 (0) +#define UC8_UART_SYS_LIN (0) +#define UC8_UART_SYS_DALI (0) +#define UC8_UART_SYS_IRDA (0) +#define UC8_UART_SYS_SMART_CARD (0) +#define UC8_UART_SYS_IDLE_LINE (0) +#define UC8_UART_SYS_MANCHESTER_ENCODING (0) +#define UC8_UART_SYS_FIFO_LENGTH (1) +#define UC8_UART_SYS_RX_TIMEOUT (0) +#define UC8_UART_SYS_DMA (0) +#define UC8_UART_SYS_EXTERNAL_DIRECTION (0) + +#define UC11_UART_SYS_GLITCH_FILTER (0) +#define UC11_UART_SYS_HW_FLOW_CONTROL (0) +#define UC11_UART_SYS_9_BIT (0) +#define UC11_UART_SYS_RS485 (0) +#define UC11_UART_SYS_LIN (0) +#define UC11_UART_SYS_DALI (0) +#define UC11_UART_SYS_IRDA (0) +#define UC11_UART_SYS_SMART_CARD (0) +#define UC11_UART_SYS_IDLE_LINE (0) +#define UC11_UART_SYS_MANCHESTER_ENCODING (0) +#define UC11_UART_SYS_FIFO_LENGTH (1) +#define UC11_UART_SYS_RX_TIMEOUT (0) +#define UC11_UART_SYS_DMA (0) +#define UC11_UART_SYS_EXTERNAL_DIRECTION (0) + +/****************************************************************************** +* DMA Triggers * +******************************************************************************/ + +/* External DMA Triggers */ +#define DMA_SOFTWARE_TRIG (0) +#define DMA_GENERIC_SUB0_TRIG (1) +#define DMA_GENERIC_SUB1_TRIG (2) +#define DMA_AESADV_AES_0_TRIG (3) +#define DMA_AESADV_AES_1_TRIG (4) +#define DMA_UC4_RX_BD_TRIG (5) +#define DMA_UC4_TX_BD_TRIG (6) +#define DMA_UC6_RX_BD_TRIG (7) +#define DMA_UC6_TX_BD_TRIG (8) +#define DMA_UC7_RX_BD_TRIG (9) +#define DMA_UC7_TX_BD_TRIG (10) +#define DMA_UC8_RX_BD_TRIG (11) +#define DMA_UC8_TX_BD_TRIG (12) +#define DMA_ADC0_EVT_GEN_BD_TRIG (13) + +/* Internal DMA Triggers */ +#define DMA_CH_0_TRIG (0) +#define DMA_CH_1_TRIG (1) +#define DMA_CH_2_TRIG (2) + + + +/****************************************************************************** +* IOMUX Pin Definitions * +******************************************************************************/ + +typedef enum IOMUX_PINCM +{ + IOMUX_PINCM1 = (0), + IOMUX_PINCM2 = (1), + IOMUX_PINCM3 = (2), + IOMUX_PINCM4 = (3), + IOMUX_PINCM5 = (4), + IOMUX_PINCM6 = (5), + IOMUX_PINCM7 = (6), + IOMUX_PINCM8 = (7), + IOMUX_PINCM9 = (8), + IOMUX_PINCM10 = (9), + IOMUX_PINCM11 = (10), + IOMUX_PINCM12 = (11), + IOMUX_PINCM13 = (12), + IOMUX_PINCM14 = (13), + IOMUX_PINCM15 = (14), + IOMUX_PINCM16 = (15), + IOMUX_PINCM17 = (16), + IOMUX_PINCM18 = (17), + IOMUX_PINCM19 = (18), + IOMUX_PINCM20 = (19), + IOMUX_PINCM21 = (20), + IOMUX_PINCM22 = (21), + IOMUX_PINCM23 = (22), + IOMUX_PINCM24 = (23), + IOMUX_PINCM25 = (24), + IOMUX_PINCM26 = (25), + IOMUX_PINCM27 = (26), + IOMUX_PINCM28 = (27), + IOMUX_PINCM29 = (28), + IOMUX_PINCM30 = (29), + IOMUX_PINCM31 = (30), + IOMUX_PINCM32 = (31), + IOMUX_PINCM33 = (32), + IOMUX_PINCM34 = (33), + IOMUX_PINCM35 = (34), + IOMUX_PINCM36 = (35), + IOMUX_PINCM37 = (36), + IOMUX_PINCM38 = (37), + IOMUX_PINCM39 = (38), + IOMUX_PINCM40 = (39), + IOMUX_PINCM41 = (40), + IOMUX_PINCM42 = (41), + IOMUX_PINCM43 = (42), + IOMUX_PINCM44 = (43), + IOMUX_PINCM45 = (44), + IOMUX_PINCM46 = (45), + IOMUX_PINCM47 = (46), + IOMUX_PINCM48 = (47), + IOMUX_PINCM49 = (48), + IOMUX_PINCM50 = (49), + IOMUX_PINCM51 = (50), + IOMUX_PINCM52 = (51), + IOMUX_PINCM53 = (52), + IOMUX_PINCM54 = (53), + IOMUX_PINCM55 = (54), + IOMUX_PINCM56 = (55), + IOMUX_PINCM57 = (56), + IOMUX_PINCM58 = (57), + IOMUX_PINCM59 = (58), + IOMUX_PINCM60 = (59), +} IOMUX_PINCM; + + +/*IOMUX_PINCM1[PF] Bits */ +#define IOMUX_PINCM1_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM1_PF_GPIOA_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM1_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM1_PF_UC6_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM1_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM1_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM1_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM1_PF_SYSCTL_BEEPER ((uint32_t)0X00000008) +#define IOMUX_PINCM1_PF_TIMG14_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM1_PF_UC7_SDA ((uint32_t)0X0000000B) + +/*IOMUX_PINCM2[PF] Bits */ +#define IOMUX_PINCM2_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM2_PF_GPIOA_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM2_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM2_PF_UC6_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM2_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM2_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM2_PF_TIMG14_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM2_PF_TIMG14_CCP2 ((uint32_t)0X00000007) +#define IOMUX_PINCM2_PF_TIMG14_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM2_PF_UC7_SCL ((uint32_t)0X0000000B) + +/*IOMUX_PINCM3[PF] Bits */ +#define IOMUX_PINCM3_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM3_PF_GPIOA_DIO28 ((uint32_t)0X00000001) +#define IOMUX_PINCM3_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM3_PF_UC6_SDA ((uint32_t)0X00000003) +#define IOMUX_PINCM3_PF_TIMA0_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM3_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM3_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM3_PF_TIMA0_CCP1 ((uint32_t)0X00000007) + +/*IOMUX_PINCM4[PF] Bits */ +#define IOMUX_PINCM4_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM4_PF_GPIOA_DIO29 ((uint32_t)0X00000001) +#define IOMUX_PINCM4_PF_UC7_SCL ((uint32_t)0X00000002) +#define IOMUX_PINCM4_PF_TIMG14_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM4_PF_TIMG1_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM4_PF_UC4_CS0 ((uint32_t)0X00000007) +#define IOMUX_PINCM4_PF_UC4_CTS ((uint32_t)0X00000007) + +/*IOMUX_PINCM5[PF] Bits */ +#define IOMUX_PINCM5_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM5_PF_GPIOA_DIO30 ((uint32_t)0X00000001) +#define IOMUX_PINCM5_PF_UC7_SDA ((uint32_t)0X00000002) +#define IOMUX_PINCM5_PF_TIMG14_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM5_PF_TIMG1_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM5_PF_UC4_POCI ((uint32_t)0X00000007) +#define IOMUX_PINCM5_PF_UC4_RTS ((uint32_t)0X00000007) + +/*IOMUX_PINCM6[PF] Bits */ +#define IOMUX_PINCM6_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM6_PF_GPIOA_DIO31 ((uint32_t)0X00000001) +#define IOMUX_PINCM6_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM6_PF_UC6_SCL ((uint32_t)0X00000003) +#define IOMUX_PINCM6_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM6_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM6_PF_TIMG2_CCP1 ((uint32_t)0X00000007) + +/*IOMUX_PINCM7[PF] Bits */ +#define IOMUX_PINCM7_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM7_PF_GPIOA_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM7_PF_TIMG14_CCP3 ((uint32_t)0X00000002) +#define IOMUX_PINCM7_PF_UC4_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_UC4_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM7_PF_TIMG2_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM7_PF_UC8_CS0 ((uint32_t)0X00000005) +#define IOMUX_PINCM7_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM7_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM7_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM7_PF_TIMA_FAULT1 ((uint32_t)0X00000009) +#define IOMUX_PINCM7_PF_TIMA0_CCP0 ((uint32_t)0X0000000B) + +/*IOMUX_PINCM8[PF] Bits */ +#define IOMUX_PINCM8_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM8_PF_GPIOA_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM8_PF_TIMG14_CCP2 ((uint32_t)0X00000002) +#define IOMUX_PINCM8_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM8_PF_TIMA0_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM8_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM8_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM8_PF_TIMA0_CCP2 ((uint32_t)0X00000008) +#define IOMUX_PINCM8_PF_UC8_PICO ((uint32_t)0X0000000A) +#define IOMUX_PINCM8_PF_UC8_TX ((uint32_t)0X0000000A) + +/*IOMUX_PINCM9[PF] Bits */ +#define IOMUX_PINCM9_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM9_PF_GPIOA_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM9_PF_TIMG14_CCP3 ((uint32_t)0X00000002) +#define IOMUX_PINCM9_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM9_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM9_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM9_PF_SYSCTL_LFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM9_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM9_PF_TIMA0_CCP3 ((uint32_t)0X00000008) +#define IOMUX_PINCM9_PF_UC8_SCLK ((uint32_t)0X0000000A) +#define IOMUX_PINCM9_PF_UC8_RX ((uint32_t)0X0000000A) +#define IOMUX_PINCM9_PF_UC4_CS0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM9_PF_UC4_CTS ((uint32_t)0X0000000B) + +/*IOMUX_PINCM10[PF] Bits */ +#define IOMUX_PINCM10_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM10_PF_GPIOA_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM10_PF_TIMG14_CCP2 ((uint32_t)0X00000002) +#define IOMUX_PINCM10_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM10_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM10_PF_TIMG14_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM10_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM10_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM10_PF_TIMA_FAULT1 ((uint32_t)0X00000008) +#define IOMUX_PINCM10_PF_UC4_CS0 ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_UC4_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM10_PF_UC8_PICO ((uint32_t)0X0000000B) +#define IOMUX_PINCM10_PF_UC8_TX ((uint32_t)0X0000000B) + +/*IOMUX_PINCM11[PF] Bits */ +#define IOMUX_PINCM11_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM11_PF_GPIOA_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM11_PF_TIMG14_CCP3 ((uint32_t)0X00000002) +#define IOMUX_PINCM11_PF_UC4_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_UC4_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM11_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM11_PF_TIMG14_CCP1 ((uint32_t)0X00000005) +#define IOMUX_PINCM11_PF_SYSCTL_HFCLKIN ((uint32_t)0X00000006) +#define IOMUX_PINCM11_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM11_PF_TIMA_FAULT0 ((uint32_t)0X00000008) +#define IOMUX_PINCM11_PF_UC4_POCI ((uint32_t)0X00000009) +#define IOMUX_PINCM11_PF_UC4_RTS ((uint32_t)0X00000009) +#define IOMUX_PINCM11_PF_TIMA0_CCP2_CMPL ((uint32_t)0X0000000A) +#define IOMUX_PINCM11_PF_UC8_SCLK ((uint32_t)0X0000000B) +#define IOMUX_PINCM11_PF_UC8_RX ((uint32_t)0X0000000B) + +/*IOMUX_PINCM12[PF] Bits */ +#define IOMUX_PINCM12_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM12_PF_GPIOB_DIO00 ((uint32_t)0X00000001) +#define IOMUX_PINCM12_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM12_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM12_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM12_PF_TIMG14_CCP0 ((uint32_t)0X00000006) + +/*IOMUX_PINCM13[PF] Bits */ +#define IOMUX_PINCM13_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM13_PF_GPIOB_DIO01 ((uint32_t)0X00000001) +#define IOMUX_PINCM13_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM13_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM13_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM13_PF_TIMG14_CCP1 ((uint32_t)0X00000006) + +/*IOMUX_PINCM14[PF] Bits */ +#define IOMUX_PINCM14_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM14_PF_GPIOA_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM14_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM14_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000003) +#define IOMUX_PINCM14_PF_TIMG14_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM14_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM14_PF_TIMG14_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM14_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM14_PF_TIMA0_CCP1 ((uint32_t)0X00000008) +#define IOMUX_PINCM14_PF_SYSCTL_FCC_IN ((uint32_t)0X0000000A) +#define IOMUX_PINCM14_PF_UC4_POCI ((uint32_t)0X0000000B) +#define IOMUX_PINCM14_PF_UC4_RTS ((uint32_t)0X0000000B) + +/*IOMUX_PINCM15[PF] Bits */ +#define IOMUX_PINCM15_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM15_PF_GPIOB_DIO02 ((uint32_t)0X00000001) +#define IOMUX_PINCM15_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM15_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM15_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM15_PF_UC11_TX ((uint32_t)0X00000008) +#define IOMUX_PINCM15_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM15_PF_UC4_PICO ((uint32_t)0X0000000B) +#define IOMUX_PINCM15_PF_UC4_TX ((uint32_t)0X0000000B) + +/*IOMUX_PINCM16[PF] Bits */ +#define IOMUX_PINCM16_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM16_PF_GPIOB_DIO03 ((uint32_t)0X00000001) +#define IOMUX_PINCM16_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM16_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM16_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM16_PF_UC11_RX ((uint32_t)0X00000008) +#define IOMUX_PINCM16_PF_TIMA0_CCP0 ((uint32_t)0X0000000A) +#define IOMUX_PINCM16_PF_UC4_SCLK ((uint32_t)0X0000000B) +#define IOMUX_PINCM16_PF_UC4_RX ((uint32_t)0X0000000B) + +/*IOMUX_PINCM17[PF] Bits */ +#define IOMUX_PINCM17_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM17_PF_GPIOB_DIO04 ((uint32_t)0X00000001) +#define IOMUX_PINCM17_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM17_PF_TIMA0_CCP1 ((uint32_t)0X00000004) +#define IOMUX_PINCM17_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM17_PF_TIMG14_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM17_PF_TIMG1_CCP0 ((uint32_t)0X00000007) + +/*IOMUX_PINCM18[PF] Bits */ +#define IOMUX_PINCM18_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM18_PF_GPIOB_DIO05 ((uint32_t)0X00000001) +#define IOMUX_PINCM18_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM18_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM18_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM18_PF_TIMG14_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM18_PF_TIMG1_CCP1 ((uint32_t)0X00000007) + +/*IOMUX_PINCM19[PF] Bits */ +#define IOMUX_PINCM19_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM19_PF_GPIOA_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM19_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM19_PF_UC4_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_UC4_CTS ((uint32_t)0X00000003) +#define IOMUX_PINCM19_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM19_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM19_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM19_PF_TIMA_FAULT0 ((uint32_t)0X00000007) +#define IOMUX_PINCM19_PF_TIMG2_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM19_PF_SYSCTL_HFCLKIN ((uint32_t)0X0000000A) +#define IOMUX_PINCM19_PF_UC4_POCI ((uint32_t)0X0000000B) +#define IOMUX_PINCM19_PF_UC4_RTS ((uint32_t)0X0000000B) + +/*IOMUX_PINCM20[PF] Bits */ +#define IOMUX_PINCM20_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM20_PF_GPIOA_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM20_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM20_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM20_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM20_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM20_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM20_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM20_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM20_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM20_PF_TIMG2_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM20_PF_UC4_CS0 ((uint32_t)0X0000000B) +#define IOMUX_PINCM20_PF_UC4_CTS ((uint32_t)0X0000000B) + +/*IOMUX_PINCM21[PF] Bits */ +#define IOMUX_PINCM21_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM21_PF_GPIOA_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM21_PF_UC4_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC4_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM21_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM21_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM21_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM21_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM21_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM21_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM21_PF_UC7_SDA ((uint32_t)0X00000008) +#define IOMUX_PINCM21_PF_TIMA_FAULT1 ((uint32_t)0X0000000A) + +/*IOMUX_PINCM22[PF] Bits */ +#define IOMUX_PINCM22_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM22_PF_GPIOA_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM22_PF_UC4_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC4_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM22_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM22_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM22_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM22_PF_TIMG14_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM22_PF_UC7_SCL ((uint32_t)0X00000008) +#define IOMUX_PINCM22_PF_TIMA_FAULT0 ((uint32_t)0X0000000A) + +/*IOMUX_PINCM23[PF] Bits */ +#define IOMUX_PINCM23_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM23_PF_GPIOB_DIO06 ((uint32_t)0X00000001) +#define IOMUX_PINCM23_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM23_PF_UC8_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM23_PF_TIMG14_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM23_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM23_PF_TIMA_FAULT2 ((uint32_t)0X00000008) + +/*IOMUX_PINCM24[PF] Bits */ +#define IOMUX_PINCM24_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM24_PF_GPIOB_DIO07 ((uint32_t)0X00000001) +#define IOMUX_PINCM24_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM24_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM24_PF_TIMG14_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM24_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM24_PF_LCD_LCDLFCLK ((uint32_t)0X00000008) + +/*IOMUX_PINCM25[PF] Bits */ +#define IOMUX_PINCM25_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM25_PF_GPIOB_DIO08 ((uint32_t)0X00000001) +#define IOMUX_PINCM25_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM25_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM25_PF_COMP0_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM25_PF_TIMG1_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM25_PF_LCD_LCDSON ((uint32_t)0X00000008) + +/*IOMUX_PINCM26[PF] Bits */ +#define IOMUX_PINCM26_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM26_PF_GPIOB_DIO09 ((uint32_t)0X00000001) +#define IOMUX_PINCM26_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM26_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM26_PF_TIMA0_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM26_PF_TIMG1_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM26_PF_LCD_LCDEN ((uint32_t)0X00000008) + +/*IOMUX_PINCM27[PF] Bits */ +#define IOMUX_PINCM27_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM27_PF_GPIOB_DIO10 ((uint32_t)0X00000001) +#define IOMUX_PINCM27_PF_TIMG14_CCP0 ((uint32_t)0X00000002) +#define IOMUX_PINCM27_PF_TIMG14_CCP2 ((uint32_t)0X00000003) +#define IOMUX_PINCM27_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM27_PF_TIMG1_CCP0 ((uint32_t)0X00000005) + +/*IOMUX_PINCM28[PF] Bits */ +#define IOMUX_PINCM28_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM28_PF_GPIOB_DIO11 ((uint32_t)0X00000001) +#define IOMUX_PINCM28_PF_TIMG14_CCP1 ((uint32_t)0X00000002) +#define IOMUX_PINCM28_PF_TIMG14_CCP3 ((uint32_t)0X00000003) +#define IOMUX_PINCM28_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM28_PF_TIMG1_CCP1 ((uint32_t)0X00000005) + +/*IOMUX_PINCM29[PF] Bits */ +#define IOMUX_PINCM29_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM29_PF_GPIOB_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM29_PF_TIMA0_CCP2 ((uint32_t)0X00000003) +#define IOMUX_PINCM29_PF_TIMA_FAULT1 ((uint32_t)0X00000004) +#define IOMUX_PINCM29_PF_TIMA0_CCP1 ((uint32_t)0X00000005) + +/*IOMUX_PINCM30[PF] Bits */ +#define IOMUX_PINCM30_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM30_PF_GPIOB_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM30_PF_TIMA0_CCP3 ((uint32_t)0X00000003) +#define IOMUX_PINCM30_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM30_PF_UC8_CS0 ((uint32_t)0X00000007) + +/*IOMUX_PINCM31[PF] Bits */ +#define IOMUX_PINCM31_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM31_PF_GPIOB_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM31_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM31_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM31_PF_SYSCTL_FCC_IN ((uint32_t)0X00000004) +#define IOMUX_PINCM31_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM31_PF_TIMG14_CCP2 ((uint32_t)0X00000006) +#define IOMUX_PINCM31_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM31_PF_COMP0_OUT ((uint32_t)0X0000000A) + +/*IOMUX_PINCM32[PF] Bits */ +#define IOMUX_PINCM32_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM32_PF_GPIOB_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM32_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM32_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM32_PF_UC4_POCI ((uint32_t)0X00000004) +#define IOMUX_PINCM32_PF_UC4_RTS ((uint32_t)0X00000004) +#define IOMUX_PINCM32_PF_TIMG14_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM32_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM32_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000007) +#define IOMUX_PINCM32_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM32_PF_TIMG14_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM32_PF_UC8_CS0 ((uint32_t)0X0000000A) + +/*IOMUX_PINCM33[PF] Bits */ +#define IOMUX_PINCM33_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM33_PF_GPIOB_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM33_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM33_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM33_PF_UC4_CS0 ((uint32_t)0X00000004) +#define IOMUX_PINCM33_PF_UC4_CTS ((uint32_t)0X00000004) +#define IOMUX_PINCM33_PF_TIMG14_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM33_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM33_PF_UC4_PICO ((uint32_t)0X00000007) +#define IOMUX_PINCM33_PF_UC4_TX ((uint32_t)0X00000007) +#define IOMUX_PINCM33_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000008) + +/*IOMUX_PINCM34[PF] Bits */ +#define IOMUX_PINCM34_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM34_PF_GPIOA_DIO12 ((uint32_t)0X00000001) +#define IOMUX_PINCM34_PF_UC4_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC4_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM34_PF_UC4_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_UC4_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM34_PF_COMP0_OUT ((uint32_t)0X00000004) +#define IOMUX_PINCM34_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM34_PF_SYSCTL_FCC_IN ((uint32_t)0X00000006) +#define IOMUX_PINCM34_PF_TIMG14_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM34_PF_UC7_SCL ((uint32_t)0X00000008) +#define IOMUX_PINCM34_PF_TIMA0_CCP2 ((uint32_t)0X00000009) + +/*IOMUX_PINCM35[PF] Bits */ +#define IOMUX_PINCM35_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM35_PF_GPIOA_DIO13 ((uint32_t)0X00000001) +#define IOMUX_PINCM35_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000002) +#define IOMUX_PINCM35_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM35_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM35_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM35_PF_LFSS_RTC_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM35_PF_TIMG14_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM35_PF_UC8_CS0 ((uint32_t)0X00000008) +#define IOMUX_PINCM35_PF_UC8_POCI ((uint32_t)0X00000009) +#define IOMUX_PINCM35_PF_UC11_TX ((uint32_t)0X0000000A) +#define IOMUX_PINCM35_PF_COMP0_OUT ((uint32_t)0X0000000B) + +/*IOMUX_PINCM36[PF] Bits */ +#define IOMUX_PINCM36_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM36_PF_GPIOA_DIO14 ((uint32_t)0X00000001) +#define IOMUX_PINCM36_PF_UC4_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM36_PF_UC4_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM36_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM36_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM36_PF_UC11_RX ((uint32_t)0X0000000A) + +/*IOMUX_PINCM37[PF] Bits */ +#define IOMUX_PINCM37_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM37_PF_GPIOA_DIO15 ((uint32_t)0X00000001) +#define IOMUX_PINCM37_PF_UC4_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_UC4_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM37_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM37_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM37_PF_TIMG14_CCP2 ((uint32_t)0X00000007) +#define IOMUX_PINCM37_PF_LCD_LCDEN ((uint32_t)0X00000009) + +/*IOMUX_PINCM38[PF] Bits */ +#define IOMUX_PINCM38_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM38_PF_GPIOA_DIO16 ((uint32_t)0X00000001) +#define IOMUX_PINCM38_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM38_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM38_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM38_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM38_PF_SYSCTL_FCC_IN ((uint32_t)0X00000007) +#define IOMUX_PINCM38_PF_LCD_LCDSON ((uint32_t)0X00000009) + +/*IOMUX_PINCM39[PF] Bits */ +#define IOMUX_PINCM39_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM39_PF_GPIOA_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM39_PF_UC8_PICO ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC8_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM39_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM39_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM39_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM39_PF_TIMG2_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM39_PF_TIMG14_CCP2 ((uint32_t)0X00000007) +#define IOMUX_PINCM39_PF_LCD_LCDLFCLK ((uint32_t)0X0000000A) + +/*IOMUX_PINCM40[PF] Bits */ +#define IOMUX_PINCM40_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM40_PF_GPIOA_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM40_PF_UC8_SCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC8_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM40_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM40_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM40_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM40_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM40_PF_TIMG14_CCP3 ((uint32_t)0X00000007) +#define IOMUX_PINCM40_PF_UC4_CS0 ((uint32_t)0X00000009) +#define IOMUX_PINCM40_PF_UC4_CTS ((uint32_t)0X00000009) +#define IOMUX_PINCM40_PF_LCD_LCDEN ((uint32_t)0X0000000A) + +/*IOMUX_PINCM41[PF] Bits */ +#define IOMUX_PINCM41_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM41_PF_GPIOA_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM41_PF_DEBUGSS_SWDIO ((uint32_t)0X00000002) +#define IOMUX_PINCM41_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM41_PF_UC7_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM41_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM41_PF_TIMG14_CCP0 ((uint32_t)0X00000006) + +/*IOMUX_PINCM42[PF] Bits */ +#define IOMUX_PINCM42_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM42_PF_GPIOA_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM42_PF_DEBUGSS_SWCLK ((uint32_t)0X00000002) +#define IOMUX_PINCM42_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM42_PF_UC7_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM42_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM42_PF_TIMG14_CCP1 ((uint32_t)0X00000006) + +/*IOMUX_PINCM43[PF] Bits */ +#define IOMUX_PINCM43_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM43_PF_GPIOB_DIO17 ((uint32_t)0X00000001) +#define IOMUX_PINCM43_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM43_PF_UC4_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_UC4_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM43_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM43_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM43_PF_TIMG14_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM43_PF_TIMG1_CCP0 ((uint32_t)0X00000009) +#define IOMUX_PINCM43_PF_LCD_LCDSON ((uint32_t)0X0000000A) + +/*IOMUX_PINCM44[PF] Bits */ +#define IOMUX_PINCM44_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM44_PF_GPIOB_DIO18 ((uint32_t)0X00000001) +#define IOMUX_PINCM44_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM44_PF_UC4_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_UC4_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM44_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM44_PF_TIMA0_CCP2_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM44_PF_TIMG14_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM44_PF_TIMG1_CCP1 ((uint32_t)0X00000009) +#define IOMUX_PINCM44_PF_LCD_LCDLFCLK ((uint32_t)0X0000000A) + +/*IOMUX_PINCM45[PF] Bits */ +#define IOMUX_PINCM45_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM45_PF_GPIOB_DIO19 ((uint32_t)0X00000001) +#define IOMUX_PINCM45_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM45_PF_UC4_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_UC4_RTS ((uint32_t)0X00000003) +#define IOMUX_PINCM45_PF_UC4_CS0 ((uint32_t)0X00000005) +#define IOMUX_PINCM45_PF_UC4_CTS ((uint32_t)0X00000005) +#define IOMUX_PINCM45_PF_TIMG2_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM45_PF_TIMG14_CCP2 ((uint32_t)0X00000007) + +/*IOMUX_PINCM46[PF] Bits */ +#define IOMUX_PINCM46_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM46_PF_GPIOA_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM46_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM46_PF_TIMA0_CCP0 ((uint32_t)0X00000005) +#define IOMUX_PINCM46_PF_TIMG1_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM46_PF_TIMG14_CCP2 ((uint32_t)0X0000000A) + +/*IOMUX_PINCM47[PF] Bits */ +#define IOMUX_PINCM47_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM47_PF_GPIOA_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM47_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM47_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM47_PF_TIMG1_CCP1 ((uint32_t)0X00000006) +#define IOMUX_PINCM47_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM47_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM47_PF_UC6_SCL ((uint32_t)0X00000009) +#define IOMUX_PINCM47_PF_TIMG14_CCP3 ((uint32_t)0X0000000A) + +/*IOMUX_PINCM48[PF] Bits */ +#define IOMUX_PINCM48_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM48_PF_GPIOB_DIO20 ((uint32_t)0X00000001) +#define IOMUX_PINCM48_PF_UC8_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM48_PF_TIMA0_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM48_PF_TIMA_FAULT1 ((uint32_t)0X00000006) +#define IOMUX_PINCM48_PF_TIMA0_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM48_PF_UC6_SDA ((uint32_t)0X00000009) + +/*IOMUX_PINCM49[PF] Bits */ +#define IOMUX_PINCM49_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM49_PF_GPIOB_DIO21 ((uint32_t)0X00000001) +#define IOMUX_PINCM49_PF_UC8_POCI ((uint32_t)0X00000003) +#define IOMUX_PINCM49_PF_UC6_SCL ((uint32_t)0X00000004) +#define IOMUX_PINCM49_PF_TIMG14_CCP2 ((uint32_t)0X00000005) +#define IOMUX_PINCM49_PF_UC8_PICO ((uint32_t)0X00000006) +#define IOMUX_PINCM49_PF_UC8_TX ((uint32_t)0X00000006) + +/*IOMUX_PINCM50[PF] Bits */ +#define IOMUX_PINCM50_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM50_PF_GPIOB_DIO22 ((uint32_t)0X00000001) +#define IOMUX_PINCM50_PF_UC8_PICO ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC8_TX ((uint32_t)0X00000003) +#define IOMUX_PINCM50_PF_UC6_SDA ((uint32_t)0X00000004) +#define IOMUX_PINCM50_PF_TIMG14_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM50_PF_UC8_SCLK ((uint32_t)0X00000006) +#define IOMUX_PINCM50_PF_UC8_RX ((uint32_t)0X00000006) + +/*IOMUX_PINCM51[PF] Bits */ +#define IOMUX_PINCM51_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM51_PF_GPIOB_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM51_PF_UC8_SCLK ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_UC8_RX ((uint32_t)0X00000003) +#define IOMUX_PINCM51_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM51_PF_COMP0_OUT ((uint32_t)0X00000005) + +/*IOMUX_PINCM52[PF] Bits */ +#define IOMUX_PINCM52_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM52_PF_GPIOB_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM52_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM52_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) + +/*IOMUX_PINCM53[PF] Bits */ +#define IOMUX_PINCM53_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM53_PF_GPIOA_DIO23 ((uint32_t)0X00000001) +#define IOMUX_PINCM53_PF_UC11_TX ((uint32_t)0X00000002) +#define IOMUX_PINCM53_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM53_PF_TIMG14_CCP2 ((uint32_t)0X00000006) +#define IOMUX_PINCM53_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM53_PF_TIMG14_CCP0 ((uint32_t)0X00000009) + +/*IOMUX_PINCM54[PF] Bits */ +#define IOMUX_PINCM54_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM54_PF_GPIOA_DIO24 ((uint32_t)0X00000001) +#define IOMUX_PINCM54_PF_UC11_RX ((uint32_t)0X00000002) +#define IOMUX_PINCM54_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM54_PF_TIMG14_CCP3 ((uint32_t)0X00000006) +#define IOMUX_PINCM54_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM54_PF_TIMG14_CCP1 ((uint32_t)0X00000009) + +/*IOMUX_PINCM55[PF] Bits */ +#define IOMUX_PINCM55_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM55_PF_GPIOA_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM55_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM55_PF_TIMA0_CCP1_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM55_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM55_PF_TIMG1_CCP0 ((uint32_t)0X0000000A) + +/*IOMUX_PINCM56[PF] Bits */ +#define IOMUX_PINCM56_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM56_PF_GPIOB_DIO25 ((uint32_t)0X00000001) +#define IOMUX_PINCM56_PF_UC4_CS0 ((uint32_t)0X00000002) +#define IOMUX_PINCM56_PF_UC4_CTS ((uint32_t)0X00000002) +#define IOMUX_PINCM56_PF_TIMA_FAULT0 ((uint32_t)0X00000004) +#define IOMUX_PINCM56_PF_TIMA_FAULT1 ((uint32_t)0X00000005) +#define IOMUX_PINCM56_PF_TIMA_FAULT2 ((uint32_t)0X00000006) +#define IOMUX_PINCM56_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM56_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/*IOMUX_PINCM57[PF] Bits */ +#define IOMUX_PINCM57_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM57_PF_GPIOB_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM57_PF_UC4_POCI ((uint32_t)0X00000002) +#define IOMUX_PINCM57_PF_UC4_RTS ((uint32_t)0X00000002) +#define IOMUX_PINCM57_PF_TIMA0_CCP0 ((uint32_t)0X00000004) +#define IOMUX_PINCM57_PF_TIMA0_CCP3 ((uint32_t)0X00000005) +#define IOMUX_PINCM57_PF_TIMG1_CCP0 ((uint32_t)0X00000006) +#define IOMUX_PINCM57_PF_COMP0_OUT ((uint32_t)0X00000007) +#define IOMUX_PINCM57_PF_SYSCTL_FCC_IN ((uint32_t)0X00000008) + +/*IOMUX_PINCM58[PF] Bits */ +#define IOMUX_PINCM58_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM58_PF_GPIOB_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM58_PF_COMP0_OUT ((uint32_t)0X00000002) +#define IOMUX_PINCM58_PF_TIMA0_CCP0_CMPL ((uint32_t)0X00000004) +#define IOMUX_PINCM58_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000005) +#define IOMUX_PINCM58_PF_TIMG1_CCP1 ((uint32_t)0X00000006) + +/*IOMUX_PINCM59[PF] Bits */ +#define IOMUX_PINCM59_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM59_PF_GPIOA_DIO26 ((uint32_t)0X00000001) +#define IOMUX_PINCM59_PF_UC8_CS0 ((uint32_t)0X00000003) +#define IOMUX_PINCM59_PF_TIMG14_CCP2 ((uint32_t)0X00000004) +#define IOMUX_PINCM59_PF_TIMA_FAULT0 ((uint32_t)0X00000005) +#define IOMUX_PINCM59_PF_TIMA0_CCP3_CMPL ((uint32_t)0X00000006) +#define IOMUX_PINCM59_PF_TIMG2_CCP0 ((uint32_t)0X00000007) +#define IOMUX_PINCM59_PF_TIMG1_CCP1 ((uint32_t)0X0000000A) + +/*IOMUX_PINCM60[PF] Bits */ +#define IOMUX_PINCM60_PF_UNCONNECTED ((uint32_t)0X00000000) +#define IOMUX_PINCM60_PF_GPIOA_DIO27 ((uint32_t)0X00000001) +#define IOMUX_PINCM60_PF_TIMG14_CCP3 ((uint32_t)0X00000004) +#define IOMUX_PINCM60_PF_TIMA_FAULT2 ((uint32_t)0X00000005) +#define IOMUX_PINCM60_PF_SYSCTL_CLK_OUT ((uint32_t)0X00000006) +#define IOMUX_PINCM60_PF_TIMG2_CCP1 ((uint32_t)0X00000007) +#define IOMUX_PINCM60_PF_LFSS_RTC_OUT ((uint32_t)0X00000008) +#define IOMUX_PINCM60_PF_COMP0_OUT ((uint32_t)0X00000009) + + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/*@}*/ /* end of group MSPM0L211X_PeripheralDecl */ + +/*@}*/ /* end of group MSPM0L211X_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_m0p_mspm0l211x__include */ + diff --git a/mspm0/source/ti/devices/msp/msp.h b/mspm0/source/ti/devices/msp/msp.h index 94f0c06..d36d215 100644 --- a/mspm0/source/ti/devices/msp/msp.h +++ b/mspm0/source/ti/devices/msp/msp.h @@ -72,10 +72,22 @@ #include #elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0G351X) #include +#elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0G352X) +#include #elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0L111X) #include #elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0H321X) #include +#elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0C1105_C1106) +#include +#elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0G511X) +#include +#elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0G518X) +#include +#elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0L211X) +#include +#elif (DeviceFamily_ID == DeviceFamily_ID_MSPM0L112X) +#include /******************************************************************** * diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_btimer.h b/mspm0/source/ti/devices/msp/peripherals/hw_btimer.h new file mode 100644 index 0000000..77f0e6d --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_btimer.h @@ -0,0 +1,1643 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_btimer__include +#define ti_devices_msp_peripherals_hw_btimer__include + +/* Filename: hw_btimer.h */ +/* Revised: 2024-06-05 04:16:28 */ +/* Revision: 952104399038670370f108bbde01f8fcea266891 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* BTIMER Registers +******************************************************************************/ +#define BTIMER_CTRREGS_OFS ((uint32_t)0x00001100U) +#define BTIMER_GEN_EVENT_OFS ((uint32_t)0x00001050U) +#define BTIMER_CPU_INT_OFS ((uint32_t)0x00001020U) +#define BTIMER_GPRCM_OFS ((uint32_t)0x00000800U) + + +/** @addtogroup BTIMER_CTRREGS + @{ +*/ + +typedef struct { + __IO uint32_t CTL0; /* !< (@ 0x00001100) CTL0 register */ + __IO uint32_t LD; /* !< (@ 0x00001104) Counter period register. */ + __IO uint32_t CNT; /* !< (@ 0x00001108) Counter register. */ + uint32_t RESERVED0[61]; +} BTIMER_CTRREGS_Regs; + +/*@}*/ /* end of group BTIMER_CTRREGS */ + +/** @addtogroup BTIMER_GEN_EVENT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001050) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt Mask. If a bit is set, then + corresponding interrupt is un-masked. Un-masking the interrupt + causes the raw interrupt to be visible in IIDX, as well as MIS. */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status. Reflects all pending + interrupts, regardless of masking. The RIS register allows the user + to implement a poll scheme. A flag set in this register can be + cleared by writing 1 to the ICLR register bit even if the + corresponding IMASK bit is not enabled. */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status. This is an AND of the + IMASK and RIS registers. */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set. Allows interrupts to be set by + software (useful in diagnostics and safety checks). Writing a 1 to + a bit in ISET will set the event and therefore the related RIS bit + also gets set. If the interrupt is enabled through the mask, then + the corresponding MIS bit is also set. */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001078) Interrupt clear. Write a 1 to clear corresponding + Interrupt. */ +} BTIMER_GEN_EVENT_Regs; + +/*@}*/ /* end of group BTIMER_GEN_EVENT */ + +/** @addtogroup BTIMER_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt Mask. If a bit is set, then + corresponding interrupt is un-masked. Un-masking the interrupt + causes the raw interrupt to be visible in IIDX, as well as MIS. */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status. Reflects all pending + interrupts, regardless of masking. The RIS register allows the user + to implement a poll scheme. A flag set in this register can be + cleared by writing 1 to the ICLR register bit even if the + corresponding IMASK bit is not enabled. */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status. This is an AND of the + IMASK and RIS registers. */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set. Allows interrupts to be set by + software (useful in diagnostics and safety checks). Writing a 1 to + a bit in ISET will set the event and therefore the related RIS bit + also gets set. If the interrupt is enabled through the mask, then + the corresponding MIS bit is also set. */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear. Write a 1 to clear corresponding + Interrupt. */ +} BTIMER_CPU_INT_Regs; + +/*@}*/ /* end of group BTIMER_CPU_INT */ + +/** @addtogroup BTIMER_GPRCM + @{ +*/ + +typedef struct { + __IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */ + __O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */ + uint32_t RESERVED0[3]; + __I uint32_t STAT; /* !< (@ 0x00000814) Status Register */ +} BTIMER_GPRCM_Regs; + +/*@}*/ /* end of group BTIMER_GPRCM */ + +/** @addtogroup BTIMER + @{ +*/ + +typedef struct { + uint32_t RESERVED0[256]; + __IO uint32_t FSUB_0; /* !< (@ 0x00000400) Subscriber Configuration Register. */ + uint32_t RESERVED1[16]; + __IO uint32_t FPUB_0; /* !< (@ 0x00000444) Publisher Port 0 */ + uint32_t RESERVED2[238]; + BTIMER_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */ + uint32_t RESERVED3[512]; + __IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */ + uint32_t RESERVED4; + BTIMER_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED5; + BTIMER_GEN_EVENT_Regs GEN_EVENT; /* !< (@ 0x00001050) */ + uint32_t RESERVED6[25]; + __I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */ + uint32_t RESERVED7[7]; + BTIMER_CTRREGS_Regs CTRREGS[2]; /* !< (@ 0x00001100) */ +} BTIMER_Regs; + +/*@}*/ /* end of group BTIMER */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* BTIMER Register Control Bits +******************************************************************************/ + +/* BTIMER_CTL0 Bits */ +/* BTIMER_CTL0[EN] Bits */ +#define BTIMER_CTL0_EN_OFS (0) /* !< EN Offset */ +#define BTIMER_CTL0_EN_MASK ((uint32_t)0x00000001U) /* !< Counter Enable */ +/* BTIMER_CTL0[STARTSEL] Bits */ +#define BTIMER_CTL0_STARTSEL_OFS (4) /* !< STARTSEL Offset */ +#define BTIMER_CTL0_STARTSEL_MASK ((uint32_t)0x000000F0U) /* !< Selects the source used to start + the counter. */ +/* BTIMER_CTL0[STOPSEL] Bits */ +#define BTIMER_CTL0_STOPSEL_OFS (8) /* !< STOPSEL Offset */ +#define BTIMER_CTL0_STOPSEL_MASK ((uint32_t)0x00000F00U) /* !< Selects the source used to stop the + counter. */ +/* BTIMER_CTL0[RESETSEL] Bits */ +#define BTIMER_CTL0_RESETSEL_OFS (12) /* !< RESETSEL Offset */ +#define BTIMER_CTL0_RESETSEL_MASK ((uint32_t)0x0000F000U) /* !< Selects the source used to reset + the counter. */ +/* BTIMER_CTL0[CLKSEL] Bits */ +#define BTIMER_CTL0_CLKSEL_OFS (16) /* !< CLKSEL Offset */ +#define BTIMER_CTL0_CLKSEL_MASK ((uint32_t)0x000F0000U) /* !< Clock sources */ + +/* BTIMER_LD Bits */ +/* BTIMER_LD[VAL] Bits */ +#define BTIMER_LD_VAL_OFS (0) /* !< VAL Offset */ +#define BTIMER_LD_VAL_MASK ((uint32_t)0x0000FFFFU) /* !< Period value */ +#define BTIMER_LD_VAL_MINIMUM ((uint32_t)0x00000001U) /* !< Minimum counter value */ +#define BTIMER_LD_VAL_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Maximum counter value */ + +/* BTIMER_CNT Bits */ +/* BTIMER_CNT[VALUE] Bits */ +#define BTIMER_CNT_VALUE_OFS (0) /* !< VALUE Offset */ +#define BTIMER_CNT_VALUE_MASK ((uint32_t)0x0000FFFFU) /* !< Counter Value */ + +/* BTIMER_GEN_EVENT_IIDX Bits */ +/* BTIMER_GEN_EVENT_IIDX[STAT] Bits */ +#define BTIMER_GEN_EVENT_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define BTIMER_GEN_EVENT_IIDX_STAT_MASK ((uint32_t)0x000003FFU) /* !< Interrupt index status */ +#define BTIMER_GEN_EVENT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No bit is set means there is no + pending interrupt request */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT0OVF ((uint32_t)0x00000001U) /* !< Counter0 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT0STRT ((uint32_t)0x00000002U) /* !< Counter 0 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT0STOP ((uint32_t)0x00000003U) /* !< Counter0 stop */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT1OVF ((uint32_t)0x00000004U) /* !< Counter1 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT1STRT ((uint32_t)0x00000005U) /* !< Counter 1 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT1STOP ((uint32_t)0x00000006U) /* !< Counter1 stop */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT2OVF ((uint32_t)0x00000007U) /* !< Counter2 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT2STRT ((uint32_t)0x00000008U) /* !< Counter 2 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT2STOP ((uint32_t)0x00000009U) /* !< Counter2 stop */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT3OVF ((uint32_t)0x0000000AU) /* !< Counter3 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT3STRT ((uint32_t)0x0000000BU) /* !< Counter 3 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT3STOP ((uint32_t)0x0000000CU) /* !< Counter3 stop */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT4OVF ((uint32_t)0x0000000DU) /* !< Counter4 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT4STRT ((uint32_t)0x0000000EU) /* !< Counter 4 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT4STOP ((uint32_t)0x0000000FU) /* !< Counter4 stop */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT5OVF ((uint32_t)0x00000010U) /* !< Counter5 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT5STRT ((uint32_t)0x00000011U) /* !< Counter 5 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT5STOP ((uint32_t)0x00000012U) /* !< Counter5 stop */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT6OVF ((uint32_t)0x00000013U) /* !< Counter6 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT6STRT ((uint32_t)0x00000014U) /* !< Counter 6 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT6STOP ((uint32_t)0x00000015U) /* !< Counter6 stop */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT7OVF ((uint32_t)0x00000016U) /* !< Counter7 period match interrupt */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT7STRT ((uint32_t)0x00000017U) /* !< Counter 7 start */ +#define BTIMER_GEN_EVENT_IIDX_STAT_CNT7STOP ((uint32_t)0x00000018U) /* !< Counter7 stop */ + +/* BTIMER_GEN_EVENT_IMASK Bits */ +/* BTIMER_GEN_EVENT_IMASK[CNT0OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< CNT0OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT0OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT0STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< CNT0STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT0STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< CNT0STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT1OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< CNT1OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT1OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT1STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< CNT1STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT1STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< CNT1STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT2OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< CNT2OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT2OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT2STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< CNT2STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT2STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< CNT2STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT3OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< CNT3OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT3OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT3STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< CNT3STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT3STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< CNT3STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT4OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< CNT4OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT4OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT4STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< CNT4STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT4STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< CNT4STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT5OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< CNT5OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT5OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT5STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< CNT5STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT5STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< CNT5STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT6OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< CNT6OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT6OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT6STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< CNT6STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT6STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< CNT6STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT7OVF] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< CNT7OVF Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT7OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT7STRT] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< CNT7STRT Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_IMASK[CNT7STOP] Bits */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< CNT7STOP Interrupt enable bit */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_IMASK_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_GEN_EVENT_RIS Bits */ +/* BTIMER_GEN_EVENT_RIS[CNT0OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Counter 0 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT0OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT0STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Counter 0 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT0STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT0STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Counter 0 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT0STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT1OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Counter 1 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT1OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT1STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Counter 1 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT1STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT1STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Counter 1 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT1STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT2OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Counter 2 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT2OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT2STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Counter 2 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT2STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT2STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Counter 2 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT2STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT3OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Counter 3 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT3OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT3STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Counter 3 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT3STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT3STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Counter 3 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT3STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT4OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Counter 4 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT4OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT4STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Counter 4 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT4STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT4STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Counter 4 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT4STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT5OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Counter 5 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT5OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT5STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Counter 5 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT5STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT5STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Counter 5 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT5STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT6OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Counter 6 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT6OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT6STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Counter 6 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT6STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT6STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Counter 6 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT6STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT7OVF] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Counter 7 Period match flag */ +#define BTIMER_GEN_EVENT_RIS_CNT7OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT7STRT] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Counter 7 start event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT7STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_RIS[CNT7STOP] Bits */ +#define BTIMER_GEN_EVENT_RIS_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_GEN_EVENT_RIS_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Counter 7 stop event flag */ +#define BTIMER_GEN_EVENT_RIS_CNT7STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_RIS_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_GEN_EVENT_MIS Bits */ +/* BTIMER_GEN_EVENT_MIS[CNT0OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Counter 0 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT0OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT0STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Counter 0 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT0STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT0STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Counter 0 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT0STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT1OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Counter 1 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT1OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT1STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Counter 1 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT1STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT1STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Counter 1 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT1STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT2OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Counter 2 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT2OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT2STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Counter 2 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT2STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT2STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Counter 2 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT2STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT3OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Counter 3 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT3OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT3STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Counter 3 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT3STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT3STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Counter 3 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT3STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT4OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Counter 4 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT4OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT4STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Counter 4 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT4STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT4STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Counter 4 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT4STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT5OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Counter 5 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT5OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT5STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Counter 5 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT5STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT5STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Counter 5 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT5STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT6OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Counter 6 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT6OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT6STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Counter 6 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT6STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT6STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Counter 6 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT6STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT7OVF] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Counter 7 period match flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT7OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT7STRT] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Counter 7 start event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT7STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_MIS[CNT7STOP] Bits */ +#define BTIMER_GEN_EVENT_MIS_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_GEN_EVENT_MIS_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Counter 7 stop event flag. */ +#define BTIMER_GEN_EVENT_MIS_CNT7STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_MIS_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_GEN_EVENT_ISET Bits */ +/* BTIMER_GEN_EVENT_ISET[CNT0OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Set Counter 0 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT0OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT0STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Set Counter 0 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT0STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT0STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Set Counter 0 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT0STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT1OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Set Counter 1 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT1OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT1STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Set Counter 1 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT1STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT1STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Set Counter 1 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT1STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT2OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Set Counter 2 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT2OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT2STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Set Counter 2 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT2STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT2STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Set Counter 2 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT2STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT3OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Set Counter 3 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT3OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT3STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Set Counter 3 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT3STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT3STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Set Counter 3 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT3STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT4OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Set Counter 4 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT4OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT4STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Set Counter 4 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT4STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT4STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Set Counter 4 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT4STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT5OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Set Counter 5 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT5OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT5STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Set Counter 5 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT5STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT5STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Set Counter 5 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT5STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT6OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Set Counter 6 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT6OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT6STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Set Counter 6 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT6STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT6STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Set Counter 6 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT6STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT7OVF] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Set Counter 7 period match flag */ +#define BTIMER_GEN_EVENT_ISET_CNT7OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT7STRT] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Set Counter 7 start event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT7STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ISET[CNT7STOP] Bits */ +#define BTIMER_GEN_EVENT_ISET_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_GEN_EVENT_ISET_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Set Counter 7 stop event flag */ +#define BTIMER_GEN_EVENT_ISET_CNT7STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ISET_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_GEN_EVENT_ICLR Bits */ +/* BTIMER_GEN_EVENT_ICLR[CNT0OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Clear Counter 0 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT0OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT0OVF_CLR ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT0STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Clear Counter 0 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STRT_CLR ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT0STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Clear Counter 0 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT0STOP_CLR ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT1OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Clear Counter 1 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT1OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT1OVF_CLR ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT1STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Clear Counter 1 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STRT_CLR ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT1STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Clear Counter 1 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT1STOP_CLR ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT2OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Clear Counter 2 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT2OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT2OVF_CLR ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT2STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Clear Counter 2 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STRT_CLR ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT2STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Clear Counter 2 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT2STOP_CLR ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT3OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Clear Counter 3 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT3OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT3OVF_CLR ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT3STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Clear Counter 3 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STRT_CLR ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT3STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Clear Counter 3 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT3STOP_CLR ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT4OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Clear Counter 4 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT4OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT4OVF_CLR ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT4STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Clear Counter 4 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STRT_CLR ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT4STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Clear Counter 4 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT4STOP_CLR ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT5OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Clear Counter 5 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT5OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT5OVF_CLR ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT5STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Clear Counter 5 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STRT_CLR ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT5STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Clear Counter 5 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT5STOP_CLR ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT6OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Clear Counter 6 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT6OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT6OVF_CLR ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT6STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Clear Counter 6 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STRT_CLR ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT6STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Clear Counter 6 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT6STOP_CLR ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT7OVF] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Clear Counter 7 period match flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT7OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT7OVF_CLR ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT7STRT] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Clear Counter 7 start event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STRT_CLR ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_GEN_EVENT_ICLR[CNT7STOP] Bits */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Clear Counter 7 stop event flag. */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_GEN_EVENT_ICLR_CNT7STOP_CLR ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_CPU_INT_IIDX Bits */ +/* BTIMER_CPU_INT_IIDX[STAT] Bits */ +#define BTIMER_CPU_INT_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define BTIMER_CPU_INT_IIDX_STAT_MASK ((uint32_t)0x000003FFU) /* !< Interrupt index status */ +#define BTIMER_CPU_INT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No bit is set means there is no + pending interrupt request */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT0OVF ((uint32_t)0x00000001U) /* !< Counter0 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT0STRT ((uint32_t)0x00000002U) /* !< Counter 0 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT0STOP ((uint32_t)0x00000003U) /* !< Counter0 stop */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT1OVF ((uint32_t)0x00000004U) /* !< Counter1 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT1STRT ((uint32_t)0x00000005U) /* !< Counter 1 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT1STOP ((uint32_t)0x00000006U) /* !< Counter1 stop */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT2OVF ((uint32_t)0x00000007U) /* !< Counter2 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT2STRT ((uint32_t)0x00000008U) /* !< Counter 2 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT2STOP ((uint32_t)0x00000009U) /* !< Counter2 stop */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT3OVF ((uint32_t)0x0000000AU) /* !< Counter3 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT3STRT ((uint32_t)0x0000000BU) /* !< Counter 3 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT3STOP ((uint32_t)0x0000000CU) /* !< Counter3 stop */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT4OVF ((uint32_t)0x0000000DU) /* !< Counter4 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT4STRT ((uint32_t)0x0000000EU) /* !< Counter 4 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT4STOP ((uint32_t)0x0000000FU) /* !< Counter4 stop */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT5OVF ((uint32_t)0x00000010U) /* !< Counter5 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT5STRT ((uint32_t)0x00000011U) /* !< Counter 5 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT5STOP ((uint32_t)0x00000012U) /* !< Counter5 stop */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT6OVF ((uint32_t)0x00000013U) /* !< Counter6 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT6STRT ((uint32_t)0x00000014U) /* !< Counter 6 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT6STOP ((uint32_t)0x00000015U) /* !< Counter6 stop */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT7OVF ((uint32_t)0x00000016U) /* !< Counter7 period match interrupt */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT7STRT ((uint32_t)0x00000017U) /* !< Counter 7 start */ +#define BTIMER_CPU_INT_IIDX_STAT_CNT7STOP ((uint32_t)0x00000018U) /* !< Counter7 stop */ + +/* BTIMER_CPU_INT_IMASK Bits */ +/* BTIMER_CPU_INT_IMASK[CNT0OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< CNT0OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT0OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT0STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< CNT0STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT0STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT0STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< CNT0STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT0STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT1OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< CNT1OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT1OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT1STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< CNT1STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT1STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT1STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< CNT1STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT1STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT2OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< CNT2OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT2OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT2STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< CNT2STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT2STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT2STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< CNT2STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT2STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT3OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< CNT3OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT3OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT3STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< CNT3STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT3STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT3STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< CNT3STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT3STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT4OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< CNT4OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT4OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT4STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< CNT4STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT4STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT4STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< CNT4STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT4STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT5OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< CNT5OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT5OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT5STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< CNT5STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT5STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT5STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< CNT5STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT5STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT6OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< CNT6OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT6OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT6STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< CNT6STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT6STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT6STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< CNT6STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT6STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT7OVF] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_CPU_INT_IMASK_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< CNT7OVF Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT7OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT7STRT] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_CPU_INT_IMASK_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< CNT7STRT Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT7STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_IMASK[CNT7STOP] Bits */ +#define BTIMER_CPU_INT_IMASK_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_CPU_INT_IMASK_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< CNT7STOP Interrupt enable bit */ +#define BTIMER_CPU_INT_IMASK_CNT7STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_IMASK_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_CPU_INT_RIS Bits */ +/* BTIMER_CPU_INT_RIS[CNT0OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Counter 0 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT0OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT0STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Counter 0 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT0STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT0STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Counter 0 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT0STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT1OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Counter 1 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT1OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT1STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Counter 1 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT1STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT1STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Counter 1 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT1STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT2OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Counter 2 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT2OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT2STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Counter 2 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT2STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT2STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Counter 2 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT2STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT3OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Counter 3 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT3OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT3STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Counter 3 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT3STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT3STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Counter 3 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT3STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT4OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Counter 4 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT4OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT4STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Counter 4 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT4STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT4STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Counter 4 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT4STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT5OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Counter 5 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT5OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT5STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Counter 5 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT5STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT5STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Counter 5 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT5STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT6OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Counter 6 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT6OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT6STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Counter 6 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT6STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT6STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Counter 6 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT6STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT7OVF] Bits */ +#define BTIMER_CPU_INT_RIS_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_CPU_INT_RIS_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Counter 7 Period match flag */ +#define BTIMER_CPU_INT_RIS_CNT7OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT7STRT] Bits */ +#define BTIMER_CPU_INT_RIS_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_CPU_INT_RIS_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Counter 7 start event flag */ +#define BTIMER_CPU_INT_RIS_CNT7STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_RIS[CNT7STOP] Bits */ +#define BTIMER_CPU_INT_RIS_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_CPU_INT_RIS_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Counter 7 stop event flag */ +#define BTIMER_CPU_INT_RIS_CNT7STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_RIS_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_CPU_INT_MIS Bits */ +/* BTIMER_CPU_INT_MIS[CNT0OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Counter 0 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT0OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT0STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Counter 0 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT0STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT0STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Counter 0 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT0STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT1OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Counter 1 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT1OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT1STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Counter 1 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT1STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT1STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Counter 1 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT1STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT2OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Counter 2 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT2OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT2STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Counter 2 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT2STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT2STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Counter 2 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT2STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT3OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Counter 3 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT3OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT3STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Counter 3 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT3STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT3STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Counter 3 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT3STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT4OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Counter 4 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT4OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT4STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Counter 4 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT4STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT4STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Counter 4 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT4STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT5OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Counter 5 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT5OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT5STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Counter 5 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT5STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT5STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Counter 5 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT5STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT6OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Counter 6 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT6OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT6STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Counter 6 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT6STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT6STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Counter 6 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT6STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT7OVF] Bits */ +#define BTIMER_CPU_INT_MIS_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_CPU_INT_MIS_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Counter 7 period match flag. */ +#define BTIMER_CPU_INT_MIS_CNT7OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT7STRT] Bits */ +#define BTIMER_CPU_INT_MIS_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_CPU_INT_MIS_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Counter 7 start event flag. */ +#define BTIMER_CPU_INT_MIS_CNT7STRT_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_MIS[CNT7STOP] Bits */ +#define BTIMER_CPU_INT_MIS_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_CPU_INT_MIS_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Counter 7 stop event flag. */ +#define BTIMER_CPU_INT_MIS_CNT7STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_MIS_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_CPU_INT_ISET Bits */ +/* BTIMER_CPU_INT_ISET[CNT0OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Set Counter 0 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT0OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT0OVF_SET ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT0STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Set Counter 0 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT0STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT0STRT_SET ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT0STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Set Counter 0 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT0STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT0STOP_SET ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT1OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Set Counter 1 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT1OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT1OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT1STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Set Counter 1 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT1STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT1STRT_SET ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT1STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Set Counter 1 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT1STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT1STOP_SET ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT2OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Set Counter 2 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT2OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT2OVF_SET ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT2STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Set Counter 2 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT2STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT2STRT_SET ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT2STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Set Counter 2 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT2STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT2STOP_SET ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT3OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Set Counter 3 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT3OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT3OVF_SET ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT3STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Set Counter 3 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT3STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT3STRT_SET ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT3STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Set Counter 3 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT3STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT3STOP_SET ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT4OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Set Counter 4 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT4OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT4OVF_SET ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT4STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Set Counter 4 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT4STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT4STRT_SET ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT4STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Set Counter 4 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT4STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT4STOP_SET ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT5OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Set Counter 5 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT5OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT5OVF_SET ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT5STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Set Counter 5 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT5STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT5STRT_SET ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT5STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Set Counter 5 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT5STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT5STOP_SET ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT6OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Set Counter 6 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT6OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT6OVF_SET ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT6STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Set Counter 6 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT6STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT6STRT_SET ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT6STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Set Counter 6 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT6STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT6STOP_SET ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT7OVF] Bits */ +#define BTIMER_CPU_INT_ISET_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_CPU_INT_ISET_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Set Counter 7 period match flag */ +#define BTIMER_CPU_INT_ISET_CNT7OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT7OVF_SET ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT7STRT] Bits */ +#define BTIMER_CPU_INT_ISET_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_CPU_INT_ISET_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Set Counter 7 start event flag */ +#define BTIMER_CPU_INT_ISET_CNT7STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT7STRT_SET ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ISET[CNT7STOP] Bits */ +#define BTIMER_CPU_INT_ISET_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_CPU_INT_ISET_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Set Counter 7 stop event flag */ +#define BTIMER_CPU_INT_ISET_CNT7STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ISET_CNT7STOP_SET ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_CPU_INT_ICLR Bits */ +/* BTIMER_CPU_INT_ICLR[CNT0OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT0OVF_OFS (0) /* !< CNT0OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT0OVF_MASK ((uint32_t)0x00000001U) /* !< Clear Counter 0 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT0OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT0OVF_CLR ((uint32_t)0x00000001U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT0STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT0STRT_OFS (1) /* !< CNT0STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT0STRT_MASK ((uint32_t)0x00000002U) /* !< Clear Counter 0 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT0STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT0STRT_CLR ((uint32_t)0x00000002U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT0STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT0STOP_OFS (2) /* !< CNT0STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT0STOP_MASK ((uint32_t)0x00000004U) /* !< Clear Counter 0 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT0STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT0STOP_CLR ((uint32_t)0x00000004U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT1OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT1OVF_OFS (3) /* !< CNT1OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT1OVF_MASK ((uint32_t)0x00000008U) /* !< Clear Counter 1 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT1OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT1OVF_CLR ((uint32_t)0x00000008U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT1STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT1STRT_OFS (4) /* !< CNT1STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT1STRT_MASK ((uint32_t)0x00000010U) /* !< Clear Counter 1 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT1STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT1STRT_CLR ((uint32_t)0x00000010U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT1STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT1STOP_OFS (5) /* !< CNT1STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT1STOP_MASK ((uint32_t)0x00000020U) /* !< Clear Counter 1 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT1STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT1STOP_CLR ((uint32_t)0x00000020U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT2OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT2OVF_OFS (6) /* !< CNT2OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT2OVF_MASK ((uint32_t)0x00000040U) /* !< Clear Counter 2 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT2OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT2OVF_CLR ((uint32_t)0x00000040U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT2STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT2STRT_OFS (7) /* !< CNT2STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT2STRT_MASK ((uint32_t)0x00000080U) /* !< Clear Counter 2 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT2STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT2STRT_CLR ((uint32_t)0x00000080U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT2STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT2STOP_OFS (8) /* !< CNT2STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT2STOP_MASK ((uint32_t)0x00000100U) /* !< Clear Counter 2 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT2STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT2STOP_CLR ((uint32_t)0x00000100U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT3OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT3OVF_OFS (9) /* !< CNT3OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT3OVF_MASK ((uint32_t)0x00000200U) /* !< Clear Counter 3 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT3OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT3OVF_CLR ((uint32_t)0x00000200U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT3STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT3STRT_OFS (10) /* !< CNT3STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT3STRT_MASK ((uint32_t)0x00000400U) /* !< Clear Counter 3 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT3STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT3STRT_CLR ((uint32_t)0x00000400U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT3STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT3STOP_OFS (11) /* !< CNT3STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT3STOP_MASK ((uint32_t)0x00000800U) /* !< Clear Counter 3 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT3STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT3STOP_CLR ((uint32_t)0x00000800U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT4OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT4OVF_OFS (12) /* !< CNT4OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT4OVF_MASK ((uint32_t)0x00001000U) /* !< Clear Counter 4 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT4OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT4OVF_CLR ((uint32_t)0x00001000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT4STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT4STRT_OFS (13) /* !< CNT4STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT4STRT_MASK ((uint32_t)0x00002000U) /* !< Clear Counter 4 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT4STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT4STRT_CLR ((uint32_t)0x00002000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT4STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT4STOP_OFS (14) /* !< CNT4STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT4STOP_MASK ((uint32_t)0x00004000U) /* !< Clear Counter 4 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT4STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT4STOP_CLR ((uint32_t)0x00004000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT5OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT5OVF_OFS (15) /* !< CNT5OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT5OVF_MASK ((uint32_t)0x00008000U) /* !< Clear Counter 5 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT5OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT5OVF_CLR ((uint32_t)0x00008000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT5STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT5STRT_OFS (16) /* !< CNT5STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT5STRT_MASK ((uint32_t)0x00010000U) /* !< Clear Counter 5 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT5STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT5STRT_CLR ((uint32_t)0x00010000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT5STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT5STOP_OFS (17) /* !< CNT5STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT5STOP_MASK ((uint32_t)0x00020000U) /* !< Clear Counter 5 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT5STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT5STOP_CLR ((uint32_t)0x00020000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT6OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT6OVF_OFS (18) /* !< CNT6OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT6OVF_MASK ((uint32_t)0x00040000U) /* !< Clear Counter 6 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT6OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT6OVF_CLR ((uint32_t)0x00040000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT6STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT6STRT_OFS (19) /* !< CNT6STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT6STRT_MASK ((uint32_t)0x00080000U) /* !< Clear Counter 6 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT6STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT6STRT_CLR ((uint32_t)0x00080000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT6STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT6STOP_OFS (20) /* !< CNT6STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT6STOP_MASK ((uint32_t)0x00100000U) /* !< Clear Counter 6 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT6STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT6STOP_CLR ((uint32_t)0x00100000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT7OVF] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT7OVF_OFS (21) /* !< CNT7OVF Offset */ +#define BTIMER_CPU_INT_ICLR_CNT7OVF_MASK ((uint32_t)0x00200000U) /* !< Clear Counter 7 period match flag. */ +#define BTIMER_CPU_INT_ICLR_CNT7OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT7OVF_CLR ((uint32_t)0x00200000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT7STRT] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT7STRT_OFS (22) /* !< CNT7STRT Offset */ +#define BTIMER_CPU_INT_ICLR_CNT7STRT_MASK ((uint32_t)0x00400000U) /* !< Clear Counter 7 start event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT7STRT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT7STRT_CLR ((uint32_t)0x00400000U) /* !< Interrupt is pending. */ +/* BTIMER_CPU_INT_ICLR[CNT7STOP] Bits */ +#define BTIMER_CPU_INT_ICLR_CNT7STOP_OFS (23) /* !< CNT7STOP Offset */ +#define BTIMER_CPU_INT_ICLR_CNT7STOP_MASK ((uint32_t)0x00800000U) /* !< Clear Counter 7 stop event flag. */ +#define BTIMER_CPU_INT_ICLR_CNT7STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt is not pending. */ +#define BTIMER_CPU_INT_ICLR_CNT7STOP_CLR ((uint32_t)0x00800000U) /* !< Interrupt is pending. */ + +/* BTIMER_PWREN Bits */ +/* BTIMER_PWREN[ENABLE] Bits */ +#define BTIMER_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define BTIMER_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */ +#define BTIMER_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */ +#define BTIMER_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */ +/* BTIMER_PWREN[KEY] Bits */ +#define BTIMER_PWREN_KEY_OFS (24) /* !< KEY Offset */ +#define BTIMER_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */ +#define BTIMER_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this + register */ + +/* BTIMER_RSTCTL Bits */ +/* BTIMER_RSTCTL[RESETSTKYCLR] Bits */ +#define BTIMER_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */ +#define BTIMER_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT + register */ +#define BTIMER_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define BTIMER_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */ +/* BTIMER_RSTCTL[RESETASSERT] Bits */ +#define BTIMER_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */ +#define BTIMER_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */ +#define BTIMER_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define BTIMER_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */ +/* BTIMER_RSTCTL[KEY] Bits */ +#define BTIMER_RSTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define BTIMER_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */ +#define BTIMER_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this + register */ + +/* BTIMER_STAT Bits */ +/* BTIMER_STAT[RESETSTKY] Bits */ +#define BTIMER_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */ +#define BTIMER_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the + peripheral was reset, since this bit + was cleared by RESETSTKYCLR in the + RSTCTL register */ +#define BTIMER_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset + since this bit was last cleared by + RESETSTKYCLR in the RSTCTL register */ +#define BTIMER_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the + last bit clear */ + +/* BTIMER_FSUB_0 Bits */ +/* BTIMER_FSUB_0[CHANID] Bits */ +#define BTIMER_FSUB_0_CHANID_OFS (0) /* !< CHANID Offset */ +#define BTIMER_FSUB_0_CHANID_MASK ((uint32_t)0x000000FFU) /* !< 0 = disconnected. 1-15 = connected + to channelID = CHANID. */ +#define BTIMER_FSUB_0_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying + that the event is unconnected */ +#define BTIMER_FSUB_0_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the + event is not connected */ +#define BTIMER_FSUB_0_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as + the actual allowed maximum may be + less than 255. */ + +/* BTIMER_FPUB_0 Bits */ +/* BTIMER_FPUB_0[CHANID] Bits */ +#define BTIMER_FPUB_0_CHANID_OFS (0) /* !< CHANID Offset */ +#define BTIMER_FPUB_0_CHANID_MASK ((uint32_t)0x000000FFU) /* !< 0 = disconnected. 1-15 = connected + to channelID = CHANID. */ +#define BTIMER_FPUB_0_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying + that the event is unconnected */ +#define BTIMER_FPUB_0_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the + event is not connected */ +#define BTIMER_FPUB_0_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as + the actual allowed maximum may be + less than 15. */ + +/* BTIMER_PDBGCTL Bits */ +/* BTIMER_PDBGCTL[FREE] Bits */ +#define BTIMER_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */ +#define BTIMER_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */ +#define BTIMER_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes + functionality while the Core Halted + input is asserted and resumes when it + is deasserted. */ +#define BTIMER_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of + the Core Halted input */ +/* BTIMER_PDBGCTL[SOFT] Bits */ +#define BTIMER_PDBGCTL_SOFT_OFS (1) /* !< SOFT Offset */ +#define BTIMER_PDBGCTL_SOFT_MASK ((uint32_t)0x00000002U) /* !< Soft halt boundary control. This + function is only available, if [FREE] + is set to 'STOP' */ +#define BTIMER_PDBGCTL_SOFT_IMMEDIATE ((uint32_t)0x00000000U) /* !< The peripheral will halt + immediately, even if the resultant + state will result in corruption if + the system is restarted */ +#define BTIMER_PDBGCTL_SOFT_DELAYED ((uint32_t)0x00000002U) /* !< The peripheral blocks the debug + freeze until it has reached a + boundary where it can resume without + corruption */ + +/* BTIMER_EVT_MODE Bits */ +/* BTIMER_EVT_MODE[CPU_INT_CFG] Bits */ +#define BTIMER_EVT_MODE_CPU_INT_CFG_OFS (0) /* !< CPU_INT_CFG Offset */ +#define BTIMER_EVT_MODE_CPU_INT_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for event + corresponding to CPU_INT */ +#define BTIMER_EVT_MODE_CPU_INT_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define BTIMER_EVT_MODE_CPU_INT_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ +#define BTIMER_EVT_MODE_CPU_INT_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in + hardware mode. The hardware (another + module) clears automatically the + associated RIS flag. */ +/* BTIMER_EVT_MODE[GEN_EVENT_CFG] Bits */ +#define BTIMER_EVT_MODE_GEN_EVENT_CFG_OFS (2) /* !< GEN_EVENT_CFG Offset */ +#define BTIMER_EVT_MODE_GEN_EVENT_CFG_MASK ((uint32_t)0x0000000CU) /* !< Event line mode select for event + corresponding to CPU_INT */ +#define BTIMER_EVT_MODE_GEN_EVENT_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define BTIMER_EVT_MODE_GEN_EVENT_CFG_SOFTWARE ((uint32_t)0x00000004U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ +#define BTIMER_EVT_MODE_GEN_EVENT_CFG_HARDWARE ((uint32_t)0x00000008U) /* !< The interrupt or event line is in + hardware mode. The hardware (another + module) clears automatically the + associated RIS flag. */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_btimer__include */ + diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_comp.h b/mspm0/source/ti/devices/msp/peripherals/hw_comp.h index 06dc246..39ec96a 100644 --- a/mspm0/source/ti/devices/msp/peripherals/hw_comp.h +++ b/mspm0/source/ti/devices/msp/peripherals/hw_comp.h @@ -1,33 +1,33 @@ /***************************************************************************** - Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright + Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ @@ -36,8 +36,8 @@ #define ti_devices_msp_peripherals_hw_comp__include /* Filename: hw_comp.h */ -/* Revised: 2023-05-10 21:23:38 */ -/* Revision: 5c29864c187960f76e656cbc0f0f844cdb69a263 */ +/* Revised: 2024-07-09 06:39:02 */ +/* Revision: ff0f23ebcffe2c65cfa0450897995c6372fa6195 */ #ifndef __CORTEX_M #ifdef __cplusplus @@ -172,10 +172,10 @@ typedef struct { #define COMP_GEN_EVENT_IIDX_STAT_OFS (0) /* !< STAT Offset */ #define COMP_GEN_EVENT_IIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< Interrupt index status */ #define COMP_GEN_EVENT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */ -#define COMP_GEN_EVENT_IIDX_STAT_COMPIFG ((uint32_t)0x00000002U) /* !< Comparator output interrupt */ -#define COMP_GEN_EVENT_IIDX_STAT_COMPINVIFG ((uint32_t)0x00000003U) /* !< Comparator output inverted +#define COMP_GEN_EVENT_IIDX_STAT_COMPIFG ((uint32_t)0x00000001U) /* !< Comparator output interrupt */ +#define COMP_GEN_EVENT_IIDX_STAT_COMPINVIFG ((uint32_t)0x00000002U) /* !< Comparator output inverted interrupt */ -#define COMP_GEN_EVENT_IIDX_STAT_OUTRDYIFG ((uint32_t)0x00000004U) /* !< Comparator output ready interrupt */ +#define COMP_GEN_EVENT_IIDX_STAT_OUTRDYIFG ((uint32_t)0x00000003U) /* !< Comparator output ready interrupt */ /* COMP_GEN_EVENT_IMASK Bits */ /* COMP_GEN_EVENT_IMASK[COMPIFG] Bits */ @@ -676,6 +676,14 @@ typedef struct { #define COMP_CTL1_FLTDLY_DLY_1 ((uint32_t)0x00000200U) /* !< Typical filter delay of 500 ns */ #define COMP_CTL1_FLTDLY_DLY_2 ((uint32_t)0x00000400U) /* !< Typical filter delay of 1200 ns */ #define COMP_CTL1_FLTDLY_DLY_3 ((uint32_t)0x00000600U) /* !< Typical filter delay of 2700 ns */ +/* COMP_CTL1[DACOUTEN] Bits */ +#define COMP_CTL1_DACOUTEN_OFS (11) /* !< DACOUTEN Offset */ +#define COMP_CTL1_DACOUTEN_MASK ((uint32_t)0x00000800U) /* !< This bit enables DAC8 output to be + connected to the pin. */ +#define COMP_CTL1_DACOUTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the DAC8 output + connectivity to pin. */ +#define COMP_CTL1_DACOUTEN_ENABLE ((uint32_t)0x00000800U) /* !< Enable the DAC8 output connectivity + to pin. */ /* COMP_CTL1[WINCOMPEN] Bits */ #define COMP_CTL1_WINCOMPEN_OFS (12) /* !< WINCOMPEN Offset */ #define COMP_CTL1_WINCOMPEN_MASK ((uint32_t)0x00001000U) /* !< This bit enables window comparator @@ -721,14 +729,9 @@ typedef struct { #define COMP_CTL2_REFSRC_VREF ((uint32_t)0x00000018U) /* !< In devices where internal VREF is buffered and hookedup to extrernal VREF pin, VREF applied as reference - to comparator. DAC is switched off. - Note: In LEGO_A3, DAC is turned off - in this selection, in other deviced - DAC is kept on. */ + to comparator. DAC is switched off. */ #define COMP_CTL2_REFSRC_VDDA ((uint32_t)0x00000028U) /* !< VDDA is used as comparator - reference. Note: In LEGO_A3, DAC is - turned off in this selection, in - other deviced DAC is kept on. */ + reference. */ #define COMP_CTL2_REFSRC_INTVREF_DAC ((uint32_t)0x00000030U) /* !< Internal reference selected as the reference source to DAC and DAC output applied as reference to @@ -792,18 +795,22 @@ typedef struct { #define COMP_CTL3_DACCODE0_OFS (0) /* !< DACCODE0 Offset */ #define COMP_CTL3_DACCODE0_MASK ((uint32_t)0x000000FFU) /* !< This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC - output will be 0 V. When the DAC code + output will be selected reference + voltage x 1/256 V. When the DAC code is 0xFF the DAC output will be - selected reference voltage x 255/256. */ + selected reference voltage x 255/256 + V. */ #define COMP_CTL3_DACCODE0_MNIMUM ((uint32_t)0x00000000U) /* !< Minimum DAC code value */ #define COMP_CTL3_DACCODE0_MAXIMUM ((uint32_t)0x000000FFU) /* !< Minimum DAC code value */ /* COMP_CTL3[DACCODE1] Bits */ #define COMP_CTL3_DACCODE1_OFS (16) /* !< DACCODE1 Offset */ #define COMP_CTL3_DACCODE1_MASK ((uint32_t)0x00FF0000U) /* !< This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC - output will be 0 V. When the DAC code + output will be selected reference + voltage x 1/256 V. When the DAC code is 0xFF the DAC output will be - selected reference voltage x 255/256. */ + selected reference voltage x 255/256 + V. */ #define COMP_CTL3_DACCODE1_MNIMUM ((uint32_t)0x00000000U) /* !< Minimum DAC code value */ #define COMP_CTL3_DACCODE1_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Minimum DAC code value */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_i2s.h b/mspm0/source/ti/devices/msp/peripherals/hw_i2s.h new file mode 100644 index 0000000..6064406 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_i2s.h @@ -0,0 +1,984 @@ +/***************************************************************************** + + Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_i2s__include +#define ti_devices_msp_peripherals_hw_i2s__include + +/* Filename: hw_i2s.h */ +/* Revised: 2025-07-22 15:38:34 */ +/* Revision: 5269ff1910f5f8ca76039289749ec80c6ead1fda */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* I2S Registers +******************************************************************************/ +#define I2S_DMA_TRIG_TX_OFS ((uint32_t)0x00001080U) +#define I2S_DMA_TRIG_RX_OFS ((uint32_t)0x00001050U) +#define I2S_CPU_INT_OFS ((uint32_t)0x00001020U) +#define I2S_GPRCM_OFS ((uint32_t)0x00000800U) + + +/** @addtogroup I2S_DMA_TRIG_TX + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001088) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001090) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001098) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x000010A0) Interrupt set */ +} I2S_DMA_TRIG_TX_Regs; + +/*@}*/ /* end of group I2S_DMA_TRIG_TX */ + +/** @addtogroup I2S_DMA_TRIG_RX + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */ +} I2S_DMA_TRIG_RX_Regs; + +/*@}*/ /* end of group I2S_DMA_TRIG_RX */ + +/** @addtogroup I2S_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt Mask Register Selects mask states of + the flags in [IRQFLAGS.*] that contribute to the I2S_IRQ event. */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) This registers gives the raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) This registers gives the raw interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt Set Register. This register can be used + by software for diagnostics and safety checking purposes. */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear register. This register allows + software to clear interrupts. */ +} I2S_CPU_INT_Regs; + +/*@}*/ /* end of group I2S_CPU_INT */ + +/** @addtogroup I2S_GPRCM + @{ +*/ + +typedef struct { + __IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */ + __O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */ + __IO uint32_t CLKCFG; /* !< (@ 0x00000808) Peripheral Clock Configuration Register */ + uint32_t RESERVED0[2]; + __I uint32_t STAT; /* !< (@ 0x00000814) Status Register */ +} I2S_GPRCM_Regs; + +/*@}*/ /* end of group I2S_GPRCM */ + +/** @addtogroup I2S + @{ +*/ + +typedef struct { + uint32_t RESERVED0[512]; + I2S_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */ + uint32_t RESERVED1[508]; + __IO uint32_t PDBGCTL; /* !< (@ 0x00001008) Peripheral Debug Control */ + uint32_t RESERVED2[5]; + I2S_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED3; + I2S_DMA_TRIG_RX_Regs DMA_TRIG_RX; /* !< (@ 0x00001050) */ + uint32_t RESERVED4[3]; + I2S_DMA_TRIG_TX_Regs DMA_TRIG_TX; /* !< (@ 0x00001080) */ + uint32_t RESERVED5[16]; + __O uint32_t INTCTL; /* !< (@ 0x000010E4) Interrupt control register */ + uint32_t RESERVED6[6]; + __IO uint32_t FMTCFG; /* !< (@ 0x00001100) This register configures the serial interface + format */ + __IO uint32_t CLKCTL; /* !< (@ 0x00001104) This register controls internal audio clock */ + __I uint32_t STAT; /* !< (@ 0x00001108) Status Register */ + __IO uint32_t IFLS; /* !< (@ 0x0000110C) Interrupt FIFO Level Select Register */ + __IO uint32_t WCLKSRC; /* !< (@ 0x00001110) This register configures the WCLK Source */ + uint32_t RESERVED7; + __IO uint32_t DIRCFG; /* !< (@ 0x00001118) This register configures the direction of data + pins(AD0/AD1) */ + uint32_t RESERVED8; + __O uint32_t TXDATA; /* !< (@ 0x00001120) Transmit Data Register */ + __I uint32_t RXDATA; /* !< (@ 0x00001124) Receive Data Register */ + uint32_t RESERVED9[8]; + __IO uint32_t WMASK0; /* !< (@ 0x00001148) This register configures the word selection dit + mask for data pin 0(AD0) */ + __IO uint32_t WMASK1; /* !< (@ 0x0000114C) This register configures the word selection dit + mask for data pin 1(AD1) */ + uint32_t RESERVED10[4]; + __IO uint32_t MCLKDIV; /* !< (@ 0x00001160) This field configures MCLK division ratio */ + __IO uint32_t WCLKDIV; /* !< (@ 0x00001164) Configures WCLK division ratio */ + __IO uint32_t BCLKDIV; /* !< (@ 0x00001168) This field configures BCLK division ratio */ +} I2S_Regs; + +/*@}*/ /* end of group I2S */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* I2S Register Control Bits +******************************************************************************/ + +/* I2S_DMA_TRIG_TX_IMASK Bits */ +/* I2S_DMA_TRIG_TX_IMASK[TXINT] Bits */ +#define I2S_DMA_TRIG_TX_IMASK_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_DMA_TRIG_TX_IMASK_TXINT_MASK ((uint32_t)0x00000004U) /* !< Enable Transmit Interrupt. */ +#define I2S_DMA_TRIG_TX_IMASK_TXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define I2S_DMA_TRIG_TX_IMASK_TXINT_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* I2S_DMA_TRIG_TX_RIS Bits */ +/* I2S_DMA_TRIG_TX_RIS[TXINT] Bits */ +#define I2S_DMA_TRIG_TX_RIS_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_DMA_TRIG_TX_RIS_TXINT_MASK ((uint32_t)0x00000004U) /* !< Transmit Interrupt. */ +#define I2S_DMA_TRIG_TX_RIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_DMA_TRIG_TX_RIS_TXINT_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */ + +/* I2S_DMA_TRIG_TX_MIS Bits */ +/* I2S_DMA_TRIG_TX_MIS[TXINT] Bits */ +#define I2S_DMA_TRIG_TX_MIS_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_DMA_TRIG_TX_MIS_TXINT_MASK ((uint32_t)0x00000004U) /* !< Masked Transmit Interrupt. */ +#define I2S_DMA_TRIG_TX_MIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_DMA_TRIG_TX_MIS_TXINT_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */ + +/* I2S_DMA_TRIG_TX_ISET Bits */ +/* I2S_DMA_TRIG_TX_ISET[TXINT] Bits */ +#define I2S_DMA_TRIG_TX_ISET_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_DMA_TRIG_TX_ISET_TXINT_MASK ((uint32_t)0x00000004U) /* !< Set Transmit Interrupt. */ +#define I2S_DMA_TRIG_TX_ISET_TXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_DMA_TRIG_TX_ISET_TXINT_SET ((uint32_t)0x00000004U) /* !< Set Interrupt */ + +/* I2S_DMA_TRIG_RX_IMASK Bits */ +/* I2S_DMA_TRIG_RX_IMASK[RXINT] Bits */ +#define I2S_DMA_TRIG_RX_IMASK_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_DMA_TRIG_RX_IMASK_RXINT_MASK ((uint32_t)0x00000002U) /* !< Enable Receive Interrupt. */ +#define I2S_DMA_TRIG_RX_IMASK_RXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define I2S_DMA_TRIG_RX_IMASK_RXINT_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ + +/* I2S_DMA_TRIG_RX_RIS Bits */ +/* I2S_DMA_TRIG_RX_RIS[RXINT] Bits */ +#define I2S_DMA_TRIG_RX_RIS_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_DMA_TRIG_RX_RIS_RXINT_MASK ((uint32_t)0x00000002U) /* !< Receive Interrupt. */ +#define I2S_DMA_TRIG_RX_RIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_DMA_TRIG_RX_RIS_RXINT_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */ + +/* I2S_DMA_TRIG_RX_MIS Bits */ +/* I2S_DMA_TRIG_RX_MIS[RXINT] Bits */ +#define I2S_DMA_TRIG_RX_MIS_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_DMA_TRIG_RX_MIS_RXINT_MASK ((uint32_t)0x00000002U) /* !< Masked Receive Interrupt. */ +#define I2S_DMA_TRIG_RX_MIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_DMA_TRIG_RX_MIS_RXINT_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */ + +/* I2S_DMA_TRIG_RX_ISET Bits */ +/* I2S_DMA_TRIG_RX_ISET[RXINT] Bits */ +#define I2S_DMA_TRIG_RX_ISET_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_DMA_TRIG_RX_ISET_RXINT_MASK ((uint32_t)0x00000002U) /* !< Set Receive Interrupt. */ +#define I2S_DMA_TRIG_RX_ISET_RXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_DMA_TRIG_RX_ISET_RXINT_SET ((uint32_t)0x00000002U) /* !< Set Interrupt */ + +/* I2S_IIDX Bits */ +/* I2S_IIDX[STAT] Bits */ +#define I2S_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define I2S_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Module Interrupt Vector Value. + This register provides the highes + priority interrupt index. A read + clears the corresponding interrupt + flag in RIS and MIS registers. + 15h-1Fh = Reserved */ +#define I2S_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define I2S_IIDX_STAT_WCLKERR ((uint32_t)0x00000001U) /* !< WCLK Error */ +#define I2S_IIDX_STAT_RXIFG ((uint32_t)0x00000002U) /* !< Receive interrupt; Interrupt Flag: + RX */ +#define I2S_IIDX_STAT_TXIFG ((uint32_t)0x00000003U) /* !< Transmit interrupt; Interrupt Flag: + TX */ +#define I2S_IIDX_STAT_RXFIFO_OVF_EVT ((uint32_t)0x00000004U) /* !< RX FIFO Overflow Event/interrupt + pending */ +#define I2S_IIDX_STAT_TXFIFO_UNF_EVT ((uint32_t)0x00000005U) /* !< TX FIFO underflow interrupt */ +#define I2S_IIDX_STAT_DMA_DONE_RX ((uint32_t)0x00000010U) /* !< DMA DONE on RX */ +#define I2S_IIDX_STAT_DMA_DONE_TX ((uint32_t)0x00000011U) /* !< DMA DONE on TX */ +#define I2S_IIDX_STAT_DMA_PREIRQ_RX ((uint32_t)0x00000013U) /* !< DMA PRE IRQ INTERRUPT */ +#define I2S_IIDX_STAT_DMA_PREIRQ_TX ((uint32_t)0x00000014U) /* !< DMA PRE IRQ INTERRUPT */ + +/* I2S_CPU_INT_IMASK Bits */ +/* I2S_CPU_INT_IMASK[WCLKERR] Bits */ +#define I2S_CPU_INT_IMASK_WCLKERR_OFS (0) /* !< WCLKERR Offset */ +#define I2S_CPU_INT_IMASK_WCLKERR_MASK ((uint32_t)0x00000001U) /* !< WCLKERR interrupt mask */ +#define I2S_CPU_INT_IMASK_WCLKERR_DIS ((uint32_t)0x00000000U) /* !< Disable the interrupt mask */ +#define I2S_CPU_INT_IMASK_WCLKERR_EN ((uint32_t)0x00000001U) /* !< Enable the interrupt mask */ +/* I2S_CPU_INT_IMASK[RXINT] Bits */ +#define I2S_CPU_INT_IMASK_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_CPU_INT_IMASK_RXINT_MASK ((uint32_t)0x00000002U) /* !< Enable Receive Interrupt. */ +#define I2S_CPU_INT_IMASK_RXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define I2S_CPU_INT_IMASK_RXINT_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* I2S_CPU_INT_IMASK[TXINT] Bits */ +#define I2S_CPU_INT_IMASK_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_CPU_INT_IMASK_TXINT_MASK ((uint32_t)0x00000004U) /* !< Enable Transmit Interrupt. */ +#define I2S_CPU_INT_IMASK_TXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define I2S_CPU_INT_IMASK_TXINT_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* I2S_CPU_INT_IMASK[DMA_DONE_RX] Bits */ +#define I2S_CPU_INT_IMASK_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define I2S_CPU_INT_IMASK_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Enable DMA Done on RX Event Channel + Interrupt */ +#define I2S_CPU_INT_IMASK_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_CPU_INT_IMASK_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* I2S_CPU_INT_IMASK[DMA_DONE_TX] Bits */ +#define I2S_CPU_INT_IMASK_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define I2S_CPU_INT_IMASK_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Enable DMA Done on TX Event Channel + Interrupt */ +#define I2S_CPU_INT_IMASK_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_CPU_INT_IMASK_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* I2S_CPU_INT_IMASK[RXFIFO_OVF] Bits */ +#define I2S_CPU_INT_IMASK_RXFIFO_OVF_OFS (3) /* !< RXFIFO_OVF Offset */ +#define I2S_CPU_INT_IMASK_RXFIFO_OVF_MASK ((uint32_t)0x00000008U) /* !< RXFIFO overflow event mask. */ +#define I2S_CPU_INT_IMASK_RXFIFO_OVF_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define I2S_CPU_INT_IMASK_RXFIFO_OVF_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* I2S_CPU_INT_IMASK[TXFIFO_UNF] Bits */ +#define I2S_CPU_INT_IMASK_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define I2S_CPU_INT_IMASK_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< TX FIFO underflow interrupt mask */ +#define I2S_CPU_INT_IMASK_TXFIFO_UNF_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define I2S_CPU_INT_IMASK_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Set Interrupt Mask */ + +/* I2S_CPU_INT_RIS Bits */ +/* I2S_CPU_INT_RIS[WCLKERR] Bits */ +#define I2S_CPU_INT_RIS_WCLKERR_OFS (0) /* !< WCLKERR Offset */ +#define I2S_CPU_INT_RIS_WCLKERR_MASK ((uint32_t)0x00000001U) /* !< This interrupt is set when: - An + unexpected WCLK edge occurs during + the data delay period of a phase. + Note unexpected WCLK edges during the + word and idle periods of the phase + are not detected. - In dual-phase + mode, when two WCLK edges are less + than 4 BCLK cycles apart. - In + single-phase mode, when a WCLK pulse + occurs before the last channel. This + error requires a complete restart + since word synchronization has been + lost. */ +#define I2S_CPU_INT_RIS_WCLKERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_RIS_WCLKERR_SET ((uint32_t)0x00000001U) /* !< Interrupt occured */ +/* I2S_CPU_INT_RIS[RXINT] Bits */ +#define I2S_CPU_INT_RIS_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_CPU_INT_RIS_RXINT_MASK ((uint32_t)0x00000002U) /* !< Receive Interrupt. */ +#define I2S_CPU_INT_RIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_RIS_RXINT_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */ +/* I2S_CPU_INT_RIS[TXINT] Bits */ +#define I2S_CPU_INT_RIS_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_CPU_INT_RIS_TXINT_MASK ((uint32_t)0x00000004U) /* !< Transmit Interrupt. */ +#define I2S_CPU_INT_RIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_RIS_TXINT_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */ +/* I2S_CPU_INT_RIS[DMA_DONE_RX] Bits */ +#define I2S_CPU_INT_RIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define I2S_CPU_INT_RIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on RX Event Channel + Interrupt */ +#define I2S_CPU_INT_RIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_CPU_INT_RIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Interrupt occured */ +/* I2S_CPU_INT_RIS[DMA_DONE_TX] Bits */ +#define I2S_CPU_INT_RIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define I2S_CPU_INT_RIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on TX Event Channel + Interrupt */ +#define I2S_CPU_INT_RIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_CPU_INT_RIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Interrupt occured */ +/* I2S_CPU_INT_RIS[RXFIFO_OVF] Bits */ +#define I2S_CPU_INT_RIS_RXFIFO_OVF_OFS (3) /* !< RXFIFO_OVF Offset */ +#define I2S_CPU_INT_RIS_RXFIFO_OVF_MASK ((uint32_t)0x00000008U) /* !< RXFIFO overflow event. This + interrupt is set if an RX FIFO + overflow has been detected. */ +#define I2S_CPU_INT_RIS_RXFIFO_OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_RIS_RXFIFO_OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt occurred */ +/* I2S_CPU_INT_RIS[TXFIFO_UNF] Bits */ +#define I2S_CPU_INT_RIS_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define I2S_CPU_INT_RIS_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< TX FIFO Underflow Interrupt */ +#define I2S_CPU_INT_RIS_TXFIFO_UNF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_RIS_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Interrupt occurred */ + +/* I2S_CPU_INT_MIS Bits */ +/* I2S_CPU_INT_MIS[WCLKERR] Bits */ +#define I2S_CPU_INT_MIS_WCLKERR_OFS (0) /* !< WCLKERR Offset */ +#define I2S_CPU_INT_MIS_WCLKERR_MASK ((uint32_t)0x00000001U) /* !< This interrupt is set when: - An + unexpected WCLK edge occurs during + the data delay period of a phase. + Note unexpected WCLK edges during the + word and idle periods of the phase + are not detected. - In dual-phase + mode, when two WCLK edges are less + than 4 BCLK cycles apart. - In + single-phase mode, when a WCLK pulse + occurs before the last channel. This + error requires a complete restart + since word synchronization has been + lost. */ +#define I2S_CPU_INT_MIS_WCLKERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_MIS_WCLKERR_SET ((uint32_t)0x00000001U) /* !< Interrupt occured */ +/* I2S_CPU_INT_MIS[RXINT] Bits */ +#define I2S_CPU_INT_MIS_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_CPU_INT_MIS_RXINT_MASK ((uint32_t)0x00000002U) /* !< Masked Receive Interrupt. */ +#define I2S_CPU_INT_MIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_MIS_RXINT_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */ +/* I2S_CPU_INT_MIS[TXINT] Bits */ +#define I2S_CPU_INT_MIS_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_CPU_INT_MIS_TXINT_MASK ((uint32_t)0x00000004U) /* !< Masked Transmit Interrupt. */ +#define I2S_CPU_INT_MIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_MIS_TXINT_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */ +/* I2S_CPU_INT_MIS[DMA_DONE_RX] Bits */ +#define I2S_CPU_INT_MIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define I2S_CPU_INT_MIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Masked DMA Done on RX Event Channel + Interrupt */ +#define I2S_CPU_INT_MIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_MIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Interrupt occured */ +/* I2S_CPU_INT_MIS[DMA_DONE_TX] Bits */ +#define I2S_CPU_INT_MIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define I2S_CPU_INT_MIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Masked DMA Done on TX Event Channel + Interrupt */ +#define I2S_CPU_INT_MIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_MIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Interrupt occured */ +/* I2S_CPU_INT_MIS[RXFIFO_OVF] Bits */ +#define I2S_CPU_INT_MIS_RXFIFO_OVF_OFS (3) /* !< RXFIFO_OVF Offset */ +#define I2S_CPU_INT_MIS_RXFIFO_OVF_MASK ((uint32_t)0x00000008U) /* !< Masked RXFIFO overflow event. This + interrupt is set if an RX FIFO + overflow has been detected. */ +#define I2S_CPU_INT_MIS_RXFIFO_OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_MIS_RXFIFO_OVF_SET ((uint32_t)0x00000008U) /* !< Interrupt occurred */ +/* I2S_CPU_INT_MIS[TXFIFO_UNF] Bits */ +#define I2S_CPU_INT_MIS_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define I2S_CPU_INT_MIS_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< TX FIFO underflow interrupt */ +#define I2S_CPU_INT_MIS_TXFIFO_UNF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define I2S_CPU_INT_MIS_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Interrupt occurred */ + +/* I2S_CPU_INT_ISET Bits */ +/* I2S_CPU_INT_ISET[WCLKERR] Bits */ +#define I2S_CPU_INT_ISET_WCLKERR_OFS (0) /* !< WCLKERR Offset */ +#define I2S_CPU_INT_ISET_WCLKERR_MASK ((uint32_t)0x00000001U) /* !< This field sets the interrupt + WCLKERR */ +#define I2S_CPU_INT_ISET_WCLKERR_NOEFF ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_CPU_INT_ISET_WCLKERR_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* I2S_CPU_INT_ISET[RXINT] Bits */ +#define I2S_CPU_INT_ISET_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_CPU_INT_ISET_RXINT_MASK ((uint32_t)0x00000002U) /* !< Set Receive Interrupt. */ +#define I2S_CPU_INT_ISET_RXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_CPU_INT_ISET_RXINT_SET ((uint32_t)0x00000002U) /* !< Set Interrupt */ +/* I2S_CPU_INT_ISET[TXINT] Bits */ +#define I2S_CPU_INT_ISET_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_CPU_INT_ISET_TXINT_MASK ((uint32_t)0x00000004U) /* !< Set Transmit Interrupt. */ +#define I2S_CPU_INT_ISET_TXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_CPU_INT_ISET_TXINT_SET ((uint32_t)0x00000004U) /* !< Set Interrupt */ +/* I2S_CPU_INT_ISET[DMA_DONE_RX] Bits */ +#define I2S_CPU_INT_ISET_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define I2S_CPU_INT_ISET_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Set DMA Done on RX Event Channel + Interrupt */ +#define I2S_CPU_INT_ISET_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_CPU_INT_ISET_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt */ +/* I2S_CPU_INT_ISET[DMA_DONE_TX] Bits */ +#define I2S_CPU_INT_ISET_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define I2S_CPU_INT_ISET_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Set DMA Done on TX Event Channel + Interrupt */ +#define I2S_CPU_INT_ISET_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_CPU_INT_ISET_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt */ +/* I2S_CPU_INT_ISET[RXFIFO_OVF] Bits */ +#define I2S_CPU_INT_ISET_RXFIFO_OVF_OFS (3) /* !< RXFIFO_OVF Offset */ +#define I2S_CPU_INT_ISET_RXFIFO_OVF_MASK ((uint32_t)0x00000008U) /* !< Set RXFIFO overflow event. */ +#define I2S_CPU_INT_ISET_RXFIFO_OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_CPU_INT_ISET_RXFIFO_OVF_SET ((uint32_t)0x00000008U) /* !< Set Interrupt */ +/* I2S_CPU_INT_ISET[TXFIFO_UNF] Bits */ +#define I2S_CPU_INT_ISET_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define I2S_CPU_INT_ISET_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< Set TX FIFO Underflow Event */ +#define I2S_CPU_INT_ISET_TXFIFO_UNF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing has no effect */ +#define I2S_CPU_INT_ISET_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Set interrupt */ + +/* I2S_ICLR Bits */ +/* I2S_ICLR[WCLKERR] Bits */ +#define I2S_ICLR_WCLKERR_OFS (0) /* !< WCLKERR Offset */ +#define I2S_ICLR_WCLKERR_MASK ((uint32_t)0x00000001U) /* !< This field clears the interrupt + WCLKERR */ +#define I2S_ICLR_WCLKERR_NOEFF ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_ICLR_WCLKERR_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* I2S_ICLR[RXINT] Bits */ +#define I2S_ICLR_RXINT_OFS (1) /* !< RXINT Offset */ +#define I2S_ICLR_RXINT_MASK ((uint32_t)0x00000002U) /* !< Clear Receive Interrupt. */ +#define I2S_ICLR_RXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_ICLR_RXINT_CLR ((uint32_t)0x00000002U) /* !< Clear Interrupt */ +/* I2S_ICLR[TXINT] Bits */ +#define I2S_ICLR_TXINT_OFS (2) /* !< TXINT Offset */ +#define I2S_ICLR_TXINT_MASK ((uint32_t)0x00000004U) /* !< Clear Transmit Interrupt. */ +#define I2S_ICLR_TXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_ICLR_TXINT_CLR ((uint32_t)0x00000004U) /* !< Clear Interrupt */ +/* I2S_ICLR[DMA_DONE_RX] Bits */ +#define I2S_ICLR_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define I2S_ICLR_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Clear DMA Done on RX Event Channel + Interrupt */ +#define I2S_ICLR_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_ICLR_DMA_DONE_RX_CLR ((uint32_t)0x00008000U) /* !< Clear Interrupt */ +/* I2S_ICLR[DMA_DONE_TX] Bits */ +#define I2S_ICLR_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define I2S_ICLR_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Clear DMA Done on TX Event Channel + Interrupt */ +#define I2S_ICLR_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define I2S_ICLR_DMA_DONE_TX_CLR ((uint32_t)0x00010000U) /* !< Clear Interrupt */ +/* I2S_ICLR[RXFIFO_OVF] Bits */ +#define I2S_ICLR_RXFIFO_OVF_OFS (3) /* !< RXFIFO_OVF Offset */ +#define I2S_ICLR_RXFIFO_OVF_MASK ((uint32_t)0x00000008U) /* !< Clear RXFIFO overflow event. */ +#define I2S_ICLR_RXFIFO_OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_ICLR_RXFIFO_OVF_CLR ((uint32_t)0x00000008U) /* !< Clear Interrupt */ +/* I2S_ICLR[TXFIFO_UNF] Bits */ +#define I2S_ICLR_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define I2S_ICLR_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< Clear TXFIFO underflow event */ +#define I2S_ICLR_TXFIFO_UNF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing has no effect */ +#define I2S_ICLR_TXFIFO_UNF_CLR ((uint32_t)0x00000010U) /* !< Clear interrupt */ + +/* I2S_PWREN Bits */ +/* I2S_PWREN[ENABLE] Bits */ +#define I2S_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define I2S_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */ +#define I2S_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */ +#define I2S_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */ +/* I2S_PWREN[KEY] Bits */ +#define I2S_PWREN_KEY_OFS (24) /* !< KEY Offset */ +#define I2S_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */ +#define I2S_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this + register */ + +/* I2S_RSTCTL Bits */ +/* I2S_RSTCTL[RESETSTKYCLR] Bits */ +#define I2S_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */ +#define I2S_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT + register */ +#define I2S_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */ +/* I2S_RSTCTL[RESETASSERT] Bits */ +#define I2S_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */ +#define I2S_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */ +#define I2S_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define I2S_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */ +/* I2S_RSTCTL[KEY] Bits */ +#define I2S_RSTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define I2S_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */ +#define I2S_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this + register */ + +/* I2S_CLKCFG Bits */ +/* I2S_CLKCFG[KEY] Bits */ +#define I2S_CLKCFG_KEY_OFS (24) /* !< KEY Offset */ +#define I2S_CLKCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to Allow State Change -- 0xA9 */ +#define I2S_CLKCFG_KEY_UNLOCK ((uint32_t)0xA9000000U) /* !< key value to allow change field of + GPRCM */ +/* I2S_CLKCFG[DAICLK] Bits */ +#define I2S_CLKCFG_DAICLK_OFS (0) /* !< DAICLK Offset */ +#define I2S_CLKCFG_DAICLK_MASK ((uint32_t)0x00000003U) /* !< Audio Clock */ +#define I2S_CLKCFG_DAICLK_SYSOSC ((uint32_t)0x00000000U) /* !< SYSOSC */ +#define I2S_CLKCFG_DAICLK_HFXT ((uint32_t)0x00000001U) /* !< HF crystal */ +#define I2S_CLKCFG_DAICLK_PLL ((uint32_t)0x00000002U) /* !< PLL */ + +/* I2S_GPRCM_STAT Bits */ +/* I2S_GPRCM_STAT[RESETSTKY] Bits */ +#define I2S_GPRCM_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */ +#define I2S_GPRCM_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the + peripheral was reset, since this bit + was cleared by RESETSTKYCLR in the + RSTCTL register */ +#define I2S_GPRCM_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset + since this bit was last cleared by + RESETSTKYCLR in the RSTCTL register */ +#define I2S_GPRCM_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the + last bit clear */ + +/* I2S_PDBGCTL Bits */ +/* I2S_PDBGCTL[FREE] Bits */ +#define I2S_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */ +#define I2S_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */ +#define I2S_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes + functionality while the Core Halted + input is asserted and resumes when it + is deasserted. */ +#define I2S_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of + the Core Halted input */ +/* I2S_PDBGCTL[SOFT] Bits */ +#define I2S_PDBGCTL_SOFT_OFS (1) /* !< SOFT Offset */ +#define I2S_PDBGCTL_SOFT_MASK ((uint32_t)0x00000002U) /* !< Soft halt boundary control. This + function is only available, if [FREE] + is set to 'STOP' */ +#define I2S_PDBGCTL_SOFT_IMMEDIATE ((uint32_t)0x00000000U) /* !< The peripheral will halt + immediately, even if the resultant + state will result in corruption if + the system is restarted */ +#define I2S_PDBGCTL_SOFT_DELAYED ((uint32_t)0x00000002U) /* !< The peripheral blocks the debug + freeze until it has reached a + boundary where it can resume without + corruption */ + +/* I2S_INTCTL Bits */ +/* I2S_INTCTL[INTEVAL] Bits */ +#define I2S_INTCTL_INTEVAL_OFS (0) /* !< INTEVAL Offset */ +#define I2S_INTCTL_INTEVAL_MASK ((uint32_t)0x00000001U) /* !< Writing a 1 to this field + re-evaluates the interrupt sources. */ +#define I2S_INTCTL_INTEVAL_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define I2S_INTCTL_INTEVAL_EVAL ((uint32_t)0x00000001U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ + +/* I2S_FMTCFG Bits */ +/* I2S_FMTCFG[WORDLEN] Bits */ +#define I2S_FMTCFG_WORDLEN_OFS (0) /* !< WORDLEN Offset */ +#define I2S_FMTCFG_WORDLEN_MASK ((uint32_t)0x0000001FU) /* !< Number of bits per word (8-32): In + single-phase format, this is the + exact number of bits per word. In + dual-phase format, this is the + maximum number of bits per word. + Values below 8 and above 32 give + undefined behavior. Data written to + memory is always aligned to 16 or 32 + bits as defined by [MEMLEN32]. Bit + widths that differ from this + alignment will either be truncated or + zero padded. */ +/* I2S_FMTCFG[DUALPHASE] Bits */ +#define I2S_FMTCFG_DUALPHASE_OFS (5) /* !< DUALPHASE Offset */ +#define I2S_FMTCFG_DUALPHASE_MASK ((uint32_t)0x00000020U) /* !< This field selects between + dual-phase or single-phase format */ +#define I2S_FMTCFG_DUALPHASE_SINGLEPHASE ((uint32_t)0x00000000U) /* !< Single-phase: DSP format */ +#define I2S_FMTCFG_DUALPHASE_DUALPHASE ((uint32_t)0x00000020U) /* !< Dual-phase: I2S, LJF and RJF + formats */ +/* I2S_FMTCFG[SMPLEDGE] Bits */ +#define I2S_FMTCFG_SMPLEDGE_OFS (6) /* !< SMPLEDGE Offset */ +#define I2S_FMTCFG_SMPLEDGE_MASK ((uint32_t)0x00000040U) /* !< This field configures the sample + edge/ transfer edge of data (and + WCLK) on BCLK */ +#define I2S_FMTCFG_SMPLEDGE_NEGEDGE ((uint32_t)0x00000000U) /* !< Data is sampled on the negative + edge and clocked out on the positive + edge. */ +#define I2S_FMTCFG_SMPLEDGE_POSEDGE ((uint32_t)0x00000040U) /* !< Data is sampled on the positive + edge and clocked out on the negative + edge. */ +/* I2S_FMTCFG[MEMLEN32] Bits */ +#define I2S_FMTCFG_MEMLEN32_OFS (7) /* !< MEMLEN32 Offset */ +#define I2S_FMTCFG_MEMLEN32_MASK ((uint32_t)0x00000080U) /* !< This register configures the size + of each word stored to or loaded from + memory */ +#define I2S_FMTCFG_MEMLEN32_16BIT ((uint32_t)0x00000000U) /* !< 16-bit (one 16 bit access per + sample) */ +#define I2S_FMTCFG_MEMLEN32_32BIT ((uint32_t)0x00000080U) /* !< 32-bit(one 32-bit access per + sample) */ +/* I2S_FMTCFG[DATADLY] Bits */ +#define I2S_FMTCFG_DATADLY_OFS (8) /* !< DATADLY Offset */ +#define I2S_FMTCFG_DATADLY_MASK ((uint32_t)0x0000FF00U) /* !< This field configures the number of + BCLK periods between a WCLK edge and + MSB of the first word in a phase + Note: When 0, MSB of the next word + will be output in the idle period + between LSB of the previous word and + the start of the next word. Otherwise + logical 0 will be output until the + data delay has expired. */ +#define I2S_FMTCFG_DATADLY_ZERO ((uint32_t)0x00000000U) /* !< Zero BCLK periods - LJF and DSP + formats */ +#define I2S_FMTCFG_DATADLY_ONE ((uint32_t)0x00000100U) /* !< One BCLK periods - I2S and DSP + formats */ +#define I2S_FMTCFG_DATADLY_TWO ((uint32_t)0x00000200U) /* !< Two(Min) BCLK periods - RJF format */ +#define I2S_FMTCFG_DATADLY_MAX ((uint32_t)0x0000FF00U) /* !< Max(255) BCLK periods - RJF format */ +/* I2S_FMTCFG[SUSPEND] Bits */ +#define I2S_FMTCFG_SUSPEND_OFS (24) /* !< SUSPEND Offset */ +#define I2S_FMTCFG_SUSPEND_MASK ((uint32_t)0x01000000U) /* !< Suspend external communication */ +#define I2S_FMTCFG_SUSPEND_DISABLE ((uint32_t)0x00000000U) /* !< Functional mode resumed */ +#define I2S_FMTCFG_SUSPEND_ENABLE ((uint32_t)0x01000000U) /* !< External communication suspended */ +/* I2S_FMTCFG[ENABLE] Bits */ +#define I2S_FMTCFG_ENABLE_OFS (31) /* !< ENABLE Offset */ +#define I2S_FMTCFG_ENABLE_MASK ((uint32_t)0x80000000U) /* !< I2S Module Enable. If the I2S + is disabled in the middle of + transmission or reception, it + completes the current character + before stopping. If ENABLE bit + is not set, all registers can still + be accessed and updated. It is + recommended to setup and change I2S + operation mode whhile ENABLE bit is + cleared to avoid unpredictable + behavior during setup or update. + If disabled, I2S module will not + send or receive any data. */ +#define I2S_FMTCFG_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Module */ +#define I2S_FMTCFG_ENABLE_ENABLE ((uint32_t)0x80000000U) /* !< Enable module */ +/* I2S_FMTCFG[EMPTYSLOTOUTPUT] Bits */ +#define I2S_FMTCFG_EMPTYSLOTOUTPUT_OFS (16) /* !< EMPTYSLOTOUTPUT Offset */ +#define I2S_FMTCFG_EMPTYSLOTOUTPUT_MASK ((uint32_t)0x00030000U) /* !< The field configures the + EMPTYSLOTOUTPUT data pin direction */ +#define I2S_FMTCFG_EMPTYSLOTOUTPUT_ZERO ((uint32_t)0x00000000U) /* !< Send out zeroes in empty slots */ +#define I2S_FMTCFG_EMPTYSLOTOUTPUT_ONE ((uint32_t)0x00010000U) /* !< send out ones in empty slot */ +#define I2S_FMTCFG_EMPTYSLOTOUTPUT_TRISTATE ((uint32_t)0x00020000U) /* !< Tristate line during empty slot */ + +/* I2S_CLKCTL Bits */ +/* I2S_CLKCTL[WBEN] Bits */ +#define I2S_CLKCTL_WBEN_OFS (0) /* !< WBEN Offset */ +#define I2S_CLKCTL_WBEN_MASK ((uint32_t)0x00000001U) /* !< This field configures WCLK/BCLK + generation */ +#define I2S_CLKCTL_WBEN_DIS ((uint32_t)0x00000000U) /* !< Disables the generation */ +#define I2S_CLKCTL_WBEN_EN ((uint32_t)0x00000001U) /* !< Enable the generation */ +/* I2S_CLKCTL[WCLKPHASE] Bits */ +#define I2S_CLKCTL_WCLKPHASE_OFS (1) /* !< WCLKPHASE Offset */ +#define I2S_CLKCTL_WCLKPHASE_MASK ((uint32_t)0x00000006U) /* !< The field configures how the WCLK + division ratio is calculated and used + to generate different duty cycles + (See [WCLKDIV.WDIV]) */ +/* I2S_CLKCTL[MEN] Bits */ +#define I2S_CLKCTL_MEN_OFS (3) /* !< MEN Offset */ +#define I2S_CLKCTL_MEN_MASK ((uint32_t)0x00000008U) /* !< This field configures the MCLK + generation */ +#define I2S_CLKCTL_MEN_DIS ((uint32_t)0x00000000U) /* !< Disable the generation */ +#define I2S_CLKCTL_MEN_EN ((uint32_t)0x00000008U) /* !< Enable the generation */ + +/* I2S_STAT Bits */ +/* I2S_STAT[TXFF] Bits */ +#define I2S_STAT_TXFF_OFS (6) /* !< TXFF Offset */ +#define I2S_STAT_TXFF_MASK ((uint32_t)0x00000040U) /* !< Transmit FIFO Full The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define I2S_STAT_TXFF_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter is not full. */ +#define I2S_STAT_TXFF_SET ((uint32_t)0x00000040U) /* !< If the FIFO is disabled (FEN is 0), + the transmit holding register is + full. If the FIFO is enabled (FEN is + 1), the transmit FIFO is full. */ +/* I2S_STAT[RXFF] Bits */ +#define I2S_STAT_RXFF_OFS (3) /* !< RXFF Offset */ +#define I2S_STAT_RXFF_MASK ((uint32_t)0x00000008U) /* !< Receive FIFO Full The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define I2S_STAT_RXFF_CLEARED ((uint32_t)0x00000000U) /* !< The receiver can receive data. */ +#define I2S_STAT_RXFF_SET ((uint32_t)0x00000008U) /* !< If the FIFO is disabled (FEN is 0), + the receive holding register is full. + If the FIFO is enabled (FEN is 1), + the receive FIFO is full. */ +/* I2S_STAT[TXFE] Bits */ +#define I2S_STAT_TXFE_OFS (5) /* !< TXFE Offset */ +#define I2S_STAT_TXFE_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define I2S_STAT_TXFE_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter has data to + transmit. */ +#define I2S_STAT_TXFE_SET ((uint32_t)0x00000020U) /* !< If the FIFO is disabled (FEN is 0), + the transmit holding register is + empty. If the FIFO is enabled (FEN is + 1), the transmit FIFO is empty. */ +/* I2S_STAT[RXFE] Bits */ +#define I2S_STAT_RXFE_OFS (2) /* !< RXFE Offset */ +#define I2S_STAT_RXFE_MASK ((uint32_t)0x00000004U) /* !< Receive FIFO Empty The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define I2S_STAT_RXFE_CLEARED ((uint32_t)0x00000000U) /* !< The receiver is not empty. */ +#define I2S_STAT_RXFE_SET ((uint32_t)0x00000004U) /* !< If the FIFO is disabled (FEN is 0), + the receive holding register is + empty. If the FIFO is enabled (FEN is + 1), the receive FIFO is empty. */ +/* I2S_STAT[RXCLR] Bits */ +#define I2S_STAT_RXCLR_OFS (4) /* !< RXCLR Offset */ +#define I2S_STAT_RXCLR_MASK ((uint32_t)0x00000010U) /* !< RX FIFO Clear Status */ +#define I2S_STAT_RXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define I2S_STAT_RXCLR_SET ((uint32_t)0x00000010U) /* !< FIFO clear is complete */ +/* I2S_STAT[TXCLR] Bits */ +#define I2S_STAT_TXCLR_OFS (7) /* !< TXCLR Offset */ +#define I2S_STAT_TXCLR_MASK ((uint32_t)0x00000080U) /* !< TX FIFO Clear Status */ +#define I2S_STAT_TXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define I2S_STAT_TXCLR_SET ((uint32_t)0x00000080U) /* !< FIFO clear is complete */ + +/* I2S_IFLS Bits */ +/* I2S_IFLS[TXIFLSEL] Bits */ +#define I2S_IFLS_TXIFLSEL_OFS (0) /* !< TXIFLSEL Offset */ +#define I2S_IFLS_TXIFLSEL_MASK ((uint32_t)0x00000007U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define I2S_IFLS_TXIFLSEL_LVL_3_4 ((uint32_t)0x00000001U) /* !< TX FIFO <= 3/4 empty */ +#define I2S_IFLS_TXIFLSEL_LVL_1_2 ((uint32_t)0x00000002U) /* !< TX FIFO <= 1/2 empty (default) */ +#define I2S_IFLS_TXIFLSEL_LVL_1_4 ((uint32_t)0x00000003U) /* !< TX FIFO <= 1/4 empty */ +#define I2S_IFLS_TXIFLSEL_LVL_EMPTY ((uint32_t)0x00000005U) /* !< TX FIFO is empty */ +#define I2S_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000006U) /* !< TX FIFO <= 1 */ +#define I2S_IFLS_TXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000007U) /* !< TX_FIFO >= (MAX_FIFO_LEN -1) */ +/* I2S_IFLS[RXIFLSEL] Bits */ +#define I2S_IFLS_RXIFLSEL_OFS (4) /* !< RXIFLSEL Offset */ +#define I2S_IFLS_RXIFLSEL_MASK ((uint32_t)0x00000070U) /* !< Receive Interrupt FIFO Level Select + The trigger points for the receive + interrupt are as follows: Note: + In ULP domain the trigger levels are + used for: 0: LVL_1_4 4: LVL_FULL + For undefined settings the default + configuration is used. */ +#define I2S_IFLS_RXIFLSEL_LVL_1_4 ((uint32_t)0x00000010U) /* !< RX FIFO >= 1/4 full */ +#define I2S_IFLS_RXIFLSEL_LVL_1_2 ((uint32_t)0x00000020U) /* !< RX FIFO >= 1/2 full (default) */ +#define I2S_IFLS_RXIFLSEL_LVL_3_4 ((uint32_t)0x00000030U) /* !< RX FIFO >= 3/4 full */ +#define I2S_IFLS_RXIFLSEL_LVL_FULL ((uint32_t)0x00000050U) /* !< RX FIFO is full */ +#define I2S_IFLS_RXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000060U) /* !< RX_FIFO >= (MAX_FIFO_LEN -1) */ +#define I2S_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000070U) /* !< RX_FIFO <= 1 */ +/* I2S_IFLS[TXCLR] Bits */ +#define I2S_IFLS_TXCLR_OFS (3) /* !< TXCLR Offset */ +#define I2S_IFLS_TXCLR_MASK ((uint32_t)0x00000008U) /* !< TX FIFO CLEAR. Setting this bit + will clear the TX FIFO contents. */ +#define I2S_IFLS_TXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define I2S_IFLS_TXCLR_ENABLE ((uint32_t)0x00000008U) /* !< Enable FIFO Clear */ +/* I2S_IFLS[RXCLR] Bits */ +#define I2S_IFLS_RXCLR_OFS (7) /* !< RXCLR Offset */ +#define I2S_IFLS_RXCLR_MASK ((uint32_t)0x00000080U) /* !< RX FIFO CLEAR. Setting this bit + will clear the RX FIFO contents. */ +#define I2S_IFLS_RXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define I2S_IFLS_RXCLR_ENABLE ((uint32_t)0x00000080U) /* !< Enable FIFO Clear */ + +/* I2S_WCLKSRC Bits */ +/* I2S_WCLKSRC[WBCLKSRC] Bits */ +#define I2S_WCLKSRC_WBCLKSRC_OFS (0) /* !< WBCLKSRC Offset */ +#define I2S_WCLKSRC_WBCLKSRC_MASK ((uint32_t)0x00000003U) /* !< This field selects WCLK/BCLK source + for I2S. */ +#define I2S_WCLKSRC_WBCLKSRC_NONE ((uint32_t)0x00000000U) /* !< None ('0') */ +#define I2S_WCLKSRC_WBCLKSRC_EXT ((uint32_t)0x00000001U) /* !< External WCLK generator, from pad */ +#define I2S_WCLKSRC_WBCLKSRC_INT ((uint32_t)0x00000002U) /* !< Internal WCLK generator, from + module PRCM */ +/* I2S_WCLKSRC[WCLKINV] Bits */ +#define I2S_WCLKSRC_WCLKINV_OFS (2) /* !< WCLKINV Offset */ +#define I2S_WCLKSRC_WCLKINV_MASK ((uint32_t)0x00000004U) /* !< This field Inverts WCLK source (pad + or internal). */ +#define I2S_WCLKSRC_WCLKINV_NOT_INVERTED ((uint32_t)0x00000000U) /* !< Source is not intverted */ +#define I2S_WCLKSRC_WCLKINV_INVERTED ((uint32_t)0x00000004U) /* !< Source is inverted */ + +/* I2S_DIRCFG Bits */ +/* I2S_DIRCFG[AD0] Bits */ +#define I2S_DIRCFG_AD0_OFS (0) /* !< AD0 Offset */ +#define I2S_DIRCFG_AD0_MASK ((uint32_t)0x00000003U) /* !< The field configures the AD0 data + pin direction */ +#define I2S_DIRCFG_AD0_DIS ((uint32_t)0x00000000U) /* !< Not in use (disabled) */ +#define I2S_DIRCFG_AD0_IN ((uint32_t)0x00000001U) /* !< Input */ +#define I2S_DIRCFG_AD0_OUT ((uint32_t)0x00000002U) /* !< Output */ +/* I2S_DIRCFG[AD1] Bits */ +#define I2S_DIRCFG_AD1_OFS (4) /* !< AD1 Offset */ +#define I2S_DIRCFG_AD1_MASK ((uint32_t)0x00000030U) /* !< The field configures the AD1 data + pin direction */ +#define I2S_DIRCFG_AD1_DIS ((uint32_t)0x00000000U) /* !< Not in use (disabled) */ +#define I2S_DIRCFG_AD1_IN ((uint32_t)0x00000010U) /* !< Input */ +#define I2S_DIRCFG_AD1_OUT ((uint32_t)0x00000020U) /* !< Output */ + +/* I2S_TXDATA Bits */ +/* I2S_TXDATA[DATA] Bits */ +#define I2S_TXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define I2S_TXDATA_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Data Transmitted or Received Data + that is to be transmitted via the is + written to this field. When read, + this field contains the data that was + received by the . */ +#define I2S_TXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define I2S_TXDATA_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* I2S_RXDATA Bits */ +/* I2S_RXDATA[DATA] Bits */ +#define I2S_RXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define I2S_RXDATA_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Received Data. When read, this + field contains the data that was + received by the . */ +#define I2S_RXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define I2S_RXDATA_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* I2S_WMASK0 Bits */ +/* I2S_WMASK0[MASK] Bits */ +#define I2S_WMASK0_MASK_OFS (0) /* !< MASK Offset */ +#define I2S_WMASK0_MASK_MASK ((uint32_t)0x000000FFU) /* !< Bit-mask indicating valid channels + in a frame on AD0. In single-phase + mode, each bit represents one + channel, starting with LSB for the + first word in the frame. A frame can + contain up to 8/16 channels based on + SoC configuration. Channels that are + not included in the mask will not be + sampled nor stored in memory; data + clocked out in these slots is as per + configured EMPTYSLOTOUTPUT. In + dual-phase mode, only the two LSBs + are considered. For a stereo + configuration, set both bits. For a + mono configuration, set bit 0 only. + In mono mode, only channel 0 will be + sampled and stored to memory, and + channel 0 will be repeated when + clocked out. In mono mode, only + channel 0 will be sampled and stored + to memory, and channel 0 will be + repeated in the second phase when + clocked out. If all bits are zero, + no input words will be stored to + memory, and the output data lines + will be constant '0'. This can be + utilized when PWM debug output is + desired without any actively used + output pins. */ + +/* I2S_WMASK1 Bits */ +/* I2S_WMASK1[MASK] Bits */ +#define I2S_WMASK1_MASK_OFS (0) /* !< MASK Offset */ +#define I2S_WMASK1_MASK_MASK ((uint32_t)0x000000FFU) /* !< Bit-mask indicating valid channels + in a frame on AD1. In single-phase + mode, each bit represents one + channel, starting with LSB for the + first word in the frame. A frame can + contain up to 8/16 channels based on + SoC configuration. Channels that are + not included in the mask will not be + sampled nor stored in memory; data + clocked out in these slots is as per + configured EMPTYSLOTOUTPUT. In + dual-phase mode, only the two LSBs + are considered. For a stereo + configuration, set both bits. For a + mono configuration, set bit 0 only. + In mono mode, only channel 0 will be + sampled and stored to memory, and + channel 0 will be repeated when + clocked out. In mono mode, only + channel 0 will be sampled and stored + to memory, and channel 0 will be + repeated in the second phase when + clocked out. If all bits are zero, + no input words will be stored to + memory, and the output data lines + will be constant '0'. This can be + utilized when PWM debug output is + desired without any actively used + output pins. */ + +/* I2S_MCLKDIV Bits */ +/* I2S_MCLKDIV[MDIV] Bits */ +#define I2S_MCLKDIV_MDIV_OFS (0) /* !< MDIV Offset */ +#define I2S_MCLKDIV_MDIV_MASK ((uint32_t)0x000003FFU) /* !< An unsigned factor of the division + ratio used to generate MCLK [2-1024]: + + MCLK = MCUCLK/MDIV[Hz] + + A value of 0 is interpreted as 1024. + + A value of 1 is invalid. + + If MDIV is odd the low phase of the + clock is one MCUCLK period longer + than the high phase. */ + +/* I2S_WCLKDIV Bits */ +/* I2S_WCLKDIV[WDIV] Bits */ +#define I2S_WCLKDIV_WDIV_OFS (0) /* !< WDIV Offset */ +#define I2S_WCLKDIV_WDIV_MASK ((uint32_t)0x0000FFFFU) /* !< If [CLKCTL.WCLKPHASE] = 0, Single + phase. WCLK is high one BCLK period + and low WDIV[9:0] (unsigned, + [1-1023]) BCLK periods. + WCLK = + MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] + + If [CLKCTL.WCLKPHASE.*] = 1, Dual + phase. Each phase on WCLK (50% duty + cycle) is WDIV[9:0] (unsigned, + [1-1023]) BCLK periods. + WCLK = + MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] + + If [CLKCTL.WCLKPHASE.*] = 2, User + defined. WCLK is high WDIV[7:0] + (unsigned, [1-255]) BCLK periods and + low WDIV[15:8] (unsigned, [1-255]) + BCLK periods. + WCLK = MCUCLK / + (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] */ + +/* I2S_BCLKDIV Bits */ +/* I2S_BCLKDIV[BDIV] Bits */ +#define I2S_BCLKDIV_BDIV_OFS (0) /* !< BDIV Offset */ +#define I2S_BCLKDIV_BDIV_MASK ((uint32_t)0x000003FFU) /* !< An unsigned factor of the division + ratio used to generate BCLK [2-1024]: + + BCLK = MCUCLK/BDIV[Hz] + A + value of 0 is interpreted as 1024. + + A value of 1 is invalid. + If + BDIV is odd and [FMTCFG.SMPLEDGE] = + 0, the low phase of the clock is one + MCUCLK period longer than the high + phase. + If BDIV is odd and + [FMTCFG.SMPLEDGE] = 1 , the high + phase of the clock is one MCUCLK + period longer than the low phase. */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_i2s__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_npu.h b/mspm0/source/ti/devices/msp/peripherals/hw_npu.h new file mode 100644 index 0000000..41cf5d0 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_npu.h @@ -0,0 +1,271 @@ +/***************************************************************************** + + Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_npu__include +#define ti_devices_msp_peripherals_hw_npu__include + +/* Filename: hw_npu.h */ +/* Revised: 2025-06-16 15:14:44 */ +/* Revision: 5443928412b4f047f17723d5fe92cb118ff208b6 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* NPU Registers +******************************************************************************/ +#define NPU_INT_EVENT_OFS ((uint32_t)0x00001020U) +#define NPU_GPRCM_OFS ((uint32_t)0x00000800U) + +/** @addtogroup NPU_INT_EVENT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */ +} NPU_INT_EVENT_Regs; + +/*@}*/ /* end of group NPU_INT_EVENT */ + +/** @addtogroup NPU_GPRCM + @{ +*/ + +typedef struct { + __IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */ + __O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */ + uint32_t RESERVED0[3]; + __I uint32_t STAT; /* !< (@ 0x00000814) Status Register */ +} NPU_GPRCM_Regs; + +/*@}*/ /* end of group NPU_GPRCM */ + +/** @addtogroup NPU + @{ +*/ + +typedef struct { + uint32_t RESERVED0[512]; + NPU_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */ + uint32_t RESERVED1[514]; + NPU_INT_EVENT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED2[37]; + __I uint32_t EVT_MODE; /* !< (@ 0x000010E0) */ + uint32_t RESERVED3[6]; + __I uint32_t DESC; /* !< (@ 0x000010FC) */ + uint32_t RESERVED4[8]; + __IO uint32_t DREG0; /* !< (@ 0x00001120) */ + __IO uint32_t DREG1; /* !< (@ 0x00001124) */ + __IO uint32_t DREG2; /* !< (@ 0x00001128) */ + __IO uint32_t DREG3; /* !< (@ 0x0000112C) */ + __IO uint32_t DREG4; /* !< (@ 0x00001130) */ + __IO uint32_t DREG5; /* !< (@ 0x00001134) */ + __IO uint32_t DREG6[6]; /* !< (@ 0x00001138) */ + __IO uint32_t DREG7; /* !< (@ 0x00001150) */ + __IO uint32_t DREG8[20]; /* !< (@ 0x00001154) */ + uint32_t RESERVED5[347]; + __IO uint32_t DREG9[2]; /* !< (@ 0x00001710) */ + uint32_t RESERVED6[2]; + __IO uint32_t DREG10; /* !< (@ 0x00001720) */ + uint32_t RESERVED7[3]; + __IO uint32_t DREG11; /* !< (@ 0x00001730) */ + __IO uint32_t DREG12; /* !< (@ 0x00001734) */ + __IO uint32_t DREG13; /* !< (@ 0x00001738) */ + __IO uint32_t DREG14; /* !< (@ 0x0000173C) */ + uint32_t RESERVED8[4]; + __IO uint32_t DREG15; /* !< (@ 0x00001750) */ + __IO uint32_t DREG16; /* !< (@ 0x00001754) */ + __IO uint32_t DREG17; /* !< (@ 0x00001758) */ + __IO uint32_t DREG18; /* !< (@ 0x0000175C) */ + uint32_t RESERVED9[296]; + __IO uint32_t DREG19[32]; /* !< (@ 0x00001C00) */ + uint32_t RESERVED10[224]; + __IO uint32_t DREG20[256]; /* !< (@ 0x00002000) */ + uint32_t RESERVED11[256]; + __IO uint32_t DREG21[512]; /* !< (@ 0x00002800) */ +} NPU_Regs; + +/*@}*/ /* end of group NPU */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* NPU Register Control Bits +******************************************************************************/ + +/* NPU_IIDX Bits */ +/* NPU_IIDX[STAT] Bits */ +#define NPU_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define NPU_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */ +#define NPU_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define NPU_IIDX_STAT_DONE ((uint32_t)0x00000001U) /* !< Done indication interrupt */ + +/* NPU_IMASK Bits */ +/* NPU_IMASK[DONE] Bits */ +#define NPU_IMASK_DONE_OFS (0) /* !< DONE Offset */ +#define NPU_IMASK_DONE_MASK ((uint32_t)0x00000001U) /* !< DONE interrupt */ +#define NPU_IMASK_DONE_CLR ((uint32_t)0x00000000U) /* !< Disable Event */ +#define NPU_IMASK_DONE_SET ((uint32_t)0x00000001U) /* !< Enable Event */ + +/* NPU_RIS Bits */ +/* NPU_RIS[DONE] Bits */ +#define NPU_RIS_DONE_OFS (0) /* !< DONE Offset */ +#define NPU_RIS_DONE_MASK ((uint32_t)0x00000001U) /* !< DONE interrupt */ +#define NPU_RIS_DONE_CLR ((uint32_t)0x00000000U) /* !< Disable Event */ +#define NPU_RIS_DONE_SET ((uint32_t)0x00000001U) /* !< Enable Event */ + +/* NPU_MIS Bits */ +/* NPU_MIS[DONE] Bits */ +#define NPU_MIS_DONE_OFS (0) /* !< DONE Offset */ +#define NPU_MIS_DONE_MASK ((uint32_t)0x00000001U) /* !< DONE interrupt */ +#define NPU_MIS_DONE_CLR ((uint32_t)0x00000000U) /* !< Disable Event */ +#define NPU_MIS_DONE_SET ((uint32_t)0x00000001U) /* !< Enable Event */ + +/* NPU_ISET Bits */ +/* NPU_ISET[DONE] Bits */ +#define NPU_ISET_DONE_OFS (0) /* !< DONE Offset */ +#define NPU_ISET_DONE_MASK ((uint32_t)0x00000001U) /* !< DONE interrupt */ +#define NPU_ISET_DONE_CLR ((uint32_t)0x00000000U) /* !< Disable Event */ +#define NPU_ISET_DONE_SET ((uint32_t)0x00000001U) /* !< Enable Event */ + +/* NPU_ICLR Bits */ +/* NPU_ICLR[DONE] Bits */ +#define NPU_ICLR_DONE_OFS (0) /* !< DONE Offset */ +#define NPU_ICLR_DONE_MASK ((uint32_t)0x00000001U) /* !< DONE interrupt */ +#define NPU_ICLR_DONE_CLR ((uint32_t)0x00000000U) /* !< Disable Event */ +#define NPU_ICLR_DONE_SET ((uint32_t)0x00000001U) /* !< Enable Event */ + +/* NPU_PWREN Bits */ +/* NPU_PWREN[ENABLE] Bits */ +#define NPU_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define NPU_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */ +#define NPU_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */ +#define NPU_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */ +/* NPU_PWREN[KEY] Bits */ +#define NPU_PWREN_KEY_OFS (24) /* !< KEY Offset */ +#define NPU_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */ +#define NPU_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this + register */ + +/* NPU_RSTCTL Bits */ +/* NPU_RSTCTL[RESETSTKYCLR] Bits */ +#define NPU_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */ +#define NPU_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT + register */ +#define NPU_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define NPU_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */ +/* NPU_RSTCTL[RESETASSERT] Bits */ +#define NPU_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */ +#define NPU_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */ +#define NPU_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define NPU_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */ +/* NPU_RSTCTL[KEY] Bits */ +#define NPU_RSTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define NPU_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */ +#define NPU_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this + register */ + +/* NPU_STAT Bits */ +/* NPU_STAT[RESETSTKY] Bits */ +#define NPU_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */ +#define NPU_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the + peripheral was reset, since this bit + was cleared by RESETSTKYCLR in the + RSTCTL register */ +#define NPU_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset + since this bit was last cleared by + RESETSTKYCLR in the RSTCTL register */ +#define NPU_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the + last bit clear */ + +/* NPU_DESC Bits */ +/* NPU_DESC[MODULEID] Bits */ +#define NPU_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */ +#define NPU_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< specifies module id */ +/* NPU_DESC[FEATUREVER] Bits */ +#define NPU_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */ +#define NPU_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< specifies feature version info */ +/* NPU_DESC[INSTNUM] Bits */ +#define NPU_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */ +#define NPU_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< specifies module instance number */ +/* NPU_DESC[MAJREV] Bits */ +#define NPU_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */ +#define NPU_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< specifies major revision id */ +/* NPU_DESC[MINREV] Bits */ +#define NPU_DESC_MINREV_OFS (0) /* !< MINREV Offset */ +#define NPU_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< specifies minor revision id */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_npu__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_rtc.h b/mspm0/source/ti/devices/msp/peripherals/hw_rtc.h index 7181604..33ae364 100644 --- a/mspm0/source/ti/devices/msp/peripherals/hw_rtc.h +++ b/mspm0/source/ti/devices/msp/peripherals/hw_rtc.h @@ -1,6 +1,6 @@ /***************************************************************************** - Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions @@ -36,8 +36,8 @@ #define ti_devices_msp_peripherals_hw_rtc__include /* Filename: hw_rtc.h */ -/* Revised: 2023-11-10 23:33:05 */ -/* Revision: 57bdd406cc3983634d43d73d4088fae123c0b478 */ +/* Revised: 2025-08-07 23:42:45 */ +/* Revision: dc9e142443540e975c7bab8070bd55003479c74b */ #ifndef __CORTEX_M #ifdef __cplusplus @@ -188,8 +188,10 @@ typedef struct { __I uint32_t TSSTAT; /* !< (@ 0x00001168) Time Stamp Status Register */ __IO uint32_t TSCTL; /* !< (@ 0x0000116C) Time Stamp Control Register */ __O uint32_t TSCLR; /* !< (@ 0x00001170) Time Stamp Clear Register */ - __IO uint32_t LFSSRST; /* !< (@ 0x00001174) Low frequency sub-system reset request */ - __IO uint32_t RTCLOCK; /* !< (@ 0x00001178) Real time clock lock register */ + uint32_t RESERVED7[31]; + __IO uint32_t LFSSRST; /* !< (@ 0x000011F0) Low frequency sub-system reset request */ + uint32_t RESERVED8[2]; + __IO uint32_t RTCLOCK; /* !< (@ 0x000011FC) Real time clock lock register */ } RTC_Regs; /*@}*/ /* end of group RTC */ @@ -1793,7 +1795,10 @@ typedef struct { measurement. The corresponding port must be configured for the peripheral module function. */ -#define RTC_CAL_RTCCALFX_OFF ((uint32_t)0x00000000U) /* !< No frequency output to RTC_OUT pin */ +#define RTC_CAL_RTCCALFX_OFF ((uint32_t)0x00000000U) /* !< No frequency output to RTC_OUT pin + (MSPM0L1x0x, MSPM0G1x0x, MSPM0G3x0x + only) */ +#define RTC_CAL_RTCCALFX_F32KHZ ((uint32_t)0x00000000U) /* !< F32KHz */ #define RTC_CAL_RTCCALFX_F512HZ ((uint32_t)0x00010000U) /* !< 512 Hz */ #define RTC_CAL_RTCCALFX_F256HZ ((uint32_t)0x00020000U) /* !< 256 Hz */ #define RTC_CAL_RTCCALFX_F1HZ ((uint32_t)0x00030000U) /* !< 1 Hz */ @@ -2747,4 +2752,3 @@ typedef struct { #endif #endif /* ti_devices_msp_peripherals_hw_rtc__include */ - diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_spgss.h b/mspm0/source/ti/devices/msp/peripherals/hw_spgss.h new file mode 100644 index 0000000..f2ac5d8 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_spgss.h @@ -0,0 +1,1069 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_spgss__include +#define ti_devices_msp_peripherals_hw_spgss__include + +/* Filename: hw_spgss.h */ +/* Revised: 2024-07-09 09:23:19 */ +/* Revision: 3060da33b0a30a38b851efb52ec3edd92cebbf75 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* SPGSS Registers +******************************************************************************/ +#define SPGSS_I2C_PAIR_OFS ((uint32_t)0x000011C0U) +#define SPGSS_UNICOMM_LPBK_OFS ((uint32_t)0x00001120U) +#define SPGSS_DMA_CHAIN_OFS ((uint32_t)0x00001100U) +#define SPGSS_DMA_CHAIN1_OFS ((uint32_t)0x00001080U) +#define SPGSS_DMA_CHAIN0_OFS ((uint32_t)0x00001050U) +#define SPGSS_CPU_INT_OFS ((uint32_t)0x00001020U) + + +/** @addtogroup SPGSS_I2C_PAIR + @{ +*/ + +typedef struct { + __IO uint32_t PAIR0; /* !< (@ 0x000011C0) Pairing of I2C for MULTI-MASTER/SMBUS applications */ + __IO uint32_t PAIR1; /* !< (@ 0x000011C4) Pairing of I2C for MULTI-MASTER/SMBUS applications */ + __IO uint32_t PAIR2; /* !< (@ 0x000011C8) Pairing of I2C for MULTI-MASTER/SMBUS applications */ + __IO uint32_t PAIR3; /* !< (@ 0x000011CC) Pairing of I2C for MULTI-MASTER/SMBUS applications */ + __IO uint32_t PAIR4; /* !< (@ 0x000011D0) Pairing of I2C for MULTI-MASTER/SMBUS applications */ + __IO uint32_t PAIR5; /* !< (@ 0x000011D4) Pairing of I2C for MULTI-MASTER/SMBUS applications */ + __IO uint32_t PAIR6; /* !< (@ 0x000011D8) Pairing of I2C for MULTI-MASTER/SMBUS applications */ + __IO uint32_t PAIR7; /* !< (@ 0x000011DC) Pairing of I2C for MULTI-MASTER/SMBUS applications */ +} SPGSS_I2C_PAIR_Regs; + +/*@}*/ /* end of group SPGSS_I2C_PAIR */ + +/** @addtogroup SPGSS_UNICOMM_LPBK + @{ +*/ + +typedef struct { + __IO uint32_t LPBK0; /* !< (@ 0x00001120) Loopback between SPG instances User has to ensure + that the SPGs looped back have the same underlying IP instantiated; + i.e. both UART, both SPI, both I2C, etc., */ + __IO uint32_t LPBK1; /* !< (@ 0x00001124) Loopback between SPG instances User has to ensure + that the SPGs looped back have the same underlying IP instantiated; + i.e. both UART, both SPI, both I2C, etc., */ +} SPGSS_UNICOMM_LPBK_Regs; + +/*@}*/ /* end of group SPGSS_UNICOMM_LPBK */ + +/** @addtogroup SPGSS_DMA_CHAIN + @{ +*/ + +typedef struct { + __IO uint32_t DMACHAIN0; /* !< (@ 0x00001100) Select SPG FIFO for system DMA chaining */ + __IO uint32_t DMACHAIN1; /* !< (@ 0x00001104) Select SPG FIFO for system DMA chaining */ +} SPGSS_DMA_CHAIN_Regs; + +/*@}*/ /* end of group SPGSS_DMA_CHAIN */ + +/** @addtogroup SPGSS_DMA_CHAIN1 + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001088) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001090) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001098) Masked interrupt status */ + uint32_t RESERVED3[3]; + __O uint32_t ICLR; /* !< (@ 0x000010A8) Interrupt clear */ +} SPGSS_DMA_CHAIN1_Regs; + +/*@}*/ /* end of group SPGSS_DMA_CHAIN1 */ + +/** @addtogroup SPGSS_DMA_CHAIN0 + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */ + uint32_t RESERVED3[3]; + __O uint32_t ICLR; /* !< (@ 0x00001078) Interrupt clear */ +} SPGSS_DMA_CHAIN0_Regs; + +/*@}*/ /* end of group SPGSS_DMA_CHAIN0 */ + +/** @addtogroup SPGSS_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */ +} SPGSS_CPU_INT_Regs; + +/*@}*/ /* end of group SPGSS_CPU_INT */ + +/** @addtogroup SPGSS + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1032]; + SPGSS_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED1; + SPGSS_DMA_CHAIN0_Regs DMA_CHAIN0; /* !< (@ 0x00001050) */ + uint32_t RESERVED2; + SPGSS_DMA_CHAIN1_Regs DMA_CHAIN1; /* !< (@ 0x00001080) */ + uint32_t RESERVED3[21]; + SPGSS_DMA_CHAIN_Regs DMA_CHAIN; /* !< (@ 0x00001100) */ + uint32_t RESERVED4[6]; + SPGSS_UNICOMM_LPBK_Regs UNICOMM_LPBK; /* !< (@ 0x00001120) */ + uint32_t RESERVED5[38]; + SPGSS_I2C_PAIR_Regs I2C_PAIR; /* !< (@ 0x000011C0) */ +} SPGSS_Regs; + +/*@}*/ /* end of group SPGSS */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* SPGSS Register Control Bits +******************************************************************************/ + +/* SPGSS_PAIR0 Bits */ +/* SPGSS_PAIR0[CTL] Bits */ +#define SPGSS_PAIR0_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR0_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR0_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR0_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR0[TARGET] Bits */ +#define SPGSS_PAIR0_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR0_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR0_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR0_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR0[EN] Bits */ +#define SPGSS_PAIR0_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR0_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR0_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR0_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_PAIR1 Bits */ +/* SPGSS_PAIR1[CTL] Bits */ +#define SPGSS_PAIR1_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR1_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR1_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR1_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR1[TARGET] Bits */ +#define SPGSS_PAIR1_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR1_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR1_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR1_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR1[EN] Bits */ +#define SPGSS_PAIR1_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR1_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR1_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR1_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_PAIR2 Bits */ +/* SPGSS_PAIR2[CTL] Bits */ +#define SPGSS_PAIR2_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR2_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR2_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR2_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR2[TARGET] Bits */ +#define SPGSS_PAIR2_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR2_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR2_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR2_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR2[EN] Bits */ +#define SPGSS_PAIR2_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR2_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR2_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR2_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_PAIR3 Bits */ +/* SPGSS_PAIR3[CTL] Bits */ +#define SPGSS_PAIR3_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR3_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR3_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR3_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR3[TARGET] Bits */ +#define SPGSS_PAIR3_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR3_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR3_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR3_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR3[EN] Bits */ +#define SPGSS_PAIR3_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR3_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR3_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR3_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_PAIR4 Bits */ +/* SPGSS_PAIR4[CTL] Bits */ +#define SPGSS_PAIR4_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR4_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR4_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR4_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR4[TARGET] Bits */ +#define SPGSS_PAIR4_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR4_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR4_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR4_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR4[EN] Bits */ +#define SPGSS_PAIR4_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR4_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR4_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR4_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_PAIR5 Bits */ +/* SPGSS_PAIR5[CTL] Bits */ +#define SPGSS_PAIR5_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR5_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR5_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR5_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR5[TARGET] Bits */ +#define SPGSS_PAIR5_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR5_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR5_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR5_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR5[EN] Bits */ +#define SPGSS_PAIR5_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR5_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR5_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR5_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_PAIR6 Bits */ +/* SPGSS_PAIR6[CTL] Bits */ +#define SPGSS_PAIR6_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR6_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR6_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR6_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR6[TARGET] Bits */ +#define SPGSS_PAIR6_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR6_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR6_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR6_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR6[EN] Bits */ +#define SPGSS_PAIR6_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR6_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR6_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR6_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_PAIR7 Bits */ +/* SPGSS_PAIR7[CTL] Bits */ +#define SPGSS_PAIR7_CTL_OFS (8) /* !< CTL Offset */ +#define SPGSS_PAIR7_CTL_MASK ((uint32_t)0x00000F00U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + controller. */ +#define SPGSS_PAIR7_CTL_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_PAIR7_CTL_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_PAIR7[TARGET] Bits */ +#define SPGSS_PAIR7_TARGET_OFS (12) /* !< TARGET Offset */ +#define SPGSS_PAIR7_TARGET_MASK ((uint32_t)0x0000F000U) /* !< UNICOMM instance for loopback. This + instance will be treated as the + target */ +#define SPGSS_PAIR7_TARGET_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_PAIR7_TARGET_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ +/* SPGSS_PAIR7[EN] Bits */ +#define SPGSS_PAIR7_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_PAIR7_EN_MASK ((uint32_t)0x00000001U) /* !< Enable */ +#define SPGSS_PAIR7_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_PAIR7_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_LPBK0 Bits */ +/* SPGSS_LPBK0[CONTROLLER] Bits */ +#define SPGSS_LPBK0_CONTROLLER_OFS (8) /* !< CONTROLLER Offset */ +#define SPGSS_LPBK0_CONTROLLER_MASK ((uint32_t)0x00000F00U) /* !< Select SPG controller for loopback. + Signals invovled in loopback based + on interface chosen 1. SPI : CS, + SCLK, SDI, SDO 2. I2C : SCL, SDA 3. + UART : TX, RX */ +#define SPGSS_LPBK0_CONTROLLER_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK0_CONTROLLER_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_LPBK0[EN] Bits */ +#define SPGSS_LPBK0_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_LPBK0_EN_MASK ((uint32_t)0x00000001U) /* !< Loopback enable */ +#define SPGSS_LPBK0_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_LPBK0_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ +/* SPGSS_LPBK0[PERIPHERAL] Bits */ +#define SPGSS_LPBK0_PERIPHERAL_OFS (12) /* !< PERIPHERAL Offset */ +#define SPGSS_LPBK0_PERIPHERAL_MASK ((uint32_t)0x0000F000U) /* !< Select SPG peripheral for loopback. + Signals invovled in loopback based + on interface chosen 1. SPI : CS, + SCLK, SDI, SDO 2. I2C : SCL, SDA 3. + UART : TX, RX */ +#define SPGSS_LPBK0_PERIPHERAL_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK0_PERIPHERAL_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ + +/* SPGSS_LPBK1 Bits */ +/* SPGSS_LPBK1[CONTROLLER] Bits */ +#define SPGSS_LPBK1_CONTROLLER_OFS (8) /* !< CONTROLLER Offset */ +#define SPGSS_LPBK1_CONTROLLER_MASK ((uint32_t)0x00000F00U) /* !< Select SPG controller for loopback. + Signals invovled in loopback based + on interface chosen 1. SPI : CS, + SCLK, SDI, SDO 2. I2C : SCL, SDA 3. + UART : TX, RX */ +#define SPGSS_LPBK1_CONTROLLER_SPG1 ((uint32_t)0x00000000U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG2 ((uint32_t)0x00000100U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG3 ((uint32_t)0x00000200U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG4 ((uint32_t)0x00000300U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG5 ((uint32_t)0x00000400U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG6 ((uint32_t)0x00000500U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG7 ((uint32_t)0x00000600U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG8 ((uint32_t)0x00000700U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG9 ((uint32_t)0x00000800U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG10 ((uint32_t)0x00000900U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG11 ((uint32_t)0x00000A00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG12 ((uint32_t)0x00000B00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG13 ((uint32_t)0x00000C00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG14 ((uint32_t)0x00000D00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG15 ((uint32_t)0x00000E00U) /* !< SPG commander select for loopback. */ +#define SPGSS_LPBK1_CONTROLLER_SPG16 ((uint32_t)0x00000F00U) /* !< SPG commander select for loopback. */ +/* SPGSS_LPBK1[EN] Bits */ +#define SPGSS_LPBK1_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_LPBK1_EN_MASK ((uint32_t)0x00000001U) /* !< Loopback enable */ +#define SPGSS_LPBK1_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_LPBK1_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ +/* SPGSS_LPBK1[PERIPHERAL] Bits */ +#define SPGSS_LPBK1_PERIPHERAL_OFS (12) /* !< PERIPHERAL Offset */ +#define SPGSS_LPBK1_PERIPHERAL_MASK ((uint32_t)0x0000F000U) /* !< Select SPG peripheral for loopback. + Signals invovled in loopback based + on interface chosen 1. SPI : CS, + SCLK, SDI, SDO 2. I2C : SCL, SDA 3. + UART : TX, RX */ +#define SPGSS_LPBK1_PERIPHERAL_SPG1 ((uint32_t)0x00000000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG2 ((uint32_t)0x00001000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG3 ((uint32_t)0x00002000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG4 ((uint32_t)0x00003000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG5 ((uint32_t)0x00004000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG6 ((uint32_t)0x00005000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG7 ((uint32_t)0x00006000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG8 ((uint32_t)0x00007000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG9 ((uint32_t)0x00008000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG10 ((uint32_t)0x00009000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG11 ((uint32_t)0x0000A000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG12 ((uint32_t)0x0000B000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG13 ((uint32_t)0x0000C000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG14 ((uint32_t)0x0000D000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG15 ((uint32_t)0x0000E000U) /* !< SPG responder select for loopback. */ +#define SPGSS_LPBK1_PERIPHERAL_SPG16 ((uint32_t)0x0000F000U) /* !< SPG responder select for loopback. */ + +/* SPGSS_DMACHAIN0 Bits */ +/* SPGSS_DMACHAIN0[SEL] Bits */ +#define SPGSS_DMACHAIN0_SEL_OFS (1) /* !< SEL Offset */ +#define SPGSS_DMACHAIN0_SEL_MASK ((uint32_t)0x0000003EU) /* !< Select FIFO for chain */ +#define SPGSS_DMACHAIN0_SEL_SPG1RXDONE ((uint32_t)0x00000000U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG2RXDONE ((uint32_t)0x00000002U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG3RXDONE ((uint32_t)0x00000004U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG4RXDONE ((uint32_t)0x00000006U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG5RXDONE ((uint32_t)0x00000008U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG6RXDONE ((uint32_t)0x0000000AU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG7RXDONE ((uint32_t)0x0000000CU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG8RXDONE ((uint32_t)0x0000000EU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG9RXDONE ((uint32_t)0x00000010U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG10RXDONE ((uint32_t)0x00000012U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG11RXDONE ((uint32_t)0x00000014U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG12RXDONE ((uint32_t)0x00000016U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG13RXDONE ((uint32_t)0x00000018U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG14RXDONE ((uint32_t)0x0000001AU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG15RXDONE ((uint32_t)0x0000001CU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG16RXDONE ((uint32_t)0x0000001EU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG1TXDONE ((uint32_t)0x00000020U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG2TXDONE ((uint32_t)0x00000022U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG3TXDONE ((uint32_t)0x00000024U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG4TXDONE ((uint32_t)0x00000026U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG5TXDONE ((uint32_t)0x00000028U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG6TXDONE ((uint32_t)0x0000002AU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG7TXDONE ((uint32_t)0x0000002CU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG8TXDONE ((uint32_t)0x0000002EU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG9TXDONE ((uint32_t)0x00000030U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG10TXDONE ((uint32_t)0x00000032U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG11TXDONE ((uint32_t)0x00000034U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG12TXDONE ((uint32_t)0x00000036U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG13TXDONE ((uint32_t)0x00000038U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG14TXDONE ((uint32_t)0x0000003AU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG15TXDONE ((uint32_t)0x0000003CU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN0_SEL_SPG16TXDONE ((uint32_t)0x0000003EU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +/* SPGSS_DMACHAIN0[EN] Bits */ +#define SPGSS_DMACHAIN0_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_DMACHAIN0_EN_MASK ((uint32_t)0x00000001U) /* !< Enable chain */ +#define SPGSS_DMACHAIN0_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_DMACHAIN0_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_DMACHAIN1 Bits */ +/* SPGSS_DMACHAIN1[SEL] Bits */ +#define SPGSS_DMACHAIN1_SEL_OFS (1) /* !< SEL Offset */ +#define SPGSS_DMACHAIN1_SEL_MASK ((uint32_t)0x0000003EU) /* !< Select FIFO for chain */ +#define SPGSS_DMACHAIN1_SEL_SPG1RXDONE ((uint32_t)0x00000000U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG2RXDONE ((uint32_t)0x00000002U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG3RXDONE ((uint32_t)0x00000004U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG4RXDONE ((uint32_t)0x00000006U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG5RXDONE ((uint32_t)0x00000008U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG6RXDONE ((uint32_t)0x0000000AU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG7RXDONE ((uint32_t)0x0000000CU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG8RXDONE ((uint32_t)0x0000000EU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG9RXDONE ((uint32_t)0x00000010U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG10RXDONE ((uint32_t)0x00000012U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG11RXDONE ((uint32_t)0x00000014U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG12RXDONE ((uint32_t)0x00000016U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG13RXDONE ((uint32_t)0x00000018U) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG14RXDONE ((uint32_t)0x0000001AU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG15RXDONE ((uint32_t)0x0000001CU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG16RXDONE ((uint32_t)0x0000001EU) /* !< SPG DMA RX Done Raw Interrupt + Status. DMA_DONE from RX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG1TXDONE ((uint32_t)0x00000020U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG2TXDONE ((uint32_t)0x00000022U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG3TXDONE ((uint32_t)0x00000024U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG4TXDONE ((uint32_t)0x00000026U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG5TXDONE ((uint32_t)0x00000028U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG6TXDONE ((uint32_t)0x0000002AU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG7TXDONE ((uint32_t)0x0000002CU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG8TXDONE ((uint32_t)0x0000002EU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG9TXDONE ((uint32_t)0x00000030U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG10TXDONE ((uint32_t)0x00000032U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG11TXDONE ((uint32_t)0x00000034U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG12TXDONE ((uint32_t)0x00000036U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG13TXDONE ((uint32_t)0x00000038U) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG14TXDONE ((uint32_t)0x0000003AU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG15TXDONE ((uint32_t)0x0000003CU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +#define SPGSS_DMACHAIN1_SEL_SPG16TXDONE ((uint32_t)0x0000003EU) /* !< SPG DMA TX Done Raw Interrupt + Status. DMA_DONE from TX is selected + as a trigger for global DMA */ +/* SPGSS_DMACHAIN1[EN] Bits */ +#define SPGSS_DMACHAIN1_EN_OFS (0) /* !< EN Offset */ +#define SPGSS_DMACHAIN1_EN_MASK ((uint32_t)0x00000001U) /* !< Enable chain */ +#define SPGSS_DMACHAIN1_EN_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define SPGSS_DMACHAIN1_EN_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */ + +/* SPGSS_DMA_CHAIN1_IMASK Bits */ +/* SPGSS_DMA_CHAIN1_IMASK[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA Done Chain0 */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* SPGSS_DMA_CHAIN1_IMASK[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< DMA Done Chain1 */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define SPGSS_DMA_CHAIN1_IMASK_DMA_DONE_CHAIN1_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ + +/* SPGSS_DMA_CHAIN1_RIS Bits */ +/* SPGSS_DMA_CHAIN1_RIS[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_DMA_CHAIN1_RIS_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_DMA_CHAIN1_RIS_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< DMA Done Chain 1 */ +#define SPGSS_DMA_CHAIN1_RIS_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_DMA_CHAIN1_RIS_DMA_DONE_CHAIN1_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ + +/* SPGSS_DMA_CHAIN1_MIS Bits */ +/* SPGSS_DMA_CHAIN1_MIS[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_DMA_CHAIN1_MIS_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_DMA_CHAIN1_MIS_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< Masked DMA_DONE_CHAIN1 */ +#define SPGSS_DMA_CHAIN1_MIS_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_DMA_CHAIN1_MIS_DMA_DONE_CHAIN1_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ + +/* SPGSS_DMA_CHAIN1_ICLR Bits */ +/* SPGSS_DMA_CHAIN1_ICLR[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_DMA_CHAIN1_ICLR_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_DMA_CHAIN1_ICLR_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< DMA DONE CHAIN1 */ +#define SPGSS_DMA_CHAIN1_ICLR_DMA_DONE_CHAIN1_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define SPGSS_DMA_CHAIN1_ICLR_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000002U) /* !< Clear Interrupt */ + +/* SPGSS_DMA_CHAIN0_IMASK Bits */ +/* SPGSS_DMA_CHAIN0_IMASK[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_DMA_CHAIN0_IMASK_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_DMA_CHAIN0_IMASK_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA Done Chain0 */ +#define SPGSS_DMA_CHAIN0_IMASK_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define SPGSS_DMA_CHAIN0_IMASK_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ + +/* SPGSS_DMA_CHAIN0_RIS Bits */ +/* SPGSS_DMA_CHAIN0_RIS[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_DMA_CHAIN0_RIS_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_DMA_CHAIN0_RIS_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA Done Chain 0 */ +#define SPGSS_DMA_CHAIN0_RIS_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_DMA_CHAIN0_RIS_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ + +/* SPGSS_DMA_CHAIN0_MIS Bits */ +/* SPGSS_DMA_CHAIN0_MIS[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_DMA_CHAIN0_MIS_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_DMA_CHAIN0_MIS_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< Masked DMA_DONE_CHAIN0 */ +#define SPGSS_DMA_CHAIN0_MIS_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_DMA_CHAIN0_MIS_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ + +/* SPGSS_DMA_CHAIN0_ICLR Bits */ +/* SPGSS_DMA_CHAIN0_ICLR[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_DMA_CHAIN0_ICLR_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_DMA_CHAIN0_ICLR_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA DONE CHAIN0 */ +#define SPGSS_DMA_CHAIN0_ICLR_DMA_DONE_CHAIN0_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define SPGSS_DMA_CHAIN0_ICLR_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000001U) /* !< Clear Interrupt */ + +/* SPGSS_IIDX Bits */ +/* SPGSS_IIDX[STAT] Bits */ +#define SPGSS_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SPGSS_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< UART Module Interrupt Vector Value. + This register provides the highes + priority interrupt index. A read + clears the corresponding interrupt + flag in RIS and MIS registers. + 15h-1Fh = Reserved */ +#define SPGSS_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SPGSS_IIDX_STAT_DMA_DONE_CHAIN0 ((uint32_t)0x00000001U) /* !< DMA_DONE_CHAIN0 */ +#define SPGSS_IIDX_STAT_DMA_DONE_CHAIN1 ((uint32_t)0x00000002U) /* !< DMA DONE CHAIN1 */ + +/* SPGSS_CPU_INT_IMASK Bits */ +/* SPGSS_CPU_INT_IMASK[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA Done Chain0 */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* SPGSS_CPU_INT_IMASK[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< DMA Done Chain1 */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define SPGSS_CPU_INT_IMASK_DMA_DONE_CHAIN1_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ + +/* SPGSS_CPU_INT_RIS Bits */ +/* SPGSS_CPU_INT_RIS[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA Done Chain 0 */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* SPGSS_CPU_INT_RIS[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< DMA Done Chain 1 */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_CPU_INT_RIS_DMA_DONE_CHAIN1_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ + +/* SPGSS_CPU_INT_MIS Bits */ +/* SPGSS_CPU_INT_MIS[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< Masked DMA_DONE_CHAIN0 */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* SPGSS_CPU_INT_MIS[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< Masked DMA_DONE_CHAIN1 */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define SPGSS_CPU_INT_MIS_DMA_DONE_CHAIN1_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ + +/* SPGSS_ISET Bits */ +/* SPGSS_ISET[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_ISET_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_ISET_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA_DONE_CHAIN0 */ +#define SPGSS_ISET_DMA_DONE_CHAIN0_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define SPGSS_ISET_DMA_DONE_CHAIN0_SET ((uint32_t)0x00000001U) /* !< Set Interrupt */ +/* SPGSS_ISET[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_ISET_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_ISET_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< DMA_DONE_CHAIN1 */ +#define SPGSS_ISET_DMA_DONE_CHAIN1_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define SPGSS_ISET_DMA_DONE_CHAIN1_SET ((uint32_t)0x00000002U) /* !< Set Interrupt */ + +/* SPGSS_CPU_INT_ICLR Bits */ +/* SPGSS_CPU_INT_ICLR[DMA_DONE_CHAIN0] Bits */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN0_OFS (0) /* !< DMA_DONE_CHAIN0 Offset */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN0_MASK ((uint32_t)0x00000001U) /* !< DMA DONE CHAIN0 */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN0_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN0_CLR ((uint32_t)0x00000001U) /* !< Clear Interrupt */ +/* SPGSS_CPU_INT_ICLR[DMA_DONE_CHAIN1] Bits */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN1_OFS (1) /* !< DMA_DONE_CHAIN1 Offset */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN1_MASK ((uint32_t)0x00000002U) /* !< DMA DONE CHAIN1 */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN1_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define SPGSS_CPU_INT_ICLR_DMA_DONE_CHAIN1_CLR ((uint32_t)0x00000002U) /* !< Clear Interrupt */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_spgss__include */ + diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_unicomm.h b/mspm0/source/ti/devices/msp/peripherals/hw_unicomm.h new file mode 100644 index 0000000..5a5f7bb --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_unicomm.h @@ -0,0 +1,199 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_unicomm__include +#define ti_devices_msp_peripherals_hw_unicomm__include + +/* Filename: hw_unicomm.h */ +/* Revised: 2024-07-09 09:20:22 */ +/* Revision: 0a8f209063d706f1d2624ae41af7d5bd8aec6cce */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* UNICOMM Registers +******************************************************************************/ +#define UNICOMM_GPRCM_OFS ((uint32_t)0x00000800U) + + +/** @addtogroup UNICOMM_GPRCM + @{ +*/ + +typedef struct { + __IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */ + __O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */ + __IO uint32_t CLKCFG; /* !< (@ 0x00000808) Peripheral Clock Configuration Register */ + uint32_t RESERVED0[2]; + __I uint32_t STAT; /* !< (@ 0x00000814) Status Register */ +} UNICOMM_GPRCM_Regs; + +/*@}*/ /* end of group UNICOMM_GPRCM */ + +/** @addtogroup UNICOMM + @{ +*/ + +typedef struct { + uint32_t RESERVED0[512]; + UNICOMM_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */ + uint32_t RESERVED1[570]; + __IO uint32_t IPMODE; /* !< (@ 0x00001100) Mode Selection Register */ + __IO uint32_t BASEADDR; /* !< (@ 0x00001104) Used in security configuration to limit the + address range that DMA can read/write */ + __IO uint32_t RANGE; /* !< (@ 0x00001108) */ +} UNICOMM_Regs; + +/*@}*/ /* end of group UNICOMM */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* UNICOMM Register Control Bits +******************************************************************************/ + +/* UNICOMM_PWREN Bits */ +/* UNICOMM_PWREN[ENABLE] Bits */ +#define UNICOMM_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define UNICOMM_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */ +#define UNICOMM_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */ +#define UNICOMM_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */ +/* UNICOMM_PWREN[KEY] Bits */ +#define UNICOMM_PWREN_KEY_OFS (24) /* !< KEY Offset */ +#define UNICOMM_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */ +#define UNICOMM_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this + register */ + +/* UNICOMM_RSTCTL Bits */ +/* UNICOMM_RSTCTL[RESETSTKYCLR] Bits */ +#define UNICOMM_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */ +#define UNICOMM_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT + register */ +#define UNICOMM_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMM_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */ +/* UNICOMM_RSTCTL[RESETASSERT] Bits */ +#define UNICOMM_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */ +#define UNICOMM_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */ +#define UNICOMM_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMM_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */ +/* UNICOMM_RSTCTL[KEY] Bits */ +#define UNICOMM_RSTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define UNICOMM_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */ +#define UNICOMM_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this + register */ + +/* UNICOMM_CLKCFG Bits */ +/* UNICOMM_CLKCFG[KEY] Bits */ +#define UNICOMM_CLKCFG_KEY_OFS (24) /* !< KEY Offset */ +#define UNICOMM_CLKCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to Allow State Change -- 0xA9 */ +#define UNICOMM_CLKCFG_KEY_UNLOCK ((uint32_t)0xA9000000U) /* !< key value to allow change field of + GPRCM */ +/* UNICOMM_CLKCFG[BLOCKASYNC] Bits */ +#define UNICOMM_CLKCFG_BLOCKASYNC_OFS (8) /* !< BLOCKASYNC Offset */ +#define UNICOMM_CLKCFG_BLOCKASYNC_MASK ((uint32_t)0x00000100U) /* !< Async Clock Request is blocked from + starting SYSOSC or forcing bus clock + to 32MHz */ +#define UNICOMM_CLKCFG_BLOCKASYNC_DISABLE ((uint32_t)0x00000000U) /* !< Not block async clock request */ +#define UNICOMM_CLKCFG_BLOCKASYNC_ENABLE ((uint32_t)0x00000100U) /* !< Block async clock request */ + +/* UNICOMM_STAT Bits */ +/* UNICOMM_STAT[RESETSTKY] Bits */ +#define UNICOMM_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */ +#define UNICOMM_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the + peripheral was reset, since this bit + was cleared by RESETSTKYCLR in the + RSTCTL register */ +#define UNICOMM_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset + since this bit was last cleared by + RESETSTKYCLR in the RSTCTL register */ +#define UNICOMM_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the + last bit clear */ + +/* UNICOMM_IPMODE Bits */ +/* UNICOMM_IPMODE[SELECT] Bits */ +#define UNICOMM_IPMODE_SELECT_OFS (0) /* !< SELECT Offset */ +#define UNICOMM_IPMODE_SELECT_MASK ((uint32_t)0x00000003U) /* !< Free run control */ +#define UNICOMM_IPMODE_SELECT_UART ((uint32_t)0x00000000U) /* !< Default functionality is UART */ +#define UNICOMM_IPMODE_SELECT_SPI ((uint32_t)0x00000001U) /* !< SPG in SPI Mode */ +#define UNICOMM_IPMODE_SELECT_I2C_CONTROLLER ((uint32_t)0x00000002U) /* !< SPG in I2C Controller Mode */ +#define UNICOMM_IPMODE_SELECT_I2C_PERIPHERAL ((uint32_t)0x00000003U) /* !< SPG in I2C Peripheral Mode */ + +/* UNICOMM_BASEADDR Bits */ +/* UNICOMM_BASEADDR[ADDR] Bits */ +#define UNICOMM_BASEADDR_ADDR_OFS (6) /* !< ADDR Offset */ +#define UNICOMM_BASEADDR_ADDR_MASK ((uint32_t)0x7FFFFFC0U) /* !< Base Address of SRAM range that DMA + can read/write. Configure a power of + 2 base that is aligned to the range + specified. */ + +/* UNICOMM_RANGE Bits */ +/* UNICOMM_RANGE[RANGE] Bits */ +#define UNICOMM_RANGE_RANGE_OFS (0) /* !< RANGE Offset */ +#define UNICOMM_RANGE_RANGE_MASK ((uint32_t)0x000FFFFFU) /* !< Range (in bytes) of address range + that DMA can access */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_unicomm__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_unicommi2cc.h b/mspm0/source/ti/devices/msp/peripherals/hw_unicommi2cc.h new file mode 100644 index 0000000..3efd99f --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_unicommi2cc.h @@ -0,0 +1,1606 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_unicommi2cc__include +#define ti_devices_msp_peripherals_hw_unicommi2cc__include + +/* Filename: hw_unicommi2cc.h */ +/* Revised: 2024-07-26 01:36:27 */ +/* Revision: c33f9a433f6f30bac4ae2ae129653a2185ebb716 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* UNICOMMI2CC Registers +******************************************************************************/ +#define UNICOMMI2CC_SPGDMA_OFS ((uint32_t)0x000010B0U) +#define UNICOMMI2CC_DMA_TRIG0_OFS ((uint32_t)0x00001080U) +#define UNICOMMI2CC_DMA_TRIG1_OFS ((uint32_t)0x00001050U) +#define UNICOMMI2CC_CPU_INT_OFS ((uint32_t)0x00001020U) + + +/** @addtogroup UNICOMMI2CC_SPGDMA + @{ +*/ + +typedef struct { + uint32_t RESERVED0; + __IO uint32_t SPGDMARXCTL; /* !< (@ 0x000010B4) DMA Channel Control */ + __IO uint32_t SPGDMARXDA; /* !< (@ 0x000010B8) DMA Channel Destination Address */ + __IO uint32_t SPGDMARXSZ; /* !< (@ 0x000010BC) DMA Channel Size */ + uint32_t RESERVED1; + __IO uint32_t SPGDMATXCTL; /* !< (@ 0x000010C4) DMA Channel Control */ + __IO uint32_t SPGDMATXSA; /* !< (@ 0x000010C8) DMA Channel Destination Address */ + __IO uint32_t SPGDMATXSZ; /* !< (@ 0x000010CC) DMA Channel Size */ +} UNICOMMI2CC_SPGDMA_Regs; + +/*@}*/ /* end of group UNICOMMI2CC_SPGDMA */ + +/** @addtogroup UNICOMMI2CC_DMA_TRIG0 + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001088) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001090) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001098) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x000010A0) Interrupt set */ +} UNICOMMI2CC_DMA_TRIG0_Regs; + +/*@}*/ /* end of group UNICOMMI2CC_DMA_TRIG0 */ + +/** @addtogroup UNICOMMI2CC_DMA_TRIG1 + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */ +} UNICOMMI2CC_DMA_TRIG1_Regs; + +/*@}*/ /* end of group UNICOMMI2CC_DMA_TRIG1 */ + +/** @addtogroup UNICOMMI2CC_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */ +} UNICOMMI2CC_CPU_INT_Regs; + +/*@}*/ /* end of group UNICOMMI2CC_CPU_INT */ + +/** @addtogroup UNICOMMI2CC + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + __IO uint32_t CLKDIV; /* !< (@ 0x00001000) Clock Divider */ + uint32_t RESERVED1; + __IO uint32_t CLKSEL; /* !< (@ 0x00001008) Clock Select for Ultra Low Power peripherals */ + uint32_t RESERVED2[3]; + __IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */ + uint32_t RESERVED3; + UNICOMMI2CC_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED4; + UNICOMMI2CC_DMA_TRIG1_Regs DMA_TRIG1; /* !< (@ 0x00001050) */ + uint32_t RESERVED5[3]; + UNICOMMI2CC_DMA_TRIG0_Regs DMA_TRIG0; /* !< (@ 0x00001080) */ + uint32_t RESERVED6[3]; + UNICOMMI2CC_SPGDMA_Regs SPGDMA; /* !< (@ 0x000010B0) */ + uint32_t RESERVED7[5]; + __O uint32_t INTCTL; /* !< (@ 0x000010E4) Interrupt control register */ + uint32_t RESERVED8[6]; + __IO uint32_t CTR; /* !< (@ 0x00001100) Control Register */ + __IO uint32_t CR; /* !< (@ 0x00001104) Configuration */ + __I uint32_t SR; /* !< (@ 0x00001108) Status Register */ + __IO uint32_t IFLS; /* !< (@ 0x0000110C) Interrupt FIFO Level Select Register */ + __IO uint32_t TPR; /* !< (@ 0x00001110) Timer Period */ + uint32_t RESERVED9; + __IO uint32_t GFCTL; /* !< (@ 0x00001118) I2C Glitch Filter Control */ + __I uint32_t BMON; /* !< (@ 0x0000111C) Bus Monitor */ + __O uint32_t TXDATA; /* !< (@ 0x00001120) TXData */ + __I uint32_t RXDATA; /* !< (@ 0x00001124) RXData */ + __I uint32_t PECSR; /* !< (@ 0x00001128) PEC status register */ + uint32_t RESERVED10[8]; + __IO uint32_t TA; /* !< (@ 0x0000114C) Target Address Register */ + __I uint32_t TIMEOUT_CNT; /* !< (@ 0x00001150) I2C Timeout Count Register */ + __IO uint32_t TIMEOUT_CTL; /* !< (@ 0x00001154) I2C Timeout Count Control Register */ + __IO uint32_t PECCTL; /* !< (@ 0x00001158) I2C PEC control register */ +} UNICOMMI2CC_Regs; + +/*@}*/ /* end of group UNICOMMI2CC */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* UNICOMMI2CC Register Control Bits +******************************************************************************/ + +/* UNICOMMI2CC_SPGDMARXCTL Bits */ +/* UNICOMMI2CC_SPGDMARXCTL[DMAEN] Bits */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMI2CC_SPGDMARXCTL[DMAMEMINCR] Bits */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMADSTWDTH) */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMADSTWDTH) */ +/* UNICOMMI2CC_SPGDMARXCTL[DMAPREIRQ] Bits */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMI2CC_SPGDMARXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMI2CC_SPGDMARXCTL[DMATM] Bits */ +#define UNICOMMI2CC_SPGDMARXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMI2CC_SPGDMARXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register */ +#define UNICOMMI2CC_SPGDMARXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMI2CC_SPGDMARXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMI2CC_SPGDMARXCTL[DMADSTWDTH] Bits */ +#define UNICOMMI2CC_SPGDMARXCTL_DMADSTWDTH_OFS (28) /* !< DMADSTWDTH Offset */ +#define UNICOMMI2CC_SPGDMARXCTL_DMADSTWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA destination width. This bit + selects the destination as a byte, + half word, word or long word. */ +#define UNICOMMI2CC_SPGDMARXCTL_DMADSTWDTH_BYTE ((uint32_t)0x00000000U) /* !< Destination data width is BYTE + (8-bit) */ +#define UNICOMMI2CC_SPGDMARXCTL_DMADSTWDTH_HALF ((uint32_t)0x10000000U) /* !< Destination data width is HALF-WORD + (16-bit) */ +#define UNICOMMI2CC_SPGDMARXCTL_DMADSTWDTH_WORD ((uint32_t)0x20000000U) /* !< Destination data width is WORD + (32-bit) */ + +/* UNICOMMI2CC_SPGDMARXDA Bits */ +/* UNICOMMI2CC_SPGDMARXDA[ADDR] Bits */ +#define UNICOMMI2CC_SPGDMARXDA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMI2CC_SPGDMARXDA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMI2CC_SPGDMARXDA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_SPGDMARXDA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CC_SPGDMARXSZ Bits */ +/* UNICOMMI2CC_SPGDMARXSZ[SIZE] Bits */ +#define UNICOMMI2CC_SPGDMARXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMI2CC_SPGDMARXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMI2CC_SPGDMARXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_SPGDMARXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CC_SPGDMATXCTL Bits */ +/* UNICOMMI2CC_SPGDMATXCTL[DMAEN] Bits */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMI2CC_SPGDMATXCTL[DMAMEMINCR] Bits */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMASRCWDTH) */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMASRCWDTH) */ +/* UNICOMMI2CC_SPGDMATXCTL[DMAPREIRQ] Bits */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMI2CC_SPGDMATXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMI2CC_SPGDMATXCTL[DMATM] Bits */ +#define UNICOMMI2CC_SPGDMATXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMI2CC_SPGDMATXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register Note: + The repeat-single (2h) and + repeat-block (3h) transfer are only + available in a FULL-channel + configuration. Please consult the + datasheet of the specific device to + map which channel number has FULL or + BASIC capability. In a BASIC channel + configuration only the values for + single (0h) and block (1h) transfer + can be set. */ +#define UNICOMMI2CC_SPGDMATXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMI2CC_SPGDMATXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMI2CC_SPGDMATXCTL[DMASRCWDTH] Bits */ +#define UNICOMMI2CC_SPGDMATXCTL_DMASRCWDTH_OFS (28) /* !< DMASRCWDTH Offset */ +#define UNICOMMI2CC_SPGDMATXCTL_DMASRCWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA source width. This bit selects + the source data width as a byte, half + word, word or long word. */ +#define UNICOMMI2CC_SPGDMATXCTL_DMASRCWDTH_BYTE ((uint32_t)0x00000000U) /* !< Source data width is BYTE (8-bit) */ +#define UNICOMMI2CC_SPGDMATXCTL_DMASRCWDTH_HALF ((uint32_t)0x10000000U) /* !< Source data width is HALF-WORD + (16-bit) */ +#define UNICOMMI2CC_SPGDMATXCTL_DMASRCWDTH_WORD ((uint32_t)0x20000000U) /* !< Source data width is WORD (32-bit) */ + +/* UNICOMMI2CC_SPGDMATXSA Bits */ +/* UNICOMMI2CC_SPGDMATXSA[ADDR] Bits */ +#define UNICOMMI2CC_SPGDMATXSA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMI2CC_SPGDMATXSA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMI2CC_SPGDMATXSA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_SPGDMATXSA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CC_SPGDMATXSZ Bits */ +/* UNICOMMI2CC_SPGDMATXSZ[SIZE] Bits */ +#define UNICOMMI2CC_SPGDMATXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMI2CC_SPGDMATXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMI2CC_SPGDMATXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_SPGDMATXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CC_DMA_TRIG0_IMASK Bits */ +/* UNICOMMI2CC_DMA_TRIG0_IMASK[TXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG0_IMASK_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG0_IMASK_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_DMA_TRIG0_IMASK_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG0_IMASK_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_DMA_TRIG0_RIS Bits */ +/* UNICOMMI2CC_DMA_TRIG0_RIS[TXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG0_RIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG0_RIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_DMA_TRIG0_RIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG0_RIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_DMA_TRIG0_MIS Bits */ +/* UNICOMMI2CC_DMA_TRIG0_MIS[TXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG0_MIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG0_MIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_DMA_TRIG0_MIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG0_MIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_DMA_TRIG0_ISET Bits */ +/* UNICOMMI2CC_DMA_TRIG0_ISET[TXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG0_ISET_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG0_ISET_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_DMA_TRIG0_ISET_TXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG0_ISET_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_DMA_TRIG1_IMASK Bits */ +/* UNICOMMI2CC_DMA_TRIG1_IMASK[RXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG1_IMASK_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG1_IMASK_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CC_DMA_TRIG1_IMASK_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG1_IMASK_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_DMA_TRIG1_RIS Bits */ +/* UNICOMMI2CC_DMA_TRIG1_RIS[RXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG1_RIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG1_RIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger When FIFO + is present, trigger when RX FIFO + contains >= defined bytes + when FIFO is not present, this + indicates when buffer is full */ +#define UNICOMMI2CC_DMA_TRIG1_RIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG1_RIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_DMA_TRIG1_MIS Bits */ +/* UNICOMMI2CC_DMA_TRIG1_MIS[RXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG1_MIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG1_MIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CC_DMA_TRIG1_MIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG1_MIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_DMA_TRIG1_ISET Bits */ +/* UNICOMMI2CC_DMA_TRIG1_ISET[RXTRG] Bits */ +#define UNICOMMI2CC_DMA_TRIG1_ISET_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_DMA_TRIG1_ISET_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CC_DMA_TRIG1_ISET_RXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_DMA_TRIG1_ISET_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_IIDX Bits */ +/* UNICOMMI2CC_IIDX[STAT] Bits */ +#define UNICOMMI2CC_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define UNICOMMI2CC_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< I2C Module Interrupt Vector Value. + This register provides the highes + priority interrupt index. A read + clears the corresponding interrupt + flag in RIS and MISC. 15h-1Fh = + Reserved */ +#define UNICOMMI2CC_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define UNICOMMI2CC_IIDX_STAT_RXDONEFG ((uint32_t)0x00000001U) /* !< Data received */ +#define UNICOMMI2CC_IIDX_STAT_TXDONEFG ((uint32_t)0x00000002U) /* !< data transmitted */ +#define UNICOMMI2CC_IIDX_STAT_RXTRG ((uint32_t)0x00000003U) /* !< Receive Trigger */ +#define UNICOMMI2CC_IIDX_STAT_TXTRG ((uint32_t)0x00000004U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_IIDX_STAT_RXFULL ((uint32_t)0x00000005U) /* !< RX FIFO FULL Event/interrupt + pending */ +#define UNICOMMI2CC_IIDX_STAT_TXEMPTY ((uint32_t)0x00000006U) /* !< Transmit FIFO/Buffer Empty + Event/interrupt pending */ +#define UNICOMMI2CC_IIDX_STAT_NACKFG ((uint32_t)0x00000008U) /* !< Address/Data NACK */ +#define UNICOMMI2CC_IIDX_STAT_STARTFG ((uint32_t)0x00000009U) /* !< Start Event */ +#define UNICOMMI2CC_IIDX_STAT_STOPFG ((uint32_t)0x0000000AU) /* !< Stop Event */ +#define UNICOMMI2CC_IIDX_STAT_ARBLOSTFG ((uint32_t)0x0000000BU) /* !< Arbitration Lost */ +#define UNICOMMI2CC_IIDX_STAT_PEC_RX_ERR ((uint32_t)0x0000000CU) /* !< PEC Receive Error Event */ +#define UNICOMMI2CC_IIDX_STAT_TIMEOUTA ((uint32_t)0x0000000DU) /* !< Timeout A Event */ +#define UNICOMMI2CC_IIDX_STAT_TIMEOUTB ((uint32_t)0x0000000EU) /* !< Timeout B Event */ +#define UNICOMMI2CC_IIDX_STAT_DMA_DONE_RX ((uint32_t)0x00000010U) /* !< DMA DONE on Channel RX */ +#define UNICOMMI2CC_IIDX_STAT_DMA_DONE_TX ((uint32_t)0x00000011U) /* !< DMA DONE on Channel TX */ +#define UNICOMMI2CC_IIDX_STAT_DMA_PREIRQ_RX ((uint32_t)0x00000013U) /* !< DMA PRE IRQ INTERRUPT */ +#define UNICOMMI2CC_IIDX_STAT_DMA_PREIRQ_TX ((uint32_t)0x00000014U) /* !< DMA PRE IRQ INTERRUPT */ + +/* UNICOMMI2CC_CPU_INT_IMASK Bits */ +/* UNICOMMI2CC_CPU_INT_IMASK[RXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXDONE_MASK ((uint32_t)0x00000001U) /* !< RXDONE interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXDONE_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[TIMEOUTA] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< TIMEOUTA interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTA_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[NACK] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_NACK_OFS (7) /* !< NACK Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_NACK_MASK ((uint32_t)0x00000080U) /* !< NACK interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_NACK_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_NACK_SET ((uint32_t)0x00000080U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[START] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_START_OFS (8) /* !< START Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_START_MASK ((uint32_t)0x00000100U) /* !< START interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_START_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_START_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[STOP] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_STOP_OFS (9) /* !< STOP Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_STOP_MASK ((uint32_t)0x00000200U) /* !< STOP interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_STOP_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_STOP_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[ARBLOST] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_ARBLOST_OFS (10) /* !< ARBLOST Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_ARBLOST_MASK ((uint32_t)0x00000400U) /* !< Arbitration Lost interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_ARBLOST_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_ARBLOST_SET ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[TXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmit Transaction completed + Interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXDONE_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[RXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[TXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[DMA_DONE_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[DMA_DONE_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[PEC_RX_ERR] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< RX Pec Error Interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_PEC_RX_ERR_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[TIMEOUTB] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTB_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< DMA Done PREIRQ RX interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< DMA Done PREIRQ TX interrupt */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_IMASK_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[RXFULL] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_RXFULL_SET ((uint32_t)0x00000010U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_IMASK[TXEMPTY] Bits */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO/Buffer Empty + interrupt. */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_IMASK_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CC_CPU_INT_RIS Bits */ +/* UNICOMMI2CC_CPU_INT_RIS[RXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Receive Done Interrupt: RXDONE + interrupt is raised when a burst + length completes Or, in case of + quick command, when a quick command + with R/Wn bit set to '1' */ +#define UNICOMMI2CC_CPU_INT_RIS_RXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[TIMEOUTA] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A Interrupt */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTA_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[NACK] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_NACK_OFS (7) /* !< NACK Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_NACK_MASK ((uint32_t)0x00000080U) /* !< Address/Data NACK Interrupt: set + when address or data nack is received */ +#define UNICOMMI2CC_CPU_INT_RIS_NACK_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_NACK_SET ((uint32_t)0x00000080U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[START] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_START_OFS (8) /* !< START Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_START_MASK ((uint32_t)0x00000100U) /* !< START Detection Interrupt */ +#define UNICOMMI2CC_CPU_INT_RIS_START_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_START_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[STOP] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_STOP_OFS (9) /* !< STOP Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_STOP_MASK ((uint32_t)0x00000200U) /* !< STOP Detection Interrupt */ +#define UNICOMMI2CC_CPU_INT_RIS_STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_STOP_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[ARBLOST] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_ARBLOST_OFS (10) /* !< ARBLOST Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_ARBLOST_MASK ((uint32_t)0x00000400U) /* !< Arbitration Lost Interrupt: in + multi-controller systems, when this + controller loses out during + arbitration */ +#define UNICOMMI2CC_CPU_INT_RIS_ARBLOST_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_ARBLOST_SET ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[TXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmit Done Interrupt: + TXDONE interrupt is raised when a + burst length completes Or, in + case of quick command, when a quick + command with R/Wn bit set to '0' */ +#define UNICOMMI2CC_CPU_INT_RIS_TXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[RXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger When FIFO + is present, as per IFLS settings + when FIFO is not present, this + indicates when buffer is full */ +#define UNICOMMI2CC_CPU_INT_RIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_RIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[TXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger When FIFO is + present, as per IFLS settings + When FIFO is not present, trigger + when transmit buffer is empty */ +#define UNICOMMI2CC_CPU_INT_RIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_RIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[DMA_DONE_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[DMA_DONE_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_RIS[PEC_RX_ERR] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< Receive PEC Error Interrupt: set + when the calculated PEC does not + match received PEC */ +#define UNICOMMI2CC_CPU_INT_RIS_PEC_RX_ERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Interrupt Occured */ +/* UNICOMMI2CC_CPU_INT_RIS[TIMEOUTB] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTB_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Interrupt occured */ +/* UNICOMMI2CC_CPU_INT_RIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< DMA Pre-emptive Interrupt on RX + Event Channel */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* UNICOMMI2CC_CPU_INT_RIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< DMA Pre-Emptive Interrupt on + Receive Channel */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_RIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ +/* UNICOMMI2CC_CPU_INT_RIS[RXFULL] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. This interrupt + is set when receive FIFO is full. */ +#define UNICOMMI2CC_CPU_INT_RIS_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_RXFULL_SET ((uint32_t)0x00000010U) /* !< Interrupt occured */ +/* UNICOMMI2CC_CPU_INT_RIS[TXEMPTY] Bits */ +#define UNICOMMI2CC_CPU_INT_RIS_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CC_CPU_INT_RIS_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty: set when + Transmit FIFO is empty */ +#define UNICOMMI2CC_CPU_INT_RIS_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_RIS_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Interrupt occured */ + +/* UNICOMMI2CC_CPU_INT_MIS Bits */ +/* UNICOMMI2CC_CPU_INT_MIS[RXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Receive Data Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_RXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[TIMEOUTA] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTA_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[NACK] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_NACK_OFS (7) /* !< NACK Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_NACK_MASK ((uint32_t)0x00000080U) /* !< Address/Data NACK Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_NACK_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_NACK_SET ((uint32_t)0x00000080U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[START] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_START_OFS (8) /* !< START Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_START_MASK ((uint32_t)0x00000100U) /* !< START Detection Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_START_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_START_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[STOP] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_STOP_OFS (9) /* !< STOP Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_STOP_MASK ((uint32_t)0x00000200U) /* !< STOP Detection Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_STOP_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_STOP_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[ARBLOST] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_ARBLOST_OFS (10) /* !< ARBLOST Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_ARBLOST_MASK ((uint32_t)0x00000400U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_ARBLOST_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_ARBLOST_SET ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[TXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmit Transaction completed + Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_TXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[RXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CC_CPU_INT_MIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_MIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[TXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_CPU_INT_MIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_MIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[DMA_DONE_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[DMA_DONE_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_MIS[PEC_RX_ERR] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< RX Pec Error Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_PEC_RX_ERR_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt mask */ +#define UNICOMMI2CC_CPU_INT_MIS_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Set interrupt mask */ +/* UNICOMMI2CC_CPU_INT_MIS[TIMEOUTB] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTB_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt mask */ +#define UNICOMMI2CC_CPU_INT_MIS_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Set interrupt mask */ +/* UNICOMMI2CC_CPU_INT_MIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Masked DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* UNICOMMI2CC_CPU_INT_MIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Masked DMA Done PREIRQ on TX Event + Channel Interrupt */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ +/* UNICOMMI2CC_CPU_INT_MIS[RXFULL] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_RXFULL_MASK ((uint32_t)0x00000010U) /* !< Masked RXFIFO full event */ +#define UNICOMMI2CC_CPU_INT_MIS_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_RXFULL_SET ((uint32_t)0x00000010U) /* !< Interrupt occured */ +/* UNICOMMI2CC_CPU_INT_MIS[TXEMPTY] Bits */ +#define UNICOMMI2CC_CPU_INT_MIS_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CC_CPU_INT_MIS_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty masked + interrupt. This interrupt is set if + all data in the Transmit FIFO have + been shifted out and the transmit + goes into idle mode. */ +#define UNICOMMI2CC_CPU_INT_MIS_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CC_CPU_INT_MIS_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Interrupt occured */ + +/* UNICOMMI2CC_CPU_INT_ISET Bits */ +/* UNICOMMI2CC_CPU_INT_ISET[RXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Receive Data Interrupt Signals that + a byte has been received */ +#define UNICOMMI2CC_CPU_INT_ISET_RXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[TIMEOUTA] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTA_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[NACK] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_NACK_OFS (7) /* !< NACK Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_NACK_MASK ((uint32_t)0x00000080U) /* !< Address/Data NACK Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_NACK_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_NACK_SET ((uint32_t)0x00000080U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[START] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_START_OFS (8) /* !< START Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_START_MASK ((uint32_t)0x00000100U) /* !< START Detection Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_START_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_START_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[STOP] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_STOP_OFS (9) /* !< STOP Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_STOP_MASK ((uint32_t)0x00000200U) /* !< STOP Detection Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_STOP_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[ARBLOST] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_ARBLOST_OFS (10) /* !< ARBLOST Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_ARBLOST_MASK ((uint32_t)0x00000400U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_ARBLOST_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_ARBLOST_SET ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[TXDONE] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmit Transaction completed + Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_TXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[RXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CC_CPU_INT_ISET_RXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_ISET_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[TXTRG] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CC_CPU_INT_ISET_TXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_CPU_INT_ISET_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[DMA_DONE_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[DMA_DONE_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_CPU_INT_ISET[PEC_RX_ERR] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< RX Pec Error Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_PEC_RX_ERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Set interrupt */ +/* UNICOMMI2CC_CPU_INT_ISET[TIMEOUTB] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTB_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Set interrupt */ +/* UNICOMMI2CC_CPU_INT_ISET[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Set DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt */ +/* UNICOMMI2CC_CPU_INT_ISET[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Set DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_CPU_INT_ISET_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt */ +/* UNICOMMI2CC_CPU_INT_ISET[RXFULL] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. */ +#define UNICOMMI2CC_CPU_INT_ISET_RXFULL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_RXFULL_SET ((uint32_t)0x00000010U) /* !< Set Interrupt */ +/* UNICOMMI2CC_CPU_INT_ISET[TXEMPTY] Bits */ +#define UNICOMMI2CC_CPU_INT_ISET_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CC_CPU_INT_ISET_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty interrupt mask. + This interrupt is set if all data in + the Transmit FIFO have been shifted + out and the transmit goes into idle + mode. */ +#define UNICOMMI2CC_CPU_INT_ISET_TXEMPTY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_CPU_INT_ISET_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Set Interrupt */ + +/* UNICOMMI2CC_ICLR Bits */ +/* UNICOMMI2CC_ICLR[RXDONE] Bits */ +#define UNICOMMI2CC_ICLR_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CC_ICLR_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Receive Data Interrupt Signals that + a byte has been received */ +#define UNICOMMI2CC_ICLR_RXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_RXDONE_CLR ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[TIMEOUTA] Bits */ +#define UNICOMMI2CC_ICLR_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CC_ICLR_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A interrupt */ +#define UNICOMMI2CC_ICLR_TIMEOUTA_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_TIMEOUTA_CLR ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[NACK] Bits */ +#define UNICOMMI2CC_ICLR_NACK_OFS (7) /* !< NACK Offset */ +#define UNICOMMI2CC_ICLR_NACK_MASK ((uint32_t)0x00000080U) /* !< Address/Data NACK Interrupt */ +#define UNICOMMI2CC_ICLR_NACK_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_NACK_CLR ((uint32_t)0x00000080U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[START] Bits */ +#define UNICOMMI2CC_ICLR_START_OFS (8) /* !< START Offset */ +#define UNICOMMI2CC_ICLR_START_MASK ((uint32_t)0x00000100U) /* !< START Detection Interrupt */ +#define UNICOMMI2CC_ICLR_START_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_START_CLR ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[STOP] Bits */ +#define UNICOMMI2CC_ICLR_STOP_OFS (9) /* !< STOP Offset */ +#define UNICOMMI2CC_ICLR_STOP_MASK ((uint32_t)0x00000200U) /* !< STOP Detection Interrupt */ +#define UNICOMMI2CC_ICLR_STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_STOP_CLR ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[ARBLOST] Bits */ +#define UNICOMMI2CC_ICLR_ARBLOST_OFS (10) /* !< ARBLOST Offset */ +#define UNICOMMI2CC_ICLR_ARBLOST_MASK ((uint32_t)0x00000400U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CC_ICLR_ARBLOST_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_ARBLOST_CLR ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[TXDONE] Bits */ +#define UNICOMMI2CC_ICLR_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CC_ICLR_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmit Transaction completed + Interrupt */ +#define UNICOMMI2CC_ICLR_TXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_TXDONE_CLR ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[RXTRG] Bits */ +#define UNICOMMI2CC_ICLR_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CC_ICLR_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CC_ICLR_RXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_ICLR_RXTRG_CLR ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[TXTRG] Bits */ +#define UNICOMMI2CC_ICLR_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CC_ICLR_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit FIFO Trigger */ +#define UNICOMMI2CC_ICLR_TXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CC_ICLR_TXTRG_CLR ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[DMA_DONE_TX] Bits */ +#define UNICOMMI2CC_ICLR_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CC_ICLR_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CC_ICLR_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_ICLR_DMA_DONE_TX_CLR ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[DMA_DONE_RX] Bits */ +#define UNICOMMI2CC_ICLR_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CC_ICLR_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CC_ICLR_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_ICLR_DMA_DONE_RX_CLR ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CC_ICLR[PEC_RX_ERR] Bits */ +#define UNICOMMI2CC_ICLR_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CC_ICLR_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< RX Pec Error Interrupt */ +#define UNICOMMI2CC_ICLR_PEC_RX_ERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_PEC_RX_ERR_CLR ((uint32_t)0x00000800U) /* !< Clear Interrupt */ +/* UNICOMMI2CC_ICLR[TIMEOUTB] Bits */ +#define UNICOMMI2CC_ICLR_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CC_ICLR_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CC_ICLR_TIMEOUTB_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_TIMEOUTB_CLR ((uint32_t)0x00002000U) /* !< Clear Interrupt */ +/* UNICOMMI2CC_ICLR[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Clear DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_RX_CLR ((uint32_t)0x00040000U) /* !< Clear Interrupt */ +/* UNICOMMI2CC_ICLR[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Clear DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CC_ICLR_DMA_PREIRQ_TX_CLR ((uint32_t)0x00080000U) /* !< Clear Interrupt */ +/* UNICOMMI2CC_ICLR[RXFULL] Bits */ +#define UNICOMMI2CC_ICLR_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CC_ICLR_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. */ +#define UNICOMMI2CC_ICLR_RXFULL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_RXFULL_CLR ((uint32_t)0x00000010U) /* !< Clear Interrupt */ +/* UNICOMMI2CC_ICLR[TXEMPTY] Bits */ +#define UNICOMMI2CC_ICLR_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CC_ICLR_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty interrupt mask. + This interrupt is set if all data in + the Transmit FIFO have been shifted + out and the transmit goes into idle + mode. */ +#define UNICOMMI2CC_ICLR_TXEMPTY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CC_ICLR_TXEMPTY_CLR ((uint32_t)0x00000020U) /* !< Clear Interrupt */ + +/* UNICOMMI2CC_CLKDIV Bits */ +/* UNICOMMI2CC_CLKDIV[RATIO] Bits */ +#define UNICOMMI2CC_CLKDIV_RATIO_OFS (0) /* !< RATIO Offset */ +#define UNICOMMI2CC_CLKDIV_RATIO_MASK ((uint32_t)0x0000003FU) /* !< Selects divide ratio of module + clock Division factor 0 : DIV_BY_1 + 1 : DIV_BY_2 .... 63: DIV_BY_64 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_1 ((uint32_t)0x00000000U) /* !< Do not divide clock source */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_2 ((uint32_t)0x00000001U) /* !< Divide clock source by 2 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_3 ((uint32_t)0x00000002U) /* !< Divide clock source by 3 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_4 ((uint32_t)0x00000003U) /* !< Divide clock source by 4 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_5 ((uint32_t)0x00000004U) /* !< Divide clock source by 5 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_6 ((uint32_t)0x00000005U) /* !< Divide clock source by 6 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_7 ((uint32_t)0x00000006U) /* !< Divide clock source by 7 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_8 ((uint32_t)0x00000007U) /* !< Divide clock source by 8 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_61 ((uint32_t)0x0000003CU) /* !< Divide clock source by 8 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_62 ((uint32_t)0x0000003DU) /* !< Divide clock source by 8 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_63 ((uint32_t)0x0000003EU) /* !< Divide clock source by 8 */ +#define UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_64 ((uint32_t)0x0000003FU) /* !< Divide clock source by 8 */ + +/* UNICOMMI2CC_CLKSEL Bits */ +/* UNICOMMI2CC_CLKSEL[MFCLK_SEL] Bits */ +#define UNICOMMI2CC_CLKSEL_MFCLK_SEL_OFS (2) /* !< MFCLK_SEL Offset */ +#define UNICOMMI2CC_CLKSEL_MFCLK_SEL_MASK ((uint32_t)0x00000004U) /* !< Selects MFCLK as clock source if + enabled */ +#define UNICOMMI2CC_CLKSEL_MFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CC_CLKSEL_MFCLK_SEL_ENABLE ((uint32_t)0x00000004U) /* !< Select this clock as a source */ +/* UNICOMMI2CC_CLKSEL[BUSCLK_SEL] Bits */ +#define UNICOMMI2CC_CLKSEL_BUSCLK_SEL_OFS (3) /* !< BUSCLK_SEL Offset */ +#define UNICOMMI2CC_CLKSEL_BUSCLK_SEL_MASK ((uint32_t)0x00000008U) /* !< Selects BUS CLK as clock source if + enabled */ +#define UNICOMMI2CC_CLKSEL_BUSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CC_CLKSEL_BUSCLK_SEL_ENABLE ((uint32_t)0x00000008U) /* !< Select this clock as a source */ +/* UNICOMMI2CC_CLKSEL[ASYNC_SYSCLK_SEL] Bits */ +#define UNICOMMI2CC_CLKSEL_ASYNC_SYSCLK_SEL_OFS (9) /* !< ASYNC_SYSCLK_SEL Offset */ +#define UNICOMMI2CC_CLKSEL_ASYNC_SYSCLK_SEL_MASK ((uint32_t)0x00000200U) /* !< Asynchronous sysclk selected as + source */ +#define UNICOMMI2CC_CLKSEL_ASYNC_SYSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CC_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE ((uint32_t)0x00000200U) /* !< Select this clock as a source */ +/* UNICOMMI2CC_CLKSEL[ASYNC_HFCLK_SEL] Bits */ +#define UNICOMMI2CC_CLKSEL_ASYNC_HFCLK_SEL_OFS (10) /* !< ASYNC_HFCLK_SEL Offset */ +#define UNICOMMI2CC_CLKSEL_ASYNC_HFCLK_SEL_MASK ((uint32_t)0x00000400U) /* !< Asynchronous HFCLK selected as + source */ +#define UNICOMMI2CC_CLKSEL_ASYNC_HFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CC_CLKSEL_ASYNC_HFCLK_SEL_ENABLE ((uint32_t)0x00000400U) /* !< Select this clock as a source */ +/* UNICOMMI2CC_CLKSEL[ASYNC_PLL_SEL] Bits */ +#define UNICOMMI2CC_CLKSEL_ASYNC_PLL_SEL_OFS (11) /* !< ASYNC_PLL_SEL Offset */ +#define UNICOMMI2CC_CLKSEL_ASYNC_PLL_SEL_MASK ((uint32_t)0x00000800U) /* !< Asynchronous PLL selected as source */ +#define UNICOMMI2CC_CLKSEL_ASYNC_PLL_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CC_CLKSEL_ASYNC_PLL_SEL_ENABLE ((uint32_t)0x00000800U) /* !< Select this clock as a source */ + +/* UNICOMMI2CC_PDBGCTL Bits */ +/* UNICOMMI2CC_PDBGCTL[FREE] Bits */ +#define UNICOMMI2CC_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */ +#define UNICOMMI2CC_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */ +#define UNICOMMI2CC_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes + functionality while the Core Halted + input is asserted and resumes when it + is deasserted. */ +#define UNICOMMI2CC_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of + the Core Halted input */ +/* UNICOMMI2CC_PDBGCTL[SOFT] Bits */ +#define UNICOMMI2CC_PDBGCTL_SOFT_OFS (1) /* !< SOFT Offset */ +#define UNICOMMI2CC_PDBGCTL_SOFT_MASK ((uint32_t)0x00000002U) /* !< Soft halt boundary control. This + function is only available, if [FREE] + is set to 'STOP' */ +#define UNICOMMI2CC_PDBGCTL_SOFT_DEPRECATED ((uint32_t)0x00000000U) /* !< Not supported */ +#define UNICOMMI2CC_PDBGCTL_SOFT_DELAYED ((uint32_t)0x00000002U) /* !< The peripheral blocks the debug + freeze until it has reached a + boundary where it can resume without + corruption */ + +/* UNICOMMI2CC_INTCTL Bits */ +/* UNICOMMI2CC_INTCTL[INTEVAL] Bits */ +#define UNICOMMI2CC_INTCTL_INTEVAL_OFS (0) /* !< INTEVAL Offset */ +#define UNICOMMI2CC_INTCTL_INTEVAL_MASK ((uint32_t)0x00000001U) /* !< Writing a 1 to this field + re-evaluates the interrupt sources. */ +#define UNICOMMI2CC_INTCTL_INTEVAL_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define UNICOMMI2CC_INTCTL_INTEVAL_EVAL ((uint32_t)0x00000001U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ + +/* UNICOMMI2CC_CTR Bits */ +/* UNICOMMI2CC_CTR[FRM_START] Bits */ +#define UNICOMMI2CC_CTR_FRM_START_OFS (0) /* !< FRM_START Offset */ +#define UNICOMMI2CC_CTR_FRM_START_MASK ((uint32_t)0x00000001U) /* !< Start Transfer */ +#define UNICOMMI2CC_CTR_FRM_START_DISABLE ((uint32_t)0x00000000U) /* !< In standard mode, this encoding + means the Controller is unable to + transmit or receive data. */ +#define UNICOMMI2CC_CTR_FRM_START_ENABLE ((uint32_t)0x00000001U) /* !< The Controller is able to transmit + or receive data. See field decoding + in Table: MCTR Field decoding. */ +/* UNICOMMI2CC_CTR[START] Bits */ +#define UNICOMMI2CC_CTR_START_OFS (1) /* !< START Offset */ +#define UNICOMMI2CC_CTR_START_MASK ((uint32_t)0x00000002U) /* !< Generate START */ +#define UNICOMMI2CC_CTR_START_DISABLE ((uint32_t)0x00000000U) /* !< The controller does not generate + the START condition. */ +#define UNICOMMI2CC_CTR_START_ENABLE ((uint32_t)0x00000002U) /* !< The controller generates the START + or repeated START condition. See + field decoding in Table: MCTR Field + decoding. */ +/* UNICOMMI2CC_CTR[STOP] Bits */ +#define UNICOMMI2CC_CTR_STOP_OFS (2) /* !< STOP Offset */ +#define UNICOMMI2CC_CTR_STOP_MASK ((uint32_t)0x00000004U) /* !< Generate STOP */ +#define UNICOMMI2CC_CTR_STOP_DISABLE ((uint32_t)0x00000000U) /* !< The controller does not generate + the STOP condition. */ +#define UNICOMMI2CC_CTR_STOP_ENABLE ((uint32_t)0x00000004U) /* !< The controller generates the STOP + condition. See field decoding in + Table: MCTR Field decoding. */ +/* UNICOMMI2CC_CTR[ACK] Bits */ +#define UNICOMMI2CC_CTR_ACK_OFS (3) /* !< ACK Offset */ +#define UNICOMMI2CC_CTR_ACK_MASK ((uint32_t)0x00000008U) /* !< Data Acknowledge Enable. Software + needs to configure this bit to send + the ACK or NACK. See field decoding + in Table: MCTR Field decoding. */ +#define UNICOMMI2CC_CTR_ACK_DISABLE ((uint32_t)0x00000000U) /* !< The last received data byte of a + transaction is not acknowledged + automatically . */ +#define UNICOMMI2CC_CTR_ACK_ENABLE ((uint32_t)0x00000008U) /* !< The last received data byte of a + transaction is acknowledged + automatically . */ +/* UNICOMMI2CC_CTR[BLEN] Bits */ +#define UNICOMMI2CC_CTR_BLEN_OFS (16) /* !< BLEN Offset */ +#define UNICOMMI2CC_CTR_BLEN_MASK ((uint32_t)0x0FFF0000U) /* !< I2C transaction length This field + contains the programmed length of + bytes of the Transaction. */ +#define UNICOMMI2CC_CTR_BLEN_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_CTR_BLEN_MAXIMUM ((uint32_t)0x0FFF0000U) /* !< Highest possible value */ +/* UNICOMMI2CC_CTR[ACKOEN] Bits */ +#define UNICOMMI2CC_CTR_ACKOEN_OFS (4) /* !< ACKOEN Offset */ +#define UNICOMMI2CC_CTR_ACKOEN_MASK ((uint32_t)0x00000010U) /* !< ACK overrride Enable */ +#define UNICOMMI2CC_CTR_ACKOEN_DISABLE ((uint32_t)0x00000000U) /* !< No special behavior */ +#define UNICOMMI2CC_CTR_ACKOEN_ENABLE ((uint32_t)0x00000010U) /* !< When 1 and the Controller is + receiving data and the number of + bytes indicated in MBLEN have been + received, the state machine will + generate an rxdone interrupt and wait + at the start of the ACK for FW to + indicate if an ACK or NACK should be + sent. The ACK or NACK is selected by + writing the MCTR register and setting + ACK accordingly. The other fields in + this register can also be written at + this time to continue on with the + transaction. If a NACK is sent the + state machine will automatically send + a Stop. */ +/* UNICOMMI2CC_CTR[RD_ON_TXEMPTY] Bits */ +#define UNICOMMI2CC_CTR_RD_ON_TXEMPTY_OFS (5) /* !< RD_ON_TXEMPTY Offset */ +#define UNICOMMI2CC_CTR_RD_ON_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Read on TX Empty */ +#define UNICOMMI2CC_CTR_RD_ON_TXEMPTY_DISABLE ((uint32_t)0x00000000U) /* !< No special behavior */ +#define UNICOMMI2CC_CTR_RD_ON_TXEMPTY_ENABLE ((uint32_t)0x00000020U) /* !< When 1 the Controller will transmit + all bytes from the TX FIFO before + continuing with the programmed Burst + Run Read. If the DIR is not set to + Read in the MSA then this bit is + ignored. The Start must be set in the + MCTR for proper I2C protocol. The + Controller will first send the Start + Condition, I2C Address with R/W bit + set to write, before sending the + bytes in the TX FIFO. When the TX + FIFO is empty, the I2C transaction + will continue as programmed in MTCR + and MSA without sending a Stop + Condition. This is intended to be + used to perform simple I2C command + based reads transition that will + complete after initiating them + without having to get an interrupt to + turn the bus around. */ +/* UNICOMMI2CC_CTR[SUSPEND] Bits */ +#define UNICOMMI2CC_CTR_SUSPEND_OFS (6) /* !< SUSPEND Offset */ +#define UNICOMMI2CC_CTR_SUSPEND_MASK ((uint32_t)0x00000040U) /* !< Suspend external communication */ +#define UNICOMMI2CC_CTR_SUSPEND_DISABLE ((uint32_t)0x00000000U) /* !< Functional mode resumed */ +#define UNICOMMI2CC_CTR_SUSPEND_ENABLE ((uint32_t)0x00000040U) /* !< External communication suspended */ + +/* UNICOMMI2CC_CR Bits */ +/* UNICOMMI2CC_CR[MCTL] Bits */ +#define UNICOMMI2CC_CR_MCTL_OFS (1) /* !< MCTL Offset */ +#define UNICOMMI2CC_CR_MCTL_MASK ((uint32_t)0x00000002U) /* !< MultiController mode. In + MultiController mode the SCL high + time counts once the SCL line has + been detected high. If this is not + enabled the high time counts as soon + as the SCL line has been set high by + the I2C controller. */ +#define UNICOMMI2CC_CR_MCTL_DISABLE ((uint32_t)0x00000000U) /* !< Disable MultiController mode. */ +#define UNICOMMI2CC_CR_MCTL_ENABLE ((uint32_t)0x00000002U) /* !< Enable MultiController mode. */ +/* UNICOMMI2CC_CR[ENABLE] Bits */ +#define UNICOMMI2CC_CR_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define UNICOMMI2CC_CR_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable module. After this bit has + been set, it should not be set again + unless it has been cleared by writing + a 0 or by a reset, otherwise transfer + failures may occur. */ +#define UNICOMMI2CC_CR_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disables operation. */ +#define UNICOMMI2CC_CR_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enables operation. */ +/* UNICOMMI2CC_CR[CLKSTRETCH] Bits */ +#define UNICOMMI2CC_CR_CLKSTRETCH_OFS (2) /* !< CLKSTRETCH Offset */ +#define UNICOMMI2CC_CR_CLKSTRETCH_MASK ((uint32_t)0x00000004U) /* !< Clock Stretching. This bit controls + the support for clock stretching of + the I2C bus. */ +#define UNICOMMI2CC_CR_CLKSTRETCH_DISABLE ((uint32_t)0x00000000U) /* !< Disables the clock stretching + detection. This can be disabled if no + Target on the bus does support clock + stretching, so that the maximum speed + on the bus can be reached. */ +#define UNICOMMI2CC_CR_CLKSTRETCH_ENABLE ((uint32_t)0x00000004U) /* !< Enables the clock stretching + detection. Enabling the clock + stretching ensures compliance to the + I2C standard but could limit the + speed due the clock stretching. */ + +/* UNICOMMI2CC_SR Bits */ +/* UNICOMMI2CC_SR[BUSY] Bits */ +#define UNICOMMI2CC_SR_BUSY_OFS (0) /* !< BUSY Offset */ +#define UNICOMMI2CC_SR_BUSY_MASK ((uint32_t)0x00000001U) /* !< FSM Busy The BUSY bit is set during + an ongoing transaction, so is set + during the transmit/receive of the + amount of data set in MBLEN including + START, RESTART, Address and STOP + signal generation when required for + the current transaction. */ +#define UNICOMMI2CC_SR_BUSY_CLEARED ((uint32_t)0x00000000U) /* !< The controller is idle. */ +#define UNICOMMI2CC_SR_BUSY_SET ((uint32_t)0x00000001U) /* !< The controller is busy. */ +/* UNICOMMI2CC_SR[ERR] Bits */ +#define UNICOMMI2CC_SR_ERR_OFS (1) /* !< ERR Offset */ +#define UNICOMMI2CC_SR_ERR_MASK ((uint32_t)0x00000002U) /* !< Error The error can be from the + Target address not being acknowledged + or the transmit data not being + acknowledged. */ +#define UNICOMMI2CC_SR_ERR_CLEARED ((uint32_t)0x00000000U) /* !< No error was detected on the last + operation. */ +#define UNICOMMI2CC_SR_ERR_SET ((uint32_t)0x00000002U) /* !< An error occurred on the last + operation. */ +/* UNICOMMI2CC_SR[ADRACK] Bits */ +#define UNICOMMI2CC_SR_ADRACK_OFS (2) /* !< ADRACK Offset */ +#define UNICOMMI2CC_SR_ADRACK_MASK ((uint32_t)0x00000004U) /* !< Acknowledge Address */ +#define UNICOMMI2CC_SR_ADRACK_CLEARED ((uint32_t)0x00000000U) /* !< The transmitted address was + acknowledged */ +#define UNICOMMI2CC_SR_ADRACK_SET ((uint32_t)0x00000004U) /* !< The transmitted address was not + acknowledged. */ +/* UNICOMMI2CC_SR[DATACK] Bits */ +#define UNICOMMI2CC_SR_DATACK_OFS (3) /* !< DATACK Offset */ +#define UNICOMMI2CC_SR_DATACK_MASK ((uint32_t)0x00000008U) /* !< Acknowledge Data */ +#define UNICOMMI2CC_SR_DATACK_CLEARED ((uint32_t)0x00000000U) /* !< The transmitted data was + acknowledged */ +#define UNICOMMI2CC_SR_DATACK_SET ((uint32_t)0x00000008U) /* !< The transmitted data was not + acknowledged. */ +/* UNICOMMI2CC_SR[ARBLST] Bits */ +#define UNICOMMI2CC_SR_ARBLST_OFS (4) /* !< ARBLST Offset */ +#define UNICOMMI2CC_SR_ARBLST_MASK ((uint32_t)0x00000010U) /* !< Arbitration Lost */ +#define UNICOMMI2CC_SR_ARBLST_CLEARED ((uint32_t)0x00000000U) /* !< The I2C controller won arbitration. */ +#define UNICOMMI2CC_SR_ARBLST_SET ((uint32_t)0x00000010U) /* !< The I2C controller lost + arbitration. */ +/* UNICOMMI2CC_SR[IDLE] Bits */ +#define UNICOMMI2CC_SR_IDLE_OFS (5) /* !< IDLE Offset */ +#define UNICOMMI2CC_SR_IDLE_MASK ((uint32_t)0x00000020U) /* !< I2C Idle */ +#define UNICOMMI2CC_SR_IDLE_CLEARED ((uint32_t)0x00000000U) /* !< The I2C controller is not idle. */ +#define UNICOMMI2CC_SR_IDLE_SET ((uint32_t)0x00000020U) /* !< The I2C controller is idle. */ +/* UNICOMMI2CC_SR[BUSBSY] Bits */ +#define UNICOMMI2CC_SR_BUSBSY_OFS (6) /* !< BUSBSY Offset */ +#define UNICOMMI2CC_SR_BUSBSY_MASK ((uint32_t)0x00000040U) /* !< I2C Bus is Busy Controller State + Machine will wait until this bit to + be cleared before starting a + transaction. When first enabling the + Controller in multi Controller + environments, FW should wait for one + I2C clock period after setting ACTIVE + high before writing to the CTR + register to start the transaction so + that if SCL goes low it will trigger + the BUSBSY. */ +#define UNICOMMI2CC_SR_BUSBSY_CLEARED ((uint32_t)0x00000000U) /* !< The I2C bus is idle. */ +#define UNICOMMI2CC_SR_BUSBSY_SET ((uint32_t)0x00000040U) /* !< 'This Status bit is set on a START + or when SCL goes low. It is cleared + on a STOP, or when a SCL high bus + busy timeout occurs and SCL and SDA + are both high. This status is cleared + when the ACTIVE bit is low. Note + that the Controller State Machine + will wait until this bit is cleared + before starting an I2C transaction. + When first enabling the Controller in + multi Controller environments, FW + should wait for one I2C clock period + after setting ACTIVE high before + writing to the MTCR register to start + the transaction so that if SCL goes + low it will trigger the BUSBSY. */ +/* UNICOMMI2CC_SR[BCNT] Bits */ +#define UNICOMMI2CC_SR_BCNT_OFS (16) /* !< BCNT Offset */ +#define UNICOMMI2CC_SR_BCNT_MASK ((uint32_t)0x0FFF0000U) /* !< Transaction Count This field + contains the current count-down value + of the transaction. */ +#define UNICOMMI2CC_SR_BCNT_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_SR_BCNT_MAXIMUM ((uint32_t)0x0FFF0000U) /* !< Highest possible value */ +/* UNICOMMI2CC_SR[RXCLR] Bits */ +#define UNICOMMI2CC_SR_RXCLR_OFS (9) /* !< RXCLR Offset */ +#define UNICOMMI2CC_SR_RXCLR_MASK ((uint32_t)0x00000200U) /* !< RX FIFO Clear Status */ +#define UNICOMMI2CC_SR_RXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMI2CC_SR_RXCLR_SET ((uint32_t)0x00000200U) /* !< FIFO clear is complete */ +/* UNICOMMI2CC_SR[TXCLR] Bits */ +#define UNICOMMI2CC_SR_TXCLR_OFS (10) /* !< TXCLR Offset */ +#define UNICOMMI2CC_SR_TXCLR_MASK ((uint32_t)0x00000400U) /* !< TX FIFO Clear Status */ +#define UNICOMMI2CC_SR_TXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMI2CC_SR_TXCLR_SET ((uint32_t)0x00000400U) /* !< FIFO clear is complete */ +/* UNICOMMI2CC_SR[RXFE] Bits */ +#define UNICOMMI2CC_SR_RXFE_OFS (11) /* !< RXFE Offset */ +#define UNICOMMI2CC_SR_RXFE_MASK ((uint32_t)0x00000800U) /* !< Receive FIFO Empty The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CC_SR_RXFE_CLEARED ((uint32_t)0x00000000U) /* !< The receiver is not empty. */ +#define UNICOMMI2CC_SR_RXFE_SET ((uint32_t)0x00000800U) /* !< If the FIFO is disabled (FEN is 0), + the receive holding register is + empty. If the FIFO is enabled (FEN is + 1), the receive FIFO is empty. */ +/* UNICOMMI2CC_SR[RXFF] Bits */ +#define UNICOMMI2CC_SR_RXFF_OFS (12) /* !< RXFF Offset */ +#define UNICOMMI2CC_SR_RXFF_MASK ((uint32_t)0x00001000U) /* !< Receive FIFO Full The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CC_SR_RXFF_CLEARED ((uint32_t)0x00000000U) /* !< The receiver can receive data. */ +#define UNICOMMI2CC_SR_RXFF_SET ((uint32_t)0x00001000U) /* !< If the FIFO is disabled (FEN is 0), + the receive holding register is full. + If the FIFO is enabled (FEN is 1), + the receive FIFO is full. */ +/* UNICOMMI2CC_SR[TXFE] Bits */ +#define UNICOMMI2CC_SR_TXFE_OFS (13) /* !< TXFE Offset */ +#define UNICOMMI2CC_SR_TXFE_MASK ((uint32_t)0x00002000U) /* !< Transmit FIFO Empty The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CC_SR_TXFE_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter has data to + transmit. */ +#define UNICOMMI2CC_SR_TXFE_SET ((uint32_t)0x00002000U) /* !< If the FIFO is disabled (FEN is 0), + the transmit holding register is + empty. If the FIFO is enabled (FEN is + 1), the transmit FIFO is empty. */ +/* UNICOMMI2CC_SR[TXFF] Bits */ +#define UNICOMMI2CC_SR_TXFF_OFS (14) /* !< TXFF Offset */ +#define UNICOMMI2CC_SR_TXFF_MASK ((uint32_t)0x00004000U) /* !< Transmit FIFO Full The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CC_SR_TXFF_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter is not full. */ +#define UNICOMMI2CC_SR_TXFF_SET ((uint32_t)0x00004000U) /* !< If the FIFO is disabled (FEN is 0), + the transmit holding register is + full. If the FIFO is enabled (FEN is + 1), the transmit FIFO is full. */ + +/* UNICOMMI2CC_IFLS Bits */ +/* UNICOMMI2CC_IFLS[TXIFLSEL] Bits */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_OFS (0) /* !< TXIFLSEL Offset */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_MASK ((uint32_t)0x00000007U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_LVL_3_4 ((uint32_t)0x00000001U) /* !< TX FIFO <= 3/4 empty */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_LVL_1_2 ((uint32_t)0x00000002U) /* !< TX FIFO <= 1/2 empty (default) */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_LVL_1_4 ((uint32_t)0x00000003U) /* !< TX FIFO <= 1/4 empty */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_LVL_NOT_FULL ((uint32_t)0x00000004U) /* !< Opposite of full */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_LVL_EMPTY ((uint32_t)0x00000005U) /* !< TX FIFO is empty */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000006U) /* !< TX FIFO <= 1 */ +#define UNICOMMI2CC_IFLS_TXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000007U) /* !< TX_FIFO >= (MAX_FIFO_LEN -1) */ +/* UNICOMMI2CC_IFLS[RXIFLSEL] Bits */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_OFS (4) /* !< RXIFLSEL Offset */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_MASK ((uint32_t)0x00000070U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_LVL_1_4 ((uint32_t)0x00000010U) /* !< RX FIFO >= 1/4 full */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_LVL_1_2 ((uint32_t)0x00000020U) /* !< RX FIFO >= 1/2 full (default) */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_LVL_3_4 ((uint32_t)0x00000030U) /* !< RX FIFO >= 3/4 full */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_LVL_NOT_EMPTY ((uint32_t)0x00000040U) /* !< Opposite of empty */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_LVL_FULL ((uint32_t)0x00000050U) /* !< RX FIFO is full */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000060U) /* !< RX_FIFO >= (MAX_FIFO_LEN -1) */ +#define UNICOMMI2CC_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000070U) /* !< RX_FIFO <= 1 */ +/* UNICOMMI2CC_IFLS[TXCLR] Bits */ +#define UNICOMMI2CC_IFLS_TXCLR_OFS (3) /* !< TXCLR Offset */ +#define UNICOMMI2CC_IFLS_TXCLR_MASK ((uint32_t)0x00000008U) /* !< TX FIFO CLEAR. Setting this bit + will clear the TX FIFO contents. */ +#define UNICOMMI2CC_IFLS_TXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMI2CC_IFLS_TXCLR_ENABLE ((uint32_t)0x00000008U) /* !< Enable FIFO Clear */ +/* UNICOMMI2CC_IFLS[RXCLR] Bits */ +#define UNICOMMI2CC_IFLS_RXCLR_OFS (7) /* !< RXCLR Offset */ +#define UNICOMMI2CC_IFLS_RXCLR_MASK ((uint32_t)0x00000080U) /* !< RX FIFO CLEAR. Setting this bit + will clear the RX FIFO contents. */ +#define UNICOMMI2CC_IFLS_RXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMI2CC_IFLS_RXCLR_ENABLE ((uint32_t)0x00000080U) /* !< Enable FIFO Clear */ + +/* UNICOMMI2CC_TPR Bits */ +/* UNICOMMI2CC_TPR[TPR] Bits */ +#define UNICOMMI2CC_TPR_TPR_OFS (0) /* !< TPR Offset */ +#define UNICOMMI2CC_TPR_TPR_MASK ((uint32_t)0x0000007FU) /* !< Timer Period This field is used in + the equation to configure SCL_PERIOD + : SCL_PERIOD = (1 + TPR ) * (SCL_LP + + SCL_HP ) * INT_CLK_PRD where: + SCL_PRD is the SCL line period (I2C + clock). TPR is the Timer Period + register value (range of 1 to 127). + SCL_LP is the SCL Low period (fixed + at 6). SCL_HP is the SCL High + period (fixed at 4). CLK_PRD is the + functional clock period in ns. */ +#define UNICOMMI2CC_TPR_TPR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_TPR_TPR_MAXIMUM ((uint32_t)0x0000007FU) /* !< Highest possible value */ + +/* UNICOMMI2CC_GFCTL Bits */ +/* UNICOMMI2CC_GFCTL[DGFSEL] Bits */ +#define UNICOMMI2CC_GFCTL_DGFSEL_OFS (0) /* !< DGFSEL Offset */ +#define UNICOMMI2CC_GFCTL_DGFSEL_MASK ((uint32_t)0x00000007U) /* !< Glitch Suppression Pulse Width + This field controls the pulse width + select for glitch suppression on the + SCL and SDA lines. The following + values are the glitch suppression + values in terms of functional clocks. + (Core Domain only) */ +#define UNICOMMI2CC_GFCTL_DGFSEL_DISABLED ((uint32_t)0x00000000U) /* !< Bypass */ +#define UNICOMMI2CC_GFCTL_DGFSEL_CLK_1 ((uint32_t)0x00000001U) /* !< 1 clock */ +#define UNICOMMI2CC_GFCTL_DGFSEL_CLK_2 ((uint32_t)0x00000002U) /* !< 2 clocks */ +#define UNICOMMI2CC_GFCTL_DGFSEL_CLK_3 ((uint32_t)0x00000003U) /* !< 3 clocks */ +#define UNICOMMI2CC_GFCTL_DGFSEL_CLK_4 ((uint32_t)0x00000004U) /* !< 4 clocks */ +#define UNICOMMI2CC_GFCTL_DGFSEL_CLK_8 ((uint32_t)0x00000005U) /* !< 8 clocks */ +#define UNICOMMI2CC_GFCTL_DGFSEL_CLK_16 ((uint32_t)0x00000006U) /* !< 16 clocks */ +#define UNICOMMI2CC_GFCTL_DGFSEL_CLK_31 ((uint32_t)0x00000007U) /* !< 31 clocks */ +/* UNICOMMI2CC_GFCTL[AGFEN] Bits */ +#define UNICOMMI2CC_GFCTL_AGFEN_OFS (8) /* !< AGFEN Offset */ +#define UNICOMMI2CC_GFCTL_AGFEN_MASK ((uint32_t)0x00000100U) /* !< Analog Glitch Suppression Enable */ +#define UNICOMMI2CC_GFCTL_AGFEN_DISABLE ((uint32_t)0x00000000U) /* !< Analog Glitch Filter disable */ +#define UNICOMMI2CC_GFCTL_AGFEN_ENABLE ((uint32_t)0x00000100U) /* !< Analog Glitch Filter enable */ + +/* UNICOMMI2CC_BMON Bits */ +/* UNICOMMI2CC_BMON[SCL] Bits */ +#define UNICOMMI2CC_BMON_SCL_OFS (0) /* !< SCL Offset */ +#define UNICOMMI2CC_BMON_SCL_MASK ((uint32_t)0x00000001U) /* !< I2C SCL Status */ +#define UNICOMMI2CC_BMON_SCL_CLEARED ((uint32_t)0x00000000U) /* !< The I2CSCL signal is low. */ +#define UNICOMMI2CC_BMON_SCL_SET ((uint32_t)0x00000001U) /* !< The I2CSCL signal is high. Note: + During and right after reset, the SCL + pin is in GPIO input mode without the + internal pull enabled. For proper I2C + operation, the user should have the + external pull-up resistor in place + before starting any I2C operations. */ +/* UNICOMMI2CC_BMON[SDA] Bits */ +#define UNICOMMI2CC_BMON_SDA_OFS (1) /* !< SDA Offset */ +#define UNICOMMI2CC_BMON_SDA_MASK ((uint32_t)0x00000002U) /* !< I2C SDA Status */ +#define UNICOMMI2CC_BMON_SDA_CLEARED ((uint32_t)0x00000000U) /* !< The I2CSDA signal is low. */ +#define UNICOMMI2CC_BMON_SDA_SET ((uint32_t)0x00000002U) /* !< The I2CSDA signal is high. Note: + During and right after reset, the SDA + pin is in GPIO input mode without the + internal pull enabled. For proper I2C + operation, the user should have the + external pull-up resistor in place + before starting any I2C operations. */ + +/* UNICOMMI2CC_TXDATA Bits */ +/* UNICOMMI2CC_TXDATA[DATA] Bits */ +#define UNICOMMI2CC_TXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMI2CC_TXDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< Transmit Data This byte contains + the data to be transferred during the + next transaction. */ +#define UNICOMMI2CC_TXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_TXDATA_DATA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ + +/* UNICOMMI2CC_RXDATA Bits */ +/* UNICOMMI2CC_RXDATA[DATA] Bits */ +#define UNICOMMI2CC_RXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMI2CC_RXDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< Received Data. This field contains + the last received data. */ +#define UNICOMMI2CC_RXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_RXDATA_DATA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ + +/* UNICOMMI2CC_PECSR Bits */ +/* UNICOMMI2CC_PECSR[PECBYTECNT] Bits */ +#define UNICOMMI2CC_PECSR_PECBYTECNT_OFS (0) /* !< PECBYTECNT Offset */ +#define UNICOMMI2CC_PECSR_PECBYTECNT_MASK ((uint32_t)0x000001FFU) /* !< PEC Byte Count This is the current + PEC Byte Count of the Controller + State Machine. */ +#define UNICOMMI2CC_PECSR_PECBYTECNT_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum Value */ +#define UNICOMMI2CC_PECSR_PECBYTECNT_MAXIMUM ((uint32_t)0x000001FFU) /* !< Maximum Value */ +/* UNICOMMI2CC_PECSR[PECSTS_CHECK] Bits */ +#define UNICOMMI2CC_PECSR_PECSTS_CHECK_OFS (16) /* !< PECSTS_CHECK Offset */ +#define UNICOMMI2CC_PECSR_PECSTS_CHECK_MASK ((uint32_t)0x00010000U) /* !< This status bit indicates if the + PEC was checked in the transaction + that occurred before the last Stop. + Latched on Stop. */ +#define UNICOMMI2CC_PECSR_PECSTS_CHECK_CLEARED ((uint32_t)0x00000000U) /* !< Indicates PEC was not checked in + the transaction that occurred before + the last Stop */ +#define UNICOMMI2CC_PECSR_PECSTS_CHECK_SET ((uint32_t)0x00010000U) /* !< Indicates if the PEC was checked in + the transaction that occurred before + the last Stop */ +/* UNICOMMI2CC_PECSR[PECSTS_ERROR] Bits */ +#define UNICOMMI2CC_PECSR_PECSTS_ERROR_OFS (17) /* !< PECSTS_ERROR Offset */ +#define UNICOMMI2CC_PECSR_PECSTS_ERROR_MASK ((uint32_t)0x00020000U) /* !< This status bit indicates if a PEC + check error occurred in the + transaction that occurred before the + last Stop. Latched on Stop. */ +#define UNICOMMI2CC_PECSR_PECSTS_ERROR_CLEARED ((uint32_t)0x00000000U) /* !< Indicates PEC check error did not + occurr in the transaction that + occurred before the last Stop */ +#define UNICOMMI2CC_PECSR_PECSTS_ERROR_SET ((uint32_t)0x00020000U) /* !< Indicates if a PEC check error + occurred in the transaction that + occurred before the last Stop */ + +/* UNICOMMI2CC_TA Bits */ +/* UNICOMMI2CC_TA[DIR] Bits */ +#define UNICOMMI2CC_TA_DIR_OFS (0) /* !< DIR Offset */ +#define UNICOMMI2CC_TA_DIR_MASK ((uint32_t)0x00000001U) /* !< Receive/Send The DIR bit specifies + if the next operation is a Receive + (High) or Transmit (Low). 0h = + Transmit 1h = Receive */ +#define UNICOMMI2CC_TA_DIR_TRANSMIT ((uint32_t)0x00000000U) /* !< in transmit mode. */ +#define UNICOMMI2CC_TA_DIR_RECEIVE ((uint32_t)0x00000001U) /* !< is in receive mode. */ +/* UNICOMMI2CC_TA[ADDR] Bits */ +#define UNICOMMI2CC_TA_ADDR_OFS (1) /* !< ADDR Offset */ +#define UNICOMMI2CC_TA_ADDR_MASK ((uint32_t)0x000007FEU) /* !< I2C Target Address This field + specifies bits A9 through A0 of the + Target address. In 7-bit addressing + mode as selected by MSA.MODE bit, the + top 3 bits are don't care */ +#define UNICOMMI2CC_TA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CC_TA_ADDR_MAXIMUM ((uint32_t)0x000007FEU) /* !< Highest possible value */ +/* UNICOMMI2CC_TA[MODE] Bits */ +#define UNICOMMI2CC_TA_MODE_OFS (15) /* !< MODE Offset */ +#define UNICOMMI2CC_TA_MODE_MASK ((uint32_t)0x00008000U) /* !< This bit selects the adressing mode + to be used When 0, 7-bit addressing + is used. When 1, 10-bit addressing is + used. */ +#define UNICOMMI2CC_TA_MODE_MODE7 ((uint32_t)0x00000000U) /* !< 7-bit addressing mode */ +#define UNICOMMI2CC_TA_MODE_MODE10 ((uint32_t)0x00008000U) /* !< 10-bit addressing mode */ + +/* UNICOMMI2CC_TIMEOUT_CNT Bits */ +/* UNICOMMI2CC_TIMEOUT_CNT[TCNTA] Bits */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTA_OFS (0) /* !< TCNTA Offset */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTA_MASK ((uint32_t)0x000000FFU) /* !< Timeout Count A Current Count: This + field contains the upper 8 bits of a + 12-bit current counter for timeout + counter A */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest Value */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ +/* UNICOMMI2CC_TIMEOUT_CNT[TCNTB] Bits */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTB_OFS (16) /* !< TCNTB Offset */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTB_MASK ((uint32_t)0x00FF0000U) /* !< Timeout Count B Current Count: This + field contains the upper 8 bits of a + 12-bit current counter for timeout + counter B */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTB_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest Value */ +#define UNICOMMI2CC_TIMEOUT_CNT_TCNTB_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */ + +/* UNICOMMI2CC_TIMEOUT_CTL Bits */ +/* UNICOMMI2CC_TIMEOUT_CTL[TCNTLA] Bits */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLA_OFS (0) /* !< TCNTLA Offset */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLA_MASK ((uint32_t)0x000000FFU) /* !< Timeout counter A load value + Counter A is used for SCL low + detection. This field contains the + upper 8 bits of a 12-bit pre-load + value for the Timeout A count. NOTE: + The value of CNTLA must be greater + than 1h. Each count is equal to 520 + times the timeout period of + functional clock. For example, with + 8MHz functional clock and a 100KHz + operating I2C clock, one timeout + period will be equal to (1 / 8MHz) * + 520 or 65 us. */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest Value */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ +/* UNICOMMI2CC_TIMEOUT_CTL[TCNTAEN] Bits */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_OFS (15) /* !< TCNTAEN Offset */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_MASK ((uint32_t)0x00008000U) /* !< Timeout Counter A Enable */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable Timeout Counter B */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_ENABLE ((uint32_t)0x00008000U) /* !< Enable Timeout Counter B */ +/* UNICOMMI2CC_TIMEOUT_CTL[TCNTLB] Bits */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_OFS (16) /* !< TCNTLB Offset */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_MASK ((uint32_t)0x00FF0000U) /* !< Timeout Count B Load: Counter B is + used for SCL High Detection. This + field contains the upper 8 bits of a + 12-bit pre-load value for the Timeout + B count. NOTE: The value of CNTLB + must be greater than 1h. Each count + is equal to 1* clock period. For + example, with 10MHz functional clock + one timeout period will be equal + to1*100ns. */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest possible value */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */ +/* UNICOMMI2CC_TIMEOUT_CTL[TCNTBEN] Bits */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_OFS (31) /* !< TCNTBEN Offset */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_MASK ((uint32_t)0x80000000U) /* !< Timeout Counter B Enable */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable Timeout Counter B */ +#define UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_ENABLE ((uint32_t)0x80000000U) /* !< Enable Timeout Counter B */ + +/* UNICOMMI2CC_PECCTL Bits */ +/* UNICOMMI2CC_PECCTL[PECCNT] Bits */ +#define UNICOMMI2CC_PECCTL_PECCNT_OFS (0) /* !< PECCNT Offset */ +#define UNICOMMI2CC_PECCTL_PECCNT_MASK ((uint32_t)0x000001FFU) /* !< PEC Count When this field is non + zero, the number of I2C bytes are + counted (Note that although the PEC + is calculated on the I2C address it + is not counted at a byte). When the + byte count = PECCNT and the state + machine is transmitting, the contents + of the LSFR is loaded into the shift + register instead of the byte received + from the Tx FIFO. When the state + machine is receiving, after the last + bit of this byte is received the LSFR + is checked and if it is non-zero, a + PEC RX Error interrupt is generated. + The I2C packet must be padded to + include the PEC byte for both + transmit and receive. In transmit + mode the FIFO must be loaded with a + dummy PEC byte. In receive mode the + PEC byte will be passed to the Rx + FIFO. In the normal Controller use + case, FW would set PECEN=1 and + PECCNT=SMB packet length (Not + including Target Address byte, but + including the PEC byte). FW would + then configure DMA to allow the + packet to complete unassisted and + write MCTR to initiate the + transaction. Note that when the byte + count = PEC CNT, the byte count is + reset to 0 and multiple PEC + calculation can automatically occur + within a single I2C transaction. + Note that any write to the I2PECCTL + Register will clear the current PEC + Byte Count in the State Machine. */ +#define UNICOMMI2CC_PECCTL_PECCNT_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum Value */ +#define UNICOMMI2CC_PECCTL_PECCNT_MAXIMUM ((uint32_t)0x000001FFU) /* !< Maximum Value */ +/* UNICOMMI2CC_PECCTL[PECEN] Bits */ +#define UNICOMMI2CC_PECCTL_PECEN_OFS (12) /* !< PECEN Offset */ +#define UNICOMMI2CC_PECCTL_PECEN_MASK ((uint32_t)0x00001000U) /* !< PEC Enable This bit enables the SMB + Packet Error Checking (PEC). When + enabled the PEC is calculated on all + bits except the Start, Stop, Ack and + Nack. The PEC LSFR and the Byte + Counter is set to 0 when the State + Machine is in the IDLE state, which + occur following a Stop or when a + timeout occurs. The Counter is also + set to 0 after the PEC byte is sent + or received. Note that the NACK is + automatically send following a PEC + byte that results in a PEC error. The + PEC Polynomial is x^8 + x^2 + x^1 + + 1. */ +#define UNICOMMI2CC_PECCTL_PECEN_DISABLE ((uint32_t)0x00000000U) /* !< PEC is disabled */ +#define UNICOMMI2CC_PECCTL_PECEN_ENABLE ((uint32_t)0x00001000U) /* !< PEC is enabled */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_unicommi2cc__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_unicommi2ct.h b/mspm0/source/ti/devices/msp/peripherals/hw_unicommi2ct.h new file mode 100644 index 0000000..053d555 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_unicommi2ct.h @@ -0,0 +1,1745 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_unicommi2ct__include +#define ti_devices_msp_peripherals_hw_unicommi2ct__include + +/* Filename: hw_unicommi2ct.h */ +/* Revised: 2024-07-26 01:47:37 */ +/* Revision: 7272f6b6a2f4592ada400278814de80dfb9c70f1 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* UNICOMMI2CT Registers +******************************************************************************/ +#define UNICOMMI2CT_SPGDMA_OFS ((uint32_t)0x000010B0U) +#define UNICOMMI2CT_DMA_TRIG0_OFS ((uint32_t)0x00001080U) +#define UNICOMMI2CT_DMA_TRIG1_OFS ((uint32_t)0x00001050U) +#define UNICOMMI2CT_CPU_INT_OFS ((uint32_t)0x00001020U) + + +/** @addtogroup UNICOMMI2CT_SPGDMA + @{ +*/ + +typedef struct { + uint32_t RESERVED0; + __IO uint32_t SPGDMARXCTL; /* !< (@ 0x000010B4) DMA Channel Control */ + __IO uint32_t SPGDMARXDA; /* !< (@ 0x000010B8) DMA Channel Destination Address */ + __IO uint32_t SPGDMARXSZ; /* !< (@ 0x000010BC) DMA Channel Size */ + uint32_t RESERVED1; + __IO uint32_t SPGDMATXCTL; /* !< (@ 0x000010C4) DMA Channel Control */ + __IO uint32_t SPGDMATXSA; /* !< (@ 0x000010C8) DMA Channel Destination Address */ + __IO uint32_t SPGDMATXSZ; /* !< (@ 0x000010CC) DMA Channel Size */ +} UNICOMMI2CT_SPGDMA_Regs; + +/*@}*/ /* end of group UNICOMMI2CT_SPGDMA */ + +/** @addtogroup UNICOMMI2CT_DMA_TRIG0 + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001088) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001090) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001098) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x000010A0) Interrupt set */ +} UNICOMMI2CT_DMA_TRIG0_Regs; + +/*@}*/ /* end of group UNICOMMI2CT_DMA_TRIG0 */ + +/** @addtogroup UNICOMMI2CT_DMA_TRIG1 + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */ +} UNICOMMI2CT_DMA_TRIG1_Regs; + +/*@}*/ /* end of group UNICOMMI2CT_DMA_TRIG1 */ + +/** @addtogroup UNICOMMI2CT_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */ +} UNICOMMI2CT_CPU_INT_Regs; + +/*@}*/ /* end of group UNICOMMI2CT_CPU_INT */ + +/** @addtogroup UNICOMMI2CT + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + __IO uint32_t CLKDIV; /* !< (@ 0x00001000) Clock Divider */ + uint32_t RESERVED1; + __IO uint32_t CLKSEL; /* !< (@ 0x00001008) Clock Select for Ultra Low Power peripherals */ + uint32_t RESERVED2[3]; + __IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */ + uint32_t RESERVED3; + UNICOMMI2CT_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED4; + UNICOMMI2CT_DMA_TRIG1_Regs DMA_TRIG1; /* !< (@ 0x00001050) */ + uint32_t RESERVED5[3]; + UNICOMMI2CT_DMA_TRIG0_Regs DMA_TRIG0; /* !< (@ 0x00001080) */ + uint32_t RESERVED6[3]; + UNICOMMI2CT_SPGDMA_Regs SPGDMA; /* !< (@ 0x000010B0) */ + uint32_t RESERVED7[5]; + __O uint32_t INTCTL; /* !< (@ 0x000010E4) Interrupt control register */ + uint32_t RESERVED8[6]; + __IO uint32_t CTR; /* !< (@ 0x00001100) I2C Target Control Register */ + __IO uint32_t ACKCTL; /* !< (@ 0x00001104) I2C Target ACK Control */ + __I uint32_t SR; /* !< (@ 0x00001108) Status Register */ + __IO uint32_t IFLS; /* !< (@ 0x0000110C) Interrupt FIFO Level Select Register */ + uint32_t RESERVED9[2]; + __IO uint32_t GFCTL; /* !< (@ 0x00001118) I2C Glitch Filter Control */ + uint32_t RESERVED10; + __O uint32_t TTXDATA; /* !< (@ 0x00001120) I2C TXData */ + __I uint32_t RXDATA; /* !< (@ 0x00001124) I2C RXData */ + __I uint32_t PECSR; /* !< (@ 0x00001128) PEC status register */ + uint32_t RESERVED11[7]; + __IO uint32_t OAR2; /* !< (@ 0x00001148) Own Address 2 */ + __IO uint32_t OAR; /* !< (@ 0x0000114C) I2C Own Address */ + __I uint32_t TIMEOUT_CNT; /* !< (@ 0x00001150) I2C Timeout Count Register */ + __IO uint32_t TIMEOUT_CTL; /* !< (@ 0x00001154) I2C Timeout Count Control Register */ + __IO uint32_t PECCTL; /* !< (@ 0x00001158) I2C PEC control register */ +} UNICOMMI2CT_Regs; + +/*@}*/ /* end of group UNICOMMI2CT */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* UNICOMMI2CT Register Control Bits +******************************************************************************/ + +/* UNICOMMI2CT_SPGDMARXCTL Bits */ +/* UNICOMMI2CT_SPGDMARXCTL[DMAEN] Bits */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMI2CT_SPGDMARXCTL[DMAMEMINCR] Bits */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMADSTWDTH) */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMADSTWDTH) */ +/* UNICOMMI2CT_SPGDMARXCTL[DMAPREIRQ] Bits */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMI2CT_SPGDMARXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMI2CT_SPGDMARXCTL[DMATM] Bits */ +#define UNICOMMI2CT_SPGDMARXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMI2CT_SPGDMARXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register */ +#define UNICOMMI2CT_SPGDMARXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMI2CT_SPGDMARXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMI2CT_SPGDMARXCTL[DMADSTWDTH] Bits */ +#define UNICOMMI2CT_SPGDMARXCTL_DMADSTWDTH_OFS (28) /* !< DMADSTWDTH Offset */ +#define UNICOMMI2CT_SPGDMARXCTL_DMADSTWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA destination width. This bit + selects the destination as a byte, + half word, word or long word. */ +#define UNICOMMI2CT_SPGDMARXCTL_DMADSTWDTH_BYTE ((uint32_t)0x00000000U) /* !< Destination data width is BYTE + (8-bit) */ +#define UNICOMMI2CT_SPGDMARXCTL_DMADSTWDTH_HALF ((uint32_t)0x10000000U) /* !< Destination data width is HALF-WORD + (16-bit) */ +#define UNICOMMI2CT_SPGDMARXCTL_DMADSTWDTH_WORD ((uint32_t)0x20000000U) /* !< Destination data width is WORD + (32-bit) */ + +/* UNICOMMI2CT_SPGDMARXDA Bits */ +/* UNICOMMI2CT_SPGDMARXDA[ADDR] Bits */ +#define UNICOMMI2CT_SPGDMARXDA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMI2CT_SPGDMARXDA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMI2CT_SPGDMARXDA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_SPGDMARXDA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CT_SPGDMARXSZ Bits */ +/* UNICOMMI2CT_SPGDMARXSZ[SIZE] Bits */ +#define UNICOMMI2CT_SPGDMARXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMI2CT_SPGDMARXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMI2CT_SPGDMARXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_SPGDMARXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CT_SPGDMATXCTL Bits */ +/* UNICOMMI2CT_SPGDMATXCTL[DMAEN] Bits */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMI2CT_SPGDMATXCTL[DMAMEMINCR] Bits */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMASRCWDTH) */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMASRCWDTH) */ +/* UNICOMMI2CT_SPGDMATXCTL[DMAPREIRQ] Bits */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMI2CT_SPGDMATXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMI2CT_SPGDMATXCTL[DMATM] Bits */ +#define UNICOMMI2CT_SPGDMATXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMI2CT_SPGDMATXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register Note: + The repeat-single (2h) and + repeat-block (3h) transfer are only + available in a FULL-channel + configuration. Please consult the + datasheet of the specific device to + map which channel number has FULL or + BASIC capability. In a BASIC channel + configuration only the values for + single (0h) and block (1h) transfer + can be set. */ +#define UNICOMMI2CT_SPGDMATXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMI2CT_SPGDMATXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMI2CT_SPGDMATXCTL[DMASRCWDTH] Bits */ +#define UNICOMMI2CT_SPGDMATXCTL_DMASRCWDTH_OFS (28) /* !< DMASRCWDTH Offset */ +#define UNICOMMI2CT_SPGDMATXCTL_DMASRCWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA source width. This bit selects + the source data width as a byte, half + word, word or long word. */ +#define UNICOMMI2CT_SPGDMATXCTL_DMASRCWDTH_BYTE ((uint32_t)0x00000000U) /* !< Source data width is BYTE (8-bit) */ +#define UNICOMMI2CT_SPGDMATXCTL_DMASRCWDTH_HALF ((uint32_t)0x10000000U) /* !< Source data width is HALF-WORD + (16-bit) */ +#define UNICOMMI2CT_SPGDMATXCTL_DMASRCWDTH_WORD ((uint32_t)0x20000000U) /* !< Source data width is WORD (32-bit) */ + +/* UNICOMMI2CT_SPGDMATXSA Bits */ +/* UNICOMMI2CT_SPGDMATXSA[ADDR] Bits */ +#define UNICOMMI2CT_SPGDMATXSA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMI2CT_SPGDMATXSA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMI2CT_SPGDMATXSA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_SPGDMATXSA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CT_SPGDMATXSZ Bits */ +/* UNICOMMI2CT_SPGDMATXSZ[SIZE] Bits */ +#define UNICOMMI2CT_SPGDMATXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMI2CT_SPGDMATXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMI2CT_SPGDMATXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_SPGDMATXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMI2CT_DMA_TRIG0_IMASK Bits */ +/* UNICOMMI2CT_DMA_TRIG0_IMASK[TXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG0_IMASK_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG0_IMASK_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_DMA_TRIG0_IMASK_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG0_IMASK_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_DMA_TRIG0_RIS Bits */ +/* UNICOMMI2CT_DMA_TRIG0_RIS[TXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG0_RIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG0_RIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_DMA_TRIG0_RIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG0_RIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_DMA_TRIG0_MIS Bits */ +/* UNICOMMI2CT_DMA_TRIG0_MIS[TXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG0_MIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG0_MIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_DMA_TRIG0_MIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG0_MIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_DMA_TRIG0_ISET Bits */ +/* UNICOMMI2CT_DMA_TRIG0_ISET[TXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG0_ISET_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG0_ISET_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_DMA_TRIG0_ISET_TXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG0_ISET_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_DMA_TRIG1_IMASK Bits */ +/* UNICOMMI2CT_DMA_TRIG1_IMASK[RXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG1_IMASK_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG1_IMASK_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_DMA_TRIG1_IMASK_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG1_IMASK_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_DMA_TRIG1_RIS Bits */ +/* UNICOMMI2CT_DMA_TRIG1_RIS[RXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG1_RIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG1_RIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_DMA_TRIG1_RIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG1_RIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_DMA_TRIG1_MIS Bits */ +/* UNICOMMI2CT_DMA_TRIG1_MIS[RXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG1_MIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG1_MIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_DMA_TRIG1_MIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG1_MIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_DMA_TRIG1_ISET Bits */ +/* UNICOMMI2CT_DMA_TRIG1_ISET[RXTRG] Bits */ +#define UNICOMMI2CT_DMA_TRIG1_ISET_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_DMA_TRIG1_ISET_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_DMA_TRIG1_ISET_RXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_DMA_TRIG1_ISET_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_IIDX Bits */ +/* UNICOMMI2CT_IIDX[STAT] Bits */ +#define UNICOMMI2CT_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define UNICOMMI2CT_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< I2C Module Interrupt Vector Value. + This register provides the highes + priority interrupt index. A read + clears the corresponding interrupt + flag in RIS and MISC. 15h-1Fh = + Reserved */ +#define UNICOMMI2CT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define UNICOMMI2CT_IIDX_STAT_RXDONEFG ((uint32_t)0x00000001U) /* !< Receive Done Flag */ +#define UNICOMMI2CT_IIDX_STAT_TXDONEFG ((uint32_t)0x00000002U) /* !< Transmit Done Flag */ +#define UNICOMMI2CT_IIDX_STAT_RXTRG ((uint32_t)0x00000003U) /* !< receive FIFO Trigger Level */ +#define UNICOMMI2CT_IIDX_STAT_TXTRG ((uint32_t)0x00000004U) /* !< transmit FIFO Trigger level */ +#define UNICOMMI2CT_IIDX_STAT_RXFULL ((uint32_t)0x00000005U) /* !< RX FIFO FULL Event/interrupt + pending */ +#define UNICOMMI2CT_IIDX_STAT_TXEMPTY ((uint32_t)0x00000006U) /* !< Transmit FIFO/Buffer Empty + Event/interrupt pending */ +#define UNICOMMI2CT_IIDX_STAT_TX_UNFL ((uint32_t)0x00000007U) /* !< Target TX FIFO underflow */ +#define UNICOMMI2CT_IIDX_STAT_RX_OVFL ((uint32_t)0x00000008U) /* !< Target RX FIFO overflow event */ +#define UNICOMMI2CT_IIDX_STAT_GENCALL ((uint32_t)0x00000009U) /* !< General Call Event */ +#define UNICOMMI2CT_IIDX_STAT_STARTFG ((uint32_t)0x0000000AU) /* !< Start Event */ +#define UNICOMMI2CT_IIDX_STAT_STOPFG ((uint32_t)0x0000000BU) /* !< Stop Event */ +#define UNICOMMI2CT_IIDX_STAT_PEC_RX_ERR ((uint32_t)0x0000000CU) /* !< PEC receive error event */ +#define UNICOMMI2CT_IIDX_STAT_TIMEOUTA ((uint32_t)0x0000000DU) /* !< Timeout A Event */ +#define UNICOMMI2CT_IIDX_STAT_TIMEOUTB ((uint32_t)0x0000000EU) /* !< Timeout B Event */ +#define UNICOMMI2CT_IIDX_STAT_DMA_DONE_RX ((uint32_t)0x00000010U) /* !< DMA DONE on Channel RX */ +#define UNICOMMI2CT_IIDX_STAT_DMA_DONE_TX ((uint32_t)0x00000011U) /* !< DMA DONE on Channel TX */ +#define UNICOMMI2CT_IIDX_STAT_ARBLOSTFG ((uint32_t)0x00000012U) /* !< Arbitration Lost */ +#define UNICOMMI2CT_IIDX_STAT_DMA_PREIRQ_RX ((uint32_t)0x00000013U) /* !< DMA PRE IRQ INTERRUPT */ +#define UNICOMMI2CT_IIDX_STAT_DMA_PREIRQ_TX ((uint32_t)0x00000014U) /* !< DMA PRE IRQ INTERRUPT */ + +/* UNICOMMI2CT_CPU_INT_IMASK Bits */ +/* UNICOMMI2CT_CPU_INT_IMASK[RXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Receive Data Interrupt Signals that + a byte has been received */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXDONE_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[TXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmit Transaction completed + Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXDONE_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[GENCALL] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_GENCALL_OFS (8) /* !< GENCALL Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_GENCALL_MASK ((uint32_t)0x00000100U) /* !< General Call Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_GENCALL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_GENCALL_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[RXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[TXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[START] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_START_OFS (9) /* !< START Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_START_MASK ((uint32_t)0x00000200U) /* !< Start Condition Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_START_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_START_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[STOP] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_STOP_OFS (10) /* !< STOP Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_STOP_MASK ((uint32_t)0x00000400U) /* !< Stop Condition Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_STOP_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_STOP_SET ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[DMA_DONE_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[DMA_DONE_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[PEC_RX_ERR] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< RX Pec Error Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_PEC_RX_ERR_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[TIMEOUTA] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTA_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[TIMEOUTB] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTB_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Enable DMA Done PREIRQ RX interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Enable DMA Done PREIRQ TX interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_CPU_INT_IMASK_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[RXFULL] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. This interrupt + is set if an Target RX FIFO is full. */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_RXFULL_SET ((uint32_t)0x00000010U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[TXEMPTY] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Target Transmit FIFO Empty + interrupt mask. This interrupt is set + if all data in the Transmit FIFO have + been shifted out and the transmit + goes into idle mode. */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[TX_UNFL] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_TX_UNFL_OFS (6) /* !< TX_UNFL Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_TX_UNFL_MASK ((uint32_t)0x00000040U) /* !< Target TX FIFO underflow */ +#define UNICOMMI2CT_CPU_INT_IMASK_TX_UNFL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_TX_UNFL_SET ((uint32_t)0x00000040U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[RX_OVFL] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_RX_OVFL_OFS (7) /* !< RX_OVFL Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_RX_OVFL_MASK ((uint32_t)0x00000080U) /* !< Target RX FIFO overflow */ +#define UNICOMMI2CT_CPU_INT_IMASK_RX_OVFL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_RX_OVFL_SET ((uint32_t)0x00000080U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_IMASK[ARBLOST] Bits */ +#define UNICOMMI2CT_CPU_INT_IMASK_ARBLOST_OFS (17) /* !< ARBLOST Offset */ +#define UNICOMMI2CT_CPU_INT_IMASK_ARBLOST_MASK ((uint32_t)0x00020000U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CT_CPU_INT_IMASK_ARBLOST_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_IMASK_ARBLOST_SET ((uint32_t)0x00020000U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_CPU_INT_RIS Bits */ +/* UNICOMMI2CT_CPU_INT_RIS[RXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Receive Done Interrupt: Set after a + byte is received */ +#define UNICOMMI2CT_CPU_INT_RIS_RXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_RIS[TXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmission Done Interrupt: Set + after a byte is transmitted */ +#define UNICOMMI2CT_CPU_INT_RIS_TXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_RIS[GENCALL] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_GENCALL_OFS (8) /* !< GENCALL Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_GENCALL_MASK ((uint32_t)0x00000100U) /* !< General Call Interrupt: set when a + general call is received */ +#define UNICOMMI2CT_CPU_INT_RIS_GENCALL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_RIS_GENCALL_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_RIS[RXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger When FIFO + is present, triggered as per IFLS + settings when FIFO is not + present, this indicates when buffer + is full */ +#define UNICOMMI2CT_CPU_INT_RIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_RIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_RIS[TXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger When FIFO is + present, triggered as per IFLS + settings + When FIFO is not present, trigger + when transmit buffer is empty */ +#define UNICOMMI2CT_CPU_INT_RIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_RIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_RIS[START] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_START_OFS (9) /* !< START Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_START_MASK ((uint32_t)0x00000200U) /* !< Start Condition Interrupt: is set + after a START condition is received + and this target is addressed */ +#define UNICOMMI2CT_CPU_INT_RIS_START_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_START_SET ((uint32_t)0x00000200U) /* !< Set when a START condition is + receivied and address matches + target's address */ +/* UNICOMMI2CT_CPU_INT_RIS[STOP] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_STOP_OFS (10) /* !< STOP Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_STOP_MASK ((uint32_t)0x00000400U) /* !< Stop Condition Interrupt: set on a + STOP condition if this target was + being addressed */ +#define UNICOMMI2CT_CPU_INT_RIS_STOP_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_STOP_SET ((uint32_t)0x00000400U) /* !< Interrupt is set when target is + addressed and STOP condition is + received */ +/* UNICOMMI2CT_CPU_INT_RIS[DMA_DONE_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_RIS[DMA_DONE_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_RIS[PEC_RX_ERR] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< RX Pec Error Interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_PEC_RX_ERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Interrupt ocuured */ +/* UNICOMMI2CT_CPU_INT_RIS[TIMEOUTA] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A Interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTA_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_RIS[TIMEOUTB] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTB_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_RIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_RIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_CPU_INT_RIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_RIS[RXFULL] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. This interrupt + is set if an RX FIFO is full. */ +#define UNICOMMI2CT_CPU_INT_RIS_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_RIS_RXFULL_SET ((uint32_t)0x00000010U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_RIS[TXEMPTY] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty Interrupt. + This interrupt is set if all data in + the Transmit FIFO have been shifted + out and FSM goes into idle mode. */ +#define UNICOMMI2CT_CPU_INT_RIS_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_RIS[TX_UNFL] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_TX_UNFL_OFS (6) /* !< TX_UNFL Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_TX_UNFL_MASK ((uint32_t)0x00000040U) /* !< Transmit FIFO underflow */ +#define UNICOMMI2CT_CPU_INT_RIS_TX_UNFL_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_TX_UNFL_SET ((uint32_t)0x00000040U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_RIS[RX_OVFL] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_RX_OVFL_OFS (7) /* !< RX_OVFL Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_RX_OVFL_MASK ((uint32_t)0x00000080U) /* !< Receive FIFO overflow */ +#define UNICOMMI2CT_CPU_INT_RIS_RX_OVFL_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_RX_OVFL_SET ((uint32_t)0x00000080U) /* !< Interrupt Occured */ +/* UNICOMMI2CT_CPU_INT_RIS[ARBLOST] Bits */ +#define UNICOMMI2CT_CPU_INT_RIS_ARBLOST_OFS (17) /* !< ARBLOST Offset */ +#define UNICOMMI2CT_CPU_INT_RIS_ARBLOST_MASK ((uint32_t)0x00020000U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CT_CPU_INT_RIS_ARBLOST_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_RIS_ARBLOST_SET ((uint32_t)0x00020000U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_CPU_INT_MIS Bits */ +/* UNICOMMI2CT_CPU_INT_MIS[RXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Receive Data Interrupt Signals that + a byte has been received */ +#define UNICOMMI2CT_CPU_INT_MIS_RXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_MIS[TXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Transmit Transaction completed + Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_TXDONE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_MIS[GENCALL] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_GENCALL_OFS (8) /* !< GENCALL Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_GENCALL_MASK ((uint32_t)0x00000100U) /* !< General Call Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_GENCALL_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_GENCALL_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_MIS[RXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_CPU_INT_MIS_RXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_MIS_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_MIS[TXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_CPU_INT_MIS_TXTRG_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_MIS_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_MIS[START] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_START_OFS (9) /* !< START Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_START_MASK ((uint32_t)0x00000200U) /* !< START Detection Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_START_CLR ((uint32_t)0x00000000U) /* !< Clear MIS */ +#define UNICOMMI2CT_CPU_INT_MIS_START_SET ((uint32_t)0x00000200U) /* !< Set MIS */ +/* UNICOMMI2CT_CPU_INT_MIS[STOP] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_STOP_OFS (10) /* !< STOP Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_STOP_MASK ((uint32_t)0x00000400U) /* !< STOP Detection Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_STOP_CLR ((uint32_t)0x00000000U) /* !< Clear MIS */ +#define UNICOMMI2CT_CPU_INT_MIS_STOP_SET ((uint32_t)0x00000400U) /* !< Set MIS */ +/* UNICOMMI2CT_CPU_INT_MIS[DMA_DONE_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Clear MIS */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set MIS */ +/* UNICOMMI2CT_CPU_INT_MIS[DMA_DONE_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Clear MIS */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set MIS */ +/* UNICOMMI2CT_CPU_INT_MIS[PEC_RX_ERR] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< Target RX Pec Error Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_PEC_RX_ERR_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt mask */ +#define UNICOMMI2CT_CPU_INT_MIS_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Set interrupt mask */ +/* UNICOMMI2CT_CPU_INT_MIS[TIMEOUTA] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTA_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_MIS[TIMEOUTB] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTB_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt mask */ +#define UNICOMMI2CT_CPU_INT_MIS_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Set interrupt mask */ +/* UNICOMMI2CT_CPU_INT_MIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Masked DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_MIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Masked DMA Done PREIRQ on TX Event + Channel Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_MIS[RXFULL] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. This interrupt + is set if an RX FIFO is full. */ +#define UNICOMMI2CT_CPU_INT_MIS_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_MIS_RXFULL_SET ((uint32_t)0x00000010U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_MIS[TXEMPTY] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty interrupt mask. + This interrupt is set if all data in + the Transmit FIFO have been shifted + out and the transmit goes into idle + mode. */ +#define UNICOMMI2CT_CPU_INT_MIS_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Interrupt occured */ +/* UNICOMMI2CT_CPU_INT_MIS[TX_UNFL] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_TX_UNFL_OFS (6) /* !< TX_UNFL Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_TX_UNFL_MASK ((uint32_t)0x00000040U) /* !< Target TX FIFO underflow */ +#define UNICOMMI2CT_CPU_INT_MIS_TX_UNFL_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt mask */ +#define UNICOMMI2CT_CPU_INT_MIS_TX_UNFL_SET ((uint32_t)0x00000040U) /* !< Set interrupt mask */ +/* UNICOMMI2CT_CPU_INT_MIS[RX_OVFL] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_RX_OVFL_OFS (7) /* !< RX_OVFL Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_RX_OVFL_MASK ((uint32_t)0x00000080U) /* !< Target RX FIFO overflow */ +#define UNICOMMI2CT_CPU_INT_MIS_RX_OVFL_CLR ((uint32_t)0x00000000U) /* !< Clear interrupt mask */ +#define UNICOMMI2CT_CPU_INT_MIS_RX_OVFL_SET ((uint32_t)0x00000080U) /* !< Set interrupt mask */ +/* UNICOMMI2CT_CPU_INT_MIS[ARBLOST] Bits */ +#define UNICOMMI2CT_CPU_INT_MIS_ARBLOST_OFS (17) /* !< ARBLOST Offset */ +#define UNICOMMI2CT_CPU_INT_MIS_ARBLOST_MASK ((uint32_t)0x00020000U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CT_CPU_INT_MIS_ARBLOST_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMI2CT_CPU_INT_MIS_ARBLOST_SET ((uint32_t)0x00020000U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_CPU_INT_ISET Bits */ +/* UNICOMMI2CT_CPU_INT_ISET[RXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Target Receive Data Interrupt + Signals that a byte has been received */ +#define UNICOMMI2CT_CPU_INT_ISET_RXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_RXDONE_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_ISET[TXDONE] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Target Transmit Transaction + completed Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_TXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_TXDONE_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_ISET[GENCALL] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_GENCALL_OFS (8) /* !< GENCALL Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_GENCALL_MASK ((uint32_t)0x00000100U) /* !< General Call Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_GENCALL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_GENCALL_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_ISET[RXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_CPU_INT_ISET_RXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_ISET_RXTRG_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_ISET[TXTRG] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_CPU_INT_ISET_TXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_ISET_TXTRG_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_ISET[START] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_START_OFS (9) /* !< START Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_START_MASK ((uint32_t)0x00000200U) /* !< Start Condition Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_START_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_START_SET ((uint32_t)0x00000200U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[STOP] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_STOP_OFS (10) /* !< STOP Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_STOP_MASK ((uint32_t)0x00000400U) /* !< Stop Condition Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_STOP_SET ((uint32_t)0x00000400U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[DMA_DONE_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[DMA_DONE_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[PEC_RX_ERR] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< Target RX Pec Error Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_PEC_RX_ERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_PEC_RX_ERR_SET ((uint32_t)0x00000800U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[TIMEOUTA] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTA_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTA_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_CPU_INT_ISET[TIMEOUTB] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTB_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_TIMEOUTB_SET ((uint32_t)0x00002000U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Set DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Set DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_CPU_INT_ISET_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[RXFULL] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. This interrupt + is set if an RX FIFO is full. */ +#define UNICOMMI2CT_CPU_INT_ISET_RXFULL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_CPU_INT_ISET_RXFULL_SET ((uint32_t)0x00000010U) /* !< Set Interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[TXEMPTY] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty interrupt mask. + This interrupt is set if all data in + the Transmit FIFO have been shifted + out and the transmit goes into idle + mode. */ +#define UNICOMMI2CT_CPU_INT_ISET_TXEMPTY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_TXEMPTY_SET ((uint32_t)0x00000020U) /* !< Set Interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[TX_UNFL] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_TX_UNFL_OFS (6) /* !< TX_UNFL Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_TX_UNFL_MASK ((uint32_t)0x00000040U) /* !< Target TX FIFO underflow */ +#define UNICOMMI2CT_CPU_INT_ISET_TX_UNFL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_TX_UNFL_SET ((uint32_t)0x00000040U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[RX_OVFL] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_RX_OVFL_OFS (7) /* !< RX_OVFL Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_RX_OVFL_MASK ((uint32_t)0x00000080U) /* !< Target RX FIFO overflow */ +#define UNICOMMI2CT_CPU_INT_ISET_RX_OVFL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_RX_OVFL_SET ((uint32_t)0x00000080U) /* !< Set interrupt */ +/* UNICOMMI2CT_CPU_INT_ISET[ARBLOST] Bits */ +#define UNICOMMI2CT_CPU_INT_ISET_ARBLOST_OFS (17) /* !< ARBLOST Offset */ +#define UNICOMMI2CT_CPU_INT_ISET_ARBLOST_MASK ((uint32_t)0x00020000U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CT_CPU_INT_ISET_ARBLOST_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_CPU_INT_ISET_ARBLOST_SET ((uint32_t)0x00020000U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_ICLR Bits */ +/* UNICOMMI2CT_ICLR[RXDONE] Bits */ +#define UNICOMMI2CT_ICLR_RXDONE_OFS (0) /* !< RXDONE Offset */ +#define UNICOMMI2CT_ICLR_RXDONE_MASK ((uint32_t)0x00000001U) /* !< Target Receive Data Interrupt + Signals that a byte has been received */ +#define UNICOMMI2CT_ICLR_RXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_RXDONE_CLR ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_ICLR[TXDONE] Bits */ +#define UNICOMMI2CT_ICLR_TXDONE_OFS (1) /* !< TXDONE Offset */ +#define UNICOMMI2CT_ICLR_TXDONE_MASK ((uint32_t)0x00000002U) /* !< Target Transmit Transaction + completed Interrupt */ +#define UNICOMMI2CT_ICLR_TXDONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_TXDONE_CLR ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_ICLR[GENCALL] Bits */ +#define UNICOMMI2CT_ICLR_GENCALL_OFS (8) /* !< GENCALL Offset */ +#define UNICOMMI2CT_ICLR_GENCALL_MASK ((uint32_t)0x00000100U) /* !< General Call Interrupt */ +#define UNICOMMI2CT_ICLR_GENCALL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_GENCALL_CLR ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_ICLR[RXTRG] Bits */ +#define UNICOMMI2CT_ICLR_RXTRG_OFS (2) /* !< RXTRG Offset */ +#define UNICOMMI2CT_ICLR_RXTRG_MASK ((uint32_t)0x00000004U) /* !< Receive Trigger */ +#define UNICOMMI2CT_ICLR_RXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_ICLR_RXTRG_CLR ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_ICLR[TXTRG] Bits */ +#define UNICOMMI2CT_ICLR_TXTRG_OFS (3) /* !< TXTRG Offset */ +#define UNICOMMI2CT_ICLR_TXTRG_MASK ((uint32_t)0x00000008U) /* !< Transmit Trigger */ +#define UNICOMMI2CT_ICLR_TXTRG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_ICLR_TXTRG_CLR ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_ICLR[START] Bits */ +#define UNICOMMI2CT_ICLR_START_OFS (9) /* !< START Offset */ +#define UNICOMMI2CT_ICLR_START_MASK ((uint32_t)0x00000200U) /* !< Target START Detection Interrupt */ +#define UNICOMMI2CT_ICLR_START_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_START_CLR ((uint32_t)0x00000200U) /* !< Clear interrupt */ +/* UNICOMMI2CT_ICLR[STOP] Bits */ +#define UNICOMMI2CT_ICLR_STOP_OFS (10) /* !< STOP Offset */ +#define UNICOMMI2CT_ICLR_STOP_MASK ((uint32_t)0x00000400U) /* !< Target STOP Detection Interrupt */ +#define UNICOMMI2CT_ICLR_STOP_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_STOP_CLR ((uint32_t)0x00000400U) /* !< Clear interrupt */ +/* UNICOMMI2CT_ICLR[DMA_DONE_TX] Bits */ +#define UNICOMMI2CT_ICLR_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMI2CT_ICLR_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on Event Channel TX */ +#define UNICOMMI2CT_ICLR_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_DMA_DONE_TX_CLR ((uint32_t)0x00010000U) /* !< Clear interrupt */ +/* UNICOMMI2CT_ICLR[DMA_DONE_RX] Bits */ +#define UNICOMMI2CT_ICLR_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMI2CT_ICLR_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on Event Channel RX */ +#define UNICOMMI2CT_ICLR_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_DMA_DONE_RX_CLR ((uint32_t)0x00008000U) /* !< Clear interrupt */ +/* UNICOMMI2CT_ICLR[PEC_RX_ERR] Bits */ +#define UNICOMMI2CT_ICLR_PEC_RX_ERR_OFS (11) /* !< PEC_RX_ERR Offset */ +#define UNICOMMI2CT_ICLR_PEC_RX_ERR_MASK ((uint32_t)0x00000800U) /* !< Target RX Pec Error Interrupt */ +#define UNICOMMI2CT_ICLR_PEC_RX_ERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_PEC_RX_ERR_CLR ((uint32_t)0x00000800U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[TIMEOUTA] Bits */ +#define UNICOMMI2CT_ICLR_TIMEOUTA_OFS (12) /* !< TIMEOUTA Offset */ +#define UNICOMMI2CT_ICLR_TIMEOUTA_MASK ((uint32_t)0x00001000U) /* !< Timeout A interrupt */ +#define UNICOMMI2CT_ICLR_TIMEOUTA_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_TIMEOUTA_CLR ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMI2CT_ICLR[TIMEOUTB] Bits */ +#define UNICOMMI2CT_ICLR_TIMEOUTB_OFS (13) /* !< TIMEOUTB Offset */ +#define UNICOMMI2CT_ICLR_TIMEOUTB_MASK ((uint32_t)0x00002000U) /* !< Timeout B Interrupt */ +#define UNICOMMI2CT_ICLR_TIMEOUTB_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_TIMEOUTB_CLR ((uint32_t)0x00002000U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[DMA_PREIRQ_RX] Bits */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Clear DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_RX_CLR ((uint32_t)0x00040000U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[DMA_PREIRQ_TX] Bits */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Clear DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMI2CT_ICLR_DMA_PREIRQ_TX_CLR ((uint32_t)0x00080000U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[RXFULL] Bits */ +#define UNICOMMI2CT_ICLR_RXFULL_OFS (4) /* !< RXFULL Offset */ +#define UNICOMMI2CT_ICLR_RXFULL_MASK ((uint32_t)0x00000010U) /* !< RXFIFO full event. This interrupt + is set if an RX FIFO is full. */ +#define UNICOMMI2CT_ICLR_RXFULL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMI2CT_ICLR_RXFULL_CLR ((uint32_t)0x00000010U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[TXEMPTY] Bits */ +#define UNICOMMI2CT_ICLR_TXEMPTY_OFS (5) /* !< TXEMPTY Offset */ +#define UNICOMMI2CT_ICLR_TXEMPTY_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO Empty interrupt mask. + This interrupt is set if all data in + the Transmit FIFO have been shifted + out and the transmit goes into idle + mode. */ +#define UNICOMMI2CT_ICLR_TXEMPTY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_TXEMPTY_CLR ((uint32_t)0x00000020U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[TX_UNFL] Bits */ +#define UNICOMMI2CT_ICLR_TX_UNFL_OFS (6) /* !< TX_UNFL Offset */ +#define UNICOMMI2CT_ICLR_TX_UNFL_MASK ((uint32_t)0x00000040U) /* !< Target TX FIFO underflow */ +#define UNICOMMI2CT_ICLR_TX_UNFL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_TX_UNFL_CLR ((uint32_t)0x00000040U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[RX_OVFL] Bits */ +#define UNICOMMI2CT_ICLR_RX_OVFL_OFS (7) /* !< RX_OVFL Offset */ +#define UNICOMMI2CT_ICLR_RX_OVFL_MASK ((uint32_t)0x00000080U) /* !< Target RX FIFO overflow */ +#define UNICOMMI2CT_ICLR_RX_OVFL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_RX_OVFL_CLR ((uint32_t)0x00000080U) /* !< Clear Interrupt */ +/* UNICOMMI2CT_ICLR[ARBLOST] Bits */ +#define UNICOMMI2CT_ICLR_ARBLOST_OFS (17) /* !< ARBLOST Offset */ +#define UNICOMMI2CT_ICLR_ARBLOST_MASK ((uint32_t)0x00020000U) /* !< Arbitration Lost Interrupt */ +#define UNICOMMI2CT_ICLR_ARBLOST_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMI2CT_ICLR_ARBLOST_CLR ((uint32_t)0x00020000U) /* !< Set Interrupt Mask */ + +/* UNICOMMI2CT_CLKDIV Bits */ +/* UNICOMMI2CT_CLKDIV[RATIO] Bits */ +#define UNICOMMI2CT_CLKDIV_RATIO_OFS (0) /* !< RATIO Offset */ +#define UNICOMMI2CT_CLKDIV_RATIO_MASK ((uint32_t)0x0000003FU) /* !< Selects divide ratio of module + clock Division factor 0 : DIV_BY_1 + 1 : DIV_BY_2 .... 63: DIV_BY_64 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_1 ((uint32_t)0x00000000U) /* !< Do not divide clock source */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_2 ((uint32_t)0x00000001U) /* !< Divide clock source by 2 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_3 ((uint32_t)0x00000002U) /* !< Divide clock source by 3 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_4 ((uint32_t)0x00000003U) /* !< Divide clock source by 4 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_5 ((uint32_t)0x00000004U) /* !< Divide clock source by 5 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_6 ((uint32_t)0x00000005U) /* !< Divide clock source by 6 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_7 ((uint32_t)0x00000006U) /* !< Divide clock source by 7 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_8 ((uint32_t)0x00000007U) /* !< Divide clock source by 8 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_61 ((uint32_t)0x0000003CU) /* !< Divide clock source by 8 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_62 ((uint32_t)0x0000003DU) /* !< Divide clock source by 8 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_63 ((uint32_t)0x0000003EU) /* !< Divide clock source by 8 */ +#define UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_64 ((uint32_t)0x0000003FU) /* !< Divide clock source by 8 */ + +/* UNICOMMI2CT_CLKSEL Bits */ +/* UNICOMMI2CT_CLKSEL[MFCLK_SEL] Bits */ +#define UNICOMMI2CT_CLKSEL_MFCLK_SEL_OFS (2) /* !< MFCLK_SEL Offset */ +#define UNICOMMI2CT_CLKSEL_MFCLK_SEL_MASK ((uint32_t)0x00000004U) /* !< Selects MFCLK as clock source if + enabled */ +#define UNICOMMI2CT_CLKSEL_MFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CT_CLKSEL_MFCLK_SEL_ENABLE ((uint32_t)0x00000004U) /* !< Select this clock as a source */ +/* UNICOMMI2CT_CLKSEL[BUSCLK_SEL] Bits */ +#define UNICOMMI2CT_CLKSEL_BUSCLK_SEL_OFS (3) /* !< BUSCLK_SEL Offset */ +#define UNICOMMI2CT_CLKSEL_BUSCLK_SEL_MASK ((uint32_t)0x00000008U) /* !< Selects BUS CLK as clock source if + enabled */ +#define UNICOMMI2CT_CLKSEL_BUSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CT_CLKSEL_BUSCLK_SEL_ENABLE ((uint32_t)0x00000008U) /* !< Select this clock as a source */ +/* UNICOMMI2CT_CLKSEL[ASYNC_SYSCLK_SEL] Bits */ +#define UNICOMMI2CT_CLKSEL_ASYNC_SYSCLK_SEL_OFS (9) /* !< ASYNC_SYSCLK_SEL Offset */ +#define UNICOMMI2CT_CLKSEL_ASYNC_SYSCLK_SEL_MASK ((uint32_t)0x00000200U) /* !< Asynchronous sysclk selected as + source */ +#define UNICOMMI2CT_CLKSEL_ASYNC_SYSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CT_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE ((uint32_t)0x00000200U) /* !< Select this clock as a source */ +/* UNICOMMI2CT_CLKSEL[ASYNC_HFCLK_SEL] Bits */ +#define UNICOMMI2CT_CLKSEL_ASYNC_HFCLK_SEL_OFS (10) /* !< ASYNC_HFCLK_SEL Offset */ +#define UNICOMMI2CT_CLKSEL_ASYNC_HFCLK_SEL_MASK ((uint32_t)0x00000400U) /* !< Asynchronous HFCLK selected as + source */ +#define UNICOMMI2CT_CLKSEL_ASYNC_HFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CT_CLKSEL_ASYNC_HFCLK_SEL_ENABLE ((uint32_t)0x00000400U) /* !< Select this clock as a source */ +/* UNICOMMI2CT_CLKSEL[ASYNC_PLL_SEL] Bits */ +#define UNICOMMI2CT_CLKSEL_ASYNC_PLL_SEL_OFS (11) /* !< ASYNC_PLL_SEL Offset */ +#define UNICOMMI2CT_CLKSEL_ASYNC_PLL_SEL_MASK ((uint32_t)0x00000800U) /* !< Asynchronous PLL selected as source */ +#define UNICOMMI2CT_CLKSEL_ASYNC_PLL_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMI2CT_CLKSEL_ASYNC_PLL_SEL_ENABLE ((uint32_t)0x00000800U) /* !< Select this clock as a source */ + +/* UNICOMMI2CT_PDBGCTL Bits */ +/* UNICOMMI2CT_PDBGCTL[FREE] Bits */ +#define UNICOMMI2CT_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */ +#define UNICOMMI2CT_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */ +#define UNICOMMI2CT_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes + functionality while the Core Halted + input is asserted and resumes when it + is deasserted. */ +#define UNICOMMI2CT_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of + the Core Halted input */ +/* UNICOMMI2CT_PDBGCTL[SOFT] Bits */ +#define UNICOMMI2CT_PDBGCTL_SOFT_OFS (1) /* !< SOFT Offset */ +#define UNICOMMI2CT_PDBGCTL_SOFT_MASK ((uint32_t)0x00000002U) /* !< Soft halt boundary control. This + function is only available, if [FREE] + is set to 'STOP' */ +#define UNICOMMI2CT_PDBGCTL_SOFT_DEPRECATED ((uint32_t)0x00000000U) /* !< Not supported */ +#define UNICOMMI2CT_PDBGCTL_SOFT_DELAYED ((uint32_t)0x00000002U) /* !< The peripheral blocks the debug + freeze until it has reached a + boundary where it can resume without + corruption */ + +/* UNICOMMI2CT_INTCTL Bits */ +/* UNICOMMI2CT_INTCTL[INTEVAL] Bits */ +#define UNICOMMI2CT_INTCTL_INTEVAL_OFS (0) /* !< INTEVAL Offset */ +#define UNICOMMI2CT_INTCTL_INTEVAL_MASK ((uint32_t)0x00000001U) /* !< Writing a 1 to this field + re-evaluates the interrupt sources. */ +#define UNICOMMI2CT_INTCTL_INTEVAL_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define UNICOMMI2CT_INTCTL_INTEVAL_EVAL ((uint32_t)0x00000001U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ + +/* UNICOMMI2CT_CTR Bits */ +/* UNICOMMI2CT_CTR[ENABLE] Bits */ +#define UNICOMMI2CT_CTR_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define UNICOMMI2CT_CTR_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Setting this bit enables the + module. */ +#define UNICOMMI2CT_CTR_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disables module operation. */ +#define UNICOMMI2CT_CTR_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enables module operation. */ +/* UNICOMMI2CT_CTR[GENCALL] Bits */ +#define UNICOMMI2CT_CTR_GENCALL_OFS (1) /* !< GENCALL Offset */ +#define UNICOMMI2CT_CTR_GENCALL_MASK ((uint32_t)0x00000002U) /* !< General call response enable Modify + only when UCSWRST = 1. 0b = Do not + respond to a general call 1b = + Respond to a general call */ +#define UNICOMMI2CT_CTR_GENCALL_DISABLE ((uint32_t)0x00000000U) /* !< Do not respond to a general call */ +#define UNICOMMI2CT_CTR_GENCALL_ENABLE ((uint32_t)0x00000002U) /* !< Respond to a general call */ +/* UNICOMMI2CT_CTR[CLKSTRETCH] Bits */ +#define UNICOMMI2CT_CTR_CLKSTRETCH_OFS (20) /* !< CLKSTRETCH Offset */ +#define UNICOMMI2CT_CTR_CLKSTRETCH_MASK ((uint32_t)0x00100000U) /* !< Clock Stretch Enable */ +#define UNICOMMI2CT_CTR_CLKSTRETCH_DISABLE ((uint32_t)0x00000000U) /* !< clock stretching is disabled */ +#define UNICOMMI2CT_CTR_CLKSTRETCH_ENABLE ((uint32_t)0x00100000U) /* !< clock stretching is enabled */ +/* UNICOMMI2CT_CTR[TXEMPTY_ON_TREQ] Bits */ +#define UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_OFS (3) /* !< TXEMPTY_ON_TREQ Offset */ +#define UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_MASK ((uint32_t)0x00000008U) /* !< Tx Empty Interrupt on TREQ */ +#define UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_DISABLE ((uint32_t)0x00000000U) /* !< When 0, RIS:TXEMPTY will be set + when only the Target TX FIFO is + empty. This allows the TXEMPTY + interrupt to be used to indicate that + the I2C bus is being clock stretched + and that Target TX data is required. */ +#define UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_ENABLE ((uint32_t)0x00000008U) /* !< When 1, RIS:TXEMPTY will be set + when the Target State Machine is in + the TX_WAIT state which occurs when + the TX FIFO is empty AND the I2C + transaction is clock stretched + waiting for the FIFO to receive data. */ +/* UNICOMMI2CT_CTR[TXTRIG_TXMODE] Bits */ +#define UNICOMMI2CT_CTR_TXTRIG_TXMODE_OFS (4) /* !< TXTRIG_TXMODE Offset */ +#define UNICOMMI2CT_CTR_TXTRIG_TXMODE_MASK ((uint32_t)0x00000010U) /* !< Tx Trigger when Target FSM is in Tx + Mode */ +#define UNICOMMI2CT_CTR_TXTRIG_TXMODE_DISABLE ((uint32_t)0x00000000U) /* !< No special behavior */ +#define UNICOMMI2CT_CTR_TXTRIG_TXMODE_ENABLE ((uint32_t)0x00000010U) /* !< When 1, RIS:TXTRG will be set when + the Target TX FIFO has reached the + trigger level AND the Target State + Machine is in the TXMODE as defined + in the SSR register. When cleared + RIS:TXTRG will be set when the Target + TX FIFO is at or above the trigger + level. This setting can be used to + hold off the TX DMA until a + transaction starts. This allows the + DMA to be configured when the I2C is + idle but have it wait till the + transaction starts to load the Target + TX FIFO, so it can load from a memory + buffer that might be changing over + time. */ +/* UNICOMMI2CT_CTR[TXWAIT_STALE_TXFIFO] Bits */ +#define UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_OFS (5) /* !< TXWAIT_STALE_TXFIFO Offset */ +#define UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_MASK ((uint32_t)0x00000020U) /* !< Tx transfer waits when stale data + in Tx FIFO. This prevents stale bytes + left in the TX FIFO from + automatically being sent on the next + I2C packet. Note: this should be used + with TXEMPTY_ON_TREQ set to prevent + the Target State Machine from waiting + for TX FIFO data without an interrupt + notification when the FIFO data is + stale. */ +#define UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_DISABLE ((uint32_t)0x00000000U) /* !< When 0, the TX FIFO empty signal to + the Target State Machine indicates + that the TX FIFO is empty. */ +#define UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_ENABLE ((uint32_t)0x00000020U) /* !< When 1, the TX FIFO empty signal to + the Target State Machine will + indicate that the TX FIFO is empty or + that the TX FIFO data is stale. The + TX FIFO data is determined to be + stale when there is data in the TX + FIFO when the Target State Machine + leaves the TXMODE as defined in the + SSR register. This can occur is a + Stop or timeout occur when there are + bytes left in the TX FIFO. */ +/* UNICOMMI2CT_CTR[RXFULL_ON_RREQ] Bits */ +#define UNICOMMI2CT_CTR_RXFULL_ON_RREQ_OFS (6) /* !< RXFULL_ON_RREQ Offset */ +#define UNICOMMI2CT_CTR_RXFULL_ON_RREQ_MASK ((uint32_t)0x00000040U) /* !< Rx full interrupt generated on RREQ + condition as indicated in SSR */ +#define UNICOMMI2CT_CTR_RXFULL_ON_RREQ_DISABLE ((uint32_t)0x00000000U) /* !< When 0, RIS:SRXFULL will be set + when only the Target RX FIFO is full. + This allows the SRXFULL interrupt to + be used to indicate that the I2C bus + is being clock stretched and that the + FW must either read the RX FIFO or + ACK/NACK the current Rx byte. */ +#define UNICOMMI2CT_CTR_RXFULL_ON_RREQ_ENABLE ((uint32_t)0x00000040U) /* !< When 1, RIS:SRXFULL will be set + when the Target State Machine is in + the RX_WAIT or RX_ACK_WAIT states + which occurs when the I2C transaction + is clock stretched because the RX + FIFO is full or the ACKOEN has been + set and the state machine is waiting + for FW to ACK/NACK the current byte. */ +/* UNICOMMI2CT_CTR[EN_DEFHOSTADR] Bits */ +#define UNICOMMI2CT_CTR_EN_DEFHOSTADR_OFS (7) /* !< EN_DEFHOSTADR Offset */ +#define UNICOMMI2CT_CTR_EN_DEFHOSTADR_MASK ((uint32_t)0x00000080U) /* !< Enable Default Host Address */ +#define UNICOMMI2CT_CTR_EN_DEFHOSTADR_DISABLE ((uint32_t)0x00000000U) /* !< When this bit is 0, the default + host address is not matched NOTE: it + may still be matched if programmed + inside SOAR/SOAR2 */ +#define UNICOMMI2CT_CTR_EN_DEFHOSTADR_ENABLE ((uint32_t)0x00000080U) /* !< When this bit is 1, default host + address of 7h000_1000 is always + matched by the Target address match + logic. */ +/* UNICOMMI2CT_CTR[EN_ALRESPADR] Bits */ +#define UNICOMMI2CT_CTR_EN_ALRESPADR_OFS (8) /* !< EN_ALRESPADR Offset */ +#define UNICOMMI2CT_CTR_EN_ALRESPADR_MASK ((uint32_t)0x00000100U) /* !< Enable Alert Response Address */ +#define UNICOMMI2CT_CTR_EN_ALRESPADR_DISABLE ((uint32_t)0x00000000U) /* !< When this bit is 0, the alert + response address is not matched. + NOTE: it may still be matched if + programmed inside SOAR/SOAR2 */ +#define UNICOMMI2CT_CTR_EN_ALRESPADR_ENABLE ((uint32_t)0x00000100U) /* !< When this bit is 1, alert response + address of 7h000_1100 is always + matched by the Target address match + logic. */ +/* UNICOMMI2CT_CTR[EN_DEFDEVADR] Bits */ +#define UNICOMMI2CT_CTR_EN_DEFDEVADR_OFS (9) /* !< EN_DEFDEVADR Offset */ +#define UNICOMMI2CT_CTR_EN_DEFDEVADR_MASK ((uint32_t)0x00000200U) /* !< Enable Default device address */ +#define UNICOMMI2CT_CTR_EN_DEFDEVADR_DISABLE ((uint32_t)0x00000000U) /* !< When this bit is 0, the default + device address is not matched. NOTE: + it may still be matched if programmed + inside SOAR/SOAR2. */ +#define UNICOMMI2CT_CTR_EN_DEFDEVADR_ENABLE ((uint32_t)0x00000200U) /* !< When this bit is 1, default device + address of 7h110_0001 is always + matched by the Target address match + logic. */ +/* UNICOMMI2CT_CTR[WUEN] Bits */ +#define UNICOMMI2CT_CTR_WUEN_OFS (21) /* !< WUEN Offset */ +#define UNICOMMI2CT_CTR_WUEN_MASK ((uint32_t)0x00200000U) /* !< Target Wakeup Enable */ +#define UNICOMMI2CT_CTR_WUEN_DISABLE ((uint32_t)0x00000000U) /* !< When 0, the Target is not allowed + to clock stretch on START detection */ +#define UNICOMMI2CT_CTR_WUEN_ENABLE ((uint32_t)0x00200000U) /* !< When 1, the Target is allowed to + clock stretch on START detection and + wait for faster clock to be + abvailable. This allows clean wake up + support for I2C in low power mode use + cases */ +/* UNICOMMI2CT_CTR[SUSPEND] Bits */ +#define UNICOMMI2CT_CTR_SUSPEND_OFS (11) /* !< SUSPEND Offset */ +#define UNICOMMI2CT_CTR_SUSPEND_MASK ((uint32_t)0x00000800U) /* !< Suspend external communication */ +#define UNICOMMI2CT_CTR_SUSPEND_DISABLE ((uint32_t)0x00000000U) /* !< Functional mode resumed */ +#define UNICOMMI2CT_CTR_SUSPEND_ENABLE ((uint32_t)0x00000800U) /* !< External communication suspended */ + +/* UNICOMMI2CT_ACKCTL Bits */ +/* UNICOMMI2CT_ACKCTL[ACKOEN] Bits */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_OFS (0) /* !< ACKOEN Offset */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_MASK ((uint32_t)0x00000001U) /* !< I2C Target ACK Override Enable + Read SR.ACKOEN to check current + status of this bit */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_DISABLE ((uint32_t)0x00000000U) /* !< A response in not provided. */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ENABLE ((uint32_t)0x00000001U) /* !< An ACK or NACK is sent according to + the value written to the ACKOVAL bit. */ +/* UNICOMMI2CT_ACKCTL[ACKOVAL] Bits */ +#define UNICOMMI2CT_ACKCTL_ACKOVAL_OFS (1) /* !< ACKOVAL Offset */ +#define UNICOMMI2CT_ACKCTL_ACKOVAL_MASK ((uint32_t)0x00000002U) /* !< ACK Override Value Note: for + General Call this bit will be ignored + if set to NACK and Target continues + to receive data. */ +#define UNICOMMI2CT_ACKCTL_ACKOVAL_DISABLE ((uint32_t)0x00000000U) /* !< An ACK is sent indicating valid + data or command. */ +#define UNICOMMI2CT_ACKCTL_ACKOVAL_ENABLE ((uint32_t)0x00000002U) /* !< A NACK is sent indicating invalid + data or command. */ +/* UNICOMMI2CT_ACKCTL[ACKOEN_ON_START] Bits */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_OFS (2) /* !< ACKOEN_ON_START Offset */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_MASK ((uint32_t)0x00000004U) /* !< When set this bit will + automatically enable target override + acknowlede following a Start + Condition. Status bit ACKOEN will + reflect a value of '1' when automatic + override enable is used. */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_DISABLE ((uint32_t)0x00000000U) /* !< No special behavior */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_ENABLE ((uint32_t)0x00000004U) /* !< When set this bit will + automatically turn on the Target + ACKOEN field following a Start + Condition. */ +/* UNICOMMI2CT_ACKCTL[ACKOEN_ON_PECNEXT] Bits */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_OFS (3) /* !< ACKOEN_ON_PECNEXT Offset */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_MASK ((uint32_t)0x00000008U) /* !< When set this bit will + automatically turn on the Target + acknowledge override following a + ACK/NACK of the byte received just + prior to the PEC byte. However, + setting ACKCTL.ACKOEN bit will not + automatically be ACKed/NACKed by the + State Machine and firmware must + perform this function by writing + Target.ACKCTL register. Status bit + ACKOEN will reflect a value of '1' + when automatic override enable is + used. */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_DISABLE ((uint32_t)0x00000000U) /* !< No special behavior */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_ENABLE ((uint32_t)0x00000008U) /* !< When set this bit will + automatically turn on the Target + ACKOEN field following the ACK/NACK + of the byte received just prior to + the PEC byte. Note that when ACKOEN + is set the PEC byte will not + automatically be ACKed/NACKed by the + State Machine and FW must perform + this function by writing + Target_SACKCTL. */ +/* UNICOMMI2CT_ACKCTL[ACKOEN_ON_PECDONE] Bits */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_OFS (4) /* !< ACKOEN_ON_PECDONE Offset */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_MASK ((uint32_t)0x00000010U) /* !< When set, this bit will + automatically turn on target + acknowledge enable field following + the ACK/NACK of the received PEC + byte. Status bit ACKOEN will reflect + a value of '1' when automatic + override enable is used. */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_DISABLE ((uint32_t)0x00000000U) /* !< No special behavior */ +#define UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_ENABLE ((uint32_t)0x00000010U) /* !< When set this bit will + automatically turn on the Target + ACKOEN field following the ACK/NACK + of the received PEC byte. */ + +/* UNICOMMI2CT_SR Bits */ +/* UNICOMMI2CT_SR[RREQ] Bits */ +#define UNICOMMI2CT_SR_RREQ_OFS (0) /* !< RREQ Offset */ +#define UNICOMMI2CT_SR_RREQ_MASK ((uint32_t)0x00000001U) /* !< Receive Request */ +#define UNICOMMI2CT_SR_RREQ_CLEARED ((uint32_t)0x00000000U) /* !< No outstanding receive data. */ +#define UNICOMMI2CT_SR_RREQ_SET ((uint32_t)0x00000001U) /* !< Module has outstanding receive data + and is using clock stretching to + delay the Controller until the data + has been read from the RXDATA FIFO + (RX FIFO is full). */ +/* UNICOMMI2CT_SR[TREQ] Bits */ +#define UNICOMMI2CT_SR_TREQ_OFS (1) /* !< TREQ Offset */ +#define UNICOMMI2CT_SR_TREQ_MASK ((uint32_t)0x00000002U) /* !< Transmit Request */ +#define UNICOMMI2CT_SR_TREQ_CLEARED ((uint32_t)0x00000000U) /* !< No outstanding transmit request. */ +#define UNICOMMI2CT_SR_TREQ_SET ((uint32_t)0x00000002U) /* !< I2C Target is addressed as a + transmitter and is using clock + stretching to delay the Controller + until data has been written to the + TXDATA FIFO (TX FIFO is empty). */ +/* UNICOMMI2CT_SR[OAR2SEL] Bits */ +#define UNICOMMI2CT_SR_OAR2SEL_OFS (3) /* !< OAR2SEL Offset */ +#define UNICOMMI2CT_SR_OAR2SEL_MASK ((uint32_t)0x00000008U) /* !< OAR2 Address Matched This bit gets + reevaluated after every address + comparison. */ +#define UNICOMMI2CT_SR_OAR2SEL_CLEARED ((uint32_t)0x00000000U) /* !< Either the OAR2 address is not + matched or the match is in legacy + mode. */ +#define UNICOMMI2CT_SR_OAR2SEL_SET ((uint32_t)0x00000008U) /* !< OAR2 address matched and ACKed by + the Target. */ +/* UNICOMMI2CT_SR[QCMDST] Bits */ +#define UNICOMMI2CT_SR_QCMDST_OFS (4) /* !< QCMDST Offset */ +#define UNICOMMI2CT_SR_QCMDST_MASK ((uint32_t)0x00000010U) /* !< Quick Command Status Value + Description: 0: The last transaction + was a normal transaction or a + transaction has not occurred. 1: The + last transaction was a Quick Command + transaction */ +#define UNICOMMI2CT_SR_QCMDST_CLEARED ((uint32_t)0x00000000U) /* !< The last transaction was a normal + transaction or a transaction has not + occurred. */ +#define UNICOMMI2CT_SR_QCMDST_SET ((uint32_t)0x00000010U) /* !< The last transaction was a Quick + Command transaction. */ +/* UNICOMMI2CT_SR[QCMDRW] Bits */ +#define UNICOMMI2CT_SR_QCMDRW_OFS (5) /* !< QCMDRW Offset */ +#define UNICOMMI2CT_SR_QCMDRW_MASK ((uint32_t)0x00000020U) /* !< Quick Command Read / Write This + bit only has meaning when the QCMDST + bit is set. Value Description: 0: + Quick command was a write 1: Quick + command was a read */ +#define UNICOMMI2CT_SR_QCMDRW_CLEARED ((uint32_t)0x00000000U) /* !< Quick command was a write */ +#define UNICOMMI2CT_SR_QCMDRW_SET ((uint32_t)0x00000020U) /* !< Quick command was a read */ +/* UNICOMMI2CT_SR[RXMODE] Bits */ +#define UNICOMMI2CT_SR_RXMODE_OFS (2) /* !< RXMODE Offset */ +#define UNICOMMI2CT_SR_RXMODE_MASK ((uint32_t)0x00000004U) /* !< Target FSM is in Rx MODE */ +#define UNICOMMI2CT_SR_RXMODE_CLEARED ((uint32_t)0x00000000U) /* !< The Target State Machine is not in + the RX_DATA, RX_ACK, RX_WAIT, + RX_ACK_WAIT or ADDR_ACK state with + the bus direction set to write. */ +#define UNICOMMI2CT_SR_RXMODE_SET ((uint32_t)0x00000004U) /* !< The Target State Machine is in the + RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT + or ADDR_ACK state with the bus + direction set to write. */ +/* UNICOMMI2CT_SR[BUSBSY] Bits */ +#define UNICOMMI2CT_SR_BUSBSY_OFS (6) /* !< BUSBSY Offset */ +#define UNICOMMI2CT_SR_BUSBSY_MASK ((uint32_t)0x00000040U) /* !< I2C bus is busy */ +#define UNICOMMI2CT_SR_BUSBSY_CLEARED ((uint32_t)0x00000000U) /* !< The I2C Bus is not busy */ +#define UNICOMMI2CT_SR_BUSBSY_SET ((uint32_t)0x00000040U) /* !< The I2C Bus is busy. This is + cleared on a timeout. */ +/* UNICOMMI2CT_SR[TXMODE] Bits */ +#define UNICOMMI2CT_SR_TXMODE_OFS (7) /* !< TXMODE Offset */ +#define UNICOMMI2CT_SR_TXMODE_MASK ((uint32_t)0x00000080U) /* !< FSM is in TX MODE */ +#define UNICOMMI2CT_SR_TXMODE_CLEARED ((uint32_t)0x00000000U) /* !< State Machine is not in TX_DATA, + TX_WAIT, TX_ACK or ADDR_ACK state + with the bus direction set to read. */ +#define UNICOMMI2CT_SR_TXMODE_SET ((uint32_t)0x00000080U) /* !< State Machine is in TX_DATA, + TX_WAIT, TX_ACK or ADDR_ACK state + with the bus direction set to read. */ +/* UNICOMMI2CT_SR[STALE_TXFIFO] Bits */ +#define UNICOMMI2CT_SR_STALE_TXFIFO_OFS (8) /* !< STALE_TXFIFO Offset */ +#define UNICOMMI2CT_SR_STALE_TXFIFO_MASK ((uint32_t)0x00000100U) /* !< Stale Tx FIFO */ +#define UNICOMMI2CT_SR_STALE_TXFIFO_CLEARED ((uint32_t)0x00000000U) /* !< Tx FIFO is not stale */ +#define UNICOMMI2CT_SR_STALE_TXFIFO_SET ((uint32_t)0x00000100U) /* !< The TX FIFO is stale. This occurs + when the TX FIFO was not emptied + during the previous I2C transaction. */ +/* UNICOMMI2CT_SR[ADDRMATCH] Bits */ +#define UNICOMMI2CT_SR_ADDRMATCH_OFS (16) /* !< ADDRMATCH Offset */ +#define UNICOMMI2CT_SR_ADDRMATCH_MASK ((uint32_t)0x03FF0000U) /* !< Indicates the address for which + Target address match happened */ +#define UNICOMMI2CT_SR_ADDRMATCH_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum Value */ +#define UNICOMMI2CT_SR_ADDRMATCH_MAXIMUM ((uint32_t)0x03FF0000U) /* !< Maximum Value */ +/* UNICOMMI2CT_SR[RXCLR] Bits */ +#define UNICOMMI2CT_SR_RXCLR_OFS (9) /* !< RXCLR Offset */ +#define UNICOMMI2CT_SR_RXCLR_MASK ((uint32_t)0x00000200U) /* !< RX FIFO Clear Status */ +#define UNICOMMI2CT_SR_RXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMI2CT_SR_RXCLR_SET ((uint32_t)0x00000200U) /* !< FIFO clear is complete */ +/* UNICOMMI2CT_SR[TXCLR] Bits */ +#define UNICOMMI2CT_SR_TXCLR_OFS (10) /* !< TXCLR Offset */ +#define UNICOMMI2CT_SR_TXCLR_MASK ((uint32_t)0x00000400U) /* !< TX FIFO Clear Status */ +#define UNICOMMI2CT_SR_TXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMI2CT_SR_TXCLR_SET ((uint32_t)0x00000400U) /* !< FIFO clear is complete */ +/* UNICOMMI2CT_SR[RXFE] Bits */ +#define UNICOMMI2CT_SR_RXFE_OFS (11) /* !< RXFE Offset */ +#define UNICOMMI2CT_SR_RXFE_MASK ((uint32_t)0x00000800U) /* !< Receive FIFO Empty The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CT_SR_RXFE_CLEARED ((uint32_t)0x00000000U) /* !< The receiver is not empty. */ +#define UNICOMMI2CT_SR_RXFE_SET ((uint32_t)0x00000800U) /* !< If the FIFO is disabled (FEN is 0), + the receive holding register is + empty. If the FIFO is enabled (FEN is + 1), the receive FIFO is empty. */ +/* UNICOMMI2CT_SR[RXFF] Bits */ +#define UNICOMMI2CT_SR_RXFF_OFS (12) /* !< RXFF Offset */ +#define UNICOMMI2CT_SR_RXFF_MASK ((uint32_t)0x00001000U) /* !< Receive FIFO Full The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CT_SR_RXFF_CLEARED ((uint32_t)0x00000000U) /* !< The receiver can receive data. */ +#define UNICOMMI2CT_SR_RXFF_SET ((uint32_t)0x00001000U) /* !< If the FIFO is disabled (FEN is 0), + the receive holding register is full. + If the FIFO is enabled (FEN is 1), + the receive FIFO is full. */ +/* UNICOMMI2CT_SR[TXFE] Bits */ +#define UNICOMMI2CT_SR_TXFE_OFS (13) /* !< TXFE Offset */ +#define UNICOMMI2CT_SR_TXFE_MASK ((uint32_t)0x00002000U) /* !< Transmit FIFO Empty The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CT_SR_TXFE_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter has data to + transmit. */ +#define UNICOMMI2CT_SR_TXFE_SET ((uint32_t)0x00002000U) /* !< If the FIFO is disabled (FEN is 0), + the transmit holding register is + empty. If the FIFO is enabled (FEN is + 1), the transmit FIFO is empty. */ +/* UNICOMMI2CT_SR[TXFF] Bits */ +#define UNICOMMI2CT_SR_TXFF_OFS (14) /* !< TXFF Offset */ +#define UNICOMMI2CT_SR_TXFF_MASK ((uint32_t)0x00004000U) /* !< Transmit FIFO Full The meaning of + this bit depends on the state of the + FEN bit in the CTL0 register. */ +#define UNICOMMI2CT_SR_TXFF_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter is not full. */ +#define UNICOMMI2CT_SR_TXFF_SET ((uint32_t)0x00004000U) /* !< If the FIFO is disabled (FEN is 0), + the transmit holding register is + full. If the FIFO is enabled (FEN is + 1), the transmit FIFO is full. */ +/* UNICOMMI2CT_SR[ACKOEN] Bits */ +#define UNICOMMI2CT_SR_ACKOEN_OFS (15) /* !< ACKOEN Offset */ +#define UNICOMMI2CT_SR_ACKOEN_MASK ((uint32_t)0x00008000U) /* !< Status of ACK Override Enable */ +#define UNICOMMI2CT_SR_ACKOEN_DISABLE ((uint32_t)0x00000000U) /* !< ACK override is disabled */ +#define UNICOMMI2CT_SR_ACKOEN_ENABLE ((uint32_t)0x00008000U) /* !< ACK override was enabled in design */ + +/* UNICOMMI2CT_IFLS Bits */ +/* UNICOMMI2CT_IFLS[TXIFLSEL] Bits */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_OFS (0) /* !< TXIFLSEL Offset */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_MASK ((uint32_t)0x00000007U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_LVL_3_4 ((uint32_t)0x00000001U) /* !< TX FIFO <= 3/4 empty */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_LVL_1_2 ((uint32_t)0x00000002U) /* !< TX FIFO <= 1/2 empty (default) */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_LVL_1_4 ((uint32_t)0x00000003U) /* !< TX FIFO <= 1/4 empty */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_LVL_NOT_FULL ((uint32_t)0x00000004U) /* !< Opposite of full */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_LVL_EMPTY ((uint32_t)0x00000005U) /* !< TX FIFO is empty */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000006U) /* !< TX FIFO <= 1 */ +#define UNICOMMI2CT_IFLS_TXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000007U) /* !< TX_FIFO >= (MAX_FIFO_LEN -1) */ +/* UNICOMMI2CT_IFLS[RXIFLSEL] Bits */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_OFS (4) /* !< RXIFLSEL Offset */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_MASK ((uint32_t)0x00000070U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_LVL_1_4 ((uint32_t)0x00000010U) /* !< RX FIFO >= 1/4 full */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_LVL_1_2 ((uint32_t)0x00000020U) /* !< RX FIFO >= 1/2 full (default) */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_LVL_3_4 ((uint32_t)0x00000030U) /* !< RX FIFO >= 3/4 full */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_LVL_NOT_EMPTY ((uint32_t)0x00000040U) /* !< Opposite of empty */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_LVL_FULL ((uint32_t)0x00000050U) /* !< RX FIFO is full */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000060U) /* !< RX_FIFO >= (MAX_FIFO_LEN -1) */ +#define UNICOMMI2CT_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000070U) /* !< RX_FIFO <= 1 */ +/* UNICOMMI2CT_IFLS[TXCLR] Bits */ +#define UNICOMMI2CT_IFLS_TXCLR_OFS (3) /* !< TXCLR Offset */ +#define UNICOMMI2CT_IFLS_TXCLR_MASK ((uint32_t)0x00000008U) /* !< TX FIFO CLEAR. Setting this bit + will clear the TX FIFO contents. */ +#define UNICOMMI2CT_IFLS_TXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMI2CT_IFLS_TXCLR_ENABLE ((uint32_t)0x00000008U) /* !< Enable FIFO Clear */ +/* UNICOMMI2CT_IFLS[RXCLR] Bits */ +#define UNICOMMI2CT_IFLS_RXCLR_OFS (7) /* !< RXCLR Offset */ +#define UNICOMMI2CT_IFLS_RXCLR_MASK ((uint32_t)0x00000080U) /* !< RX FIFO CLEAR. Setting this bit + will clear the RX FIFO contents. */ +#define UNICOMMI2CT_IFLS_RXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMI2CT_IFLS_RXCLR_ENABLE ((uint32_t)0x00000080U) /* !< Enable FIFO Clear */ + +/* UNICOMMI2CT_GFCTL Bits */ +/* UNICOMMI2CT_GFCTL[DGFSEL] Bits */ +#define UNICOMMI2CT_GFCTL_DGFSEL_OFS (0) /* !< DGFSEL Offset */ +#define UNICOMMI2CT_GFCTL_DGFSEL_MASK ((uint32_t)0x00000007U) /* !< Glitch Suppression Pulse Width This + field controls the pulse width select + for glitch suppression on the SCL and + SDA lines. The following values are + the glitch suppression values in + terms of functional clocks. (Core + Domain only) */ +#define UNICOMMI2CT_GFCTL_DGFSEL_DISABLED ((uint32_t)0x00000000U) /* !< Bypass */ +#define UNICOMMI2CT_GFCTL_DGFSEL_CLK_1 ((uint32_t)0x00000001U) /* !< 1 clock */ +#define UNICOMMI2CT_GFCTL_DGFSEL_CLK_2 ((uint32_t)0x00000002U) /* !< 2 clocks */ +#define UNICOMMI2CT_GFCTL_DGFSEL_CLK_3 ((uint32_t)0x00000003U) /* !< 3 clocks */ +#define UNICOMMI2CT_GFCTL_DGFSEL_CLK_4 ((uint32_t)0x00000004U) /* !< 4 clocks */ +#define UNICOMMI2CT_GFCTL_DGFSEL_CLK_8 ((uint32_t)0x00000005U) /* !< 8 clocks */ +#define UNICOMMI2CT_GFCTL_DGFSEL_CLK_16 ((uint32_t)0x00000006U) /* !< 16 clocks */ +#define UNICOMMI2CT_GFCTL_DGFSEL_CLK_31 ((uint32_t)0x00000007U) /* !< 31 clocks */ +/* UNICOMMI2CT_GFCTL[AGFEN] Bits */ +#define UNICOMMI2CT_GFCTL_AGFEN_OFS (8) /* !< AGFEN Offset */ +#define UNICOMMI2CT_GFCTL_AGFEN_MASK ((uint32_t)0x00000100U) /* !< Analog Glitch Suppression Enable */ +#define UNICOMMI2CT_GFCTL_AGFEN_DISABLE ((uint32_t)0x00000000U) /* !< Analog Glitch Filter disable */ +#define UNICOMMI2CT_GFCTL_AGFEN_ENABLE ((uint32_t)0x00000100U) /* !< Analog Glitch Filter enable */ + +/* UNICOMMI2CT_TTXDATA Bits */ +/* UNICOMMI2CT_TTXDATA[DATA] Bits */ +#define UNICOMMI2CT_TTXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMI2CT_TTXDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< Transmit Data This byte contains + the data to be transferred during the + next transaction. */ +#define UNICOMMI2CT_TTXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_TTXDATA_DATA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ + +/* UNICOMMI2CT_RXDATA Bits */ +/* UNICOMMI2CT_RXDATA[DATA] Bits */ +#define UNICOMMI2CT_RXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMI2CT_RXDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< Received Data. This field contains + the last received data. */ +#define UNICOMMI2CT_RXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_RXDATA_DATA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ + +/* UNICOMMI2CT_PECSR Bits */ +/* UNICOMMI2CT_PECSR[PECBYTECNT] Bits */ +#define UNICOMMI2CT_PECSR_PECBYTECNT_OFS (0) /* !< PECBYTECNT Offset */ +#define UNICOMMI2CT_PECSR_PECBYTECNT_MASK ((uint32_t)0x000001FFU) /* !< This is the current PEC Byte Count + of the State Machine. */ +#define UNICOMMI2CT_PECSR_PECBYTECNT_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum Value */ +#define UNICOMMI2CT_PECSR_PECBYTECNT_MAXIMUM ((uint32_t)0x000001FFU) /* !< Maximum Value */ +/* UNICOMMI2CT_PECSR[PECSTS_CHECK] Bits */ +#define UNICOMMI2CT_PECSR_PECSTS_CHECK_OFS (16) /* !< PECSTS_CHECK Offset */ +#define UNICOMMI2CT_PECSR_PECSTS_CHECK_MASK ((uint32_t)0x00010000U) /* !< This status bit indicates if the + PEC was checked in the transaction + that occurred before the last Stop. + Latched on Stop. */ +#define UNICOMMI2CT_PECSR_PECSTS_CHECK_CLEARED ((uint32_t)0x00000000U) /* !< Indicates PEC was not checked in + the transaction that occurred before + the last Stop */ +#define UNICOMMI2CT_PECSR_PECSTS_CHECK_SET ((uint32_t)0x00010000U) /* !< Indicates PEC was checked in the + transaction that occurred before the + last Stop */ +/* UNICOMMI2CT_PECSR[PECSTS_ERROR] Bits */ +#define UNICOMMI2CT_PECSR_PECSTS_ERROR_OFS (17) /* !< PECSTS_ERROR Offset */ +#define UNICOMMI2CT_PECSR_PECSTS_ERROR_MASK ((uint32_t)0x00020000U) /* !< This status bit indicates if a PEC + check error occurred in the + transaction that occurred before the + last Stop. Latched on Stop. */ +#define UNICOMMI2CT_PECSR_PECSTS_ERROR_CLEARED ((uint32_t)0x00000000U) /* !< Indicates PEC check error did not + occurr in the transaction that + occurred before the last Stop */ +#define UNICOMMI2CT_PECSR_PECSTS_ERROR_SET ((uint32_t)0x00020000U) /* !< Indicates PEC check error occurred + in the transaction that occurred + before the last Stop */ + +/* UNICOMMI2CT_OAR2 Bits */ +/* UNICOMMI2CT_OAR2[OAR2] Bits */ +#define UNICOMMI2CT_OAR2_OAR2_OFS (0) /* !< OAR2 Offset */ +#define UNICOMMI2CT_OAR2_OAR2_MASK ((uint32_t)0x0000007FU) /* !< Own Address 2This field specifies + the alternate OAR2 address. */ +#define UNICOMMI2CT_OAR2_OAR2_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_OAR2_OAR2_MAXIMUM ((uint32_t)0x0000007FU) /* !< Highest possible value */ +/* UNICOMMI2CT_OAR2[OAR2EN] Bits */ +#define UNICOMMI2CT_OAR2_OAR2EN_OFS (7) /* !< OAR2EN Offset */ +#define UNICOMMI2CT_OAR2_OAR2EN_MASK ((uint32_t)0x00000080U) /* !< Own Address 2 Enable */ +#define UNICOMMI2CT_OAR2_OAR2EN_DISABLE ((uint32_t)0x00000000U) /* !< The alternate address is disabled. */ +#define UNICOMMI2CT_OAR2_OAR2EN_ENABLE ((uint32_t)0x00000080U) /* !< Enables the use of the alternate + address in the OAR2 field. */ +/* UNICOMMI2CT_OAR2[OAR2_MASK] Bits */ +#define UNICOMMI2CT_OAR2_OAR2_MASK_OFS (16) /* !< OAR2_MASK Offset */ +#define UNICOMMI2CT_OAR2_OAR2_MASK_MASK ((uint32_t)0x007F0000U) /* !< Own Address 2 Mask: This field + specifies bits A6 through A0 of the + Target address. The bits with value 1 + in SOAR2.OAR2_MASK field will make + the corresponding incoming address + bits to match by default regardless + of the value inside SOAR2.OAR2 i.e. + corresponding SOAR2.OAR2 bit is a + dont care. */ +#define UNICOMMI2CT_OAR2_OAR2_MASK_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum Value */ +#define UNICOMMI2CT_OAR2_OAR2_MASK_MAXIMUM ((uint32_t)0x007F0000U) /* !< Maximum Value */ + +/* UNICOMMI2CT_OAR Bits */ +/* UNICOMMI2CT_OAR[OAR] Bits */ +#define UNICOMMI2CT_OAR_OAR_OFS (0) /* !< OAR Offset */ +#define UNICOMMI2CT_OAR_OAR_MASK ((uint32_t)0x000003FFU) /* !< Own Address: This field specifies + bits A9 through A0 of the Target + address. In 7-bit addressing mode as + selected by I2CSOAR.MODE bit, the top + 3 bits are don't care */ +#define UNICOMMI2CT_OAR_OAR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMI2CT_OAR_OAR_MAXIMUM ((uint32_t)0x000003FFU) /* !< Highest possible value */ +/* UNICOMMI2CT_OAR[OAREN] Bits */ +#define UNICOMMI2CT_OAR_OAREN_OFS (14) /* !< OAREN Offset */ +#define UNICOMMI2CT_OAR_OAREN_MASK ((uint32_t)0x00004000U) /* !< Own Address Enable */ +#define UNICOMMI2CT_OAR_OAREN_DISABLE ((uint32_t)0x00000000U) /* !< Disable OAR address */ +#define UNICOMMI2CT_OAR_OAREN_ENABLE ((uint32_t)0x00004000U) /* !< Enable OAR address */ +/* UNICOMMI2CT_OAR[MODE] Bits */ +#define UNICOMMI2CT_OAR_MODE_OFS (15) /* !< MODE Offset */ +#define UNICOMMI2CT_OAR_MODE_MASK ((uint32_t)0x00008000U) /* !< This bit selects the adressing mode + to be used. When 0, 7-bit addressing + is used. When 1, 10-bit addressing is + used. */ +#define UNICOMMI2CT_OAR_MODE_MODE7 ((uint32_t)0x00000000U) /* !< Enable 7-bit addressing */ +#define UNICOMMI2CT_OAR_MODE_MODE10 ((uint32_t)0x00008000U) /* !< Enable 10-bit addressing */ + +/* UNICOMMI2CT_TIMEOUT_CNT Bits */ +/* UNICOMMI2CT_TIMEOUT_CNT[TCNTA] Bits */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTA_OFS (0) /* !< TCNTA Offset */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTA_MASK ((uint32_t)0x000000FFU) /* !< Timeout Count A Current Count: This + field contains the upper 8 bits of a + 12-bit current counter for timeout + counter A */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest Value */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ +/* UNICOMMI2CT_TIMEOUT_CNT[TCNTB] Bits */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTB_OFS (16) /* !< TCNTB Offset */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTB_MASK ((uint32_t)0x00FF0000U) /* !< Timeout Count B Current Count: This + field contains the upper 8 bits of a + 12-bit current counter for timeout + counter B */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTB_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest Value */ +#define UNICOMMI2CT_TIMEOUT_CNT_TCNTB_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */ + +/* UNICOMMI2CT_TIMEOUT_CTL Bits */ +/* UNICOMMI2CT_TIMEOUT_CTL[TCNTLA] Bits */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLA_OFS (0) /* !< TCNTLA Offset */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLA_MASK ((uint32_t)0x000000FFU) /* !< Timeout counter A load value + Counter A is used for SCL low + detection. This field contains the + upper 8 bits of a 12-bit pre-load + value for the Timeout A count. NOTE: + The value of CNTLA must be greater + than 1h. Each count is equal to 520 + times the timeout period of + functional clock. For example, with + 8MHz functional clock and a 100KHz + operating I2C clock, one timeout + period will be equal to (1 / 8MHz) * + 520 or 65 us. */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest Value */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ +/* UNICOMMI2CT_TIMEOUT_CTL[TCNTAEN] Bits */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_OFS (15) /* !< TCNTAEN Offset */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_MASK ((uint32_t)0x00008000U) /* !< Timeout Counter A Enable */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable Timeout Counter B */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_ENABLE ((uint32_t)0x00008000U) /* !< Enable Timeout Counter B */ +/* UNICOMMI2CT_TIMEOUT_CTL[TCNTLB] Bits */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_OFS (16) /* !< TCNTLB Offset */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_MASK ((uint32_t)0x00FF0000U) /* !< Timeout Count B Load: Counter B is + used for SCL High Detection. This + field contains the upper 8 bits of a + 12-bit pre-load value for the Timeout + B count. NOTE: The value of CNTLB + must be greater than 1h. Each count + is equal to 1* clock period. For + example, with 10MHz functional clock + one timeout period will be equal + to1*100ns. */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest possible value */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */ +/* UNICOMMI2CT_TIMEOUT_CTL[TCNTBEN] Bits */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_OFS (31) /* !< TCNTBEN Offset */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_MASK ((uint32_t)0x80000000U) /* !< Timeout Counter B Enable */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable Timeout Counter B */ +#define UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_ENABLE ((uint32_t)0x80000000U) /* !< Enable Timeout Counter B */ + +/* UNICOMMI2CT_PECCTL Bits */ +/* UNICOMMI2CT_PECCTL[PECCNT] Bits */ +#define UNICOMMI2CT_PECCTL_PECCNT_OFS (0) /* !< PECCNT Offset */ +#define UNICOMMI2CT_PECCTL_PECCNT_MASK ((uint32_t)0x000001FFU) /* !< When this field is non zero, the + number of I2C data bytes are counted. + When the byte count = PECCNT and the + state machine is transmitting, the + contents of the LSFR is loaded into + the shift register instead of the + byte received from the Tx FIFO. When + the state machine is receiving, after + the last bit of this byte is received + the LSFR is checked and if it is + non-zero, a PEC RX Error interrupt is + generated. The I2C packet must be + padded to include the PEC byte for + both transmit and receive. In + transmit mode the FIFO must be loaded + with a dummy PEC byte. In receive + mode the PEC byte will be passed to + the Rx FIFO. In the normal use case, + FW would set PECEN=1 and PECCNT=0 and + use the ACKOEN until the remaining + SMB packet length is known. FW would + then set the PECCNT to the remaining + packet length (Including PEC bye). FW + would then configure DMA to allow the + packet to complete unassisted and + exit NoAck mode. Note that when the + byte count = PEC CNT, the byte count + is reset to 0 and multiple PEC + calculation can automatically occur + within a single I2C transaction */ +#define UNICOMMI2CT_PECCTL_PECCNT_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum Value */ +#define UNICOMMI2CT_PECCTL_PECCNT_MAXIMUM ((uint32_t)0x000001FFU) /* !< Maximum Value */ +/* UNICOMMI2CT_PECCTL[PECEN] Bits */ +#define UNICOMMI2CT_PECCTL_PECEN_OFS (12) /* !< PECEN Offset */ +#define UNICOMMI2CT_PECCTL_PECEN_MASK ((uint32_t)0x00001000U) /* !< PEC Enable This bit enables the SMB + Packet Error Checking (PEC). When + enabled the PEC is calculated on all + bits except the Start, Stop, Ack and + Nack. The PEC LSFR and the Byte + Counter is set to 0 when the State + Machine is in the IDLE state, which + occur following a Stop or when a + timeout occurs. The Counter is also + set to 0 after the PEC byte is sent + or received. Note that the NACK is + automatically send following a PEC + byte that results in a PEC error. The + PEC Polynomial is x^8 + x^2 + x^1 + + 1. */ +#define UNICOMMI2CT_PECCTL_PECEN_DISABLE ((uint32_t)0x00000000U) /* !< PEC transmission and check is + disabled */ +#define UNICOMMI2CT_PECCTL_PECEN_ENABLE ((uint32_t)0x00001000U) /* !< PEC transmission and check is + enabled */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_unicommi2ct__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_unicommspi.h b/mspm0/source/ti/devices/msp/peripherals/hw_unicommspi.h new file mode 100644 index 0000000..b0cf895 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_unicommspi.h @@ -0,0 +1,1369 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_unicommspi__include +#define ti_devices_msp_peripherals_hw_unicommspi__include + +/* Filename: hw_unicommspi.h */ +/* Revised: 2024-06-14 13:21:47 */ +/* Revision: 5bc8734305a9423d65be20daaaf863aee834bedf */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* UNICOMMSPI Registers +******************************************************************************/ +#define UNICOMMSPI_SPGDMA_OFS ((uint32_t)0x000010B0U) +#define UNICOMMSPI_DMA_TRIG_TX_OFS ((uint32_t)0x00001080U) +#define UNICOMMSPI_DMA_TRIG_RX_OFS ((uint32_t)0x00001050U) +#define UNICOMMSPI_CPU_INT_OFS ((uint32_t)0x00001020U) + + +/** @addtogroup UNICOMMSPI_SPGDMA + @{ +*/ + +typedef struct { + uint32_t RESERVED0; + __IO uint32_t SPGDMARXCTL; /* !< (@ 0x000010B4) DMA Channel Control */ + __IO uint32_t SPGDMARXDA; /* !< (@ 0x000010B8) DMA Channel Destination Address */ + __IO uint32_t SPGDMARXSZ; /* !< (@ 0x000010BC) DMA Channel Size */ + uint32_t RESERVED1; + __IO uint32_t SPGDMATXCTL; /* !< (@ 0x000010C4) DMA Channel Control */ + __IO uint32_t SPGDMATXSA; /* !< (@ 0x000010C8) DMA Channel Destination Address */ + __IO uint32_t SPGDMATXSZ; /* !< (@ 0x000010CC) DMA Channel Size */ +} UNICOMMSPI_SPGDMA_Regs; + +/*@}*/ /* end of group UNICOMMSPI_SPGDMA */ + +/** @addtogroup UNICOMMSPI_DMA_TRIG_TX + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001088) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001090) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001098) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x000010A0) Interrupt set */ +} UNICOMMSPI_DMA_TRIG_TX_Regs; + +/*@}*/ /* end of group UNICOMMSPI_DMA_TRIG_TX */ + +/** @addtogroup UNICOMMSPI_DMA_TRIG_RX + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */ +} UNICOMMSPI_DMA_TRIG_RX_Regs; + +/*@}*/ /* end of group UNICOMMSPI_DMA_TRIG_RX */ + +/** @addtogroup UNICOMMSPI_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt Index Register */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */ +} UNICOMMSPI_CPU_INT_Regs; + +/*@}*/ /* end of group UNICOMMSPI_CPU_INT */ + +/** @addtogroup UNICOMMSPI + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + __IO uint32_t CLKDIV; /* !< (@ 0x00001000) Clock Divider */ + uint32_t RESERVED1; + __IO uint32_t CLKSEL; /* !< (@ 0x00001008) Clock Select for Ultra Low Power peripherals */ + uint32_t RESERVED2[3]; + __IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */ + uint32_t RESERVED3; + UNICOMMSPI_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED4; + UNICOMMSPI_DMA_TRIG_RX_Regs DMA_TRIG_RX; /* !< (@ 0x00001050) */ + uint32_t RESERVED5[3]; + UNICOMMSPI_DMA_TRIG_TX_Regs DMA_TRIG_TX; /* !< (@ 0x00001080) */ + uint32_t RESERVED6[3]; + UNICOMMSPI_SPGDMA_Regs SPGDMA; /* !< (@ 0x000010B0) */ + uint32_t RESERVED7[5]; + __O uint32_t INTCTL; /* !< (@ 0x000010E4) Interrupt control register */ + uint32_t RESERVED8[6]; + __IO uint32_t CTL0; /* !< (@ 0x00001100) SPI control register 0 */ + uint32_t RESERVED9; + __I uint32_t STAT; /* !< (@ 0x00001108) Status Register */ + __IO uint32_t IFLS; /* !< (@ 0x0000110C) Interrupt FIFO Level Select Register */ + __IO uint32_t CLKCTL; /* !< (@ 0x00001110) Clock prescaler and divider register. */ + uint32_t RESERVED10[3]; + __O uint32_t TXDATA; /* !< (@ 0x00001120) TXDATA Register */ + __I uint32_t RXDATA; /* !< (@ 0x00001124) RXDATA Register */ + uint32_t RESERVED11[9]; + __IO uint32_t CTL1; /* !< (@ 0x0000114C) SPI control register 1 */ +} UNICOMMSPI_Regs; + +/*@}*/ /* end of group UNICOMMSPI */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* UNICOMMSPI Register Control Bits +******************************************************************************/ + +/* UNICOMMSPI_SPGDMARXCTL Bits */ +/* UNICOMMSPI_SPGDMARXCTL[DMAEN] Bits */ +#define UNICOMMSPI_SPGDMARXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMSPI_SPGDMARXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMSPI_SPGDMARXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMSPI_SPGDMARXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMSPI_SPGDMARXCTL[DMAMEMINCR] Bits */ +#define UNICOMMSPI_SPGDMARXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMSPI_SPGDMARXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMSPI_SPGDMARXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMADSTWDTH) */ +#define UNICOMMSPI_SPGDMARXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMADSTWDTH) */ +/* UNICOMMSPI_SPGDMARXCTL[DMAPREIRQ] Bits */ +#define UNICOMMSPI_SPGDMARXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMSPI_SPGDMARXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMSPI_SPGDMARXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMSPI_SPGDMARXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMSPI_SPGDMARXCTL[DMATM] Bits */ +#define UNICOMMSPI_SPGDMARXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMSPI_SPGDMARXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register */ +#define UNICOMMSPI_SPGDMARXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMSPI_SPGDMARXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMSPI_SPGDMARXCTL[DMADSTWDTH] Bits */ +#define UNICOMMSPI_SPGDMARXCTL_DMADSTWDTH_OFS (28) /* !< DMADSTWDTH Offset */ +#define UNICOMMSPI_SPGDMARXCTL_DMADSTWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA destination width. This bit + selects the destination as a byte, + half word, word or long word. */ +#define UNICOMMSPI_SPGDMARXCTL_DMADSTWDTH_BYTE ((uint32_t)0x00000000U) /* !< Destination data width is BYTE + (8-bit) */ +#define UNICOMMSPI_SPGDMARXCTL_DMADSTWDTH_HALF ((uint32_t)0x10000000U) /* !< Destination data width is HALF-WORD + (16-bit) */ +#define UNICOMMSPI_SPGDMARXCTL_DMADSTWDTH_WORD ((uint32_t)0x20000000U) /* !< Destination data width is WORD + (32-bit) */ + +/* UNICOMMSPI_SPGDMARXDA Bits */ +/* UNICOMMSPI_SPGDMARXDA[ADDR] Bits */ +#define UNICOMMSPI_SPGDMARXDA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMSPI_SPGDMARXDA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMSPI_SPGDMARXDA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_SPGDMARXDA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMSPI_SPGDMARXSZ Bits */ +/* UNICOMMSPI_SPGDMARXSZ[SIZE] Bits */ +#define UNICOMMSPI_SPGDMARXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMSPI_SPGDMARXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMSPI_SPGDMARXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_SPGDMARXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMSPI_SPGDMATXCTL Bits */ +/* UNICOMMSPI_SPGDMATXCTL[DMAEN] Bits */ +#define UNICOMMSPI_SPGDMATXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMSPI_SPGDMATXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMSPI_SPGDMATXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMSPI_SPGDMATXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMSPI_SPGDMATXCTL[DMAMEMINCR] Bits */ +#define UNICOMMSPI_SPGDMATXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMSPI_SPGDMATXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMSPI_SPGDMATXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMASRCWDTH) */ +#define UNICOMMSPI_SPGDMATXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMASRCWDTH) */ +/* UNICOMMSPI_SPGDMATXCTL[DMAPREIRQ] Bits */ +#define UNICOMMSPI_SPGDMATXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMSPI_SPGDMATXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMSPI_SPGDMATXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMSPI_SPGDMATXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMSPI_SPGDMATXCTL[DMATM] Bits */ +#define UNICOMMSPI_SPGDMATXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMSPI_SPGDMATXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register Note: + The repeat-single (2h) and + repeat-block (3h) transfer are only + available in a FULL-channel + configuration. Please consult the + datasheet of the specific device to + map which channel number has FULL or + BASIC capability. In a BASIC channel + configuration only the values for + single (0h) and block (1h) transfer + can be set. */ +#define UNICOMMSPI_SPGDMATXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMSPI_SPGDMATXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMSPI_SPGDMATXCTL[DMASRCWDTH] Bits */ +#define UNICOMMSPI_SPGDMATXCTL_DMASRCWDTH_OFS (28) /* !< DMASRCWDTH Offset */ +#define UNICOMMSPI_SPGDMATXCTL_DMASRCWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA source width. This bit selects + the source data width as a byte, half + word, word or long word. */ +#define UNICOMMSPI_SPGDMATXCTL_DMASRCWDTH_BYTE ((uint32_t)0x00000000U) /* !< Source data width is BYTE (8-bit) */ +#define UNICOMMSPI_SPGDMATXCTL_DMASRCWDTH_HALF ((uint32_t)0x10000000U) /* !< Source data width is HALF-WORD + (16-bit) */ +#define UNICOMMSPI_SPGDMATXCTL_DMASRCWDTH_WORD ((uint32_t)0x20000000U) /* !< Source data width is WORD (32-bit) */ + +/* UNICOMMSPI_SPGDMATXSA Bits */ +/* UNICOMMSPI_SPGDMATXSA[ADDR] Bits */ +#define UNICOMMSPI_SPGDMATXSA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMSPI_SPGDMATXSA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMSPI_SPGDMATXSA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_SPGDMATXSA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMSPI_SPGDMATXSZ Bits */ +/* UNICOMMSPI_SPGDMATXSZ[SIZE] Bits */ +#define UNICOMMSPI_SPGDMATXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMSPI_SPGDMATXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMSPI_SPGDMATXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_SPGDMATXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMSPI_DMA_TRIG_TX_IMASK Bits */ +/* UNICOMMSPI_DMA_TRIG_TX_IMASK[TX] Bits */ +#define UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO event mask. */ +#define UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_SET ((uint32_t)0x00000020U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_DMA_TRIG_TX_RIS Bits */ +/* UNICOMMSPI_DMA_TRIG_TX_RIS[TX] Bits */ +#define UNICOMMSPI_DMA_TRIG_TX_RIS_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_DMA_TRIG_TX_RIS_TX_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO event: A read returns + the current mask for transmit FIFO + interrupt. On a write of 1, the mask + for transmit FIFO interrupt is set + which means the interrupt state will + be reflected in MIS.TXMIS. A write of + 0 clears the mask which means + MIS.TXMIS will not reflect the + interrupt. */ +#define UNICOMMSPI_DMA_TRIG_TX_RIS_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_DMA_TRIG_TX_RIS_TX_SET ((uint32_t)0x00000020U) /* !< Interrupt occurred */ + +/* UNICOMMSPI_DMA_TRIG_TX_MIS Bits */ +/* UNICOMMSPI_DMA_TRIG_TX_MIS[TX] Bits */ +#define UNICOMMSPI_DMA_TRIG_TX_MIS_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_DMA_TRIG_TX_MIS_TX_MASK ((uint32_t)0x00000020U) /* !< Masked Transmit FIFO event */ +#define UNICOMMSPI_DMA_TRIG_TX_MIS_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_DMA_TRIG_TX_MIS_TX_SET ((uint32_t)0x00000020U) /* !< Interrupt occurred */ + +/* UNICOMMSPI_DMA_TRIG_TX_ISET Bits */ +/* UNICOMMSPI_DMA_TRIG_TX_ISET[TX] Bits */ +#define UNICOMMSPI_DMA_TRIG_TX_ISET_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_DMA_TRIG_TX_ISET_TX_MASK ((uint32_t)0x00000020U) /* !< Set Transmit FIFO event. */ +#define UNICOMMSPI_DMA_TRIG_TX_ISET_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_DMA_TRIG_TX_ISET_TX_SET ((uint32_t)0x00000020U) /* !< Set Interrupt */ + +/* UNICOMMSPI_DMA_TRIG_RX_IMASK Bits */ +/* UNICOMMSPI_DMA_TRIG_RX_IMASK[RX] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RX_MASK ((uint32_t)0x00000004U) /* !< Receive FIFO event mask. */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RX_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RX_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_DMA_TRIG_RX_IMASK[RTOUT] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RTOUT_MASK ((uint32_t)0x00000200U) /* !< SPI Receive Time-Out event mask. */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_DMA_TRIG_RX_IMASK_RTOUT_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_DMA_TRIG_RX_RIS Bits */ +/* UNICOMMSPI_DMA_TRIG_RX_RIS[RX] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RX_MASK ((uint32_t)0x00000004U) /* !< Receive FIFO event.This interrupt + is set if the selected Receive FIFO + level has been reached */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RX_SET ((uint32_t)0x00000004U) /* !< Interrupt occurred */ +/* UNICOMMSPI_DMA_TRIG_RX_RIS[RTOUT] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RTOUT_MASK ((uint32_t)0x00000200U) /* !< SPI Receive Time-Out Event. This + bit is set when there is still + contents in the FIFO after the + timeout period */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_DMA_TRIG_RX_RIS_RTOUT_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_DMA_TRIG_RX_MIS Bits */ +/* UNICOMMSPI_DMA_TRIG_RX_MIS[RX] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RX_MASK ((uint32_t)0x00000004U) /* !< Receive FIFO event mask. */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RX_SET ((uint32_t)0x00000004U) /* !< Interrupt occurred */ +/* UNICOMMSPI_DMA_TRIG_RX_MIS[RTOUT] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RTOUT_MASK ((uint32_t)0x00000200U) /* !< SPI Receive Time-Out event mask. */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_DMA_TRIG_RX_MIS_RTOUT_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_DMA_TRIG_RX_ISET Bits */ +/* UNICOMMSPI_DMA_TRIG_RX_ISET[RX] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RX_MASK ((uint32_t)0x00000004U) /* !< Set Receive FIFO event. */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RX_SET ((uint32_t)0x00000004U) /* !< Set Interrupt */ +/* UNICOMMSPI_DMA_TRIG_RX_ISET[RTOUT] Bits */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RTOUT_MASK ((uint32_t)0x00000200U) /* !< Set SPI Receive Time-Out event. */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_DMA_TRIG_RX_ISET_RTOUT_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_IIDX Bits */ +/* UNICOMMSPI_IIDX[STAT] Bits */ +#define UNICOMMSPI_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define UNICOMMSPI_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */ +#define UNICOMMSPI_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define UNICOMMSPI_IIDX_STAT_PER_EVT ((uint32_t)0x00000001U) /* !< Transmit Parity Event/interrupt + pending */ +#define UNICOMMSPI_IIDX_STAT_RXFIFO_OFV_EVT ((uint32_t)0x00000002U) /* !< RX FIFO Overflow Event/interrupt + pending */ +#define UNICOMMSPI_IIDX_STAT_RX_EVT ((uint32_t)0x00000003U) /* !< Receive interrupt */ +#define UNICOMMSPI_IIDX_STAT_RXFULL_EVT ((uint32_t)0x00000004U) /* !< RX FIFO Full Interrupt */ +#define UNICOMMSPI_IIDX_STAT_TXFIFO_UNF_EVT ((uint32_t)0x00000005U) /* !< TX FIFO underflow interrupt */ +#define UNICOMMSPI_IIDX_STAT_TX_EVT ((uint32_t)0x00000006U) /* !< Transmit Event */ +#define UNICOMMSPI_IIDX_STAT_TX_EMPTY ((uint32_t)0x00000007U) /* !< Transmit Buffer Empty + Event/interrupt pending */ +#define UNICOMMSPI_IIDX_STAT_IDLE_EVT ((uint32_t)0x00000009U) /* !< End of Transmit Event/interrupt + pending */ +#define UNICOMMSPI_IIDX_STAT_RTOUT_EVT ((uint32_t)0x0000000AU) /* !< SPI receive time-out interrupt */ +#define UNICOMMSPI_IIDX_STAT_DMA_DONE_RX ((uint32_t)0x00000010U) /* !< DMA DONE on RX */ +#define UNICOMMSPI_IIDX_STAT_DMA_DONE_TX ((uint32_t)0x00000011U) /* !< DMA DONE on TX */ +#define UNICOMMSPI_IIDX_STAT_DMA_PREIRQ_RX ((uint32_t)0x00000013U) /* !< DMA PRE IRQ RX INTERRUPT */ +#define UNICOMMSPI_IIDX_STAT_DMA_PREIRQ_TX ((uint32_t)0x00000014U) /* !< DMA PRE IRQ TX INTERRUPT */ +#define UNICOMMSPI_IIDX_STAT_LTOUT ((uint32_t)0x00000015U) /* !< SPI line time-out interrupt */ + +/* UNICOMMSPI_CPU_INT_IMASK Bits */ +/* UNICOMMSPI_CPU_INT_IMASK[RX] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_RX_MASK ((uint32_t)0x00000004U) /* !< Mask Receive Event */ +#define UNICOMMSPI_CPU_INT_IMASK_RX_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_RX_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[TX] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_TX_MASK ((uint32_t)0x00000020U) /* !< Mask Transmit Event */ +#define UNICOMMSPI_CPU_INT_IMASK_TX_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_TX_SET ((uint32_t)0x00000020U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[TXEMPTY] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_TXEMPTY_OFS (6) /* !< TXEMPTY Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_TXEMPTY_MASK ((uint32_t)0x00000040U) /* !< Transmit FIFO Empty event mask. */ +#define UNICOMMSPI_CPU_INT_IMASK_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_TXEMPTY_SET ((uint32_t)0x00000040U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[PER] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_PER_OFS (0) /* !< PER Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_PER_MASK ((uint32_t)0x00000001U) /* !< Parity error event mask. */ +#define UNICOMMSPI_CPU_INT_IMASK_PER_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_PER_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[RXFIFO_OVF] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFIFO_OVF_OFS (1) /* !< RXFIFO_OVF Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFIFO_OVF_MASK ((uint32_t)0x00000002U) /* !< RXFIFO overflow event mask. */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFIFO_OVF_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFIFO_OVF_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[IDLE] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_IDLE_OFS (8) /* !< IDLE Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_IDLE_MASK ((uint32_t)0x00000100U) /* !< SPI Idle event mask. */ +#define UNICOMMSPI_CPU_INT_IMASK_IDLE_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_IDLE_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[RTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_RTOUT_MASK ((uint32_t)0x00000200U) /* !< Enable SPI Receive Time-Out event + mask. */ +#define UNICOMMSPI_CPU_INT_IMASK_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_RTOUT_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[RXFULL] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFULL_OFS (3) /* !< RXFULL Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFULL_MASK ((uint32_t)0x00000008U) /* !< RX FIFO Full Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_RXFULL_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[TXFIFO_UNF] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< TX FIFO underflow interrupt mask */ +#define UNICOMMSPI_CPU_INT_IMASK_TXFIFO_UNF_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[DMA_DONE_RX] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Enable DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[DMA_DONE_TX] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Enable DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[DMA_PREIRQ_RX] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Enable DMA Done PREIRQ RX interrupt */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[DMA_PREIRQ_TX] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Enable DMA Done PREIRQ TX interrupt */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_IMASK[LTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_IMASK_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMSPI_CPU_INT_IMASK_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Enable SPI Line Time-Out event + mask. */ +#define UNICOMMSPI_CPU_INT_IMASK_LTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_IMASK_LTOUT_SET ((uint32_t)0x00100000U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_CPU_INT_RIS Bits */ +/* UNICOMMSPI_CPU_INT_RIS[RX] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_CPU_INT_RIS_RX_MASK ((uint32_t)0x00000004U) /* !< Receive event When FIFO is present, + this bit is set when FIFO threshold + is reached When FIFO is not present, + this bit is set when a frame is + received */ +#define UNICOMMSPI_CPU_INT_RIS_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_RX_SET ((uint32_t)0x00000004U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[TX] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_CPU_INT_RIS_TX_MASK ((uint32_t)0x00000020U) /* !< Transmit event When FIFO is + present, this bit is set when Tx FIFO + threshold is reached When FIFO is not + present, this bit is set when tx + buffer is empty */ +#define UNICOMMSPI_CPU_INT_RIS_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_TX_SET ((uint32_t)0x00000020U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[TXEMPTY] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_TXEMPTY_OFS (6) /* !< TXEMPTY Offset */ +#define UNICOMMSPI_CPU_INT_RIS_TXEMPTY_MASK ((uint32_t)0x00000040U) /* !< Transmit FIFO Empty interrupt mask. + This interrupt is set if all data in + the Transmit FIFO have been move to + the shift register. */ +#define UNICOMMSPI_CPU_INT_RIS_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_TXEMPTY_SET ((uint32_t)0x00000040U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[PER] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_PER_OFS (0) /* !< PER Offset */ +#define UNICOMMSPI_CPU_INT_RIS_PER_MASK ((uint32_t)0x00000001U) /* !< Parity error event: this bit is set + if a Parity error has been detected */ +#define UNICOMMSPI_CPU_INT_RIS_PER_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_PER_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[RXFIFO_OVF] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_RXFIFO_OVF_OFS (1) /* !< RXFIFO_OVF Offset */ +#define UNICOMMSPI_CPU_INT_RIS_RXFIFO_OVF_MASK ((uint32_t)0x00000002U) /* !< RXFIFO overflow event. This + interrupt is set if an RX FIFO + overflow has been detected. */ +#define UNICOMMSPI_CPU_INT_RIS_RXFIFO_OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_RXFIFO_OVF_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[IDLE] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_IDLE_OFS (8) /* !< IDLE Offset */ +#define UNICOMMSPI_CPU_INT_RIS_IDLE_MASK ((uint32_t)0x00000100U) /* !< SPI has done finished transfers and + changed into IDLE mode. This bit is + set when BUSY goes low. */ +#define UNICOMMSPI_CPU_INT_RIS_IDLE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_IDLE_SET ((uint32_t)0x00000100U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[RTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_CPU_INT_RIS_RTOUT_MASK ((uint32_t)0x00000200U) /* !< SPI Receive Time-Out event. This + bit is set when there is still + contents in the FIFO after the + timeout period */ +#define UNICOMMSPI_CPU_INT_RIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_RTOUT_SET ((uint32_t)0x00000200U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[TXFIFO_UNF] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define UNICOMMSPI_CPU_INT_RIS_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< TX FIFO Underflow Interrupt */ +#define UNICOMMSPI_CPU_INT_RIS_TXFIFO_UNF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[RXFULL] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_RXFULL_OFS (3) /* !< RXFULL Offset */ +#define UNICOMMSPI_CPU_INT_RIS_RXFULL_MASK ((uint32_t)0x00000008U) /* !< RX FIFO Full Interrupt */ +#define UNICOMMSPI_CPU_INT_RIS_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_RXFULL_SET ((uint32_t)0x00000008U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_RIS[DMA_DONE_RX] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_RIS[DMA_DONE_TX] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_RIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_RIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_RIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_RIS[LTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_RIS_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMSPI_CPU_INT_RIS_LTOUT_MASK ((uint32_t)0x00100000U) /* !< SPI Line Time-Out event. This bit + is set after timeout period has + lapsed */ +#define UNICOMMSPI_CPU_INT_RIS_LTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_RIS_LTOUT_SET ((uint32_t)0x00100000U) /* !< Interrupt occurred */ + +/* UNICOMMSPI_CPU_INT_MIS Bits */ +/* UNICOMMSPI_CPU_INT_MIS[RX] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_CPU_INT_MIS_RX_MASK ((uint32_t)0x00000004U) /* !< Masked Receive Event */ +#define UNICOMMSPI_CPU_INT_MIS_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_RX_SET ((uint32_t)0x00000004U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[TX] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_CPU_INT_MIS_TX_MASK ((uint32_t)0x00000020U) /* !< Masked Transmit FIFO event. This + interrupt is set if the selected + Transmit FIFO level has been reached. */ +#define UNICOMMSPI_CPU_INT_MIS_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_TX_SET ((uint32_t)0x00000020U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[TXEMPTY] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_TXEMPTY_OFS (6) /* !< TXEMPTY Offset */ +#define UNICOMMSPI_CPU_INT_MIS_TXEMPTY_MASK ((uint32_t)0x00000040U) /* !< Masked Transmit FIFO Empty event. */ +#define UNICOMMSPI_CPU_INT_MIS_TXEMPTY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_TXEMPTY_SET ((uint32_t)0x00000040U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[PER] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_PER_OFS (0) /* !< PER Offset */ +#define UNICOMMSPI_CPU_INT_MIS_PER_MASK ((uint32_t)0x00000001U) /* !< Masked Parity error event: this bit + if a Parity error has been detected */ +#define UNICOMMSPI_CPU_INT_MIS_PER_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_PER_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[RXFIFO_OVF] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_RXFIFO_OVF_OFS (1) /* !< RXFIFO_OVF Offset */ +#define UNICOMMSPI_CPU_INT_MIS_RXFIFO_OVF_MASK ((uint32_t)0x00000002U) /* !< Masked RXFIFO overflow event. This + interrupt is set if an RX FIFO + overflow has been detected. */ +#define UNICOMMSPI_CPU_INT_MIS_RXFIFO_OVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_RXFIFO_OVF_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[IDLE] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_IDLE_OFS (8) /* !< IDLE Offset */ +#define UNICOMMSPI_CPU_INT_MIS_IDLE_MASK ((uint32_t)0x00000100U) /* !< Masked SPI IDLE mode event. */ +#define UNICOMMSPI_CPU_INT_MIS_IDLE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_IDLE_SET ((uint32_t)0x00000100U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[RTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_CPU_INT_MIS_RTOUT_MASK ((uint32_t)0x00000200U) /* !< Masked SPI Receive Time-Out + Interrupt. */ +#define UNICOMMSPI_CPU_INT_MIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_MIS_RTOUT_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_MIS[RXFULL] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_RXFULL_OFS (3) /* !< RXFULL Offset */ +#define UNICOMMSPI_CPU_INT_MIS_RXFULL_MASK ((uint32_t)0x00000008U) /* !< RX FIFO Full Interrupt */ +#define UNICOMMSPI_CPU_INT_MIS_RXFULL_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_RXFULL_SET ((uint32_t)0x00000008U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[TXFIFO_UNF] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define UNICOMMSPI_CPU_INT_MIS_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< TX FIFO underflow interrupt */ +#define UNICOMMSPI_CPU_INT_MIS_TXFIFO_UNF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Interrupt occurred */ +/* UNICOMMSPI_CPU_INT_MIS[DMA_DONE_RX] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Masked DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_MIS[DMA_DONE_TX] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Masked DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_MIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_RX_OFS (19) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00080000U) /* !< Masked DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_MIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_TX_OFS (18) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00040000U) /* !< Masked DMA Done PREIRQ on TX Event + Channel Interrupt */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMSPI_CPU_INT_MIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* UNICOMMSPI_CPU_INT_MIS[LTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_MIS_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMSPI_CPU_INT_MIS_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Masked SPI Line Time-Out Interrupt. */ +#define UNICOMMSPI_CPU_INT_MIS_LTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMSPI_CPU_INT_MIS_LTOUT_SET ((uint32_t)0x00100000U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_CPU_INT_ISET Bits */ +/* UNICOMMSPI_CPU_INT_ISET[RX] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_CPU_INT_ISET_RX_MASK ((uint32_t)0x00000004U) /* !< Set Receive event. */ +#define UNICOMMSPI_CPU_INT_ISET_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_RX_SET ((uint32_t)0x00000004U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[TX] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_CPU_INT_ISET_TX_MASK ((uint32_t)0x00000020U) /* !< Set Transmit event. */ +#define UNICOMMSPI_CPU_INT_ISET_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_TX_SET ((uint32_t)0x00000020U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[TXEMPTY] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_TXEMPTY_OFS (6) /* !< TXEMPTY Offset */ +#define UNICOMMSPI_CPU_INT_ISET_TXEMPTY_MASK ((uint32_t)0x00000040U) /* !< Set Transmit FIFO Empty event. */ +#define UNICOMMSPI_CPU_INT_ISET_TXEMPTY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_TXEMPTY_SET ((uint32_t)0x00000040U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[PER] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_PER_OFS (0) /* !< PER Offset */ +#define UNICOMMSPI_CPU_INT_ISET_PER_MASK ((uint32_t)0x00000001U) /* !< Set Parity error event. */ +#define UNICOMMSPI_CPU_INT_ISET_PER_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_PER_SET ((uint32_t)0x00000001U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[RXFIFO_OVF] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_RXFIFO_OVF_OFS (1) /* !< RXFIFO_OVF Offset */ +#define UNICOMMSPI_CPU_INT_ISET_RXFIFO_OVF_MASK ((uint32_t)0x00000002U) /* !< Set RXFIFO overflow event. */ +#define UNICOMMSPI_CPU_INT_ISET_RXFIFO_OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_RXFIFO_OVF_SET ((uint32_t)0x00000002U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[IDLE] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_IDLE_OFS (8) /* !< IDLE Offset */ +#define UNICOMMSPI_CPU_INT_ISET_IDLE_MASK ((uint32_t)0x00000100U) /* !< Set SPI IDLE mode event. */ +#define UNICOMMSPI_CPU_INT_ISET_IDLE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_IDLE_SET ((uint32_t)0x00000100U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[RTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_CPU_INT_ISET_RTOUT_MASK ((uint32_t)0x00000200U) /* !< Set SPI Receive Time-Out Event. */ +#define UNICOMMSPI_CPU_INT_ISET_RTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_RTOUT_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_CPU_INT_ISET[TXFIFO_UNF] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define UNICOMMSPI_CPU_INT_ISET_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< Set TX FIFO Underflow Event */ +#define UNICOMMSPI_CPU_INT_ISET_TXFIFO_UNF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_TXFIFO_UNF_SET ((uint32_t)0x00000010U) /* !< Set interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[RXFULL] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_RXFULL_OFS (3) /* !< RXFULL Offset */ +#define UNICOMMSPI_CPU_INT_ISET_RXFULL_MASK ((uint32_t)0x00000008U) /* !< Set RX FIFO Full Event */ +#define UNICOMMSPI_CPU_INT_ISET_RXFULL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_RXFULL_SET ((uint32_t)0x00000008U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[DMA_DONE_RX] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Set DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[DMA_DONE_TX] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Set DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[DMA_PREIRQ_RX] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Set DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[DMA_PREIRQ_TX] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Set DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_CPU_INT_ISET_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt */ +/* UNICOMMSPI_CPU_INT_ISET[LTOUT] Bits */ +#define UNICOMMSPI_CPU_INT_ISET_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMSPI_CPU_INT_ISET_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Set SPI Line Time-Out Event. */ +#define UNICOMMSPI_CPU_INT_ISET_LTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_CPU_INT_ISET_LTOUT_SET ((uint32_t)0x00100000U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_ICLR Bits */ +/* UNICOMMSPI_ICLR[RX] Bits */ +#define UNICOMMSPI_ICLR_RX_OFS (2) /* !< RX Offset */ +#define UNICOMMSPI_ICLR_RX_MASK ((uint32_t)0x00000004U) /* !< Clear Receive event. */ +#define UNICOMMSPI_ICLR_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_RX_CLR ((uint32_t)0x00000004U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[TX] Bits */ +#define UNICOMMSPI_ICLR_TX_OFS (5) /* !< TX Offset */ +#define UNICOMMSPI_ICLR_TX_MASK ((uint32_t)0x00000020U) /* !< Clear Transmit event. */ +#define UNICOMMSPI_ICLR_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_TX_CLR ((uint32_t)0x00000020U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[TXEMPTY] Bits */ +#define UNICOMMSPI_ICLR_TXEMPTY_OFS (6) /* !< TXEMPTY Offset */ +#define UNICOMMSPI_ICLR_TXEMPTY_MASK ((uint32_t)0x00000040U) /* !< Clear Transmit FIFO Empty event. */ +#define UNICOMMSPI_ICLR_TXEMPTY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_TXEMPTY_CLR ((uint32_t)0x00000040U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[PER] Bits */ +#define UNICOMMSPI_ICLR_PER_OFS (0) /* !< PER Offset */ +#define UNICOMMSPI_ICLR_PER_MASK ((uint32_t)0x00000001U) /* !< Clear Parity error event. */ +#define UNICOMMSPI_ICLR_PER_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_PER_CLR ((uint32_t)0x00000001U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[RXFIFO_OVF] Bits */ +#define UNICOMMSPI_ICLR_RXFIFO_OVF_OFS (1) /* !< RXFIFO_OVF Offset */ +#define UNICOMMSPI_ICLR_RXFIFO_OVF_MASK ((uint32_t)0x00000002U) /* !< Clear RXFIFO overflow event. */ +#define UNICOMMSPI_ICLR_RXFIFO_OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_RXFIFO_OVF_CLR ((uint32_t)0x00000002U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[IDLE] Bits */ +#define UNICOMMSPI_ICLR_IDLE_OFS (8) /* !< IDLE Offset */ +#define UNICOMMSPI_ICLR_IDLE_MASK ((uint32_t)0x00000100U) /* !< Clear SPI IDLE mode event. */ +#define UNICOMMSPI_ICLR_IDLE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_IDLE_CLR ((uint32_t)0x00000100U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[RTOUT] Bits */ +#define UNICOMMSPI_ICLR_RTOUT_OFS (9) /* !< RTOUT Offset */ +#define UNICOMMSPI_ICLR_RTOUT_MASK ((uint32_t)0x00000200U) /* !< Clear SPI Receive Time-Out Event. */ +#define UNICOMMSPI_ICLR_RTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_RTOUT_CLR ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMSPI_ICLR[TXFIFO_UNF] Bits */ +#define UNICOMMSPI_ICLR_TXFIFO_UNF_OFS (4) /* !< TXFIFO_UNF Offset */ +#define UNICOMMSPI_ICLR_TXFIFO_UNF_MASK ((uint32_t)0x00000010U) /* !< Clear TXFIFO underflow event */ +#define UNICOMMSPI_ICLR_TXFIFO_UNF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing has no effect */ +#define UNICOMMSPI_ICLR_TXFIFO_UNF_CLR ((uint32_t)0x00000010U) /* !< Clear interrupt */ +/* UNICOMMSPI_ICLR[RXFULL] Bits */ +#define UNICOMMSPI_ICLR_RXFULL_OFS (3) /* !< RXFULL Offset */ +#define UNICOMMSPI_ICLR_RXFULL_MASK ((uint32_t)0x00000008U) /* !< Clear RX FIFO underflow event */ +#define UNICOMMSPI_ICLR_RXFULL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing has no effect */ +#define UNICOMMSPI_ICLR_RXFULL_CLR ((uint32_t)0x00000008U) /* !< Clear interrupt */ +/* UNICOMMSPI_ICLR[DMA_DONE_RX] Bits */ +#define UNICOMMSPI_ICLR_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMSPI_ICLR_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Clear DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMSPI_ICLR_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_ICLR_DMA_DONE_RX_CLR ((uint32_t)0x00008000U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[DMA_DONE_TX] Bits */ +#define UNICOMMSPI_ICLR_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMSPI_ICLR_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Clear DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMSPI_ICLR_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_ICLR_DMA_DONE_TX_CLR ((uint32_t)0x00010000U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[DMA_PREIRQ_RX] Bits */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Clear DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_RX_CLR ((uint32_t)0x00040000U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[DMA_PREIRQ_TX] Bits */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Clear DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMSPI_ICLR_DMA_PREIRQ_TX_CLR ((uint32_t)0x00080000U) /* !< Clear Interrupt */ +/* UNICOMMSPI_ICLR[LTOUT] Bits */ +#define UNICOMMSPI_ICLR_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMSPI_ICLR_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Clear SPI Line Time-Out Event. */ +#define UNICOMMSPI_ICLR_LTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMSPI_ICLR_LTOUT_CLR ((uint32_t)0x00100000U) /* !< Set Interrupt Mask */ + +/* UNICOMMSPI_CLKDIV Bits */ +/* UNICOMMSPI_CLKDIV[RATIO] Bits */ +#define UNICOMMSPI_CLKDIV_RATIO_OFS (0) /* !< RATIO Offset */ +#define UNICOMMSPI_CLKDIV_RATIO_MASK ((uint32_t)0x00000007U) /* !< Selects divide ratio of module + clock */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_1 ((uint32_t)0x00000000U) /* !< Do not divide clock source */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_2 ((uint32_t)0x00000001U) /* !< Divide clock source by 2 */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_3 ((uint32_t)0x00000002U) /* !< Divide clock source by 3 */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_4 ((uint32_t)0x00000003U) /* !< Divide clock source by 4 */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_5 ((uint32_t)0x00000004U) /* !< Divide clock source by 5 */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_6 ((uint32_t)0x00000005U) /* !< Divide clock source by 6 */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_7 ((uint32_t)0x00000006U) /* !< Divide clock source by 7 */ +#define UNICOMMSPI_CLKDIV_RATIO_DIV_BY_8 ((uint32_t)0x00000007U) /* !< Divide clock source by 8 */ + +/* UNICOMMSPI_CLKSEL Bits */ +/* UNICOMMSPI_CLKSEL[LFCLK_SEL] Bits */ +#define UNICOMMSPI_CLKSEL_LFCLK_SEL_OFS (1) /* !< LFCLK_SEL Offset */ +#define UNICOMMSPI_CLKSEL_LFCLK_SEL_MASK ((uint32_t)0x00000002U) /* !< Selects LFCLK as clock source if + enabled */ +#define UNICOMMSPI_CLKSEL_LFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMSPI_CLKSEL_LFCLK_SEL_ENABLE ((uint32_t)0x00000002U) /* !< Select this clock as a source */ +/* UNICOMMSPI_CLKSEL[MFCLK_SEL] Bits */ +#define UNICOMMSPI_CLKSEL_MFCLK_SEL_OFS (2) /* !< MFCLK_SEL Offset */ +#define UNICOMMSPI_CLKSEL_MFCLK_SEL_MASK ((uint32_t)0x00000004U) /* !< Selects MFCLK as clock source if + enabled */ +#define UNICOMMSPI_CLKSEL_MFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMSPI_CLKSEL_MFCLK_SEL_ENABLE ((uint32_t)0x00000004U) /* !< Select this clock as a source */ +/* UNICOMMSPI_CLKSEL[BUSCLK_SEL] Bits */ +#define UNICOMMSPI_CLKSEL_BUSCLK_SEL_OFS (3) /* !< BUSCLK_SEL Offset */ +#define UNICOMMSPI_CLKSEL_BUSCLK_SEL_MASK ((uint32_t)0x00000008U) /* !< Selects buscclk as clock source if + enabled */ +#define UNICOMMSPI_CLKSEL_BUSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMSPI_CLKSEL_BUSCLK_SEL_ENABLE ((uint32_t)0x00000008U) /* !< Select this clock as a source */ +/* UNICOMMSPI_CLKSEL[ASYNC_SYSCLK_SEL] Bits */ +#define UNICOMMSPI_CLKSEL_ASYNC_SYSCLK_SEL_OFS (9) /* !< ASYNC_SYSCLK_SEL Offset */ +#define UNICOMMSPI_CLKSEL_ASYNC_SYSCLK_SEL_MASK ((uint32_t)0x00000200U) /* !< Asynchronous sys clock selected as + source */ +#define UNICOMMSPI_CLKSEL_ASYNC_SYSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMSPI_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE ((uint32_t)0x00000200U) /* !< Select this clock as a source */ +/* UNICOMMSPI_CLKSEL[ASYNC_HFCLK_SEL] Bits */ +#define UNICOMMSPI_CLKSEL_ASYNC_HFCLK_SEL_OFS (10) /* !< ASYNC_HFCLK_SEL Offset */ +#define UNICOMMSPI_CLKSEL_ASYNC_HFCLK_SEL_MASK ((uint32_t)0x00000400U) /* !< Asynchronous HFCLK selected as + source */ +#define UNICOMMSPI_CLKSEL_ASYNC_HFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMSPI_CLKSEL_ASYNC_HFCLK_SEL_ENABLE ((uint32_t)0x00000400U) /* !< Select this clock as a source */ +/* UNICOMMSPI_CLKSEL[ASYNC_PLL_SEL] Bits */ +#define UNICOMMSPI_CLKSEL_ASYNC_PLL_SEL_OFS (11) /* !< ASYNC_PLL_SEL Offset */ +#define UNICOMMSPI_CLKSEL_ASYNC_PLL_SEL_MASK ((uint32_t)0x00000800U) /* !< Asynchronous PLL selected as source */ +#define UNICOMMSPI_CLKSEL_ASYNC_PLL_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMSPI_CLKSEL_ASYNC_PLL_SEL_ENABLE ((uint32_t)0x00000800U) /* !< Select this clock as a source */ +/* UNICOMMSPI_CLKSEL[ASYNC_LFCLK_SEL] Bits */ +#define UNICOMMSPI_CLKSEL_ASYNC_LFCLK_SEL_OFS (8) /* !< ASYNC_LFCLK_SEL Offset */ +#define UNICOMMSPI_CLKSEL_ASYNC_LFCLK_SEL_MASK ((uint32_t)0x00000100U) /* !< Asynchronous lfclk selected as + source */ +#define UNICOMMSPI_CLKSEL_ASYNC_LFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMSPI_CLKSEL_ASYNC_LFCLK_SEL_ENABLE ((uint32_t)0x00000100U) /* !< Select this clock as a source */ + +/* UNICOMMSPI_PDBGCTL Bits */ +/* UNICOMMSPI_PDBGCTL[FREE] Bits */ +#define UNICOMMSPI_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */ +#define UNICOMMSPI_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */ +#define UNICOMMSPI_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes + functionality while the Core Halted + input is asserted and resumes when it + is deasserted. */ +#define UNICOMMSPI_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of + the Core Halted input */ +/* UNICOMMSPI_PDBGCTL[SOFT] Bits */ +#define UNICOMMSPI_PDBGCTL_SOFT_OFS (1) /* !< SOFT Offset */ +#define UNICOMMSPI_PDBGCTL_SOFT_MASK ((uint32_t)0x00000002U) /* !< Soft halt boundary control. This + function is only available, if [FREE] + is set to 'STOP' */ +#define UNICOMMSPI_PDBGCTL_SOFT_DEPRECATED ((uint32_t)0x00000000U) /* !< Not supported */ +#define UNICOMMSPI_PDBGCTL_SOFT_DELAYED ((uint32_t)0x00000002U) /* !< The peripheral blocks the debug + freeze until it has reached a + boundary where it can resume without + corruption */ + +/* UNICOMMSPI_INTCTL Bits */ +/* UNICOMMSPI_INTCTL[INTEVAL] Bits */ +#define UNICOMMSPI_INTCTL_INTEVAL_OFS (0) /* !< INTEVAL Offset */ +#define UNICOMMSPI_INTCTL_INTEVAL_MASK ((uint32_t)0x00000001U) /* !< Writing a 1 to this field + re-evaluates the interrupt sources. */ +#define UNICOMMSPI_INTCTL_INTEVAL_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define UNICOMMSPI_INTCTL_INTEVAL_EVAL ((uint32_t)0x00000001U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ + +/* UNICOMMSPI_CTL0 Bits */ +/* UNICOMMSPI_CTL0[DSS] Bits */ +#define UNICOMMSPI_CTL0_DSS_OFS (0) /* !< DSS Offset */ +#define UNICOMMSPI_CTL0_DSS_MASK ((uint32_t)0x0000001FU) /* !< Data Size Select. Values 0 - 2 are + reserved and shall not be used. 3h = + 4_BIT : 4-bit data SPI allows only + values up to 16 Bit */ +#define UNICOMMSPI_CTL0_DSS_DSS_4 ((uint32_t)0x00000003U) /* !< Data Size Select bits: 4 */ +#define UNICOMMSPI_CTL0_DSS_DSS_5 ((uint32_t)0x00000004U) /* !< Data Size Select bits: 5 */ +#define UNICOMMSPI_CTL0_DSS_DSS_6 ((uint32_t)0x00000005U) /* !< Data Size Select bits: 6 */ +#define UNICOMMSPI_CTL0_DSS_DSS_7 ((uint32_t)0x00000006U) /* !< Data Size Select bits: 7 */ +#define UNICOMMSPI_CTL0_DSS_DSS_8 ((uint32_t)0x00000007U) /* !< Data Size Select bits: 8 */ +#define UNICOMMSPI_CTL0_DSS_DSS_9 ((uint32_t)0x00000008U) /* !< Data Size Select bits: 9 */ +#define UNICOMMSPI_CTL0_DSS_DSS_10 ((uint32_t)0x00000009U) /* !< Data Size Select bits: 10 */ +#define UNICOMMSPI_CTL0_DSS_DSS_11 ((uint32_t)0x0000000AU) /* !< Data Size Select bits: 11 */ +#define UNICOMMSPI_CTL0_DSS_DSS_12 ((uint32_t)0x0000000BU) /* !< Data Size Select bits: 12 */ +#define UNICOMMSPI_CTL0_DSS_DSS_13 ((uint32_t)0x0000000CU) /* !< Data Size Select bits: 13 */ +#define UNICOMMSPI_CTL0_DSS_DSS_14 ((uint32_t)0x0000000DU) /* !< Data Size Select bits: 14 */ +#define UNICOMMSPI_CTL0_DSS_DSS_15 ((uint32_t)0x0000000EU) /* !< Data Size Select bits: 15 */ +#define UNICOMMSPI_CTL0_DSS_DSS_16 ((uint32_t)0x0000000FU) /* !< Data Size Select bits: 16 */ +/* UNICOMMSPI_CTL0[FRF] Bits */ +#define UNICOMMSPI_CTL0_FRF_OFS (5) /* !< FRF Offset */ +#define UNICOMMSPI_CTL0_FRF_MASK ((uint32_t)0x00000060U) /* !< Frame format Select */ +#define UNICOMMSPI_CTL0_FRF_MOTOROLA_3WIRE ((uint32_t)0x00000000U) /* !< Motorola SPI frame format (3 wire + mode) */ +#define UNICOMMSPI_CTL0_FRF_MOTOROLA_4WIRE ((uint32_t)0x00000020U) /* !< Motorola SPI frame format (4 wire + mode) */ +#define UNICOMMSPI_CTL0_FRF_TI_SYNC ((uint32_t)0x00000040U) /* !< TI synchronous serial frame format */ +#define UNICOMMSPI_CTL0_FRF_MIRCOWIRE ((uint32_t)0x00000060U) /* !< National Microwire frame format */ +/* UNICOMMSPI_CTL0[SPO] Bits */ +#define UNICOMMSPI_CTL0_SPO_OFS (8) /* !< SPO Offset */ +#define UNICOMMSPI_CTL0_SPO_MASK ((uint32_t)0x00000100U) /* !< CLKOUT polarity (Motorola SPI frame + format only) */ +#define UNICOMMSPI_CTL0_SPO_LOW ((uint32_t)0x00000000U) /* !< SPI produces a steady state LOW + value on the CLKOUT */ +#define UNICOMMSPI_CTL0_SPO_HIGH ((uint32_t)0x00000100U) /* !< SPI produces a steady state HIGH + value on the CLKOUT */ +/* UNICOMMSPI_CTL0[SPH] Bits */ +#define UNICOMMSPI_CTL0_SPH_OFS (9) /* !< SPH Offset */ +#define UNICOMMSPI_CTL0_SPH_MASK ((uint32_t)0x00000200U) /* !< CLKOUT phase (Motorola SPI frame + format only) This bit selects the + clock edge that captures data and + enables it to change state. It has + the most impact on the first bit + transmitted by either permitting or + not permitting a clock transition + before the first data capture edge. */ +#define UNICOMMSPI_CTL0_SPH_FIRST ((uint32_t)0x00000000U) /* !< Data is captured on the first clock + edge transition. */ +#define UNICOMMSPI_CTL0_SPH_SECOND ((uint32_t)0x00000200U) /* !< Data is captured on the second + clock edge transition. */ +/* UNICOMMSPI_CTL0[CSSEL] Bits */ +#define UNICOMMSPI_CTL0_CSSEL_OFS (12) /* !< CSSEL Offset */ +#define UNICOMMSPI_CTL0_CSSEL_MASK ((uint32_t)0x00003000U) /* !< Select the CS line to control on + data transfer This bit is applicable + for both controller/target mode */ +#define UNICOMMSPI_CTL0_CSSEL_CSSEL_0 ((uint32_t)0x00000000U) /* !< CS line select: 0 */ +#define UNICOMMSPI_CTL0_CSSEL_CSSEL_1 ((uint32_t)0x00001000U) /* !< CS line select: 1 */ +#define UNICOMMSPI_CTL0_CSSEL_CSSEL_2 ((uint32_t)0x00002000U) /* !< CS line select: 2 */ +#define UNICOMMSPI_CTL0_CSSEL_CSSEL_3 ((uint32_t)0x00003000U) /* !< CS line select: 3 */ +/* UNICOMMSPI_CTL0[CSCLR] Bits */ +#define UNICOMMSPI_CTL0_CSCLR_OFS (14) /* !< CSCLR Offset */ +#define UNICOMMSPI_CTL0_CSCLR_MASK ((uint32_t)0x00004000U) /* !< Clear shift register counter on CS + inactive This bit is relevant only in + the peripheral, CTL1.CP=0. */ +#define UNICOMMSPI_CTL0_CSCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable automatic clear of shift + register when CS goes to disable. */ +#define UNICOMMSPI_CTL0_CSCLR_ENABLE ((uint32_t)0x00004000U) /* !< Enable automatic clear of shift + register when CS goes to disable. */ +/* UNICOMMSPI_CTL0[PACKEN] Bits */ +#define UNICOMMSPI_CTL0_PACKEN_OFS (7) /* !< PACKEN Offset */ +#define UNICOMMSPI_CTL0_PACKEN_MASK ((uint32_t)0x00000080U) /* !< Packing Enable. When 1, packing + feature is enabled inside the IP When + 0, packing feature is disabled inside + the IP */ +#define UNICOMMSPI_CTL0_PACKEN_DISABLED ((uint32_t)0x00000000U) /* !< Packing feature disabled */ +#define UNICOMMSPI_CTL0_PACKEN_ENABLED ((uint32_t)0x00000080U) /* !< Packing feature enabled */ + +/* UNICOMMSPI_STAT Bits */ +/* UNICOMMSPI_STAT[TXFE] Bits */ +#define UNICOMMSPI_STAT_TXFE_OFS (5) /* !< TXFE Offset */ +#define UNICOMMSPI_STAT_TXFE_MASK ((uint32_t)0x00000020U) /* !< Transmit FIFO empty. */ +#define UNICOMMSPI_STAT_TXFE_NOT_EMPTY ((uint32_t)0x00000000U) /* !< Transmit FIFO is not empty. */ +#define UNICOMMSPI_STAT_TXFE_EMPTY ((uint32_t)0x00000020U) /* !< Transmit FIFO is empty. */ +/* UNICOMMSPI_STAT[RXFE] Bits */ +#define UNICOMMSPI_STAT_RXFE_OFS (2) /* !< RXFE Offset */ +#define UNICOMMSPI_STAT_RXFE_MASK ((uint32_t)0x00000004U) /* !< Receive FIFO empty. */ +#define UNICOMMSPI_STAT_RXFE_NOT_EMPTY ((uint32_t)0x00000000U) /* !< Receive FIFO is not empty. */ +#define UNICOMMSPI_STAT_RXFE_EMPTY ((uint32_t)0x00000004U) /* !< Receive FIFO is empty. */ +/* UNICOMMSPI_STAT[BUSY] Bits */ +#define UNICOMMSPI_STAT_BUSY_OFS (8) /* !< BUSY Offset */ +#define UNICOMMSPI_STAT_BUSY_MASK ((uint32_t)0x00000100U) /* !< Busy */ +#define UNICOMMSPI_STAT_BUSY_IDLE ((uint32_t)0x00000000U) /* !< SPI is in idle mode. */ +#define UNICOMMSPI_STAT_BUSY_ACTIVE ((uint32_t)0x00000100U) /* !< SPI is currently transmitting + and/or receiving data, or transmit + FIFO is not empty. */ +/* UNICOMMSPI_STAT[RXCLR] Bits */ +#define UNICOMMSPI_STAT_RXCLR_OFS (4) /* !< RXCLR Offset */ +#define UNICOMMSPI_STAT_RXCLR_MASK ((uint32_t)0x00000010U) /* !< RX FIFO Clear Status */ +#define UNICOMMSPI_STAT_RXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMSPI_STAT_RXCLR_SET ((uint32_t)0x00000010U) /* !< FIFO clear is complete */ +/* UNICOMMSPI_STAT[TXCLR] Bits */ +#define UNICOMMSPI_STAT_TXCLR_OFS (7) /* !< TXCLR Offset */ +#define UNICOMMSPI_STAT_TXCLR_MASK ((uint32_t)0x00000080U) /* !< TX FIFO Clear Status */ +#define UNICOMMSPI_STAT_TXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMSPI_STAT_TXCLR_SET ((uint32_t)0x00000080U) /* !< FIFO clear is complete */ +/* UNICOMMSPI_STAT[RXFF] Bits */ +#define UNICOMMSPI_STAT_RXFF_OFS (3) /* !< RXFF Offset */ +#define UNICOMMSPI_STAT_RXFF_MASK ((uint32_t)0x00000008U) /* !< UART Receive FIFO Full The meaning + of this bit depends on the state of + the FEN bit in the CTL0 register. */ +#define UNICOMMSPI_STAT_RXFF_CLEARED ((uint32_t)0x00000000U) /* !< The receiver can receive data. */ +#define UNICOMMSPI_STAT_RXFF_SET ((uint32_t)0x00000008U) /* !< If the FIFO is disabled (FEN is 0), + the receive holding register is full. + If the FIFO is enabled (FEN is 1), + the receive FIFO is full. */ +/* UNICOMMSPI_STAT[TXFF] Bits */ +#define UNICOMMSPI_STAT_TXFF_OFS (6) /* !< TXFF Offset */ +#define UNICOMMSPI_STAT_TXFF_MASK ((uint32_t)0x00000040U) /* !< UART Transmit FIFO Full The + meaning of this bit depends on the + state of the FEN bit in the CTL0 + register. */ +#define UNICOMMSPI_STAT_TXFF_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter is not full. */ +#define UNICOMMSPI_STAT_TXFF_SET ((uint32_t)0x00000040U) /* !< If the FIFO is disabled (FEN is 0), + the transmit holding register is + full. If the FIFO is enabled (FEN is + 1), the transmit FIFO is full. */ +/* UNICOMMSPI_STAT[CDMODE] Bits */ +#define UNICOMMSPI_STAT_CDMODE_OFS (12) /* !< CDMODE Offset */ +#define UNICOMMSPI_STAT_CDMODE_MASK ((uint32_t)0x0000F000U) /* !< Current CDMODE status. This + reflects the current counter counter + value. */ +#define UNICOMMSPI_STAT_CDMODE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_STAT_CDMODE_DATA ((uint32_t)0x00000000U) /* !< Manual mode: Data */ +#define UNICOMMSPI_STAT_CDMODE_MAXIMUM ((uint32_t)0x0000F000U) /* !< Highest possible value */ +#define UNICOMMSPI_STAT_CDMODE_COMMAND ((uint32_t)0x0000F000U) /* !< Manual mode: Command */ + +/* UNICOMMSPI_IFLS Bits */ +/* UNICOMMSPI_IFLS[TXIFLSEL] Bits */ +#define UNICOMMSPI_IFLS_TXIFLSEL_OFS (0) /* !< TXIFLSEL Offset */ +#define UNICOMMSPI_IFLS_TXIFLSEL_MASK ((uint32_t)0x00000007U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMSPI_IFLS_TXIFLSEL_LVL_3_4 ((uint32_t)0x00000001U) /* !< TX FIFO <= 3/4 empty */ +#define UNICOMMSPI_IFLS_TXIFLSEL_LVL_1_2 ((uint32_t)0x00000002U) /* !< TX FIFO <= 1/2 empty (default) */ +#define UNICOMMSPI_IFLS_TXIFLSEL_LVL_1_4 ((uint32_t)0x00000003U) /* !< TX FIFO <= 1/4 empty */ +#define UNICOMMSPI_IFLS_TXIFLSEL_LVL_NOT_FULL ((uint32_t)0x00000004U) /* !< Opposite of full */ +#define UNICOMMSPI_IFLS_TXIFLSEL_LVL_EMPTY ((uint32_t)0x00000005U) /* !< TX FIFO is empty */ +#define UNICOMMSPI_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000006U) /* !< TX FIFO <= 1 */ +#define UNICOMMSPI_IFLS_TXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000007U) /* !< TX_FIFO >= (MAX_FIFO_LEN -1) */ +/* UNICOMMSPI_IFLS[RXIFLSEL] Bits */ +#define UNICOMMSPI_IFLS_RXIFLSEL_OFS (4) /* !< RXIFLSEL Offset */ +#define UNICOMMSPI_IFLS_RXIFLSEL_MASK ((uint32_t)0x00000070U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMSPI_IFLS_RXIFLSEL_LVL_1_4 ((uint32_t)0x00000010U) /* !< RX FIFO >= 1/4 full */ +#define UNICOMMSPI_IFLS_RXIFLSEL_LVL_1_2 ((uint32_t)0x00000020U) /* !< RX FIFO >= 1/2 full (default) */ +#define UNICOMMSPI_IFLS_RXIFLSEL_LVL_3_4 ((uint32_t)0x00000030U) /* !< RX FIFO >= 3/4 full */ +#define UNICOMMSPI_IFLS_RXIFLSEL_LVL_NOT_EMPTY ((uint32_t)0x00000040U) /* !< Opposite of empty */ +#define UNICOMMSPI_IFLS_RXIFLSEL_LVL_FULL ((uint32_t)0x00000050U) /* !< RX FIFO is full */ +#define UNICOMMSPI_IFLS_RXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000060U) /* !< RX_FIFO >= (MAX_FIFO_LEN -1) */ +#define UNICOMMSPI_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000070U) /* !< RX_FIFO <= 1 */ +/* UNICOMMSPI_IFLS[TXCLR] Bits */ +#define UNICOMMSPI_IFLS_TXCLR_OFS (3) /* !< TXCLR Offset */ +#define UNICOMMSPI_IFLS_TXCLR_MASK ((uint32_t)0x00000008U) /* !< TX FIFO CLEAR. Setting this bit + will clear the TX FIFO contents. */ +#define UNICOMMSPI_IFLS_TXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMSPI_IFLS_TXCLR_ENABLE ((uint32_t)0x00000008U) /* !< Enable FIFO Clear */ +/* UNICOMMSPI_IFLS[RXCLR] Bits */ +#define UNICOMMSPI_IFLS_RXCLR_OFS (7) /* !< RXCLR Offset */ +#define UNICOMMSPI_IFLS_RXCLR_MASK ((uint32_t)0x00000080U) /* !< RX FIFO CLEAR. Setting this bit + will clear the RX FIFO contents. */ +#define UNICOMMSPI_IFLS_RXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMSPI_IFLS_RXCLR_ENABLE ((uint32_t)0x00000080U) /* !< Enable FIFO Clear */ + +/* UNICOMMSPI_CLKCTL Bits */ +/* UNICOMMSPI_CLKCTL[SCR] Bits */ +#define UNICOMMSPI_CLKCTL_SCR_OFS (0) /* !< SCR Offset */ +#define UNICOMMSPI_CLKCTL_SCR_MASK ((uint32_t)0x000003FFU) /* !< Serial clock divider: This is used + to generate the transmit and receive + bit rate of the SPI. The SPI bit rate + is (SPI's functional clock + frequency)/((SCR+1)*2). SCR is a + value from 0-1023. */ +#define UNICOMMSPI_CLKCTL_SCR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_CLKCTL_SCR_MAXIMUM ((uint32_t)0x000003FFU) /* !< Highest possible value */ +/* UNICOMMSPI_CLKCTL[DSAMPLE] Bits */ +#define UNICOMMSPI_CLKCTL_DSAMPLE_OFS (28) /* !< DSAMPLE Offset */ +#define UNICOMMSPI_CLKCTL_DSAMPLE_MASK ((uint32_t)0xF0000000U) /* !< Delayed sampling value. In + controller mode the data on the input + pin will be delayed sampled by the + defined clock cycles of internal + functional clock hence relaxing the + setup time of input data. This + setting is useful in systems where + the board delays and external + peripheral delays are more than the + input setup time of the controller. + Please refer to the datasheet for + values of controller input setup time + and assess what DSAMPLE value meets + the requirement of the system. Note: + High values of DSAMPLE can cause HOLD + time violations and must be factored + in the calculations. */ +#define UNICOMMSPI_CLKCTL_DSAMPLE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_CLKCTL_DSAMPLE_MAXIMUM ((uint32_t)0xF0000000U) /* !< Highest possible value */ + +/* UNICOMMSPI_TXDATA Bits */ +/* UNICOMMSPI_TXDATA[DATA] Bits */ +#define UNICOMMSPI_TXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMSPI_TXDATA_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Transmit Data When read, last + written value will be returned. If + the last write to this field was a + 32-bit write (with PACKEN=1), 32-bits + will be returned and if the last + write was a 16-bit write (PACKEN=0), + those 16-bits will be returned. + When written, one or two FIFO entries + will be written depending on PACKEN + value. Data values are removed from + the transmit FIFO one value at a time + by the transmit logic. It is loaded + into the transmit serial shifter, + then serially shifted out onto the + TXD output pin at the programmed bit + rate. When a data size of less than + 16 bits is selected, the user must + right-justify data written to the + transmit FIFO. The transmit logic + ignores the unused bits. */ +#define UNICOMMSPI_TXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_TXDATA_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMSPI_RXDATA Bits */ +/* UNICOMMSPI_RXDATA[DATA] Bits */ +#define UNICOMMSPI_RXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMSPI_RXDATA_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Received Data When PACKEN=1,two + entries of the FIFO are returned as a + 32-bit value. When PACKEN=0, 1 entry + of FIFO is returned as 16-bit value. + As data values are removed by the + receive logic from the incoming data + frame, they are placed into the entry + in the receive FIFO, pointed to by + the current FIFO write pointer. + Received data less than 16 bits is + automatically right justified in the + receive buffer. */ +#define UNICOMMSPI_RXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_RXDATA_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMSPI_CTL1 Bits */ +/* UNICOMMSPI_CTL1[LBM] Bits */ +#define UNICOMMSPI_CTL1_LBM_OFS (1) /* !< LBM Offset */ +#define UNICOMMSPI_CTL1_LBM_MASK ((uint32_t)0x00000002U) /* !< Loop back mode */ +#define UNICOMMSPI_CTL1_LBM_DISABLE ((uint32_t)0x00000000U) /* !< Disable loopback mode */ +#define UNICOMMSPI_CTL1_LBM_ENABLE ((uint32_t)0x00000002U) /* !< Enable loopback mode */ +/* UNICOMMSPI_CTL1[CP] Bits */ +#define UNICOMMSPI_CTL1_CP_OFS (2) /* !< CP Offset */ +#define UNICOMMSPI_CTL1_CP_MASK ((uint32_t)0x00000004U) /* !< Controller or peripheral mode + select. This bit can be modified only + when SPI is disabled, CTL1.ENABLE=0. */ +#define UNICOMMSPI_CTL1_CP_DISABLE ((uint32_t)0x00000000U) /* !< Select Peripheral mode */ +#define UNICOMMSPI_CTL1_CP_ENABLE ((uint32_t)0x00000004U) /* !< Select Controller Mode */ +/* UNICOMMSPI_CTL1[POD] Bits */ +#define UNICOMMSPI_CTL1_POD_OFS (3) /* !< POD Offset */ +#define UNICOMMSPI_CTL1_POD_MASK ((uint32_t)0x00000008U) /* !< Peripheral-mode: Data output + disabled This bit is relevant only in + Peripheral mode. In + multiple-peripheral system + topologies, SPI controller can + broadcast a message to all + peripherals, while only one + peripheral drives the line. POD can + be used by the SPI peripheral to + disable driving data on the line. */ +#define UNICOMMSPI_CTL1_POD_DISABLE ((uint32_t)0x00000000U) /* !< SPI can drive the POCI output in + peripheral mode. */ +#define UNICOMMSPI_CTL1_POD_ENABLE ((uint32_t)0x00000008U) /* !< SPI cannot drive the POCI output in + peripheral mode. */ +/* UNICOMMSPI_CTL1[MSB] Bits */ +#define UNICOMMSPI_CTL1_MSB_OFS (4) /* !< MSB Offset */ +#define UNICOMMSPI_CTL1_MSB_MASK ((uint32_t)0x00000010U) /* !< MSB first select. Controls the + direction of the receive and transmit + shift register. */ +#define UNICOMMSPI_CTL1_MSB_DISABLE ((uint32_t)0x00000000U) /* !< LSB first */ +#define UNICOMMSPI_CTL1_MSB_ENABLE ((uint32_t)0x00000010U) /* !< MSB first */ +/* UNICOMMSPI_CTL1[PREN] Bits */ +#define UNICOMMSPI_CTL1_PREN_OFS (5) /* !< PREN Offset */ +#define UNICOMMSPI_CTL1_PREN_MASK ((uint32_t)0x00000020U) /* !< Parity receive enable If enabled, + parity reception check will be done + for both controller and peripheral + modes In case of a parity miss-match + the parity error flag RIS.PER will be + set. */ +#define UNICOMMSPI_CTL1_PREN_DISABLE ((uint32_t)0x00000000U) /* !< Disable Parity receive function */ +#define UNICOMMSPI_CTL1_PREN_ENABLE ((uint32_t)0x00000020U) /* !< Enable Parity receive function */ +/* UNICOMMSPI_CTL1[REPEATTX] Bits */ +#define UNICOMMSPI_CTL1_REPEATTX_OFS (16) /* !< REPEATTX Offset */ +#define UNICOMMSPI_CTL1_REPEATTX_MASK ((uint32_t)0x00FF0000U) /* !< Counter to repeat last transfer 0: + repeat last transfer is disabled. x: + repeat the last transfer with the + given number. The transfer will be + started with writing a data into the + TX Buffer. Sending the data will be + repeated with the given value, so the + data will be transferred X+1 times in + total. The behavior is identical as + if the data would be written into the + TX Buffer that many times as defined + by the value here. It can be used to + clean a transfer or to pull a certain + amount of data by a peripheral. */ +#define UNICOMMSPI_CTL1_REPEATTX_DISABLE ((uint32_t)0x00000000U) /* !< REPEATTX disable */ +#define UNICOMMSPI_CTL1_REPEATTX_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_CTL1_REPEATTX_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */ +/* UNICOMMSPI_CTL1[PES] Bits */ +#define UNICOMMSPI_CTL1_PES_OFS (6) /* !< PES Offset */ +#define UNICOMMSPI_CTL1_PES_MASK ((uint32_t)0x00000040U) /* !< Even Parity Select */ +#define UNICOMMSPI_CTL1_PES_DISABLE ((uint32_t)0x00000000U) /* !< Odd Parity mode */ +#define UNICOMMSPI_CTL1_PES_ENABLE ((uint32_t)0x00000040U) /* !< Even Parity mode */ +/* UNICOMMSPI_CTL1[CDMODE] Bits */ +#define UNICOMMSPI_CTL1_CDMODE_OFS (12) /* !< CDMODE Offset */ +#define UNICOMMSPI_CTL1_CDMODE_MASK ((uint32_t)0x0000F000U) /* !< Command/Data Mode Value When + CTL1.CDENABLE is 1, CS3 line is used + as C/D signal to distinguish between + Command (C/D low) and Data (C/D high) + information. When a value is written + into the CTL1.CDMODE bits, the C/D + (CS3) line will go low for the given + numbers of byte which are sent by the + SPI, starting with the next value to + be transmitted after which, C/D line + will go high automatically 0: Manual + mode with C/D signal as High 1-14: + C/D is low while this number of bytes + are being sent after which, this + field sets to 0 and C/D goes high. + Reading this field at any time + returns the remaining number of + command bytes. 15: Manual mode with + C/D signal as Low. */ +#define UNICOMMSPI_CTL1_CDMODE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_CTL1_CDMODE_DATA ((uint32_t)0x00000000U) /* !< Manual mode: Data */ +#define UNICOMMSPI_CTL1_CDMODE_MAXIMUM ((uint32_t)0x0000F000U) /* !< Highest possible value */ +#define UNICOMMSPI_CTL1_CDMODE_COMMAND ((uint32_t)0x0000F000U) /* !< Manual mode: Command */ +/* UNICOMMSPI_CTL1[ENABLE] Bits */ +#define UNICOMMSPI_CTL1_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define UNICOMMSPI_CTL1_ENABLE_MASK ((uint32_t)0x00000001U) /* !< SPI enable */ +#define UNICOMMSPI_CTL1_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable module function */ +#define UNICOMMSPI_CTL1_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable module function */ +/* UNICOMMSPI_CTL1[RXTIMEOUT] Bits */ +#define UNICOMMSPI_CTL1_RXTIMEOUT_OFS (24) /* !< RXTIMEOUT Offset */ +#define UNICOMMSPI_CTL1_RXTIMEOUT_MASK ((uint32_t)0x3F000000U) /* !< Receive Timeout (only for + Peripheral mode) Defines the number + of Clock Cycles before after which + the Receive Timeout flag RTOUT is + set. The time is calculated using the + control register for the clock + selection and divider in the + Controller mode configuration. A + value of 0 disables this function. */ +#define UNICOMMSPI_CTL1_RXTIMEOUT_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMSPI_CTL1_RXTIMEOUT_MAXIMUM ((uint32_t)0x3F000000U) /* !< Highest possible value */ +/* UNICOMMSPI_CTL1[CDENABLE] Bits */ +#define UNICOMMSPI_CTL1_CDENABLE_OFS (11) /* !< CDENABLE Offset */ +#define UNICOMMSPI_CTL1_CDENABLE_MASK ((uint32_t)0x00000800U) /* !< Command/Data Mode enable */ +#define UNICOMMSPI_CTL1_CDENABLE_DISABLE ((uint32_t)0x00000000U) /* !< CS3 is used for Chip Select */ +#define UNICOMMSPI_CTL1_CDENABLE_ENABLE ((uint32_t)0x00000800U) /* !< CS3 is used as CD signal */ +/* UNICOMMSPI_CTL1[PTEN] Bits */ +#define UNICOMMSPI_CTL1_PTEN_OFS (8) /* !< PTEN Offset */ +#define UNICOMMSPI_CTL1_PTEN_MASK ((uint32_t)0x00000100U) /* !< Parity transmit enable If enabled, + parity transmission will be done for + both controller and peripheral modes. */ +#define UNICOMMSPI_CTL1_PTEN_DISABLE ((uint32_t)0x00000000U) /* !< Parity transmission is disabled */ +#define UNICOMMSPI_CTL1_PTEN_ENABLE ((uint32_t)0x00000100U) /* !< Parity transmission is enabled */ +/* UNICOMMSPI_CTL1[SUSPEND] Bits */ +#define UNICOMMSPI_CTL1_SUSPEND_OFS (9) /* !< SUSPEND Offset */ +#define UNICOMMSPI_CTL1_SUSPEND_MASK ((uint32_t)0x00000200U) /* !< Suspend external communication */ +#define UNICOMMSPI_CTL1_SUSPEND_DISABLE ((uint32_t)0x00000000U) /* !< Functional mode resumed */ +#define UNICOMMSPI_CTL1_SUSPEND_ENABLE ((uint32_t)0x00000200U) /* !< External communication suspended */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_unicommspi__include */ + diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_unicommuart.h b/mspm0/source/ti/devices/msp/peripherals/hw_unicommuart.h new file mode 100644 index 0000000..dcff156 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_unicommuart.h @@ -0,0 +1,1929 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_unicommuart__include +#define ti_devices_msp_peripherals_hw_unicommuart__include + +/* Filename: hw_unicommuart.h */ +/* Revised: 2024-07-23 05:21:00 */ +/* Revision: 7c260ce5cfafbadcd25e0fb6ff8594c604ea1d77 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* UNICOMMUART Registers +******************************************************************************/ +#define UNICOMMUART_SPGDMA_OFS ((uint32_t)0x000010B0U) +#define UNICOMMUART_DMA_TRIG_TX_OFS ((uint32_t)0x00001080U) +#define UNICOMMUART_DMA_TRIG_RX_OFS ((uint32_t)0x00001050U) +#define UNICOMMUART_CPU_INT_OFS ((uint32_t)0x00001020U) + + +/** @addtogroup UNICOMMUART_SPGDMA + @{ +*/ + +typedef struct { + uint32_t RESERVED0; + __IO uint32_t SPGDMARXCTL; /* !< (@ 0x000010B4) DMA Channel Control */ + __IO uint32_t SPGDMARXDA; /* !< (@ 0x000010B8) DMA Channel Destination Address */ + __IO uint32_t SPGDMARXSZ; /* !< (@ 0x000010BC) DMA Channel Size */ + uint32_t RESERVED1; + __IO uint32_t SPGDMATXCTL; /* !< (@ 0x000010C4) DMA Channel Control */ + __IO uint32_t SPGDMATXSA; /* !< (@ 0x000010C8) DMA Channel Destination Address */ + __IO uint32_t SPGDMATXSZ; /* !< (@ 0x000010CC) DMA Channel Size */ +} UNICOMMUART_SPGDMA_Regs; + +/*@}*/ /* end of group UNICOMMUART_SPGDMA */ + +/** @addtogroup UNICOMMUART_DMA_TRIG_TX + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001088) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001090) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001098) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x000010A0) Interrupt set */ +} UNICOMMUART_DMA_TRIG_TX_Regs; + +/*@}*/ /* end of group UNICOMMUART_DMA_TRIG_TX */ + +/** @addtogroup UNICOMMUART_DMA_TRIG_RX + @{ +*/ + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */ +} UNICOMMUART_DMA_TRIG_RX_Regs; + +/*@}*/ /* end of group UNICOMMUART_DMA_TRIG_RX */ + +/** @addtogroup UNICOMMUART_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */ +} UNICOMMUART_CPU_INT_Regs; + +/*@}*/ /* end of group UNICOMMUART_CPU_INT */ + +/** @addtogroup UNICOMMUART + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + __IO uint32_t CLKDIV; /* !< (@ 0x00001000) Clock Divider */ + uint32_t RESERVED1; + __IO uint32_t CLKSEL; /* !< (@ 0x00001008) Clock Select for Ultra Low Power peripherals */ + uint32_t RESERVED2[3]; + __IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */ + uint32_t RESERVED3; + UNICOMMUART_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED4; + UNICOMMUART_DMA_TRIG_RX_Regs DMA_TRIG_RX; /* !< (@ 0x00001050) */ + uint32_t RESERVED5[3]; + UNICOMMUART_DMA_TRIG_TX_Regs DMA_TRIG_TX; /* !< (@ 0x00001080) */ + uint32_t RESERVED6[3]; + UNICOMMUART_SPGDMA_Regs SPGDMA; /* !< (@ 0x000010B0) */ + uint32_t RESERVED7[5]; + __O uint32_t INTCTL; /* !< (@ 0x000010E4) Interrupt control register */ + uint32_t RESERVED8[6]; + __IO uint32_t CTL0; /* !< (@ 0x00001100) UART Control Register 0 */ + __IO uint32_t LCRH; /* !< (@ 0x00001104) UART Line Control Register */ + __I uint32_t STAT; /* !< (@ 0x00001108) UART Status Register */ + __IO uint32_t IFLS; /* !< (@ 0x0000110C) UART Interrupt FIFO Level Select Register */ + __IO uint32_t IBRD; /* !< (@ 0x00001110) UART Integer Baud-Rate Divisor Register */ + __IO uint32_t FBRD; /* !< (@ 0x00001114) UART Fractional Baud-Rate Divisor Register */ + __IO uint32_t GFCTL; /* !< (@ 0x00001118) Glitch Filter Control */ + uint32_t RESERVED9; + __O uint32_t TXDATA; /* !< (@ 0x00001120) UART Transmit Data Register */ + __I uint32_t RXDATA; /* !< (@ 0x00001124) UART Receive Data Register */ + uint32_t RESERVED10[2]; + __IO uint32_t LINCNT; /* !< (@ 0x00001130) UART LIN Mode Counter Register */ + __IO uint32_t LINCTL; /* !< (@ 0x00001134) UART LIN Mode Control Register */ + __IO uint32_t LINC0; /* !< (@ 0x00001138) UART LIN Mode Capture 0 Register */ + __IO uint32_t LINC1; /* !< (@ 0x0000113C) UART LIN Mode Capture 1 Register */ + __IO uint32_t IRCTL; /* !< (@ 0x00001140) eUSCI_Ax IrDA Control Word Register */ + uint32_t RESERVED11; + __IO uint32_t AMASK; /* !< (@ 0x00001148) Self Address Mask Register */ + __IO uint32_t ADDR; /* !< (@ 0x0000114C) Self Address Register */ +} UNICOMMUART_Regs; + +/*@}*/ /* end of group UNICOMMUART */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* UNICOMMUART Register Control Bits +******************************************************************************/ + +/* UNICOMMUART_SPGDMARXCTL Bits */ +/* UNICOMMUART_SPGDMARXCTL[DMAEN] Bits */ +#define UNICOMMUART_SPGDMARXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMUART_SPGDMARXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMUART_SPGDMARXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMUART_SPGDMARXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMUART_SPGDMARXCTL[DMAMEMINCR] Bits */ +#define UNICOMMUART_SPGDMARXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMUART_SPGDMARXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMUART_SPGDMARXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMADSTWDTH) */ +#define UNICOMMUART_SPGDMARXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMADSTWDTH) */ +/* UNICOMMUART_SPGDMARXCTL[DMAPREIRQ] Bits */ +#define UNICOMMUART_SPGDMARXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMUART_SPGDMARXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMUART_SPGDMARXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMUART_SPGDMARXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMUART_SPGDMARXCTL[DMATM] Bits */ +#define UNICOMMUART_SPGDMARXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMUART_SPGDMARXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register */ +#define UNICOMMUART_SPGDMARXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMUART_SPGDMARXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMUART_SPGDMARXCTL[DMADSTWDTH] Bits */ +#define UNICOMMUART_SPGDMARXCTL_DMADSTWDTH_OFS (28) /* !< DMADSTWDTH Offset */ +#define UNICOMMUART_SPGDMARXCTL_DMADSTWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA destination width. This bit + selects the destination as a byte, + half word, word or long word. */ +#define UNICOMMUART_SPGDMARXCTL_DMADSTWDTH_BYTE ((uint32_t)0x00000000U) /* !< Destination data width is BYTE + (8-bit) */ +#define UNICOMMUART_SPGDMARXCTL_DMADSTWDTH_HALF ((uint32_t)0x10000000U) /* !< Destination data width is HALF-WORD + (16-bit) */ +#define UNICOMMUART_SPGDMARXCTL_DMADSTWDTH_WORD ((uint32_t)0x20000000U) /* !< Destination data width is WORD + (32-bit) */ + +/* UNICOMMUART_SPGDMARXDA Bits */ +/* UNICOMMUART_SPGDMARXDA[ADDR] Bits */ +#define UNICOMMUART_SPGDMARXDA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMUART_SPGDMARXDA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMUART_SPGDMARXDA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_SPGDMARXDA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_SPGDMARXSZ Bits */ +/* UNICOMMUART_SPGDMARXSZ[SIZE] Bits */ +#define UNICOMMUART_SPGDMARXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMUART_SPGDMARXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMUART_SPGDMARXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_SPGDMARXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_SPGDMATXCTL Bits */ +/* UNICOMMUART_SPGDMATXCTL[DMAEN] Bits */ +#define UNICOMMUART_SPGDMATXCTL_DMAEN_OFS (1) /* !< DMAEN Offset */ +#define UNICOMMUART_SPGDMATXCTL_DMAEN_MASK ((uint32_t)0x00000002U) /* !< DMA enable */ +#define UNICOMMUART_SPGDMATXCTL_DMAEN_DISABLE ((uint32_t)0x00000000U) /* !< DMA channel disabled */ +#define UNICOMMUART_SPGDMATXCTL_DMAEN_ENABLE ((uint32_t)0x00000002U) /* !< DMA channel enabled */ +/* UNICOMMUART_SPGDMATXCTL[DMAMEMINCR] Bits */ +#define UNICOMMUART_SPGDMATXCTL_DMAMEMINCR_OFS (20) /* !< DMAMEMINCR Offset */ +#define UNICOMMUART_SPGDMATXCTL_DMAMEMINCR_MASK ((uint32_t)0x00100000U) /* !< DMA destination increment. This bit + selects automatic incrementing or + decrementing of the destination + address DMADA for each transfer. The + amount of change to the DMADA is + based on the definition in the + DMADSTWDTH. For example, an increment + of 1 (+1) on a WORD transfer will + increment the DMADA by 4. */ +#define UNICOMMUART_SPGDMATXCTL_DMAMEMINCR_INCREMENT ((uint32_t)0x00000000U) /* !< Incremented by 1 (+1 * DMASRCWDTH) */ +#define UNICOMMUART_SPGDMATXCTL_DMAMEMINCR_DECREMENT ((uint32_t)0x00100000U) /* !< Decremented by 1 (-1 * DMASRCWDTH) */ +/* UNICOMMUART_SPGDMATXCTL[DMAPREIRQ] Bits */ +#define UNICOMMUART_SPGDMATXCTL_DMAPREIRQ_OFS (24) /* !< DMAPREIRQ Offset */ +#define UNICOMMUART_SPGDMATXCTL_DMAPREIRQ_MASK ((uint32_t)0x01000000U) /* !< Enable an early IRQ event. This can + help software to react quicker to and + DMA done event or allows some + additional configuration before the + channel is complete. Note: This + register is only available in a + FULL-channel configuration. Please + consult the datasheet of the specific + device to map which channel number + has FULL or BASIC capability. In a + BASIC configuration this register is + a read only value and always reads as + 0x0. */ +#define UNICOMMUART_SPGDMATXCTL_DMAPREIRQ_PREIRQ_DISABLE ((uint32_t)0x00000000U) /* !< Pre-IRQ event disabled. */ +#define UNICOMMUART_SPGDMATXCTL_DMAPREIRQ_PREIRQ_HALF ((uint32_t)0x01000000U) /* !< Issue Pre-IRQ event when DMASZ + reached the half size point of the + original transfer size */ +/* UNICOMMUART_SPGDMATXCTL[DMATM] Bits */ +#define UNICOMMUART_SPGDMATXCTL_DMATM_OFS (27) /* !< DMATM Offset */ +#define UNICOMMUART_SPGDMATXCTL_DMATM_MASK ((uint32_t)0x08000000U) /* !< DMA transfer mode register Note: + The repeat-single (2h) and + repeat-block (3h) transfer are only + available in a FULL-channel + configuration. Please consult the + datasheet of the specific device to + map which channel number has FULL or + BASIC capability. In a BASIC channel + configuration only the values for + single (0h) and block (1h) transfer + can be set. */ +#define UNICOMMUART_SPGDMATXCTL_DMATM_SINGLE ((uint32_t)0x00000000U) /* !< Single transfer. Each transfer + requires a new trigger. When the + DMASZ counts down to zero an event + can be generated and the DMAEN is + cleared. */ +#define UNICOMMUART_SPGDMATXCTL_DMATM_RPTSNGL ((uint32_t)0x08000000U) /* !< Repeated single transfer. Each + transfer requires a new trigger. When + the DMASZ counts down to zero an + event can be generated. After the + last transfer the DMASA, DMADA, DAMSZ + registers are restored to its initial + value and the DMAEN stays enabled. */ +/* UNICOMMUART_SPGDMATXCTL[DMASRCWDTH] Bits */ +#define UNICOMMUART_SPGDMATXCTL_DMASRCWDTH_OFS (28) /* !< DMASRCWDTH Offset */ +#define UNICOMMUART_SPGDMATXCTL_DMASRCWDTH_MASK ((uint32_t)0x30000000U) /* !< DMA source width. This bit selects + the source data width as a byte, half + word, word or long word. */ +#define UNICOMMUART_SPGDMATXCTL_DMASRCWDTH_BYTE ((uint32_t)0x00000000U) /* !< Source data width is BYTE (8-bit) */ +#define UNICOMMUART_SPGDMATXCTL_DMASRCWDTH_HALF ((uint32_t)0x10000000U) /* !< Source data width is HALF-WORD + (16-bit) */ +#define UNICOMMUART_SPGDMATXCTL_DMASRCWDTH_WORD ((uint32_t)0x20000000U) /* !< Source data width is WORD (32-bit) */ + +/* UNICOMMUART_SPGDMATXSA Bits */ +/* UNICOMMUART_SPGDMATXSA[ADDR] Bits */ +#define UNICOMMUART_SPGDMATXSA_ADDR_OFS (0) /* !< ADDR Offset */ +#define UNICOMMUART_SPGDMATXSA_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< DMA Channel Destination Address */ +#define UNICOMMUART_SPGDMATXSA_ADDR_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_SPGDMATXSA_ADDR_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_SPGDMATXSZ Bits */ +/* UNICOMMUART_SPGDMATXSZ[SIZE] Bits */ +#define UNICOMMUART_SPGDMATXSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define UNICOMMUART_SPGDMATXSZ_SIZE_MASK ((uint32_t)0x0000FFFFU) /* !< DMA Channel Size in number of + transfers */ +#define UNICOMMUART_SPGDMATXSZ_SIZE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_SPGDMATXSZ_SIZE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_DMA_TRIG_TX_IMASK Bits */ +/* UNICOMMUART_DMA_TRIG_TX_IMASK[TXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_MASK ((uint32_t)0x00000800U) /* !< Enable UART Transmit Interrupt. */ +#define UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_SET ((uint32_t)0x00000800U) /* !< Set Interrupt Mask */ + +/* UNICOMMUART_DMA_TRIG_TX_RIS Bits */ +/* UNICOMMUART_DMA_TRIG_TX_RIS[TXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_TX_RIS_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_DMA_TRIG_TX_RIS_TXINT_MASK ((uint32_t)0x00000800U) /* !< UART Transmit Interrupt. */ +#define UNICOMMUART_DMA_TRIG_TX_RIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_DMA_TRIG_TX_RIS_TXINT_SET ((uint32_t)0x00000800U) /* !< Interrupt occurred */ + +/* UNICOMMUART_DMA_TRIG_TX_MIS Bits */ +/* UNICOMMUART_DMA_TRIG_TX_MIS[TXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_TX_MIS_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_DMA_TRIG_TX_MIS_TXINT_MASK ((uint32_t)0x00000800U) /* !< Masked UART Transmit Interrupt. */ +#define UNICOMMUART_DMA_TRIG_TX_MIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_DMA_TRIG_TX_MIS_TXINT_SET ((uint32_t)0x00000800U) /* !< Interrupt occurred */ + +/* UNICOMMUART_DMA_TRIG_TX_ISET Bits */ +/* UNICOMMUART_DMA_TRIG_TX_ISET[TXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_TX_ISET_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_DMA_TRIG_TX_ISET_TXINT_MASK ((uint32_t)0x00000800U) /* !< Set UART Transmit Interrupt. */ +#define UNICOMMUART_DMA_TRIG_TX_ISET_TXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_DMA_TRIG_TX_ISET_TXINT_SET ((uint32_t)0x00000800U) /* !< Set Interrupt */ + +/* UNICOMMUART_DMA_TRIG_RX_IMASK Bits */ +/* UNICOMMUART_DMA_TRIG_RX_IMASK[RTOUT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RTOUT_MASK ((uint32_t)0x00000001U) /* !< Enable UARTOUT Receive Time-Out + Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RTOUT_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_DMA_TRIG_RX_IMASK[RXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RXINT_MASK ((uint32_t)0x00000400U) /* !< Enable UART Receive Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_DMA_TRIG_RX_IMASK_RXINT_SET ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ + +/* UNICOMMUART_DMA_TRIG_RX_RIS Bits */ +/* UNICOMMUART_DMA_TRIG_RX_RIS[RTOUT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RTOUT_MASK ((uint32_t)0x00000001U) /* !< UARTOUT Receive Time-Out Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RTOUT_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* UNICOMMUART_DMA_TRIG_RX_RIS[RXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RXINT_MASK ((uint32_t)0x00000400U) /* !< UART Receive Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_DMA_TRIG_RX_RIS_RXINT_SET ((uint32_t)0x00000400U) /* !< Interrupt occurred */ + +/* UNICOMMUART_DMA_TRIG_RX_MIS Bits */ +/* UNICOMMUART_DMA_TRIG_RX_MIS[RTOUT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RTOUT_MASK ((uint32_t)0x00000001U) /* !< Masked UARTOUT Receive Time-Out + Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RTOUT_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* UNICOMMUART_DMA_TRIG_RX_MIS[RXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RXINT_MASK ((uint32_t)0x00000400U) /* !< Masked UART Receive Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_DMA_TRIG_RX_MIS_RXINT_SET ((uint32_t)0x00000400U) /* !< Interrupt occurred */ + +/* UNICOMMUART_DMA_TRIG_RX_ISET Bits */ +/* UNICOMMUART_DMA_TRIG_RX_ISET[RTOUT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RTOUT_MASK ((uint32_t)0x00000001U) /* !< Set UARTOUT Receive Time-Out + Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RTOUT_SET ((uint32_t)0x00000001U) /* !< Set Interrupt */ +/* UNICOMMUART_DMA_TRIG_RX_ISET[RXINT] Bits */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RXINT_MASK ((uint32_t)0x00000400U) /* !< Set UART Receive Interrupt. */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_DMA_TRIG_RX_ISET_RXINT_SET ((uint32_t)0x00000400U) /* !< Set Interrupt */ + +/* UNICOMMUART_IIDX Bits */ +/* UNICOMMUART_IIDX[STAT] Bits */ +#define UNICOMMUART_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define UNICOMMUART_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< UART Module Interrupt Vector Value. + This register provides the highes + priority interrupt index. A read + clears the corresponding interrupt + flag in RIS and MIS registers. + 15h-1Fh = Reserved */ +#define UNICOMMUART_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define UNICOMMUART_IIDX_STAT_RTFG ((uint32_t)0x00000001U) /* !< UART receive time-out interrupt; + Interrupt Flag: RT; Interrupt + Priority: Highest */ +#define UNICOMMUART_IIDX_STAT_FEFG ((uint32_t)0x00000002U) /* !< UART framing error interrupt; + Interrupt Flag: FE */ +#define UNICOMMUART_IIDX_STAT_PEFG ((uint32_t)0x00000003U) /* !< UART parity error interrupt; + Interrupt Flag: PE */ +#define UNICOMMUART_IIDX_STAT_BEFG ((uint32_t)0x00000004U) /* !< UART break error interrupt; + Interrupt Flag: BE */ +#define UNICOMMUART_IIDX_STAT_OEFG ((uint32_t)0x00000005U) /* !< UART receive overrun error + interrupt; Interrupt Flag: OE */ +#define UNICOMMUART_IIDX_STAT_RXNE ((uint32_t)0x00000006U) /* !< Negative edge on UARTxRXD + interrupt; Interrupt Flag: RXNE */ +#define UNICOMMUART_IIDX_STAT_RXPE ((uint32_t)0x00000007U) /* !< Positive edge on UARTxRXD + interrupt; Interrupt Flag: RXPE */ +#define UNICOMMUART_IIDX_STAT_LINC0 ((uint32_t)0x00000008U) /* !< LIN capture 0 / match interrupt; + Interrupt Flag: LINC0 */ +#define UNICOMMUART_IIDX_STAT_LINC1 ((uint32_t)0x00000009U) /* !< LIN capture 1 interrupt; Interrupt + Flag: LINC1 */ +#define UNICOMMUART_IIDX_STAT_LINOVF ((uint32_t)0x0000000AU) /* !< LIN hardware counter overflow + interrupt; Interrupt Flag: LINOVF */ +#define UNICOMMUART_IIDX_STAT_RXIFG ((uint32_t)0x0000000BU) /* !< UART receive interrupt; Interrupt + Flag: RX */ +#define UNICOMMUART_IIDX_STAT_TXIFG ((uint32_t)0x0000000CU) /* !< UART transmit interrupt; Interrupt + Flag: TX */ +#define UNICOMMUART_IIDX_STAT_EOT ((uint32_t)0x0000000DU) /* !< UART end of transmission interrupt + (transmit serializer empty); + Interrupt Flag: EOT */ +#define UNICOMMUART_IIDX_STAT_ADDR_MATCH ((uint32_t)0x0000000EU) /* !< 9-bit mode address match interrupt; + Interrupt Flag: ADDR_MATCH */ +#define UNICOMMUART_IIDX_STAT_CTS ((uint32_t)0x0000000FU) /* !< UART Clear to Send Modem interrupt; + Interrupt Flag: CTS */ +#define UNICOMMUART_IIDX_STAT_DMA_DONE_RX ((uint32_t)0x00000010U) /* !< DMA DONE on RX */ +#define UNICOMMUART_IIDX_STAT_DMA_DONE_TX ((uint32_t)0x00000011U) /* !< DMA DONE on TX */ +#define UNICOMMUART_IIDX_STAT_NERR_EVT ((uint32_t)0x00000012U) /* !< Noise Error Event */ +#define UNICOMMUART_IIDX_STAT_DMA_PREIRQ_RX ((uint32_t)0x00000013U) /* !< DMA PRE IRQ INTERRUPT */ +#define UNICOMMUART_IIDX_STAT_DMA_PREIRQ_TX ((uint32_t)0x00000014U) /* !< DMA PRE IRQ INTERRUPT */ +#define UNICOMMUART_IIDX_STAT_LTFG ((uint32_t)0x00000015U) /* !< UART line time-out interrupt; + Interrupt Flag */ + +/* UNICOMMUART_CPU_INT_IMASK Bits */ +/* UNICOMMUART_CPU_INT_IMASK[FRMERR] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_FRMERR_OFS (1) /* !< FRMERR Offset */ +#define UNICOMMUART_CPU_INT_IMASK_FRMERR_MASK ((uint32_t)0x00000002U) /* !< Enable UART Framing Error + Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_FRMERR_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_FRMERR_SET ((uint32_t)0x00000002U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[PARERR] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_PARERR_OFS (2) /* !< PARERR Offset */ +#define UNICOMMUART_CPU_INT_IMASK_PARERR_MASK ((uint32_t)0x00000004U) /* !< Enable UART Parity Error Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_PARERR_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_PARERR_SET ((uint32_t)0x00000004U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[BRKERR] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_BRKERR_OFS (3) /* !< BRKERR Offset */ +#define UNICOMMUART_CPU_INT_IMASK_BRKERR_MASK ((uint32_t)0x00000008U) /* !< Enable UART Break Error Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_BRKERR_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_BRKERR_SET ((uint32_t)0x00000008U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[OVRERR] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_OVRERR_OFS (4) /* !< OVRERR Offset */ +#define UNICOMMUART_CPU_INT_IMASK_OVRERR_MASK ((uint32_t)0x00000010U) /* !< Enable UART Receive Overrun Error + Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_OVRERR_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_OVRERR_SET ((uint32_t)0x00000010U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[RXNE] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_RXNE_OFS (5) /* !< RXNE Offset */ +#define UNICOMMUART_CPU_INT_IMASK_RXNE_MASK ((uint32_t)0x00000020U) /* !< Enable Negative Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_RXNE_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_RXNE_SET ((uint32_t)0x00000020U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[RXPE] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_RXPE_OFS (6) /* !< RXPE Offset */ +#define UNICOMMUART_CPU_INT_IMASK_RXPE_MASK ((uint32_t)0x00000040U) /* !< Enable Positive Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_RXPE_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_RXPE_SET ((uint32_t)0x00000040U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[LINOVF] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_LINOVF_OFS (9) /* !< LINOVF Offset */ +#define UNICOMMUART_CPU_INT_IMASK_LINOVF_MASK ((uint32_t)0x00000200U) /* !< Enable LIN Hardware Counter + Overflow Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_LINOVF_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_LINOVF_SET ((uint32_t)0x00000200U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[RXINT] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_CPU_INT_IMASK_RXINT_MASK ((uint32_t)0x00000400U) /* !< Enable UART Receive Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_RXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_RXINT_SET ((uint32_t)0x00000400U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[TXINT] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_CPU_INT_IMASK_TXINT_MASK ((uint32_t)0x00000800U) /* !< Enable UART Transmit Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_TXINT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_TXINT_SET ((uint32_t)0x00000800U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[EOT] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_EOT_OFS (12) /* !< EOT Offset */ +#define UNICOMMUART_CPU_INT_IMASK_EOT_MASK ((uint32_t)0x00001000U) /* !< Enable UART End of Transmission + Interrupt Indicates that the last bit + of all transmitted data and flags has + left the serializer and without any + further Data in the TX Fifo or + Buffer. */ +#define UNICOMMUART_CPU_INT_IMASK_EOT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_EOT_SET ((uint32_t)0x00001000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[ADDR_MATCH] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_ADDR_MATCH_OFS (13) /* !< ADDR_MATCH Offset */ +#define UNICOMMUART_CPU_INT_IMASK_ADDR_MATCH_MASK ((uint32_t)0x00002000U) /* !< Enable Address Match Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_ADDR_MATCH_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_ADDR_MATCH_SET ((uint32_t)0x00002000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[CTS] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_CTS_OFS (14) /* !< CTS Offset */ +#define UNICOMMUART_CPU_INT_IMASK_CTS_MASK ((uint32_t)0x00004000U) /* !< Enable UART Clear to Send Modem + Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_CTS_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_IMASK_CTS_SET ((uint32_t)0x00004000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[DMA_DONE_RX] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Enable DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[DMA_DONE_TX] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Enable DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[RTOUT] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_CPU_INT_IMASK_RTOUT_MASK ((uint32_t)0x00000001U) /* !< Enable UARTOUT Receive Time-Out + Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_RTOUT_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[LINC0] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_LINC0_OFS (7) /* !< LINC0 Offset */ +#define UNICOMMUART_CPU_INT_IMASK_LINC0_MASK ((uint32_t)0x00000080U) /* !< Enable LIN Capture 0 / Match + Interrupt . */ +#define UNICOMMUART_CPU_INT_IMASK_LINC0_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_LINC0_SET ((uint32_t)0x00000080U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[LINC1] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_LINC1_OFS (8) /* !< LINC1 Offset */ +#define UNICOMMUART_CPU_INT_IMASK_LINC1_MASK ((uint32_t)0x00000100U) /* !< Enable LIN Capture 1 Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_LINC1_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_LINC1_SET ((uint32_t)0x00000100U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[NERR] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_NERR_OFS (17) /* !< NERR Offset */ +#define UNICOMMUART_CPU_INT_IMASK_NERR_MASK ((uint32_t)0x00020000U) /* !< Noise Error on triple voting. + Asserted when the 3 samples of + majority voting are not equal */ +#define UNICOMMUART_CPU_INT_IMASK_NERR_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_NERR_SET ((uint32_t)0x00020000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[DMA_PREIRQ_RX] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Enable DMA Done PREIRQ RX interrupt */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[DMA_PREIRQ_TX] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Enable DMA Done PREIRQ TX interrupt */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_IMASK_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt Mask */ +/* UNICOMMUART_CPU_INT_IMASK[LTOUT] Bits */ +#define UNICOMMUART_CPU_INT_IMASK_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMUART_CPU_INT_IMASK_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Enable UARTOUT Line Time-Out + Interrupt. */ +#define UNICOMMUART_CPU_INT_IMASK_LTOUT_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */ +#define UNICOMMUART_CPU_INT_IMASK_LTOUT_SET ((uint32_t)0x00100000U) /* !< Set Interrupt Mask */ + +/* UNICOMMUART_CPU_INT_RIS Bits */ +/* UNICOMMUART_CPU_INT_RIS[RTOUT] Bits */ +#define UNICOMMUART_CPU_INT_RIS_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_CPU_INT_RIS_RTOUT_MASK ((uint32_t)0x00000001U) /* !< UARTOUT Receive Time-Out Interrupt. + Interupt is raised when a time-out + has lapsed and there are still items + in the FIFO */ +#define UNICOMMUART_CPU_INT_RIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_RTOUT_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[FRMERR] Bits */ +#define UNICOMMUART_CPU_INT_RIS_FRMERR_OFS (1) /* !< FRMERR Offset */ +#define UNICOMMUART_CPU_INT_RIS_FRMERR_MASK ((uint32_t)0x00000002U) /* !< UART Framing Error Interrupt. + Framing error interrupt is raised + when a "low" stop bit is detected. */ +#define UNICOMMUART_CPU_INT_RIS_FRMERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_FRMERR_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[PARERR] Bits */ +#define UNICOMMUART_CPU_INT_RIS_PARERR_OFS (2) /* !< PARERR Offset */ +#define UNICOMMUART_CPU_INT_RIS_PARERR_MASK ((uint32_t)0x00000004U) /* !< UART Parity Error Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_PARERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_PARERR_SET ((uint32_t)0x00000004U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[BRKERR] Bits */ +#define UNICOMMUART_CPU_INT_RIS_BRKERR_OFS (3) /* !< BRKERR Offset */ +#define UNICOMMUART_CPU_INT_RIS_BRKERR_MASK ((uint32_t)0x00000008U) /* !< UART Break Error Interrupt. Break + Error Interrupt is raised when all + data bits, parity bit and stop bits + are '0' */ +#define UNICOMMUART_CPU_INT_RIS_BRKERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_BRKERR_SET ((uint32_t)0x00000008U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[OVRERR] Bits */ +#define UNICOMMUART_CPU_INT_RIS_OVRERR_OFS (4) /* !< OVRERR Offset */ +#define UNICOMMUART_CPU_INT_RIS_OVRERR_MASK ((uint32_t)0x00000010U) /* !< UART Receive Overrun Error + Interrupt. UART Receive Overrun + Error Interrupt is raised when the + receive FIFO is flow and a new frame + is received */ +#define UNICOMMUART_CPU_INT_RIS_OVRERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_OVRERR_SET ((uint32_t)0x00000010U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[RXNE] Bits */ +#define UNICOMMUART_CPU_INT_RIS_RXNE_OFS (5) /* !< RXNE Offset */ +#define UNICOMMUART_CPU_INT_RIS_RXNE_MASK ((uint32_t)0x00000020U) /* !< Negative Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_RXNE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_RXNE_SET ((uint32_t)0x00000020U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[RXPE] Bits */ +#define UNICOMMUART_CPU_INT_RIS_RXPE_OFS (6) /* !< RXPE Offset */ +#define UNICOMMUART_CPU_INT_RIS_RXPE_MASK ((uint32_t)0x00000040U) /* !< Positive Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_RXPE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_RXPE_SET ((uint32_t)0x00000040U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[LINC0] Bits */ +#define UNICOMMUART_CPU_INT_RIS_LINC0_OFS (7) /* !< LINC0 Offset */ +#define UNICOMMUART_CPU_INT_RIS_LINC0_MASK ((uint32_t)0x00000080U) /* !< LIN Capture 0 / Match Interrupt . */ +#define UNICOMMUART_CPU_INT_RIS_LINC0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_LINC0_SET ((uint32_t)0x00000080U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[LINC1] Bits */ +#define UNICOMMUART_CPU_INT_RIS_LINC1_OFS (8) /* !< LINC1 Offset */ +#define UNICOMMUART_CPU_INT_RIS_LINC1_MASK ((uint32_t)0x00000100U) /* !< LIN Capture 1 Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_LINC1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_LINC1_SET ((uint32_t)0x00000100U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[LINOVF] Bits */ +#define UNICOMMUART_CPU_INT_RIS_LINOVF_OFS (9) /* !< LINOVF Offset */ +#define UNICOMMUART_CPU_INT_RIS_LINOVF_MASK ((uint32_t)0x00000200U) /* !< LIN Hardware Counter Overflow + Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_LINOVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_LINOVF_SET ((uint32_t)0x00000200U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[RXINT] Bits */ +#define UNICOMMUART_CPU_INT_RIS_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_CPU_INT_RIS_RXINT_MASK ((uint32_t)0x00000400U) /* !< UART Receive Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_RXINT_SET ((uint32_t)0x00000400U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[TXINT] Bits */ +#define UNICOMMUART_CPU_INT_RIS_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_CPU_INT_RIS_TXINT_MASK ((uint32_t)0x00000800U) /* !< UART Transmit Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_TXINT_SET ((uint32_t)0x00000800U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[EOT] Bits */ +#define UNICOMMUART_CPU_INT_RIS_EOT_OFS (12) /* !< EOT Offset */ +#define UNICOMMUART_CPU_INT_RIS_EOT_MASK ((uint32_t)0x00001000U) /* !< UART End of Transmission Interrupt + Indicates that the last bit of all + transmitted data and flags has left + the serializer and without any + further Data in the TX Fifo or + Buffer. */ +#define UNICOMMUART_CPU_INT_RIS_EOT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_EOT_SET ((uint32_t)0x00001000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[ADDR_MATCH] Bits */ +#define UNICOMMUART_CPU_INT_RIS_ADDR_MATCH_OFS (13) /* !< ADDR_MATCH Offset */ +#define UNICOMMUART_CPU_INT_RIS_ADDR_MATCH_MASK ((uint32_t)0x00002000U) /* !< Address Match Interrupt. */ +#define UNICOMMUART_CPU_INT_RIS_ADDR_MATCH_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_ADDR_MATCH_SET ((uint32_t)0x00002000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[CTS] Bits */ +#define UNICOMMUART_CPU_INT_RIS_CTS_OFS (14) /* !< CTS Offset */ +#define UNICOMMUART_CPU_INT_RIS_CTS_MASK ((uint32_t)0x00004000U) /* !< UART Clear to Send Modem Interrupt. + This interrupt is raised when CTS + toggles, either from '0' to '1' or + from '1' to '0'. */ +#define UNICOMMUART_CPU_INT_RIS_CTS_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_RIS_CTS_SET ((uint32_t)0x00004000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[DMA_DONE_RX] Bits */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[DMA_DONE_TX] Bits */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_RIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[NERR] Bits */ +#define UNICOMMUART_CPU_INT_RIS_NERR_OFS (17) /* !< NERR Offset */ +#define UNICOMMUART_CPU_INT_RIS_NERR_MASK ((uint32_t)0x00020000U) /* !< Noise Error on triple voting. + Asserted when the 3 samples of + majority voting are not equal */ +#define UNICOMMUART_CPU_INT_RIS_NERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_NERR_SET ((uint32_t)0x00020000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< DMA Pre-emptive Interrupt Done on + RX Event Channel Interrupt */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< DMA Pre-Emptive Done on TX Event + Channel Interrupt */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_RIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_RIS[LTOUT] Bits */ +#define UNICOMMUART_CPU_INT_RIS_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMUART_CPU_INT_RIS_LTOUT_MASK ((uint32_t)0x00100000U) /* !< UARTOUT Line Time-Out Interrupt. + Set: no start edge has been detected + for an additional character period + after reception of last character. + This is irrespective of FIFO contents + Clear: timeout has not occured */ +#define UNICOMMUART_CPU_INT_RIS_LTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_RIS_LTOUT_SET ((uint32_t)0x00100000U) /* !< Interrupt occurred */ + +/* UNICOMMUART_CPU_INT_MIS Bits */ +/* UNICOMMUART_CPU_INT_MIS[RTOUT] Bits */ +#define UNICOMMUART_CPU_INT_MIS_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_CPU_INT_MIS_RTOUT_MASK ((uint32_t)0x00000001U) /* !< Masked UARTOUT Receive Time-Out + Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_RTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_RTOUT_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[FRMERR] Bits */ +#define UNICOMMUART_CPU_INT_MIS_FRMERR_OFS (1) /* !< FRMERR Offset */ +#define UNICOMMUART_CPU_INT_MIS_FRMERR_MASK ((uint32_t)0x00000002U) /* !< Masked UART Framing Error + Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_FRMERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_FRMERR_SET ((uint32_t)0x00000002U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[PARERR] Bits */ +#define UNICOMMUART_CPU_INT_MIS_PARERR_OFS (2) /* !< PARERR Offset */ +#define UNICOMMUART_CPU_INT_MIS_PARERR_MASK ((uint32_t)0x00000004U) /* !< Masked UART Parity Error Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_PARERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_PARERR_SET ((uint32_t)0x00000004U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[BRKERR] Bits */ +#define UNICOMMUART_CPU_INT_MIS_BRKERR_OFS (3) /* !< BRKERR Offset */ +#define UNICOMMUART_CPU_INT_MIS_BRKERR_MASK ((uint32_t)0x00000008U) /* !< Masked UART Break Error Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_BRKERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_BRKERR_SET ((uint32_t)0x00000008U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[OVRERR] Bits */ +#define UNICOMMUART_CPU_INT_MIS_OVRERR_OFS (4) /* !< OVRERR Offset */ +#define UNICOMMUART_CPU_INT_MIS_OVRERR_MASK ((uint32_t)0x00000010U) /* !< Masked UART Receive Overrun Error + Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_OVRERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_OVRERR_SET ((uint32_t)0x00000010U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[RXNE] Bits */ +#define UNICOMMUART_CPU_INT_MIS_RXNE_OFS (5) /* !< RXNE Offset */ +#define UNICOMMUART_CPU_INT_MIS_RXNE_MASK ((uint32_t)0x00000020U) /* !< Masked Negative Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_RXNE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_RXNE_SET ((uint32_t)0x00000020U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[RXPE] Bits */ +#define UNICOMMUART_CPU_INT_MIS_RXPE_OFS (6) /* !< RXPE Offset */ +#define UNICOMMUART_CPU_INT_MIS_RXPE_MASK ((uint32_t)0x00000040U) /* !< Masked Positive Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_RXPE_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_RXPE_SET ((uint32_t)0x00000040U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[LINC0] Bits */ +#define UNICOMMUART_CPU_INT_MIS_LINC0_OFS (7) /* !< LINC0 Offset */ +#define UNICOMMUART_CPU_INT_MIS_LINC0_MASK ((uint32_t)0x00000080U) /* !< Masked LIN Capture 0 / Match + Interrupt . */ +#define UNICOMMUART_CPU_INT_MIS_LINC0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_LINC0_SET ((uint32_t)0x00000080U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[LINC1] Bits */ +#define UNICOMMUART_CPU_INT_MIS_LINC1_OFS (8) /* !< LINC1 Offset */ +#define UNICOMMUART_CPU_INT_MIS_LINC1_MASK ((uint32_t)0x00000100U) /* !< Masked LIN Capture 1 Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_LINC1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_LINC1_SET ((uint32_t)0x00000100U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[LINOVF] Bits */ +#define UNICOMMUART_CPU_INT_MIS_LINOVF_OFS (9) /* !< LINOVF Offset */ +#define UNICOMMUART_CPU_INT_MIS_LINOVF_MASK ((uint32_t)0x00000200U) /* !< Masked LIN Hardware Counter + Overflow Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_LINOVF_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_LINOVF_SET ((uint32_t)0x00000200U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[RXINT] Bits */ +#define UNICOMMUART_CPU_INT_MIS_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_CPU_INT_MIS_RXINT_MASK ((uint32_t)0x00000400U) /* !< Masked UART Receive Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_RXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_RXINT_SET ((uint32_t)0x00000400U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[TXINT] Bits */ +#define UNICOMMUART_CPU_INT_MIS_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_CPU_INT_MIS_TXINT_MASK ((uint32_t)0x00000800U) /* !< Masked UART Transmit Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_TXINT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_TXINT_SET ((uint32_t)0x00000800U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[EOT] Bits */ +#define UNICOMMUART_CPU_INT_MIS_EOT_OFS (12) /* !< EOT Offset */ +#define UNICOMMUART_CPU_INT_MIS_EOT_MASK ((uint32_t)0x00001000U) /* !< UART End of Transmission Interrupt + Indicates that the last bit of all + transmitted data and flags has left + the serializer and without any + further Data in the TX Fifo or + Buffer. */ +#define UNICOMMUART_CPU_INT_MIS_EOT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_EOT_SET ((uint32_t)0x00001000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[ADDR_MATCH] Bits */ +#define UNICOMMUART_CPU_INT_MIS_ADDR_MATCH_OFS (13) /* !< ADDR_MATCH Offset */ +#define UNICOMMUART_CPU_INT_MIS_ADDR_MATCH_MASK ((uint32_t)0x00002000U) /* !< Masked Address Match Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_ADDR_MATCH_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_ADDR_MATCH_SET ((uint32_t)0x00002000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[CTS] Bits */ +#define UNICOMMUART_CPU_INT_MIS_CTS_OFS (14) /* !< CTS Offset */ +#define UNICOMMUART_CPU_INT_MIS_CTS_MASK ((uint32_t)0x00004000U) /* !< Masked UART Clear to Send Modem + Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_CTS_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_CTS_SET ((uint32_t)0x00004000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[DMA_DONE_RX] Bits */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Masked DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[DMA_DONE_TX] Bits */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Masked DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[NERR] Bits */ +#define UNICOMMUART_CPU_INT_MIS_NERR_OFS (17) /* !< NERR Offset */ +#define UNICOMMUART_CPU_INT_MIS_NERR_MASK ((uint32_t)0x00020000U) /* !< Noise Error on triple voting. + Asserted when the 3 samples of + majority voting are not equal */ +#define UNICOMMUART_CPU_INT_MIS_NERR_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_NERR_SET ((uint32_t)0x00020000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[DMA_PREIRQ_RX] Bits */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Masked DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_RX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[DMA_PREIRQ_TX] Bits */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Masked DMA Done PREIRQ on TX Event + Channel Interrupt */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_TX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Interrupt occurred */ +/* UNICOMMUART_CPU_INT_MIS[LTOUT] Bits */ +#define UNICOMMUART_CPU_INT_MIS_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMUART_CPU_INT_MIS_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Masked UARTOUT Line Time-Out + Interrupt. */ +#define UNICOMMUART_CPU_INT_MIS_LTOUT_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define UNICOMMUART_CPU_INT_MIS_LTOUT_SET ((uint32_t)0x00100000U) /* !< Interrupt occurred */ + +/* UNICOMMUART_CPU_INT_ISET Bits */ +/* UNICOMMUART_CPU_INT_ISET[FRMERR] Bits */ +#define UNICOMMUART_CPU_INT_ISET_FRMERR_OFS (1) /* !< FRMERR Offset */ +#define UNICOMMUART_CPU_INT_ISET_FRMERR_MASK ((uint32_t)0x00000002U) /* !< Set UART Framing Error Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_FRMERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_FRMERR_SET ((uint32_t)0x00000002U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[PARERR] Bits */ +#define UNICOMMUART_CPU_INT_ISET_PARERR_OFS (2) /* !< PARERR Offset */ +#define UNICOMMUART_CPU_INT_ISET_PARERR_MASK ((uint32_t)0x00000004U) /* !< Set UART Parity Error Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_PARERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_PARERR_SET ((uint32_t)0x00000004U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[BRKERR] Bits */ +#define UNICOMMUART_CPU_INT_ISET_BRKERR_OFS (3) /* !< BRKERR Offset */ +#define UNICOMMUART_CPU_INT_ISET_BRKERR_MASK ((uint32_t)0x00000008U) /* !< Set UART Break Error Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_BRKERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_BRKERR_SET ((uint32_t)0x00000008U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[OVRERR] Bits */ +#define UNICOMMUART_CPU_INT_ISET_OVRERR_OFS (4) /* !< OVRERR Offset */ +#define UNICOMMUART_CPU_INT_ISET_OVRERR_MASK ((uint32_t)0x00000010U) /* !< Set UART Receive Overrun Error + Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_OVRERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_OVRERR_SET ((uint32_t)0x00000010U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[RXNE] Bits */ +#define UNICOMMUART_CPU_INT_ISET_RXNE_OFS (5) /* !< RXNE Offset */ +#define UNICOMMUART_CPU_INT_ISET_RXNE_MASK ((uint32_t)0x00000020U) /* !< Set Negative Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_RXNE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_RXNE_SET ((uint32_t)0x00000020U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[RXPE] Bits */ +#define UNICOMMUART_CPU_INT_ISET_RXPE_OFS (6) /* !< RXPE Offset */ +#define UNICOMMUART_CPU_INT_ISET_RXPE_MASK ((uint32_t)0x00000040U) /* !< Set Positive Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_RXPE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_RXPE_SET ((uint32_t)0x00000040U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[LINC0] Bits */ +#define UNICOMMUART_CPU_INT_ISET_LINC0_OFS (7) /* !< LINC0 Offset */ +#define UNICOMMUART_CPU_INT_ISET_LINC0_MASK ((uint32_t)0x00000080U) /* !< Set LIN Capture 0 / Match Interrupt + . */ +#define UNICOMMUART_CPU_INT_ISET_LINC0_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_LINC0_SET ((uint32_t)0x00000080U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[LINC1] Bits */ +#define UNICOMMUART_CPU_INT_ISET_LINC1_OFS (8) /* !< LINC1 Offset */ +#define UNICOMMUART_CPU_INT_ISET_LINC1_MASK ((uint32_t)0x00000100U) /* !< Set LIN Capture 1 Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_LINC1_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_LINC1_SET ((uint32_t)0x00000100U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[LINOVF] Bits */ +#define UNICOMMUART_CPU_INT_ISET_LINOVF_OFS (9) /* !< LINOVF Offset */ +#define UNICOMMUART_CPU_INT_ISET_LINOVF_MASK ((uint32_t)0x00000200U) /* !< Set LIN Hardware Counter Overflow + Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_LINOVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_LINOVF_SET ((uint32_t)0x00000200U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[RXINT] Bits */ +#define UNICOMMUART_CPU_INT_ISET_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_CPU_INT_ISET_RXINT_MASK ((uint32_t)0x00000400U) /* !< Set UART Receive Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_RXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_RXINT_SET ((uint32_t)0x00000400U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[TXINT] Bits */ +#define UNICOMMUART_CPU_INT_ISET_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_CPU_INT_ISET_TXINT_MASK ((uint32_t)0x00000800U) /* !< Set UART Transmit Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_TXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_TXINT_SET ((uint32_t)0x00000800U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[EOT] Bits */ +#define UNICOMMUART_CPU_INT_ISET_EOT_OFS (12) /* !< EOT Offset */ +#define UNICOMMUART_CPU_INT_ISET_EOT_MASK ((uint32_t)0x00001000U) /* !< Set UART End of Transmission + Interrupt Indicates that the last bit + of all transmitted data and flags has + left the serializer and without any + further Data in the TX Fifo or + Buffer. */ +#define UNICOMMUART_CPU_INT_ISET_EOT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_EOT_SET ((uint32_t)0x00001000U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[ADDR_MATCH] Bits */ +#define UNICOMMUART_CPU_INT_ISET_ADDR_MATCH_OFS (13) /* !< ADDR_MATCH Offset */ +#define UNICOMMUART_CPU_INT_ISET_ADDR_MATCH_MASK ((uint32_t)0x00002000U) /* !< Set Address Match Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_ADDR_MATCH_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_ADDR_MATCH_SET ((uint32_t)0x00002000U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[CTS] Bits */ +#define UNICOMMUART_CPU_INT_ISET_CTS_OFS (14) /* !< CTS Offset */ +#define UNICOMMUART_CPU_INT_ISET_CTS_MASK ((uint32_t)0x00004000U) /* !< Set UART Clear to Send Modem + Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_CTS_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_CTS_SET ((uint32_t)0x00004000U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[DMA_DONE_RX] Bits */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Set DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_RX_SET ((uint32_t)0x00008000U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[DMA_DONE_TX] Bits */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Set DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_ISET_DMA_DONE_TX_SET ((uint32_t)0x00010000U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[RTOUT] Bits */ +#define UNICOMMUART_CPU_INT_ISET_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_CPU_INT_ISET_RTOUT_MASK ((uint32_t)0x00000001U) /* !< Set UARTOUT Receive Time-Out + Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_RTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_RTOUT_SET ((uint32_t)0x00000001U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[NERR] Bits */ +#define UNICOMMUART_CPU_INT_ISET_NERR_OFS (17) /* !< NERR Offset */ +#define UNICOMMUART_CPU_INT_ISET_NERR_MASK ((uint32_t)0x00020000U) /* !< Noise Error on triple voting. + Asserted when the 3 samples of + majority voting are not equal */ +#define UNICOMMUART_CPU_INT_ISET_NERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing this has no effect */ +#define UNICOMMUART_CPU_INT_ISET_NERR_SET ((uint32_t)0x00020000U) /* !< Set the interrupt */ +/* UNICOMMUART_CPU_INT_ISET[DMA_PREIRQ_RX] Bits */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Set DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_RX_SET ((uint32_t)0x00040000U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[DMA_PREIRQ_TX] Bits */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Set DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_CPU_INT_ISET_DMA_PREIRQ_TX_SET ((uint32_t)0x00080000U) /* !< Set Interrupt */ +/* UNICOMMUART_CPU_INT_ISET[LTOUT] Bits */ +#define UNICOMMUART_CPU_INT_ISET_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMUART_CPU_INT_ISET_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Set UARTOUT Line Time-Out + Interrupt. */ +#define UNICOMMUART_CPU_INT_ISET_LTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_CPU_INT_ISET_LTOUT_SET ((uint32_t)0x00100000U) /* !< Set Interrupt */ + +/* UNICOMMUART_ICLR Bits */ +/* UNICOMMUART_ICLR[FRMERR] Bits */ +#define UNICOMMUART_ICLR_FRMERR_OFS (1) /* !< FRMERR Offset */ +#define UNICOMMUART_ICLR_FRMERR_MASK ((uint32_t)0x00000002U) /* !< Clear UART Framing Error Interrupt. */ +#define UNICOMMUART_ICLR_FRMERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_FRMERR_CLR ((uint32_t)0x00000002U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[PARERR] Bits */ +#define UNICOMMUART_ICLR_PARERR_OFS (2) /* !< PARERR Offset */ +#define UNICOMMUART_ICLR_PARERR_MASK ((uint32_t)0x00000004U) /* !< Clear UART Parity Error Interrupt. */ +#define UNICOMMUART_ICLR_PARERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_PARERR_CLR ((uint32_t)0x00000004U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[BRKERR] Bits */ +#define UNICOMMUART_ICLR_BRKERR_OFS (3) /* !< BRKERR Offset */ +#define UNICOMMUART_ICLR_BRKERR_MASK ((uint32_t)0x00000008U) /* !< Clear UART Break Error Interrupt. */ +#define UNICOMMUART_ICLR_BRKERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_BRKERR_CLR ((uint32_t)0x00000008U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[OVRERR] Bits */ +#define UNICOMMUART_ICLR_OVRERR_OFS (4) /* !< OVRERR Offset */ +#define UNICOMMUART_ICLR_OVRERR_MASK ((uint32_t)0x00000010U) /* !< Clear UART Receive Overrun Error + Interrupt. */ +#define UNICOMMUART_ICLR_OVRERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_OVRERR_CLR ((uint32_t)0x00000010U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[RXNE] Bits */ +#define UNICOMMUART_ICLR_RXNE_OFS (5) /* !< RXNE Offset */ +#define UNICOMMUART_ICLR_RXNE_MASK ((uint32_t)0x00000020U) /* !< Clear Negative Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_ICLR_RXNE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_RXNE_CLR ((uint32_t)0x00000020U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[RXPE] Bits */ +#define UNICOMMUART_ICLR_RXPE_OFS (6) /* !< RXPE Offset */ +#define UNICOMMUART_ICLR_RXPE_MASK ((uint32_t)0x00000040U) /* !< Clear Positive Edge on UARTxRXD + Interrupt. */ +#define UNICOMMUART_ICLR_RXPE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_RXPE_CLR ((uint32_t)0x00000040U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[LINC0] Bits */ +#define UNICOMMUART_ICLR_LINC0_OFS (7) /* !< LINC0 Offset */ +#define UNICOMMUART_ICLR_LINC0_MASK ((uint32_t)0x00000080U) /* !< Clear LIN Capture 0 / Match + Interrupt . */ +#define UNICOMMUART_ICLR_LINC0_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_LINC0_CLR ((uint32_t)0x00000080U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[LINC1] Bits */ +#define UNICOMMUART_ICLR_LINC1_OFS (8) /* !< LINC1 Offset */ +#define UNICOMMUART_ICLR_LINC1_MASK ((uint32_t)0x00000100U) /* !< Clear LIN Capture 1 Interrupt. */ +#define UNICOMMUART_ICLR_LINC1_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_LINC1_CLR ((uint32_t)0x00000100U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[LINOVF] Bits */ +#define UNICOMMUART_ICLR_LINOVF_OFS (9) /* !< LINOVF Offset */ +#define UNICOMMUART_ICLR_LINOVF_MASK ((uint32_t)0x00000200U) /* !< Clear LIN Hardware Counter Overflow + Interrupt. */ +#define UNICOMMUART_ICLR_LINOVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_LINOVF_CLR ((uint32_t)0x00000200U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[RXINT] Bits */ +#define UNICOMMUART_ICLR_RXINT_OFS (10) /* !< RXINT Offset */ +#define UNICOMMUART_ICLR_RXINT_MASK ((uint32_t)0x00000400U) /* !< Clear UART Receive Interrupt. */ +#define UNICOMMUART_ICLR_RXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_RXINT_CLR ((uint32_t)0x00000400U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[TXINT] Bits */ +#define UNICOMMUART_ICLR_TXINT_OFS (11) /* !< TXINT Offset */ +#define UNICOMMUART_ICLR_TXINT_MASK ((uint32_t)0x00000800U) /* !< Clear UART Transmit Interrupt. */ +#define UNICOMMUART_ICLR_TXINT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_TXINT_CLR ((uint32_t)0x00000800U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[EOT] Bits */ +#define UNICOMMUART_ICLR_EOT_OFS (12) /* !< EOT Offset */ +#define UNICOMMUART_ICLR_EOT_MASK ((uint32_t)0x00001000U) /* !< Clear UART End of Transmission + Interrupt Indicates that the last bit + of all transmitted data and flags has + left the serializer and without any + further Data in the TX Fifo or + Buffer. */ +#define UNICOMMUART_ICLR_EOT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_EOT_CLR ((uint32_t)0x00001000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[ADDR_MATCH] Bits */ +#define UNICOMMUART_ICLR_ADDR_MATCH_OFS (13) /* !< ADDR_MATCH Offset */ +#define UNICOMMUART_ICLR_ADDR_MATCH_MASK ((uint32_t)0x00002000U) /* !< Clear Address Match Interrupt. */ +#define UNICOMMUART_ICLR_ADDR_MATCH_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_ADDR_MATCH_CLR ((uint32_t)0x00002000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[CTS] Bits */ +#define UNICOMMUART_ICLR_CTS_OFS (14) /* !< CTS Offset */ +#define UNICOMMUART_ICLR_CTS_MASK ((uint32_t)0x00004000U) /* !< Clear UART Clear to Send Modem + Interrupt. */ +#define UNICOMMUART_ICLR_CTS_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_CTS_CLR ((uint32_t)0x00004000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[DMA_DONE_RX] Bits */ +#define UNICOMMUART_ICLR_DMA_DONE_RX_OFS (15) /* !< DMA_DONE_RX Offset */ +#define UNICOMMUART_ICLR_DMA_DONE_RX_MASK ((uint32_t)0x00008000U) /* !< Clear DMA Done on RX Event Channel + Interrupt */ +#define UNICOMMUART_ICLR_DMA_DONE_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_ICLR_DMA_DONE_RX_CLR ((uint32_t)0x00008000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[DMA_DONE_TX] Bits */ +#define UNICOMMUART_ICLR_DMA_DONE_TX_OFS (16) /* !< DMA_DONE_TX Offset */ +#define UNICOMMUART_ICLR_DMA_DONE_TX_MASK ((uint32_t)0x00010000U) /* !< Clear DMA Done on TX Event Channel + Interrupt */ +#define UNICOMMUART_ICLR_DMA_DONE_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_ICLR_DMA_DONE_TX_CLR ((uint32_t)0x00010000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[RTOUT] Bits */ +#define UNICOMMUART_ICLR_RTOUT_OFS (0) /* !< RTOUT Offset */ +#define UNICOMMUART_ICLR_RTOUT_MASK ((uint32_t)0x00000001U) /* !< Clear UARTOUT Receive Time-Out + Interrupt. */ +#define UNICOMMUART_ICLR_RTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_RTOUT_CLR ((uint32_t)0x00000001U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[NERR] Bits */ +#define UNICOMMUART_ICLR_NERR_OFS (17) /* !< NERR Offset */ +#define UNICOMMUART_ICLR_NERR_MASK ((uint32_t)0x00020000U) /* !< Noise Error on triple voting. + Asserted when the 3 samples of + majority voting are not equal */ +#define UNICOMMUART_ICLR_NERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_NERR_CLR ((uint32_t)0x00020000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[DMA_PREIRQ_RX] Bits */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_RX_OFS (18) /* !< DMA_PREIRQ_RX Offset */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_RX_MASK ((uint32_t)0x00040000U) /* !< Clear DMA PREIRQ Done on RX Event + Channel Interrupt */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_RX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_RX_CLR ((uint32_t)0x00040000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[DMA_PREIRQ_TX] Bits */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_TX_OFS (19) /* !< DMA_PREIRQ_TX Offset */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_TX_MASK ((uint32_t)0x00080000U) /* !< Clear DMA PREIRQ Done on TX Event + Channel Interrupt */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_TX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define UNICOMMUART_ICLR_DMA_PREIRQ_TX_CLR ((uint32_t)0x00080000U) /* !< Clear Interrupt */ +/* UNICOMMUART_ICLR[LTOUT] Bits */ +#define UNICOMMUART_ICLR_LTOUT_OFS (20) /* !< LTOUT Offset */ +#define UNICOMMUART_ICLR_LTOUT_MASK ((uint32_t)0x00100000U) /* !< Clear UARTOUT Line Time-Out + Interrupt. */ +#define UNICOMMUART_ICLR_LTOUT_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define UNICOMMUART_ICLR_LTOUT_CLR ((uint32_t)0x00100000U) /* !< Clear Interrupt */ + +/* UNICOMMUART_CLKDIV Bits */ +/* UNICOMMUART_CLKDIV[RATIO] Bits */ +#define UNICOMMUART_CLKDIV_RATIO_OFS (0) /* !< RATIO Offset */ +#define UNICOMMUART_CLKDIV_RATIO_MASK ((uint32_t)0x0000003FU) /* !< Selects divide ratio of module + clock Division factor 0 : DIV_BY_1 + 1 : DIV_BY_2 .... 63: DIV_BY_64 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_1 ((uint32_t)0x00000000U) /* !< Do not divide clock source */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_2 ((uint32_t)0x00000001U) /* !< Divide clock source by 2 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_3 ((uint32_t)0x00000002U) /* !< Divide clock source by 3 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_4 ((uint32_t)0x00000003U) /* !< Divide clock source by 4 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_5 ((uint32_t)0x00000004U) /* !< Divide clock source by 5 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_6 ((uint32_t)0x00000005U) /* !< Divide clock source by 6 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_7 ((uint32_t)0x00000006U) /* !< Divide clock source by 7 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_8 ((uint32_t)0x00000007U) /* !< Divide clock source by 8 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_61 ((uint32_t)0x0000003CU) /* !< Divide clock source by 8 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_62 ((uint32_t)0x0000003DU) /* !< Divide clock source by 8 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_63 ((uint32_t)0x0000003EU) /* !< Divide clock source by 8 */ +#define UNICOMMUART_CLKDIV_RATIO_DIV_BY_64 ((uint32_t)0x0000003FU) /* !< Divide clock source by 8 */ + +/* UNICOMMUART_CLKSEL Bits */ +/* UNICOMMUART_CLKSEL[MFCLK_SEL] Bits */ +#define UNICOMMUART_CLKSEL_MFCLK_SEL_OFS (2) /* !< MFCLK_SEL Offset */ +#define UNICOMMUART_CLKSEL_MFCLK_SEL_MASK ((uint32_t)0x00000004U) /* !< Selects MFCLK as clock source if + enabled */ +#define UNICOMMUART_CLKSEL_MFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMUART_CLKSEL_MFCLK_SEL_ENABLE ((uint32_t)0x00000004U) /* !< Select this clock as a source */ +/* UNICOMMUART_CLKSEL[BUSCLK_SEL] Bits */ +#define UNICOMMUART_CLKSEL_BUSCLK_SEL_OFS (3) /* !< BUSCLK_SEL Offset */ +#define UNICOMMUART_CLKSEL_BUSCLK_SEL_MASK ((uint32_t)0x00000008U) /* !< Selects BUS CLK as clock source if + enabled */ +#define UNICOMMUART_CLKSEL_BUSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMUART_CLKSEL_BUSCLK_SEL_ENABLE ((uint32_t)0x00000008U) /* !< Select this clock as a source */ +/* UNICOMMUART_CLKSEL[LFCLK_SEL] Bits */ +#define UNICOMMUART_CLKSEL_LFCLK_SEL_OFS (1) /* !< LFCLK_SEL Offset */ +#define UNICOMMUART_CLKSEL_LFCLK_SEL_MASK ((uint32_t)0x00000002U) /* !< Selects LFCLK as clock source if + enabled */ +#define UNICOMMUART_CLKSEL_LFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMUART_CLKSEL_LFCLK_SEL_ENABLE ((uint32_t)0x00000002U) /* !< Select this clock as a source */ +/* UNICOMMUART_CLKSEL[ASYNC_LFCLK_SEL] Bits */ +#define UNICOMMUART_CLKSEL_ASYNC_LFCLK_SEL_OFS (8) /* !< ASYNC_LFCLK_SEL Offset */ +#define UNICOMMUART_CLKSEL_ASYNC_LFCLK_SEL_MASK ((uint32_t)0x00000100U) /* !< Asynchronous lfclk selected as + source */ +#define UNICOMMUART_CLKSEL_ASYNC_LFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMUART_CLKSEL_ASYNC_LFCLK_SEL_ENABLE ((uint32_t)0x00000100U) /* !< Select this clock as a source */ +/* UNICOMMUART_CLKSEL[ASYNC_SYSCLK_SEL] Bits */ +#define UNICOMMUART_CLKSEL_ASYNC_SYSCLK_SEL_OFS (9) /* !< ASYNC_SYSCLK_SEL Offset */ +#define UNICOMMUART_CLKSEL_ASYNC_SYSCLK_SEL_MASK ((uint32_t)0x00000200U) /* !< Asynchronous sysclk selected as + source */ +#define UNICOMMUART_CLKSEL_ASYNC_SYSCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMUART_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE ((uint32_t)0x00000200U) /* !< Select this clock as a source */ +/* UNICOMMUART_CLKSEL[ASYNC_HFCLK_SEL] Bits */ +#define UNICOMMUART_CLKSEL_ASYNC_HFCLK_SEL_OFS (10) /* !< ASYNC_HFCLK_SEL Offset */ +#define UNICOMMUART_CLKSEL_ASYNC_HFCLK_SEL_MASK ((uint32_t)0x00000400U) /* !< Asynchronous HFCLK selected as + source */ +#define UNICOMMUART_CLKSEL_ASYNC_HFCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMUART_CLKSEL_ASYNC_HFCLK_SEL_ENABLE ((uint32_t)0x00000400U) /* !< Select this clock as a source */ +/* UNICOMMUART_CLKSEL[ASYNC_PLL_SEL] Bits */ +#define UNICOMMUART_CLKSEL_ASYNC_PLL_SEL_OFS (11) /* !< ASYNC_PLL_SEL Offset */ +#define UNICOMMUART_CLKSEL_ASYNC_PLL_SEL_MASK ((uint32_t)0x00000800U) /* !< Asynchronous PLL selected as source */ +#define UNICOMMUART_CLKSEL_ASYNC_PLL_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a + source */ +#define UNICOMMUART_CLKSEL_ASYNC_PLL_SEL_ENABLE ((uint32_t)0x00000800U) /* !< Select this clock as a source */ + +/* UNICOMMUART_PDBGCTL Bits */ +/* UNICOMMUART_PDBGCTL[FREE] Bits */ +#define UNICOMMUART_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */ +#define UNICOMMUART_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */ +#define UNICOMMUART_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes + functionality while the Core Halted + input is asserted and resumes when it + is deasserted. */ +#define UNICOMMUART_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of + the Core Halted input */ +/* UNICOMMUART_PDBGCTL[SOFT] Bits */ +#define UNICOMMUART_PDBGCTL_SOFT_OFS (1) /* !< SOFT Offset */ +#define UNICOMMUART_PDBGCTL_SOFT_MASK ((uint32_t)0x00000002U) /* !< Soft halt boundary control. This + function is only available, if [FREE] + is set to 'STOP' */ +#define UNICOMMUART_PDBGCTL_SOFT_DEPRECATED ((uint32_t)0x00000000U) /* !< Not supported */ +#define UNICOMMUART_PDBGCTL_SOFT_DELAYED ((uint32_t)0x00000002U) /* !< The peripheral blocks the debug + freeze until it has reached a + boundary where it can resume without + corruption */ + +/* UNICOMMUART_INTCTL Bits */ +/* UNICOMMUART_INTCTL[INTEVAL] Bits */ +#define UNICOMMUART_INTCTL_INTEVAL_OFS (0) /* !< INTEVAL Offset */ +#define UNICOMMUART_INTCTL_INTEVAL_MASK ((uint32_t)0x00000001U) /* !< Writing a 1 to this field + re-evaluates the interrupt sources. */ +#define UNICOMMUART_INTCTL_INTEVAL_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define UNICOMMUART_INTCTL_INTEVAL_EVAL ((uint32_t)0x00000001U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ + +/* UNICOMMUART_CTL0 Bits */ +/* UNICOMMUART_CTL0[ENABLE] Bits */ +#define UNICOMMUART_CTL0_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define UNICOMMUART_CTL0_ENABLE_MASK ((uint32_t)0x00000001U) /* !< UART Module Enable. If the UART is + disabled in the middle of + transmission or reception, it + completes the current character + before stopping. If the ENABLE bit + is not set, all registers can still + be accessed and updated. It is + recommended to setup and change the + UART operation mode with having the + ENABLE bit cleared to avoid + unpredictable behavior during the + setup or update. If disabled the UART + module will not send or receive any + data and the logic is held in reset + state. */ +#define UNICOMMUART_CTL0_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Module */ +#define UNICOMMUART_CTL0_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable module */ +/* UNICOMMUART_CTL0[HSE] Bits */ +#define UNICOMMUART_CTL0_HSE_OFS (15) /* !< HSE Offset */ +#define UNICOMMUART_CTL0_HSE_MASK ((uint32_t)0x00018000U) /* !< High-Speed Bit Oversampling Enable + #b#NOTE:#/b# The bit oversampling + influences the UART baud-rate + configuration. The state of this bit + has no effect on clock generation in + ISO7816 smart card mode (the SMART + bit is set). */ +#define UNICOMMUART_CTL0_HSE_OVS16 ((uint32_t)0x00000000U) /* !< 16x oversampling. */ +#define UNICOMMUART_CTL0_HSE_OVS8 ((uint32_t)0x00008000U) /* !< 8x oversampling. */ +#define UNICOMMUART_CTL0_HSE_OVS3 ((uint32_t)0x00010000U) /* !< 3x oversampling. IrDA, Manchester + and DALI not supported when 3x + oversampling is enabled. */ +/* UNICOMMUART_CTL0[LBE] Bits */ +#define UNICOMMUART_CTL0_LBE_OFS (2) /* !< LBE Offset */ +#define UNICOMMUART_CTL0_LBE_MASK ((uint32_t)0x00000004U) /* !< UART Loop Back Enable */ +#define UNICOMMUART_CTL0_LBE_DISABLE ((uint32_t)0x00000000U) /* !< Normal operation. */ +#define UNICOMMUART_CTL0_LBE_ENABLE ((uint32_t)0x00000004U) /* !< The UARTxTX path is fed through the + UARTxRX path internally. */ +/* UNICOMMUART_CTL0[RXE] Bits */ +#define UNICOMMUART_CTL0_RXE_OFS (3) /* !< RXE Offset */ +#define UNICOMMUART_CTL0_RXE_MASK ((uint32_t)0x00000008U) /* !< UART Receive Enable If the UART is + disabled in the middle of a receive, + it completes the current character + before stopping. #b#NOTE:#/b# To + enable reception, the UARTEN bit must + be set. */ +#define UNICOMMUART_CTL0_RXE_DISABLE ((uint32_t)0x00000000U) /* !< The receive section of the UART is + disabled. */ +#define UNICOMMUART_CTL0_RXE_ENABLE ((uint32_t)0x00000008U) /* !< The receive section of the UART is + enabled. */ +/* UNICOMMUART_CTL0[TXE] Bits */ +#define UNICOMMUART_CTL0_TXE_OFS (4) /* !< TXE Offset */ +#define UNICOMMUART_CTL0_TXE_MASK ((uint32_t)0x00000010U) /* !< UART Transmit Enable If the UART + is disabled in the middle of a + transmission, it completes the + current character before stopping. + #b#NOTE:#/b# To enable transmission, + the UARTEN bit must be set. */ +#define UNICOMMUART_CTL0_TXE_DISABLE ((uint32_t)0x00000000U) /* !< The transmit section of the UART is + disabled. The UARTxTXD pin of the + UART can be controlled by the TXD_CTL + bit when enabled. */ +#define UNICOMMUART_CTL0_TXE_ENABLE ((uint32_t)0x00000010U) /* !< The transmit section of the UART is + enabled. */ +/* UNICOMMUART_CTL0[RTS] Bits */ +#define UNICOMMUART_CTL0_RTS_OFS (12) /* !< RTS Offset */ +#define UNICOMMUART_CTL0_RTS_MASK ((uint32_t)0x00001000U) /* !< Request to Send If RTSEN is set + the RTS output signals is controlled + by the hardware logic using the FIFO + fill level or buffer status. If + RTSEN is cleared the RTS output is + controlled by the RTS bit. The bit is + the complement of the UART request to + send, RTS modem status output. */ +#define UNICOMMUART_CTL0_RTS_CLR ((uint32_t)0x00000000U) /* !< Signal not RTS */ +#define UNICOMMUART_CTL0_RTS_SET ((uint32_t)0x00001000U) /* !< Signal RTS */ +/* UNICOMMUART_CTL0[RTSEN] Bits */ +#define UNICOMMUART_CTL0_RTSEN_OFS (13) /* !< RTSEN Offset */ +#define UNICOMMUART_CTL0_RTSEN_MASK ((uint32_t)0x00002000U) /* !< Enable hardware controlled Request + to Send */ +#define UNICOMMUART_CTL0_RTSEN_DISABLE ((uint32_t)0x00000000U) /* !< RTS hardware flow control is + disabled. */ +#define UNICOMMUART_CTL0_RTSEN_ENABLE ((uint32_t)0x00002000U) /* !< RTS hardware flow control is + enabled. Data is only requested (by + asserting UARTxRTS) when the receive + FIFO/buffer has available entries. */ +/* UNICOMMUART_CTL0[CTSEN] Bits */ +#define UNICOMMUART_CTL0_CTSEN_OFS (14) /* !< CTSEN Offset */ +#define UNICOMMUART_CTL0_CTSEN_MASK ((uint32_t)0x00004000U) /* !< Enable Clear To Send */ +#define UNICOMMUART_CTL0_CTSEN_DISABLE ((uint32_t)0x00000000U) /* !< CTS hardware flow control is + disabled. */ +#define UNICOMMUART_CTL0_CTSEN_ENABLE ((uint32_t)0x00004000U) /* !< CTS hardware flow control is + enabled. Data is only transmitted + when the UARTxCTS signal is asserted. */ +/* UNICOMMUART_CTL0[MENC] Bits */ +#define UNICOMMUART_CTL0_MENC_OFS (7) /* !< MENC Offset */ +#define UNICOMMUART_CTL0_MENC_MASK ((uint32_t)0x00000080U) /* !< Manchester Encode enable */ +#define UNICOMMUART_CTL0_MENC_DISABLE ((uint32_t)0x00000000U) /* !< Disable Manchester Encoding */ +#define UNICOMMUART_CTL0_MENC_ENABLE ((uint32_t)0x00000080U) /* !< Enable Manchester Encoding */ +/* UNICOMMUART_CTL0[MODE] Bits */ +#define UNICOMMUART_CTL0_MODE_OFS (8) /* !< MODE Offset */ +#define UNICOMMUART_CTL0_MODE_MASK ((uint32_t)0x00000700U) /* !< Set the communication mode and + protocol used. (Not defined settings + uses the default setting: 0) */ +#define UNICOMMUART_CTL0_MODE_UART ((uint32_t)0x00000000U) /* !< Normal operation */ +#define UNICOMMUART_CTL0_MODE_RS485 ((uint32_t)0x00000100U) /* !< RS485 mode: UART needs to be IDLE + with receiving data for the in + EXTDIR_HOLD set time. EXTDIR_SETUP + defines the time the RTS line is set + to high before sending. When the + buffer is empty the RTS line is set + low again. A transmit will be delayed + as long the UART is receiving data. */ +#define UNICOMMUART_CTL0_MODE_IDLELINE ((uint32_t)0x00000200U) /* !< The UART operates in IDLE Line Mode */ +#define UNICOMMUART_CTL0_MODE_ADDR9BIT ((uint32_t)0x00000300U) /* !< The UART operates in 9 Bit Address + mode */ +#define UNICOMMUART_CTL0_MODE_SMART ((uint32_t)0x00000400U) /* !< ISO7816 Smart Card Support The + application must ensure that it sets + 8-bit word length (WLEN set to 3h) + and even parity (PEN set to 1, EPS + set to 1, SPS set to 0) in UARTLCRH + when using ISO7816 mode. The value of + the STP2 bit in UARTLCRH is ignored + and the number of stop bits is forced + to 2. */ +#define UNICOMMUART_CTL0_MODE_DALI ((uint32_t)0x00000500U) /* !< DALI Mode: */ +/* UNICOMMUART_CTL0[TXD_OUT] Bits */ +#define UNICOMMUART_CTL0_TXD_OUT_OFS (6) /* !< TXD_OUT Offset */ +#define UNICOMMUART_CTL0_TXD_OUT_MASK ((uint32_t)0x00000040U) /* !< TXD Pin Control Controls the TXD + pin when TXD_OUT_EN = 1 and TXE = 0. */ +#define UNICOMMUART_CTL0_TXD_OUT_LOW ((uint32_t)0x00000000U) /* !< TXD pin is low */ +#define UNICOMMUART_CTL0_TXD_OUT_HIGH ((uint32_t)0x00000040U) /* !< TXD pin is high */ +/* UNICOMMUART_CTL0[TXD_OUT_EN] Bits */ +#define UNICOMMUART_CTL0_TXD_OUT_EN_OFS (5) /* !< TXD_OUT_EN Offset */ +#define UNICOMMUART_CTL0_TXD_OUT_EN_MASK ((uint32_t)0x00000020U) /* !< TXD Pin Control Enable. When the + transmit section of the UART is + disabled (TXE = 0), the TXD pin can + be controlled by the TXD_OUT bit. */ +#define UNICOMMUART_CTL0_TXD_OUT_EN_DISABLE ((uint32_t)0x00000000U) /* !< TXD pin can not be controlled by + TXD_OUT */ +#define UNICOMMUART_CTL0_TXD_OUT_EN_ENABLE ((uint32_t)0x00000020U) /* !< TXD pin can be controlled by + TXD_OUT */ +/* UNICOMMUART_CTL0[MAJVOTE] Bits */ +#define UNICOMMUART_CTL0_MAJVOTE_OFS (18) /* !< MAJVOTE Offset */ +#define UNICOMMUART_CTL0_MAJVOTE_MASK ((uint32_t)0x00040000U) /* !< Majority Vote Enable When + Majority Voting is enabled, the three + center bits are used to determine + received sample value. In case of + error (i.e. all 3 bits are not the + same), noise error is detected and + bits RIS.NERR and register + RXDATA.NERR are set. + Oversampling of 16 : bits 7, 8, 9 are + used Oversampling of 8 : bits 3, + 4, 5 are used Disabled : Single + sample value (center value) used */ +#define UNICOMMUART_CTL0_MAJVOTE_DISABLE ((uint32_t)0x00000000U) /* !< Majority voting is disabled */ +#define UNICOMMUART_CTL0_MAJVOTE_ENABLE ((uint32_t)0x00040000U) /* !< Majority voting is enabled */ +/* UNICOMMUART_CTL0[MSBFIRST] Bits */ +#define UNICOMMUART_CTL0_MSBFIRST_OFS (19) /* !< MSBFIRST Offset */ +#define UNICOMMUART_CTL0_MSBFIRST_MASK ((uint32_t)0x00080000U) /* !< Most Significant Bit First This bit + has effect both on the way protocol + byte is transmitted and received. + Notes: User needs to match the + protocol to the correct value of this + bit to send MSb or LSb first. The + hardware engine will send the byte + entirely based on this bit. */ +#define UNICOMMUART_CTL0_MSBFIRST_DISABLE ((uint32_t)0x00000000U) /* !< Least significant bit is sent first + in the protocol packet */ +#define UNICOMMUART_CTL0_MSBFIRST_ENABLE ((uint32_t)0x00080000U) /* !< Most significant bit is sent first + in the protocol packet */ + +/* UNICOMMUART_LCRH Bits */ +/* UNICOMMUART_LCRH[BRK] Bits */ +#define UNICOMMUART_LCRH_BRK_OFS (0) /* !< BRK Offset */ +#define UNICOMMUART_LCRH_BRK_MASK ((uint32_t)0x00000001U) /* !< UART Send Break (for LIN Protocol) + 1. Break condition is sent on the + line for as long as this bit is set */ +#define UNICOMMUART_LCRH_BRK_DISABLE ((uint32_t)0x00000000U) /* !< Normal operation */ +#define UNICOMMUART_LCRH_BRK_ENABLE ((uint32_t)0x00000001U) /* !< A low level is continually output + on the UARTxTXD signal, after + completing transmission of the + current character. For the proper + execution of the break command, + software must set this bit for at + least two frames (character periods). */ +/* UNICOMMUART_LCRH[PEN] Bits */ +#define UNICOMMUART_LCRH_PEN_OFS (1) /* !< PEN Offset */ +#define UNICOMMUART_LCRH_PEN_MASK ((uint32_t)0x00000002U) /* !< UART Parity Enable */ +#define UNICOMMUART_LCRH_PEN_DISABLE ((uint32_t)0x00000000U) /* !< Parity is disabled and no parity + bit is added to the data frame. */ +#define UNICOMMUART_LCRH_PEN_ENABLE ((uint32_t)0x00000002U) /* !< Parity checking and generation is + enabled. */ +/* UNICOMMUART_LCRH[EPS] Bits */ +#define UNICOMMUART_LCRH_EPS_OFS (2) /* !< EPS Offset */ +#define UNICOMMUART_LCRH_EPS_MASK ((uint32_t)0x00000004U) /* !< UART Even Parity Select This bit + has no effect when parity is disabled + by the PEN bit. For 9-Bit UART Mode + transmissions, this bit controls the + address byte and data byte indication + (9th bit). 0 = The transferred byte + is a data byte 1 = The transferred + byte is an address byte */ +#define UNICOMMUART_LCRH_EPS_ODD ((uint32_t)0x00000000U) /* !< Odd parity is performed, which + checks for an odd number of 1s. */ +#define UNICOMMUART_LCRH_EPS_EVEN ((uint32_t)0x00000004U) /* !< Even parity generation and checking + is performed during transmission and + reception, which checks for an even + number of 1s in data and parity bits. */ +/* UNICOMMUART_LCRH[STP2] Bits */ +#define UNICOMMUART_LCRH_STP2_OFS (3) /* !< STP2 Offset */ +#define UNICOMMUART_LCRH_STP2_MASK ((uint32_t)0x00000008U) /* !< UART Two Stop Bits Select When + in 7816 smart card mode (the SMART + bit is set in the UARTCTL register), + the number of stop bits is forced to + 2. */ +#define UNICOMMUART_LCRH_STP2_DISABLE ((uint32_t)0x00000000U) /* !< One stop bit is transmitted at the + end of a frame. */ +#define UNICOMMUART_LCRH_STP2_ENABLE ((uint32_t)0x00000008U) /* !< Two stop bits are transmitted at + the end of a frame. The receive logic + checks for two stop bits being + received and provide Frame Error if + either is invalid. */ +/* UNICOMMUART_LCRH[WLEN] Bits */ +#define UNICOMMUART_LCRH_WLEN_OFS (4) /* !< WLEN Offset */ +#define UNICOMMUART_LCRH_WLEN_MASK ((uint32_t)0x00000030U) /* !< UART Word Length The bits indicate + the number of data bits transmitted + or received in a frame as follows: */ +#define UNICOMMUART_LCRH_WLEN_DATABIT5 ((uint32_t)0x00000000U) /* !< 5 bits (default) */ +#define UNICOMMUART_LCRH_WLEN_DATABIT6 ((uint32_t)0x00000010U) /* !< 6 bits */ +#define UNICOMMUART_LCRH_WLEN_DATABIT7 ((uint32_t)0x00000020U) /* !< 7 bits */ +#define UNICOMMUART_LCRH_WLEN_DATABIT8 ((uint32_t)0x00000030U) /* !< 8 bits */ +/* UNICOMMUART_LCRH[SPS] Bits */ +#define UNICOMMUART_LCRH_SPS_OFS (6) /* !< SPS Offset */ +#define UNICOMMUART_LCRH_SPS_MASK ((uint32_t)0x00000040U) /* !< UART Stick Parity Select The Stick + Parity Select (SPS) bit is used to + set either a permanent '1' or a + permanent '0' as parity when + transmitting or receiving data. Its + purpose is to typically indicate the + first byte of a package or to mark an + address byte, for example in a + multi-drop RS-485 network. When bits + PEN, EPS, and SPS of UARTLCRH are + set, the parity bit is transmitted + and checked as a 0. When bits PEN + and SPS are set and EPS is cleared, + the parity bit is transmitted and + checked as a 1. */ +#define UNICOMMUART_LCRH_SPS_DISABLE ((uint32_t)0x00000000U) /* !< Disable Stick Parity */ +#define UNICOMMUART_LCRH_SPS_ENABLE ((uint32_t)0x00000040U) /* !< Enable Stick Parity */ +/* UNICOMMUART_LCRH[SENDIDLE] Bits */ +#define UNICOMMUART_LCRH_SENDIDLE_OFS (7) /* !< SENDIDLE Offset */ +#define UNICOMMUART_LCRH_SENDIDLE_MASK ((uint32_t)0x00000080U) /* !< UART send IDLE pattern. When this + bit is set, SENDIDLE period of 11 + bit times will be sent on the TX + line. Read STAT.SENDIDLE bit to + readback current status of SENDIDLE */ +#define UNICOMMUART_LCRH_SENDIDLE_DISABLE ((uint32_t)0x00000000U) /* !< Normal operation */ +#define UNICOMMUART_LCRH_SENDIDLE_ENABLE ((uint32_t)0x00000080U) /* !< Send Idle Pattern */ +/* UNICOMMUART_LCRH[EXTDIR_SETUP] Bits */ +#define UNICOMMUART_LCRH_EXTDIR_SETUP_OFS (16) /* !< EXTDIR_SETUP Offset */ +#define UNICOMMUART_LCRH_EXTDIR_SETUP_MASK ((uint32_t)0x001F0000U) /* !< Defines the number of UARTclk ticks + the signal to control the external + driver for the RS485 will be set + before the START bit is send */ +#define UNICOMMUART_LCRH_EXTDIR_SETUP_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_LCRH_EXTDIR_SETUP_MAXIMUM ((uint32_t)0x001F0000U) /* !< Highest possible value */ +/* UNICOMMUART_LCRH[EXTDIR_HOLD] Bits */ +#define UNICOMMUART_LCRH_EXTDIR_HOLD_OFS (21) /* !< EXTDIR_HOLD Offset */ +#define UNICOMMUART_LCRH_EXTDIR_HOLD_MASK ((uint32_t)0x03E00000U) /* !< Defines the number of UARTclk ticks + the signal to control the external + driver for the RS485 will be reset + after the beginning of the stop bit. + (If 2 STOP bits are enabled the + beginning of the 2nd STOP bit.) */ +#define UNICOMMUART_LCRH_EXTDIR_HOLD_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_LCRH_EXTDIR_HOLD_MAXIMUM ((uint32_t)0x03E00000U) /* !< Highest possible value */ +/* UNICOMMUART_LCRH[SUSPEND] Bits */ +#define UNICOMMUART_LCRH_SUSPEND_OFS (26) /* !< SUSPEND Offset */ +#define UNICOMMUART_LCRH_SUSPEND_MASK ((uint32_t)0x04000000U) /* !< Suspend external communication */ +#define UNICOMMUART_LCRH_SUSPEND_DISABLE ((uint32_t)0x00000000U) /* !< Functional mode resumed */ +#define UNICOMMUART_LCRH_SUSPEND_ENABLE ((uint32_t)0x04000000U) /* !< External communication suspended */ + +/* UNICOMMUART_STAT Bits */ +/* UNICOMMUART_STAT[BUSY] Bits */ +#define UNICOMMUART_STAT_BUSY_OFS (0) /* !< BUSY Offset */ +#define UNICOMMUART_STAT_BUSY_MASK ((uint32_t)0x00000001U) /* !< UART Busy This bit is set as + soon as the transmit FIFO/buffer + becomes non-empty (regardless of + whether UART is enabled) or if a + receive data is currently ongoing + (after the start edge have been + detected until a complete byte, + including all stop bits, has been + received by the shift register). In + IDLE_Line mode the Busy signal also + stays set during the idle time + generation. */ +#define UNICOMMUART_STAT_BUSY_CLEARED ((uint32_t)0x00000000U) /* !< The UART is not busy. */ +#define UNICOMMUART_STAT_BUSY_SET ((uint32_t)0x00000001U) /* !< The UART is busy transmitting data. + This bit remains set until the + complete byte, including all stop + bits, has been sent/received + from/into the shift register. */ +/* UNICOMMUART_STAT[TXFF] Bits */ +#define UNICOMMUART_STAT_TXFF_OFS (6) /* !< TXFF Offset */ +#define UNICOMMUART_STAT_TXFF_MASK ((uint32_t)0x00000040U) /* !< UART Transmit FIFO Full The + meaning of this bit depends on the + state of the FEN bit in the CTL0 + register. */ +#define UNICOMMUART_STAT_TXFF_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter is not full. */ +#define UNICOMMUART_STAT_TXFF_SET ((uint32_t)0x00000040U) /* !< transmit FIFO is full. */ +/* UNICOMMUART_STAT[RXFF] Bits */ +#define UNICOMMUART_STAT_RXFF_OFS (3) /* !< RXFF Offset */ +#define UNICOMMUART_STAT_RXFF_MASK ((uint32_t)0x00000008U) /* !< UART Receive FIFO Full */ +#define UNICOMMUART_STAT_RXFF_CLEARED ((uint32_t)0x00000000U) /* !< The receiver can receive data. */ +#define UNICOMMUART_STAT_RXFF_SET ((uint32_t)0x00000008U) /* !< receive FIFO is full. */ +/* UNICOMMUART_STAT[TXFE] Bits */ +#define UNICOMMUART_STAT_TXFE_OFS (5) /* !< TXFE Offset */ +#define UNICOMMUART_STAT_TXFE_MASK ((uint32_t)0x00000020U) /* !< UART Transmit FIFO Empty */ +#define UNICOMMUART_STAT_TXFE_CLEARED ((uint32_t)0x00000000U) /* !< The transmitter has data to + transmit. */ +#define UNICOMMUART_STAT_TXFE_SET ((uint32_t)0x00000020U) /* !< transmit FIFO is empty. */ +/* UNICOMMUART_STAT[CTS] Bits */ +#define UNICOMMUART_STAT_CTS_OFS (8) /* !< CTS Offset */ +#define UNICOMMUART_STAT_CTS_MASK ((uint32_t)0x00000100U) /* !< Clear To Send */ +#define UNICOMMUART_STAT_CTS_CLEARED ((uint32_t)0x00000000U) /* !< The CTS signal is not asserted + (high). */ +#define UNICOMMUART_STAT_CTS_SET ((uint32_t)0x00000100U) /* !< The CTS signal is asserted (low). */ +/* UNICOMMUART_STAT[IDLE] Bits */ +#define UNICOMMUART_STAT_IDLE_OFS (9) /* !< IDLE Offset */ +#define UNICOMMUART_STAT_IDLE_MASK ((uint32_t)0x00000200U) /* !< IDLE mode has been detected in + Idleline-Multiprocessor-Mode. The + IDLE bit is used as an address tag + for each block of characters. In + idle-line multiprocessor format, this + bit is set when a received character + is an address. */ +#define UNICOMMUART_STAT_IDLE_CLEARED ((uint32_t)0x00000000U) /* !< IDLE has not been detected before + last received character. (In + idle-line multiprocessor mode). */ +#define UNICOMMUART_STAT_IDLE_SET ((uint32_t)0x00000200U) /* !< IDLE has been detected before last + received character. (In idle-line + multiprocessor mode). */ +/* UNICOMMUART_STAT[RXFE] Bits */ +#define UNICOMMUART_STAT_RXFE_OFS (2) /* !< RXFE Offset */ +#define UNICOMMUART_STAT_RXFE_MASK ((uint32_t)0x00000004U) /* !< UART Receive FIFO Empty */ +#define UNICOMMUART_STAT_RXFE_CLEARED ((uint32_t)0x00000000U) /* !< The receiver is not empty. */ +#define UNICOMMUART_STAT_RXFE_SET ((uint32_t)0x00000004U) /* !< eceive FIFO is empty. */ +/* UNICOMMUART_STAT[RXCLR] Bits */ +#define UNICOMMUART_STAT_RXCLR_OFS (4) /* !< RXCLR Offset */ +#define UNICOMMUART_STAT_RXCLR_MASK ((uint32_t)0x00000010U) /* !< RX FIFO Clear Status */ +#define UNICOMMUART_STAT_RXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMUART_STAT_RXCLR_SET ((uint32_t)0x00000010U) /* !< FIFO clear is complete */ +/* UNICOMMUART_STAT[TXCLR] Bits */ +#define UNICOMMUART_STAT_TXCLR_OFS (7) /* !< TXCLR Offset */ +#define UNICOMMUART_STAT_TXCLR_MASK ((uint32_t)0x00000080U) /* !< TX FIFO Clear Status */ +#define UNICOMMUART_STAT_TXCLR_CLEARED ((uint32_t)0x00000000U) /* !< FIFO is not cleared */ +#define UNICOMMUART_STAT_TXCLR_SET ((uint32_t)0x00000080U) /* !< FIFO clear is complete */ +/* UNICOMMUART_STAT[SENDIDLE] Bits */ +#define UNICOMMUART_STAT_SENDIDLE_OFS (10) /* !< SENDIDLE Offset */ +#define UNICOMMUART_STAT_SENDIDLE_MASK ((uint32_t)0x00000400U) /* !< TX FIFO Clear Status */ +#define UNICOMMUART_STAT_SENDIDLE_CLEARED ((uint32_t)0x00000000U) /* !< IDLE condition has not yet been + sent on the line */ +#define UNICOMMUART_STAT_SENDIDLE_SET ((uint32_t)0x00000400U) /* !< IDLE condition has been sent on the + line */ + +/* UNICOMMUART_IFLS Bits */ +/* UNICOMMUART_IFLS[TXIFLSEL] Bits */ +#define UNICOMMUART_IFLS_TXIFLSEL_OFS (0) /* !< TXIFLSEL Offset */ +#define UNICOMMUART_IFLS_TXIFLSEL_MASK ((uint32_t)0x00000007U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMUART_IFLS_TXIFLSEL_LVL_3_4 ((uint32_t)0x00000001U) /* !< TX FIFO <= 3/4 empty */ +#define UNICOMMUART_IFLS_TXIFLSEL_LVL_1_2 ((uint32_t)0x00000002U) /* !< TX FIFO <= 1/2 empty (default) */ +#define UNICOMMUART_IFLS_TXIFLSEL_LVL_1_4 ((uint32_t)0x00000003U) /* !< TX FIFO <= 1/4 empty */ +#define UNICOMMUART_IFLS_TXIFLSEL_LVL_NOT_FULL ((uint32_t)0x00000004U) /* !< Opposite of full */ +#define UNICOMMUART_IFLS_TXIFLSEL_LVL_EMPTY ((uint32_t)0x00000005U) /* !< TX FIFO is empty */ +#define UNICOMMUART_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000006U) /* !< TX FIFO <= 1 */ +#define UNICOMMUART_IFLS_TXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000007U) /* !< TX_FIFO >= (MAX_FIFO_LEN -1) */ +/* UNICOMMUART_IFLS[RXIFLSEL] Bits */ +#define UNICOMMUART_IFLS_RXIFLSEL_OFS (4) /* !< RXIFLSEL Offset */ +#define UNICOMMUART_IFLS_RXIFLSEL_MASK ((uint32_t)0x00000070U) /* !< FIFO Level Select for generating + events (interrupt/dma). Note: for + undefined settings the default + configuration is used. */ +#define UNICOMMUART_IFLS_RXIFLSEL_LVL_1_4 ((uint32_t)0x00000010U) /* !< RX FIFO >= 1/4 full */ +#define UNICOMMUART_IFLS_RXIFLSEL_LVL_1_2 ((uint32_t)0x00000020U) /* !< RX FIFO >= 1/2 full (default) */ +#define UNICOMMUART_IFLS_RXIFLSEL_LVL_3_4 ((uint32_t)0x00000030U) /* !< RX FIFO >= 3/4 full */ +#define UNICOMMUART_IFLS_RXIFLSEL_LVL_NOT_EMPTY ((uint32_t)0x00000040U) /* !< Opposite of empty */ +#define UNICOMMUART_IFLS_RXIFLSEL_LVL_FULL ((uint32_t)0x00000050U) /* !< RX FIFO is full */ +#define UNICOMMUART_IFLS_RXIFLSEL_LVL_ALMOST_FULL ((uint32_t)0x00000060U) /* !< RX_FIFO >= (MAX_FIFO_LEN -1) */ +#define UNICOMMUART_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY ((uint32_t)0x00000070U) /* !< RX_FIFO <= 1 */ +/* UNICOMMUART_IFLS[RXTOSEL] Bits */ +#define UNICOMMUART_IFLS_RXTOSEL_OFS (8) /* !< RXTOSEL Offset */ +#define UNICOMMUART_IFLS_RXTOSEL_MASK ((uint32_t)0x00000F00U) /* !< UART Receive Interrupt Timeout + Select. When receiving no start edge + for an additional character within + the set bittimes a RX interrupt is + set even if the FIFO level is not + reached. A value of 0 disables this + function. */ +#define UNICOMMUART_IFLS_RXTOSEL_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_IFLS_RXTOSEL_MAXIMUM ((uint32_t)0x00000F00U) /* !< Highest possible value */ +/* UNICOMMUART_IFLS[TXCLR] Bits */ +#define UNICOMMUART_IFLS_TXCLR_OFS (3) /* !< TXCLR Offset */ +#define UNICOMMUART_IFLS_TXCLR_MASK ((uint32_t)0x00000008U) /* !< TX FIFO CLEAR. Setting this bit + will clear the TX FIFO contents. */ +#define UNICOMMUART_IFLS_TXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMUART_IFLS_TXCLR_ENABLE ((uint32_t)0x00000008U) /* !< Enable FIFO Clear */ +/* UNICOMMUART_IFLS[RXCLR] Bits */ +#define UNICOMMUART_IFLS_RXCLR_OFS (7) /* !< RXCLR Offset */ +#define UNICOMMUART_IFLS_RXCLR_MASK ((uint32_t)0x00000080U) /* !< RX FIFO CLEAR. Setting this bit + will clear the RX FIFO contents. */ +#define UNICOMMUART_IFLS_RXCLR_DISABLE ((uint32_t)0x00000000U) /* !< Disable FIFO clear */ +#define UNICOMMUART_IFLS_RXCLR_ENABLE ((uint32_t)0x00000080U) /* !< Enable FIFO Clear */ + +/* UNICOMMUART_IBRD Bits */ +/* UNICOMMUART_IBRD[DIVINT] Bits */ +#define UNICOMMUART_IBRD_DIVINT_OFS (0) /* !< DIVINT Offset */ +#define UNICOMMUART_IBRD_DIVINT_MASK ((uint32_t)0x0000FFFFU) /* !< Integer Baud-Rate Divisor */ +#define UNICOMMUART_IBRD_DIVINT_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_IBRD_DIVINT_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_FBRD Bits */ +/* UNICOMMUART_FBRD[DIVFRAC] Bits */ +#define UNICOMMUART_FBRD_DIVFRAC_OFS (0) /* !< DIVFRAC Offset */ +#define UNICOMMUART_FBRD_DIVFRAC_MASK ((uint32_t)0x0000003FU) /* !< Fractional Baud-Rate Divisor */ +#define UNICOMMUART_FBRD_DIVFRAC_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_FBRD_DIVFRAC_MAXIMUM ((uint32_t)0x0000003FU) /* !< Highest possible value */ + +/* UNICOMMUART_GFCTL Bits */ +/* UNICOMMUART_GFCTL[DGFSEL] Bits */ +#define UNICOMMUART_GFCTL_DGFSEL_OFS (0) /* !< DGFSEL Offset */ +#define UNICOMMUART_GFCTL_DGFSEL_MASK ((uint32_t)0x0000003FU) /* !< Glitch Suppression Pulse Width + This field controls the pulse width + select for glitch suppression on the + RX line. The value programmed in + this field gives the number of cycles + of functional clock up to which the + glitch has to be suppressed on the RX + line. In IRDA mode: The minimum + pulse length for receive is given by: + t(MIN) = (DGFSEL) / f(IRTXCLK) */ +#define UNICOMMUART_GFCTL_DGFSEL_DISABLED ((uint32_t)0x00000000U) /* !< Bypass GF */ +#define UNICOMMUART_GFCTL_DGFSEL_MAXIMUM ((uint32_t)0x0000003FU) /* !< Highest Possible Value */ + +/* UNICOMMUART_TXDATA Bits */ +/* UNICOMMUART_TXDATA[DATA] Bits */ +#define UNICOMMUART_TXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMUART_TXDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< Data Transmitted or Received Data + that is to be transmitted via the + UART is written to this field. When + read, this field contains the data + that was received by the UART. */ +#define UNICOMMUART_TXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_TXDATA_DATA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ + +/* UNICOMMUART_RXDATA Bits */ +/* UNICOMMUART_RXDATA[DATA] Bits */ +#define UNICOMMUART_RXDATA_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMUART_RXDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< Received Data. When read, this + field contains the data that was + received by the UART. */ +#define UNICOMMUART_RXDATA_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_RXDATA_DATA_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ +/* UNICOMMUART_RXDATA[FRMERR] Bits */ +#define UNICOMMUART_RXDATA_FRMERR_OFS (8) /* !< FRMERR Offset */ +#define UNICOMMUART_RXDATA_FRMERR_MASK ((uint32_t)0x00000100U) /* !< UART Framing Error Writing to this + bit has no effect. The flag is + cleared by writing 1 to the FRMERR + bit in the UART EVENT ICLR register. + This error is associated with the + character at the top of the FIFO. */ +#define UNICOMMUART_RXDATA_FRMERR_CLR ((uint32_t)0x00000000U) /* !< No framing error has occurred */ +#define UNICOMMUART_RXDATA_FRMERR_SET ((uint32_t)0x00000100U) /* !< The received character does not + have a valid stop bit sequence, which + is one or two stop bits depending on + the UARTLCRH.STP2 setting (a valid + stop bit is 1). */ +/* UNICOMMUART_RXDATA[PARERR] Bits */ +#define UNICOMMUART_RXDATA_PARERR_OFS (9) /* !< PARERR Offset */ +#define UNICOMMUART_RXDATA_PARERR_MASK ((uint32_t)0x00000200U) /* !< UART Parity Error Writing to this + bit has no effect. The flag is + cleared by writing 1 to the PARERR + bit in the UART EVENT ICLR register. */ +#define UNICOMMUART_RXDATA_PARERR_CLR ((uint32_t)0x00000000U) /* !< No parity error has occurred */ +#define UNICOMMUART_RXDATA_PARERR_SET ((uint32_t)0x00000200U) /* !< The parity of the received data + character does not match the parity + defined by bits 2 and 7 of the + UARTLCRH register. */ +/* UNICOMMUART_RXDATA[BRKERR] Bits */ +#define UNICOMMUART_RXDATA_BRKERR_OFS (10) /* !< BRKERR Offset */ +#define UNICOMMUART_RXDATA_BRKERR_MASK ((uint32_t)0x00000400U) /* !< UART Break Error Writing to this + bit has no effect. The flag is + cleared by writing 1 to the BRKERR + bit in the UART EVENT ICLR register. + This error is associated with the + character at the top of the FIFO. + When a break occurs, only one 0 + character is loaded into the FIFO. + The next character is only enabled + after the receive data input goes to + a 1 (marking state) and the next + valid start bit is received. */ +#define UNICOMMUART_RXDATA_BRKERR_CLR ((uint32_t)0x00000000U) /* !< No break condition has occurred */ +#define UNICOMMUART_RXDATA_BRKERR_SET ((uint32_t)0x00000400U) /* !< A break condition has been + detected, indicating that the receive + data input was held low for longer + than a full-word transmission time + (defined as start, data, parity, and + stop bits). */ +/* UNICOMMUART_RXDATA[NERR] Bits */ +#define UNICOMMUART_RXDATA_NERR_OFS (11) /* !< NERR Offset */ +#define UNICOMMUART_RXDATA_NERR_MASK ((uint32_t)0x00000800U) /* !< Noise Error. Writing to this bit + has no effect. The flag is cleared by + writing 1 to the NERR bit in the UART + EVENT ICLR register. */ +#define UNICOMMUART_RXDATA_NERR_CLR ((uint32_t)0x00000000U) /* !< No noise error occurred */ +#define UNICOMMUART_RXDATA_NERR_SET ((uint32_t)0x00000800U) /* !< Noise error occurred during + majority voting */ + +/* UNICOMMUART_LINCNT Bits */ +/* UNICOMMUART_LINCNT[VALUE] Bits */ +#define UNICOMMUART_LINCNT_VALUE_OFS (0) /* !< VALUE Offset */ +#define UNICOMMUART_LINCNT_VALUE_MASK ((uint32_t)0x0000FFFFU) /* !< 16 bit up counter clocked by the + functional clock of the UART. */ +#define UNICOMMUART_LINCNT_VALUE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_LINCNT_VALUE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_LINCTL Bits */ +/* UNICOMMUART_LINCTL[CTRENA] Bits */ +#define UNICOMMUART_LINCTL_CTRENA_OFS (0) /* !< CTRENA Offset */ +#define UNICOMMUART_LINCTL_CTRENA_MASK ((uint32_t)0x00000001U) /* !< LIN Counter Enable. LIN counter + will only count when enabled. */ +#define UNICOMMUART_LINCTL_CTRENA_DISABLE ((uint32_t)0x00000000U) /* !< Counter disabled */ +#define UNICOMMUART_LINCTL_CTRENA_ENABLE ((uint32_t)0x00000001U) /* !< Counter enabled */ +/* UNICOMMUART_LINCTL[ZERONE] Bits */ +#define UNICOMMUART_LINCTL_ZERONE_OFS (1) /* !< ZERONE Offset */ +#define UNICOMMUART_LINCTL_ZERONE_MASK ((uint32_t)0x00000002U) /* !< Zero on negative Edge of RXD. When + enabled the counter is set to 0 and + starts counting on a negative edge of + RXD */ +#define UNICOMMUART_LINCTL_ZERONE_DISABLE ((uint32_t)0x00000000U) /* !< Zero on negative edge disabled */ +#define UNICOMMUART_LINCTL_ZERONE_ENABLE ((uint32_t)0x00000002U) /* !< Zero on negative edge enabled */ +/* UNICOMMUART_LINCTL[CNTRXLOW] Bits */ +#define UNICOMMUART_LINCTL_CNTRXLOW_OFS (2) /* !< CNTRXLOW Offset */ +#define UNICOMMUART_LINCTL_CNTRXLOW_MASK ((uint32_t)0x00000004U) /* !< Count while low Signal on RXD When + counter is enabled and the signal on + RXD is low, the counter increments. */ +#define UNICOMMUART_LINCTL_CNTRXLOW_DISABLE ((uint32_t)0x00000000U) /* !< Count while low Signal on UARTxRXD + disabled */ +#define UNICOMMUART_LINCTL_CNTRXLOW_ENABLE ((uint32_t)0x00000004U) /* !< Count while low Signal on UARTxRXD + enabled */ +/* UNICOMMUART_LINCTL[LINC0CAP] Bits */ +#define UNICOMMUART_LINCTL_LINC0CAP_OFS (4) /* !< LINC0CAP Offset */ +#define UNICOMMUART_LINCTL_LINC0CAP_MASK ((uint32_t)0x00000010U) /* !< Capture Counter on negative RXD + Edge. When enabled the counter value + is captured to LINC0 register on each + negative RXD edge. A LINC0 interrupt + is triggered when enabled. */ +#define UNICOMMUART_LINCTL_LINC0CAP_DISABLE ((uint32_t)0x00000000U) /* !< Capture counter on negative + UARTxRXD edge disabled */ +#define UNICOMMUART_LINCTL_LINC0CAP_ENABLE ((uint32_t)0x00000010U) /* !< Capture counter on negative + UARTxRXD edge enabled */ +/* UNICOMMUART_LINCTL[LINC1CAP] Bits */ +#define UNICOMMUART_LINCTL_LINC1CAP_OFS (5) /* !< LINC1CAP Offset */ +#define UNICOMMUART_LINCTL_LINC1CAP_MASK ((uint32_t)0x00000020U) /* !< Capture Counter on positive RXD + Edge. When enabled the counter value + is captured to LINC1 register on each + positive RXD edge. A LINC1 interrupt + is triggered when enabled. */ +#define UNICOMMUART_LINCTL_LINC1CAP_DISABLE ((uint32_t)0x00000000U) /* !< Capture counter on positive + UARTxRXD edge disabled */ +#define UNICOMMUART_LINCTL_LINC1CAP_ENABLE ((uint32_t)0x00000020U) /* !< Capture counter on positive + UARTxRXD edge enabled */ +/* UNICOMMUART_LINCTL[LINC0_MATCH] Bits */ +#define UNICOMMUART_LINCTL_LINC0_MATCH_OFS (6) /* !< LINC0_MATCH Offset */ +#define UNICOMMUART_LINCTL_LINC0_MATCH_MASK ((uint32_t)0x00000040U) /* !< Counter Compare Match Mode When + this bit is set to 1 a counter + compare match with LINC0 register + triggers an LINC0 interrupt when + enabled. */ +#define UNICOMMUART_LINCTL_LINC0_MATCH_DISABLE ((uint32_t)0x00000000U) /* !< Counter compare match mode disabled + (capture mode enabled) */ +#define UNICOMMUART_LINCTL_LINC0_MATCH_ENABLE ((uint32_t)0x00000040U) /* !< Counter compare match enabled + (capture mode disabled) */ + +/* UNICOMMUART_LINC0 Bits */ +/* UNICOMMUART_LINC0[DATA] Bits */ +#define UNICOMMUART_LINC0_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMUART_LINC0_DATA_MASK ((uint32_t)0x0000FFFFU) /* !< 16 Bit Capture / Compare Register + Captures current LINCTR value on RXD + falling edge and can generate a LINC0 + interrupt when capture is enabled + (LINC0CAP = 1). If compare mode is + enabled (LINC0_MATCH = 1), a counter + match can generate a LINC0 interrupt. */ +#define UNICOMMUART_LINC0_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_LINC0_DATA_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_LINC1 Bits */ +/* UNICOMMUART_LINC1[DATA] Bits */ +#define UNICOMMUART_LINC1_DATA_OFS (0) /* !< DATA Offset */ +#define UNICOMMUART_LINC1_DATA_MASK ((uint32_t)0x0000FFFFU) /* !< 16 Bit Capture / Compare Register + Captures current LINCTR value on RXD + rising edge and can generate a LINC1 + interrupt when capture is enabled + (LINC1CAP = 1) */ +#define UNICOMMUART_LINC1_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_LINC1_DATA_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< Highest possible value */ + +/* UNICOMMUART_IRCTL Bits */ +/* UNICOMMUART_IRCTL[IRTXPL] Bits */ +#define UNICOMMUART_IRCTL_IRTXPL_OFS (2) /* !< IRTXPL Offset */ +#define UNICOMMUART_IRCTL_IRTXPL_MASK ((uint32_t)0x000000FCU) /* !< Transmit pulse length. Pulse length + t(PULSE) = (IRTXPLx + 1) / [2 * + f(IRTXCLK)] (IRTXCLK = functional + clock of the UART) */ +#define UNICOMMUART_IRCTL_IRTXPL_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_IRCTL_IRTXPL_MAXIMUM ((uint32_t)0x000000FCU) /* !< Highest possible value */ +/* UNICOMMUART_IRCTL[IRRXPL] Bits */ +#define UNICOMMUART_IRCTL_IRRXPL_OFS (9) /* !< IRRXPL Offset */ +#define UNICOMMUART_IRCTL_IRRXPL_MASK ((uint32_t)0x00000200U) /* !< IrDA receive input UCAxRXD polarity */ +#define UNICOMMUART_IRCTL_IRRXPL_HIGH ((uint32_t)0x00000000U) /* !< IrDA transceiver delivers a high + pulse when a light pulse is seen */ +#define UNICOMMUART_IRCTL_IRRXPL_LOW ((uint32_t)0x00000200U) /* !< IrDA transceiver delivers a low + pulse when a light pulse is seen */ +/* UNICOMMUART_IRCTL[IREN] Bits */ +#define UNICOMMUART_IRCTL_IREN_OFS (0) /* !< IREN Offset */ +#define UNICOMMUART_IRCTL_IREN_MASK ((uint32_t)0x00000001U) /* !< IrDA encoder/decoder enable */ +#define UNICOMMUART_IRCTL_IREN_DISABLE ((uint32_t)0x00000000U) /* !< IrDA encoder/decoder disabled */ +#define UNICOMMUART_IRCTL_IREN_ENABLE ((uint32_t)0x00000001U) /* !< IrDA encoder/decoder enabled */ +/* UNICOMMUART_IRCTL[IRTXCLK] Bits */ +#define UNICOMMUART_IRCTL_IRTXCLK_OFS (1) /* !< IRTXCLK Offset */ +#define UNICOMMUART_IRCTL_IRTXCLK_MASK ((uint32_t)0x00000002U) /* !< IrDA transmit pulse clock select */ +#define UNICOMMUART_IRCTL_IRTXCLK_BITCLK ((uint32_t)0x00000000U) /* !< IrDA encode data is based on the + functional clock. */ +#define UNICOMMUART_IRCTL_IRTXCLK_BRCLK ((uint32_t)0x00000002U) /* !< IrDA encode data is based on the + Baud Rate clock< when select 8x + oversampling, the IRTXPL cycle should + less 8; when select 16x + oversampling, the IRTXPL cycle should + less 16. */ + +/* UNICOMMUART_AMASK Bits */ +/* UNICOMMUART_AMASK[VALUE] Bits */ +#define UNICOMMUART_AMASK_VALUE_OFS (0) /* !< VALUE Offset */ +#define UNICOMMUART_AMASK_VALUE_MASK ((uint32_t)0x000000FFU) /* !< Self Address Mask for 9-Bit Mode + This field contains the address mask + that creates a set of addresses that + should be matched. A 0 bit in the + MSK bitfield configures, that the + corresponding bit in the ADDR + bitfield of the UARTxADDR register is + don't care. A 1 bit in the MSK + bitfield configures, that the + corresponding bit in the ADDR + bitfield of the UARTxADDR register + must match. */ +#define UNICOMMUART_AMASK_VALUE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_AMASK_VALUE_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ + +/* UNICOMMUART_ADDR Bits */ +/* UNICOMMUART_ADDR[VALUE] Bits */ +#define UNICOMMUART_ADDR_VALUE_OFS (0) /* !< VALUE Offset */ +#define UNICOMMUART_ADDR_VALUE_MASK ((uint32_t)0x000000FFU) /* !< Self Address for 9-Bit Mode This + field contains the address that + should be matched when UARTxAMASK is + FFh. */ +#define UNICOMMUART_ADDR_VALUE_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define UNICOMMUART_ADDR_VALUE_MAXIMUM ((uint32_t)0x000000FFU) /* !< Highest possible value */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_unicommuart__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_usb.h b/mspm0/source/ti/devices/msp/peripherals/hw_usb.h new file mode 100644 index 0000000..370ce5a --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/hw_usb.h @@ -0,0 +1,3512 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_hw_usb__include +#define ti_devices_msp_peripherals_hw_usb__include + +/* Filename: hw_usb.h */ +/* Revised: 2024-10-17 19:02:43 */ +/* Revision: 57ee25d5f5e8d3be5c1a7d5449fc2e7ef36548c9 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* USB Registers +******************************************************************************/ +#define USB_CSR_OFS ((uint32_t)0x00002110U) +#define USB_TADDR_OFS ((uint32_t)0x00002080U) +#define USB_REGISTERS_OFS ((uint32_t)0x00002000U) +#define USB_CPU_INT_OFS ((uint32_t)0x00001020U) +#define USB_GPRCM_OFS ((uint32_t)0x00000800U) + + +/** @addtogroup USB_CSR + @{ +*/ + +typedef struct { + __IO uint16_t TXMAXP; /* !< (@ 0x00002110) USB Maximum Transmit Data Endpoint [n] */ + __IO uint8_t TXCSRL; /* !< (@ 0x00002112) USB Transmit Control and Status Endpoint [n] Low */ + __IO uint8_t TXCSRH; /* !< (@ 0x00002113) USB Transmit Control and Status Endpoint [n] High */ + __IO uint16_t RXMAXP; /* !< (@ 0x00002114) USB Maximum Receive Data Endpoint [n] */ + __IO uint8_t RXCSRL; /* !< (@ 0x00002116) USB Receive Control and Status Endpoint [n] Low */ + __IO uint8_t RXCSRH; /* !< (@ 0x00002117) USB Receive Control and Status Endpoint [n] High */ + __IO uint16_t RXCOUNT; /* !< (@ 0x00002118) USB Receive Byte Count Endpoint [n] */ + __IO uint8_t TXTYPE; /* !< (@ 0x0000211A) USB Host Transmit Configure Type Endpoint [n] */ + __IO uint8_t TXINTERVAL; /* !< (@ 0x0000211B) USB Host Transmit Interval Endpoint [n] */ + __IO uint8_t RXTYPE; /* !< (@ 0x0000211C) USB Host Configure Receive Type Endpoint [n] */ + __IO uint8_t RXINTERVAL; /* !< (@ 0x0000211D) USB Host Receive Polling Interval Endpoint [n] */ + uint8_t RESERVED0; + __I uint8_t FIFOSZ; /* !< (@ 0x0000211F) USB TX and RX FIFO Size Endpoint [n] */ +} USB_CSR_Regs; + +/*@}*/ /* end of group USB_CSR */ + +/** @addtogroup USB_TADDR + @{ +*/ + +typedef struct { + __IO uint8_t TXFUNCADDR; /* !< (@ 0x00002080) USB Transmit Functional Address Endpoint [n] */ + uint8_t RESERVED0; + __IO uint8_t TXHUBADDR; /* !< (@ 0x00002082) USB Transmit Hub Address Endpoint [n] */ + __IO uint8_t TXHUBPORT; /* !< (@ 0x00002083) USB Transmit Hub Port Endpoint [n] */ + __IO uint8_t RXFUNCADDR; /* !< (@ 0x00002084) USB Receive Functional Address Endpoint [n] */ + uint8_t RESERVED1; + __IO uint8_t RXHUBADDR; /* !< (@ 0x00002086) USB Receive Hub Address Endpoint [n] */ + __IO uint8_t RXHUBPORT; /* !< (@ 0x00002087) USB Receive Hub Port Endpoint [n] */ +} USB_TADDR_Regs; + +/*@}*/ /* end of group USB_TADDR */ + +/** @addtogroup USB_REGISTERS + @{ +*/ + +typedef struct { + __IO uint8_t FADDR; /* !< (@ 0x00002000) USB Device Functional Address */ + __IO uint8_t POWER; /* !< (@ 0x00002001) USB Power Control */ + __I uint16_t TXIS; /* !< (@ 0x00002002) USB Transmit Interrupt Status */ + __I uint16_t RXIS; /* !< (@ 0x00002004) USB Receive Interrupt Status */ + __IO uint16_t TXIE; /* !< (@ 0x00002006) USB Transmit Interrupt Enable */ + __IO uint16_t RXIE; /* !< (@ 0x00002008) USB Receive Interrupt Enable */ + __IO uint8_t USBIS; /* !< (@ 0x0000200A) USB General Interrupt Status */ + __IO uint8_t USBIE; /* !< (@ 0x0000200B) USB General Interrupt Enable */ + __IO uint16_t FRAME; /* !< (@ 0x0000200C) USB Last Received Frame Number */ + __IO uint8_t EPINDEX; /* !< (@ 0x0000200E) USB Endpoint Index */ + __IO uint8_t TESTMODE; /* !< (@ 0x0000200F) USB Test Mode */ + __IO uint16_t IDXTXMAXP; /* !< (@ 0x00002010) Indexed TXMAP */ + __IO uint8_t IDXTXCSRL; /* !< (@ 0x00002012) Indexed TXCSRL */ + __IO uint8_t IDXTXCSRH; /* !< (@ 0x00002013) Indexed TXCSRH */ + __IO uint16_t IDXRXMAXP; /* !< (@ 0x00002014) Indexed RXMAXP */ + __IO uint8_t IDXRXCSRL; /* !< (@ 0x00002016) Indexed RXCSRL */ + __IO uint8_t IDXRXCSRH; /* !< (@ 0x00002017) Indexed RXCSRH */ + __IO uint16_t IDXRXCOUNT; /* !< (@ 0x00002018) Indexed RXCOUNT */ + __IO uint8_t IDXTXTYPE; /* !< (@ 0x0000201A) Indexed TXTYPE */ + __IO uint8_t IDXTXINTERVAL; /* !< (@ 0x0000201B) Indexed TXINTERVAL */ + __IO uint8_t IDXRXTYPE; /* !< (@ 0x0000201C) Indexed RXTYPE */ + __IO uint8_t IDXRXINTERVAL; /* !< (@ 0x0000201D) Indexed RXINTERVAL */ + uint8_t RESERVED0; + __IO uint8_t IDXFIFOSZ; /* !< (@ 0x0000201F) Indexed FIFOSZ */ + union { + __IO uint32_t FIFO[16]; /* !< USB FIFO Endpoint [n] */ + __IO uint8_t FIFO_BYTE[16]; /* !< Byte access to FIFO for Endpoint [y]. */ + __IO uint16_t FIFO_HALF[16]; /* !< Half word access to FIFO for Endpoint [y]. */ + __IO uint32_t FIFO_WORD[16]; /* !< Word access to FIFO for Endpoint [y]. */ + }; + __IO uint8_t DEVCTL; /* !< (@ 0x00002060) USB Device Control */ + __IO uint8_t MISC; /* !< (@ 0x00002061) USB Miscellaneous Register */ + __IO uint8_t IDXTXFIFOSZ; /* !< (@ 0x00002062) Indexed USB Transmit Dynamic FIFO Sizing */ + __IO uint8_t IDXRXFIFOSZ; /* !< (@ 0x00002063) Indexed USB Receive Dynamic FIFO Sizing */ + __IO uint16_t IDXTXFIFOADD; /* !< (@ 0x00002064) Indexed USB Transmit FIFO Start Address */ + __IO uint16_t IDXRXFIFOADD; /* !< (@ 0x00002066) Indexed USB Receive FIFO Start Address */ + uint32_t RESERVED1[4]; + __I uint8_t EPINFO; /* !< (@ 0x00002078) Endpoint Information */ + __I uint8_t RAMINFO; /* !< (@ 0x00002079) USB FIFO Buffer RAM Information */ + __IO uint8_t CONTIM; /* !< (@ 0x0000207A) USB Connect Timing */ + uint8_t RESERVED2[2]; + __IO uint8_t FSEOF; /* !< (@ 0x0000207D) USB Full-Speed Last Transaction to End of Frame + Timing */ + __IO uint8_t LSEOF; /* !< (@ 0x0000207E) USB Low-Speed Last Transaction to End of Frame + Timing */ + uint8_t RESERVED3; + USB_TADDR_Regs TADDR[16]; /* !< (@ 0x00002080) */ + uint16_t RESERVED4; + __IO uint8_t CSR0L; /* !< (@ 0x00002102) USB Control and Status Endpoint 0 Low */ + __IO uint8_t CSR0H; /* !< (@ 0x00002103) USB Control and Status Endpoint 0 High */ + uint32_t RESERVED5; + __IO uint8_t COUNT0; /* !< (@ 0x00002108) USB Receive Byte Count Endpoint 0 */ + uint8_t RESERVED6; + __IO uint8_t TYPE0; /* !< (@ 0x0000210A) USB Type Endpoint 0 */ + __IO uint8_t NAKLMT0; /* !< (@ 0x0000210B) USB NAK Limit Endpoint 0 */ + uint8_t RESERVED7[3]; + __I uint8_t CONFIG; /* !< (@ 0x0000210F) USB Config Data */ + USB_CSR_Regs CSR[15]; /* !< (@ 0x00002110) */ + uint32_t RESERVED8[65]; + __IO uint32_t RQPKTCOUNT[15]; /* !< (@ 0x00002304) USB Request Packet Count in Block Transfer + Endpoint [n] */ + __IO uint16_t RXDPKTBUFDIS; /* !< (@ 0x00002340) USB Receive Double Packet Buffer Disable */ + __IO uint16_t TXDPKTBUFDIS; /* !< (@ 0x00002342) USB Transmit Double Packet Buffer Disable */ +} USB_REGISTERS_Regs; + +/*@}*/ /* end of group USB_REGISTERS */ + +/** @addtogroup USB_CPU_INT + @{ +*/ + +typedef struct { + __I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */ + uint32_t RESERVED0; + __IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */ + uint32_t RESERVED1; + __I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */ + uint32_t RESERVED2; + __I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */ + uint32_t RESERVED3; + __O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */ + uint32_t RESERVED4; + __O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */ +} USB_CPU_INT_Regs; + +/*@}*/ /* end of group USB_CPU_INT */ + +/** @addtogroup USB_GPRCM + @{ +*/ + +typedef struct { + __IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */ + __O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */ + __IO uint32_t CLKCTL; /* !< (@ 0x00000808) Clock control */ + uint32_t RESERVED0[2]; + __I uint32_t STAT; /* !< (@ 0x00000814) Status Register */ +} USB_GPRCM_Regs; + +/*@}*/ /* end of group USB_GPRCM */ + +/** @addtogroup USB + @{ +*/ + +typedef struct { + uint32_t RESERVED0[512]; + USB_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */ + uint32_t RESERVED1[514]; + USB_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */ + uint32_t RESERVED2[37]; + __I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */ + uint32_t RESERVED3[6]; + __I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */ + __IO uint32_t USBMODE; /* !< (@ 0x00001100) USB mode control */ + __IO uint32_t USBMONITOR; /* !< (@ 0x00001104) USB Clock Control Register */ + __IO uint32_t USBDMASEL; /* !< (@ 0x00001108) USB DMA trigger select */ + uint32_t RESERVED4[957]; + USB_REGISTERS_Regs REGISTERS; /* !< (@ 0x00002000) */ +} USB_Regs; + +/*@}*/ /* end of group USB */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* USB Register Control Bits +******************************************************************************/ + +/* USB_TXMAXP Bits */ +/* USB_TXMAXP[MAXLOAD] Bits */ +#define USB_TXMAXP_MAXLOAD_OFS (0) /* !< MAXLOAD Offset */ +#define USB_TXMAXP_MAXLOAD_MASK ((uint16_t)0x000007FFU) /* !< Maximum Payload specifies the + maximum payload in bytes per + transaction. */ + +/* USB_TXCSRL Bits */ +/* USB_TXCSRL[TXRDY] Bits */ +#define USB_TXCSRL_TXRDY_OFS (0) /* !< TXRDY Offset */ +#define USB_TXCSRL_TXRDY_MASK ((uint8_t)0x00000001U) /* !< Transmit Packet Ready. The CPU sets + this bit after loading a data packet + into the FIFO. This bit is cleared + automatically when a data packet has + been transmitted. The EPn bit in the + USBTXIS register is also set at this + point. TXRDY is also automatically + cleared prior to loading a second + packet into a double-buffered FIFO. + Note: Host and device mode */ +#define USB_TXCSRL_TXRDY_WAIT ((uint8_t)0x00000000U) /* !< No transmit packet is ready. */ +#define USB_TXCSRL_TXRDY_READY ((uint8_t)0x00000001U) /* !< Software sets this bit after + loading a data packet into the TX + FIFO. */ +/* USB_TXCSRL[FIFONE] Bits */ +#define USB_TXCSRL_FIFONE_OFS (1) /* !< FIFONE Offset */ +#define USB_TXCSRL_FIFONE_MASK ((uint8_t)0x00000002U) /* !< FIFO Not Empty. The USB controller + sets this bit when there is at least + 1 packet in the TX FIFO. Note: Host + and device mode. */ +#define USB_TXCSRL_FIFONE_EMPTY ((uint8_t)0x00000000U) /* !< The FIFO is empty */ +#define USB_TXCSRL_FIFONE_NOT_EMPTY ((uint8_t)0x00000002U) /* !< At least one packet is in the + transmit FIFO. */ +/* USB_TXCSRL[UNDRNERROR] Bits */ +#define USB_TXCSRL_UNDRNERROR_OFS (2) /* !< UNDRNERROR Offset */ +#define USB_TXCSRL_UNDRNERROR_MASK ((uint8_t)0x00000004U) /* !< Underrun / Error condition. Device + mode: The USB controller sets this + bit if an IN token is received when + TXRDY is not set. The CPU should + clear this bit. Host mode: The USB + controller sets this bit when 3 + attempts have been made to send a + packet and no handshake packet has + been received. When the bit is set, + an interrupt is generated, TXRDY is + cleared and the FIFO is completely + flushed. The CPU should clear this + bit. Valid only when the endpoint is + operating in Bulk or Interrupt mode. */ +#define USB_TXCSRL_UNDRNERROR_CLEAR ((uint8_t)0x00000000U) /* !< No underrun or error condition */ +#define USB_TXCSRL_UNDRNERROR_SET ((uint8_t)0x00000004U) /* !< Underrun or error condition exist. */ +/* USB_TXCSRL[FLUSH] Bits */ +#define USB_TXCSRL_FLUSH_OFS (3) /* !< FLUSH Offset */ +#define USB_TXCSRL_FLUSH_MASK ((uint8_t)0x00000008U) /* !< Flush FIFO. The CPU writes a 1 to + this bit to flush the latest packet + from the endpoint TX FIFO. The FIFO + pointer is reset, the TXRDY bit is + cleared and an interrupt is + generated. May be set simultaneously + with TXRDY to abort the packet that + is currently being loaded into the + FIFO. Note: FLUSH should only be + used when TXRDY is set. At other + times, it may cause data to be + corrupted. Also note that, if the + FIFO is double-buffered, FLUSH may + need to be set twice to completely + clear the FIFO. Note: Host and device + mode. */ +#define USB_TXCSRL_FLUSH_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_TXCSRL_FLUSH_EFFECT ((uint8_t)0x00000008U) /* !< Flushes the latest packet from the + endpoint transmit FIFO. */ +/* USB_TXCSRL[STALLSETUP] Bits */ +#define USB_TXCSRL_STALLSETUP_OFS (4) /* !< STALLSETUP Offset */ +#define USB_TXCSRL_STALLSETUP_MASK ((uint8_t)0x00000010U) /* !< Send stall / Setup packet request. + Device mode: The CPU writes a 1 to + this bit to issue a STALL handshake + to an IN token. The CPU clears this + bit to terminate the stall condition. + Note: This bit has no effect where + the endpoint is being used for + Isochronous transfers. Host mode: The + CPU sets this bit, at the same time + as the TXRDY bit is set, to send a + SETUP token instead of an OUT token + for the transaction. Note: Setting + this bit also clears the USBTXCSRH.DT + register. */ +#define USB_TXCSRL_STALLSETUP_CLEAR ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_TXCSRL_STALLSETUP_SET ((uint8_t)0x00000010U) /* !< Send stall or setup packet request. */ +/* USB_TXCSRL[STALLED] Bits */ +#define USB_TXCSRL_STALLED_OFS (5) /* !< STALLED Offset */ +#define USB_TXCSRL_STALLED_MASK ((uint8_t)0x00000020U) /* !< Sent stall / RX stalled. Device + mode: This bit is set when a STALL + handshake is transmitted. The FIFO is + flushed and the TXRDY bit is cleared. + The CPU should clear this bit. Host + mode: This bit is set when a STALL + handshake is received. When this bit + is set, any DMA request that is in + progress is stopped, the FIFO is + completely flushed and the TXRDY bit + is cleared. The CPU should clear this + bit. */ +#define USB_TXCSRL_STALLED_CLEAR ((uint8_t)0x00000000U) /* !< Clear stall indication. */ +#define USB_TXCSRL_STALLED_SET ((uint8_t)0x00000020U) /* !< Indicates that a STALL handshake + has been sent or received. */ +/* USB_TXCSRL[CLRDT] Bits */ +#define USB_TXCSRL_CLRDT_OFS (6) /* !< CLRDT Offset */ +#define USB_TXCSRL_CLRDT_MASK ((uint8_t)0x00000040U) /* !< Clear DataToggle. The CPU writes a + 1 to this bit to reset the endpoint + data toggle to 0. Note: Host and + device mode. */ +#define USB_TXCSRL_CLRDT_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_TXCSRL_CLRDT_EFFECT ((uint8_t)0x00000040U) /* !< Writing a 1 to this bit clears the + DT bit in the USBTXCSRH[n] register. */ +/* USB_TXCSRL[INCOMPNAKTO] Bits */ +#define USB_TXCSRL_INCOMPNAKTO_OFS (7) /* !< INCOMPNAKTO Offset */ +#define USB_TXCSRL_INCOMPNAKTO_MASK ((uint8_t)0x00000080U) /* !< Incomplete TX / NAK Timeout. Device + mode: When the endpoint is being used + for high-bandwidth Isochronous, this + bit is set to indicate where a large + packet has been split into 2 or 3 + packets for transmission but + insufficient IN tokens have been + received to send all the parts. Note: + In anything other than isochronous + transfers, this bit will always + return 0. Host mode - bulk endpoints + only: This bit will be set when the + TX endpoint is halted following the + receipt of NAK responses for longer + than the time set as theTXPOLLNAKLMT + by the TXINTERVAL register. The CPU + should clear this bit to allow the + endpoint to continue. Host mode - + high-bandwidth Interrupt endpoints + only: This bit will be set if no + response is received from the device + to which the packet is being sent. */ +#define USB_TXCSRL_INCOMPNAKTO_CLEAR ((uint8_t)0x00000000U) /* !< No condition present / clear + condition. */ +#define USB_TXCSRL_INCOMPNAKTO_SET ((uint8_t)0x00000080U) /* !< Condition present. */ + +/* USB_TXCSRH Bits */ +/* USB_TXCSRH[DT] Bits */ +#define USB_TXCSRH_DT_OFS (0) /* !< DT Offset */ +#define USB_TXCSRH_DT_MASK ((uint8_t)0x00000001U) /* !< Data Toggle. When read, this bit + indicates the current state of the + transmit endpoint data toggle. If + DTWE is High, this bit can be written + with the required setting of the data + toggle. If DTWE is Low, any value + written to this bit is ignored. Care + should be taken when writing to this + bit as it should only be changed to + RESET the transmit endpoint. Note: + Host mode only */ +#define USB_TXCSRH_DT_LOW ((uint8_t)0x00000000U) /* !< Data toggle is low */ +#define USB_TXCSRH_DT_HIGH ((uint8_t)0x00000001U) /* !< Data toggle is high */ +/* USB_TXCSRH[DTWE] Bits */ +#define USB_TXCSRH_DTWE_OFS (1) /* !< DTWE Offset */ +#define USB_TXCSRH_DTWE_MASK ((uint8_t)0x00000002U) /* !< Data Toggle Write Enable. The CPU + writes a 1 to this bit to enable the + current state of the TX Endpoint data + toggle to be written. This bit is + automatically cleared once the new + value is written. Note: Host mode + only. */ +#define USB_TXCSRH_DTWE_DISABLE ((uint8_t)0x00000000U) /* !< The DT bit cannot be written. */ +#define USB_TXCSRH_DTWE_ENABLE ((uint8_t)0x00000002U) /* !< Enables the current state of the + transmit endpoint data to be written + (see DT bit). */ +/* USB_TXCSRH[DMAMOD] Bits */ +#define USB_TXCSRH_DMAMOD_OFS (2) /* !< DMAMOD Offset */ +#define USB_TXCSRH_DMAMOD_MASK ((uint8_t)0x00000004U) /* !< DMA Request Mode. The CPU sets this + bit to select DMA Request Mode 1 and + clears it to select DMA Request Mode + 0. Note: This bit must not be cleared + either before or in the same cycle as + the DMAEN bit is cleared. Note: + Device and host mode. */ +#define USB_TXCSRH_DMAMOD_MODE0 ((uint8_t)0x00000000U) /* !< An interrupt is generated after + every DMA packet transfer. */ +#define USB_TXCSRH_DMAMOD_MODE1 ((uint8_t)0x00000004U) /* !< An interrupt is generated only + after the entire DMA transfer is + complete. */ +/* USB_TXCSRH[FDT] Bits */ +#define USB_TXCSRH_FDT_OFS (3) /* !< FDT Offset */ +#define USB_TXCSRH_FDT_MASK ((uint8_t)0x00000008U) /* !< Force Data Toggle. The CPU sets + this bit to force the endpoint DT bit + to switch and the data packet to be + cleared from the FIFO, regardless of + whether an ACK was received. This can + be used by Interrupt TX endpoints + that are used to communicate rate + feedback for Isochronous endpoints. + Note: This bit should only be set + when the TXRDY bit is set. At other + times, it may cause data to be + corrupted. Note: Device and host + mode. */ +#define USB_TXCSRH_FDT_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_TXCSRH_FDT_EFFECT ((uint8_t)0x00000008U) /* !< Forces data toggle */ +/* USB_TXCSRH[DMAEN] Bits */ +#define USB_TXCSRH_DMAEN_OFS (4) /* !< DMAEN Offset */ +#define USB_TXCSRH_DMAEN_MASK ((uint8_t)0x00000010U) /* !< DMA Request Enable The CPU sets + this bit to enable the DMA request + for the TX endpoint. Note: Four TX + and four RX endpoints can be + connected to the DMA module. If this + bit is set for a particular endpoint, + the TRIGATX, TRIGBTX, TRIGCTX, or + TRIGDTX field in the USB DMA Select + (USBDMASEL) register must be + programmed correspondingly. Note: + Device and host mode. */ +#define USB_TXCSRH_DMAEN_DISABLE ((uint8_t)0x00000000U) /* !< Disables the DMA request for the + transmit endpoint. */ +#define USB_TXCSRH_DMAEN_ENABLE ((uint8_t)0x00000010U) /* !< Enables the DMA request for the + transmit endpoint. */ +/* USB_TXCSRH[MODE] Bits */ +#define USB_TXCSRH_MODE_OFS (5) /* !< MODE Offset */ +#define USB_TXCSRH_MODE_MASK ((uint8_t)0x00000020U) /* !< Mode The CPU sets this bit to + enable the endpoint direction as TX, + and clears the bit to enable it as + Rx. Note: This bit only has an + effect when the same endpoint FIFO is + used for both transmit and receive + transactions. Note: Host and device + mode. */ +#define USB_TXCSRH_MODE_RX ((uint8_t)0x00000000U) /* !< Enables the endpoint direction as + RX. */ +#define USB_TXCSRH_MODE_TX ((uint8_t)0x00000020U) /* !< Enables the endpoint direction as + TX. */ +/* USB_TXCSRH[ISO] Bits */ +#define USB_TXCSRH_ISO_OFS (6) /* !< ISO Offset */ +#define USB_TXCSRH_ISO_MASK ((uint8_t)0x00000040U) /* !< Isochronous Transfers. The CPU sets + this bit to enable the TX endpoint + for Isochronous transfers, and clears + it to enable the TX endpoint for Bulk + or Interrupt transfers. Note: This + bit only has any effect in device + mode. In host mode, it always returns + zero. */ +#define USB_TXCSRH_ISO_BULK_INT_TRANSFER ((uint8_t)0x00000000U) /* !< Enables the transmit endpoint for + bulk or interrupt transfers. */ +#define USB_TXCSRH_ISO_ISO_TRANSFER ((uint8_t)0x00000040U) /* !< Enables the transmit endpoint for + isochronous transfers. */ +/* USB_TXCSRH[AUTOSET] Bits */ +#define USB_TXCSRH_AUTOSET_OFS (7) /* !< AUTOSET Offset */ +#define USB_TXCSRH_AUTOSET_MASK ((uint8_t)0x00000080U) /* !< Auto Set. If the CPU sets this bit, + the TXRDY bit will be be + automatically set when data of the + maximum packet size (value in + USBTXMAXP[n]) is loaded into the + transmit FIFO. If a packet of less + than the maximum packet size is + loaded, then the TXRDY bit must be + set manually. Note: Should not be set + for either high-bandwidth Isochronous + endpoints or high-bandwidth Interrupt + endpoints. Note: Device and host + mode. */ +#define USB_TXCSRH_AUTOSET_MANUAL ((uint8_t)0x00000000U) /* !< The TXRDY bit must be set manually. */ +#define USB_TXCSRH_AUTOSET_AUTO ((uint8_t)0x00000080U) /* !< The TXRDY bit is automatically set + when maximum packet size is loaded + into the TX FIFO. */ + +/* USB_RXMAXP Bits */ +/* USB_RXMAXP[MAXLOAD] Bits */ +#define USB_RXMAXP_MAXLOAD_OFS (0) /* !< MAXLOAD Offset */ +#define USB_RXMAXP_MAXLOAD_MASK ((uint16_t)0x000007FFU) /* !< Maximum Payload specifies the + maximum payload in bytes per + transaction. */ + +/* USB_RXCSRL Bits */ +/* USB_RXCSRL[RXRDY] Bits */ +#define USB_RXCSRL_RXRDY_OFS (0) /* !< RXRDY Offset */ +#define USB_RXCSRL_RXRDY_MASK ((uint8_t)0x00000001U) /* !< Receive Packet Ready. This bit is + set when a data packet has been + received. The CPU should clear this + bit when the packet has been unloaded + from the Rx FIFO. An interrupt is + generated when the bit is set. If the + AUTOCLR bit in the USBRXCSRH[n] + register is set, then the this bit is + automatically cleared when a packet + of USBRXMAXP[n] bytes has been + unloaded from the receive FIFO. If + the AUTOCLR bit is clear, or if + packets of less than the maximum + packet size are unloaded, then + software must clear this bit manually + when the packet has been unloaded + from the receive FIFO. Note: Device + and host mode. */ +#define USB_RXCSRL_RXRDY_WAIT ((uint8_t)0x00000000U) /* !< No data packet has been received. */ +#define USB_RXCSRL_RXRDY_READY ((uint8_t)0x00000001U) /* !< Indicates that a data packet has + been received. The EP[j] bit in the + USBTXIS register is also set in this + situation */ +/* USB_RXCSRL[FULL] Bits */ +#define USB_RXCSRL_FULL_OFS (1) /* !< FULL Offset */ +#define USB_RXCSRL_FULL_MASK ((uint8_t)0x00000002U) /* !< FIFO Full. This bit is set when no + more packets can be loaded into the + RX FIFO. Note: Device and host mode. */ +#define USB_RXCSRL_FULL_NO ((uint8_t)0x00000000U) /* !< The receive FIFO is not full. */ +#define USB_RXCSRL_FULL_YES ((uint8_t)0x00000002U) /* !< The receive FIFO is full. No more + packets can be loaded into the + receive FIFO. */ +/* USB_RXCSRL[OVERERROR] Bits */ +#define USB_RXCSRL_OVERERROR_OFS (2) /* !< OVERERROR Offset */ +#define USB_RXCSRL_OVERERROR_MASK ((uint8_t)0x00000004U) /* !< Over run / Error. Device mode: Over + run - This bit is set if an OUT + packet cannot be loaded into the + receive FIFO. The CPU should clear + this bit. - Note: This bit is only + valid when the endpoint is operating + in ISO mode. In Bulk mode, it always + returns zero. Host mode: The USB sets + this bit when 3 attempts have been + made to receive a packet and no data + packet has been received. The CPU + should clear this bit. An interrupt + is generated when the bit is set. - + Note: This bit is only valid when the + RX endpoint is operating in Bulk or + Interrupt mode. In ISO mode, it + always returns zero. */ +#define USB_RXCSRL_OVERERROR_CLEAR ((uint8_t)0x00000000U) /* !< No over run or error condition. */ +#define USB_RXCSRL_OVERERROR_SET ((uint8_t)0x00000004U) /* !< Under run or error condition exist. */ +/* USB_RXCSRL[DATAERRNAKTO] Bits */ +#define USB_RXCSRL_DATAERRNAKTO_OFS (3) /* !< DATAERRNAKTO Offset */ +#define USB_RXCSRL_DATAERRNAKTO_MASK ((uint8_t)0x00000008U) /* !< Data Error / NAK Timeout Device + mode: Data Error - This bit is set + when RXRDY is set, if the data packet + has a CRC or bit-stuff error. It is + cleared when RXRDY is cleared. - + Note: This bit is only valid when the + endpoint is operating in ISO mode. In + Bulk mode, it always returns zero. + Host mode: NAK Timeout - When + operating in ISO mode, this bit is + set when RXRDY is set, if the data + packet has a CRC or bit-stuff error + and cleared when RXRDY is cleared. In + Bulk mode, this bit will be set when + the Rx endpoint is halted following + the receipt of NAK responses for + longer than the time set as the NAK + Limit by the USBRXINTERVAL register. + The CPU should clear this bit to + allow the endpoint to continue. */ +#define USB_RXCSRL_DATAERRNAKTO_CLEAR ((uint8_t)0x00000000U) /* !< Normal operation */ +#define USB_RXCSRL_DATAERRNAKTO_SET ((uint8_t)0x00000008U) /* !< Data error or NAK Timeout condition + exist. */ +/* USB_RXCSRL[FLUSH] Bits */ +#define USB_RXCSRL_FLUSH_OFS (4) /* !< FLUSH Offset */ +#define USB_RXCSRL_FLUSH_MASK ((uint8_t)0x00000010U) /* !< Flush FIFO. The CPU writes a 1 to + this bit to flush the next packet to + be read from the endpoint RX FIFO. + The FIFO pointer is reset and the + RXRDY bit is cleared. Note: Thsi bit + should only be set when RXRDY is set. + At other times, it may cause data to + be corrupted. Note: If the FIFO is + double-buffered, FLUSH may need to be + set twice to completely clear the + FIFO. Note: Device and host mode. */ +#define USB_RXCSRL_FLUSH_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_RXCSRL_FLUSH_EFFECT ((uint8_t)0x00000010U) /* !< Flushes the next packet to be read + from the endpoint receive FIFO. The + FIFO pointer is reset and the RXRDY + bit is cleared */ +/* USB_RXCSRL[STALLREQPKT] Bits */ +#define USB_RXCSRL_STALLREQPKT_OFS (5) /* !< STALLREQPKT Offset */ +#define USB_RXCSRL_STALLREQPKT_MASK ((uint8_t)0x00000020U) /* !< Send Stall / Request Packet. Device + mode: The CPU writes a 1 to this bit + to issue a STALL handshake. The CPU + clears this bit to terminate the + stall condition. - Note: This bit has + no effect where the endpoint is being + used for Isochronous transfers. Host + mode: The CPU writes a 1 to this bit + to request an IN transaction. It is + cleared when RXRDY is set. */ +#define USB_RXCSRL_STALLREQPKT_CLEAR ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_RXCSRL_STALLREQPKT_SET ((uint8_t)0x00000020U) /* !< Send stall or packet request. */ +/* USB_RXCSRL[STALLED] Bits */ +#define USB_RXCSRL_STALLED_OFS (6) /* !< STALLED Offset */ +#define USB_RXCSRL_STALLED_MASK ((uint8_t)0x00000040U) /* !< Sent Stall / RX Stall Device mode: + This bit is set when a STALL + handshake is transmitted. The CPU + should clear this bit. Host mode: + When a STALL handshake is received, + this bit is set and an interrupt is + generated. The CPU should clear this + bit. */ +#define USB_RXCSRL_STALLED_STALLED_WAIT ((uint8_t)0x00000000U) /* !< No handshake has been received. */ +#define USB_RXCSRL_STALLED_STALLED_RECEIVE ((uint8_t)0x00000040U) /* !< A STALL handshake has been + received. The EPn bit in the USBRXIS + register is also set. */ +/* USB_RXCSRL[CLRDT] Bits */ +#define USB_RXCSRL_CLRDT_OFS (7) /* !< CLRDT Offset */ +#define USB_RXCSRL_CLRDT_MASK ((uint8_t)0x00000080U) /* !< Clear Data Toggle. The CPU writes a + 1 to this bit to reset the endpoint + data toggle to 0. Note: Device and + host mode. */ +#define USB_RXCSRL_CLRDT_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_RXCSRL_CLRDT_EFFECT ((uint8_t)0x00000080U) /* !< Writing a 1 to this bit clears the + DT bit in the USBRXCSRH[n] register. */ + +/* USB_RXCSRH Bits */ +/* USB_RXCSRH[INCOMPRX] Bits */ +#define USB_RXCSRH_INCOMPRX_OFS (0) /* !< INCOMPRX Offset */ +#define USB_RXCSRH_INCOMPRX_MASK ((uint8_t)0x00000001U) /* !< This bit will be set in a + high-bandwidth Isochronous or + Interrupt transfer if the packet + received is incomplete, because parts + of the data were not received. It is + cleared when RXRDY is cleared. Note: + In anything other than Isochronous + transfer, this bit will always return + 0. Note: Device and host mode. */ +/* USB_RXCSRH[DT] Bits */ +#define USB_RXCSRH_DT_OFS (1) /* !< DT Offset */ +#define USB_RXCSRH_DT_MASK ((uint8_t)0x00000002U) /* !< Data Toggle. When read, this bit + indicates the current state of the + receive data toggle. If DTWE is High, + this bit may be written with the + required setting of the data toggle. + If DTWE is Low, any value written to + this bit is ignored. Care should be + taken when writing to this bit as it + should only be changed to RESET the + receive endpoint. Note: Host mode + only. */ +#define USB_RXCSRH_DT_LOW ((uint8_t)0x00000000U) /* !< Data toggle is low */ +#define USB_RXCSRH_DT_HIGH ((uint8_t)0x00000002U) /* !< Data toggle is high */ +/* USB_RXCSRH[DTWE] Bits */ +#define USB_RXCSRH_DTWE_OFS (2) /* !< DTWE Offset */ +#define USB_RXCSRH_DTWE_MASK ((uint8_t)0x00000004U) /* !< Data Toggle Write Enable. The CPU + writes a 1 to this bit to enable the + current state of the Endpoint 0 data + toggle to be written. This bit is + automatically cleared once the new + value is written. Note: Host mode + only. */ +#define USB_RXCSRH_DTWE_DISABLE ((uint8_t)0x00000000U) /* !< The DT bit cannot be written. */ +#define USB_RXCSRH_DTWE_ENABLE ((uint8_t)0x00000004U) /* !< Enables the current state of the + receive endpoint data to be written + (see DT bit). */ +/* USB_RXCSRH[DMAMOD] Bits */ +#define USB_RXCSRH_DMAMOD_OFS (3) /* !< DMAMOD Offset */ +#define USB_RXCSRH_DMAMOD_MASK ((uint8_t)0x00000008U) /* !< DMA request mode The CPU sets this + bit to select DMA Request Mode 1 and + clears it to select DMA Request Mode + 0. Note: This bit must not be cleared + either before or in the same cycle as + the above DMAEN bit is cleared. Note: + Device and host mode. */ +#define USB_RXCSRH_DMAMOD_MODE0 ((uint8_t)0x00000000U) /* !< An interrupt is generated after + every DMA packet transfer. */ +#define USB_RXCSRH_DMAMOD_MODE1 ((uint8_t)0x00000008U) /* !< An interrupt is generated only + after the entire DMA transfer is + complete. */ +/* USB_RXCSRH[PIDERR] Bits */ +#define USB_RXCSRH_PIDERR_OFS (4) /* !< PIDERR Offset */ +#define USB_RXCSRH_PIDERR_MASK ((uint8_t)0x00000010U) /* !< PID error ISO Transactions: The USB + controller sets this bit to indicate + a PID error in the received packet. + Bulk/Interrupt Transactions: The + setting of this bit is ignored. Note: + Device and host mode. */ +#define USB_RXCSRH_PIDERR_NO_ERROR ((uint8_t)0x00000000U) /* !< No error */ +#define USB_RXCSRH_PIDERR_ERROR ((uint8_t)0x00000010U) /* !< Indicates a PID error in the + received packet of an isochronous + transaction. */ +/* USB_RXCSRH[DMAEN] Bits */ +#define USB_RXCSRH_DMAEN_OFS (5) /* !< DMAEN Offset */ +#define USB_RXCSRH_DMAEN_MASK ((uint8_t)0x00000020U) /* !< DMA Request Enable The CPU sets + this bit to enable the DMA request + for the Rx endpoint. Note: Four TX + and four RX endpoints can be + connected to the DMA module. If this + bit is set for a particular endpoint, + the TRIGARX, TRIGBRX, TRIGCRX, or + TRIGDRX field in the USB DMA Select + (USBDMASEL) register must be + programmed correspondingly */ +#define USB_RXCSRH_DMAEN_DISABLE ((uint8_t)0x00000000U) /* !< Disables the DMA request for the + receive endpoint. */ +#define USB_RXCSRH_DMAEN_ENABLE ((uint8_t)0x00000020U) /* !< Enables the DMA request for the + receive endpoint. */ +/* USB_RXCSRH[ISOAUTORQ] Bits */ +#define USB_RXCSRH_ISOAUTORQ_OFS (6) /* !< ISOAUTORQ Offset */ +#define USB_RXCSRH_ISOAUTORQ_MASK ((uint8_t)0x00000040U) /* !< Isochronous transfer mode / Auto + request. Device mode: The CPU sets + this bit to enable the Rx endpoint + for Isochronous transfers, and clears + it to enable the Rx endpoint for + Bulk/Interrupt transfers. Host mode: + If the CPU sets this bit, the + STALLREQPKT bit will be automatically + set when the RXRDY bit is cleared. - + Note: This bit is automatically + cleared when a short packet is + received. */ +#define USB_RXCSRH_ISOAUTORQ_DISABLE ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_RXCSRH_ISOAUTORQ_ENABLE ((uint8_t)0x00000040U) /* !< Sets ISO transfer mode or enables + the REQPKT bit to be automatically + set when the RXRDY bit is cleared. */ +/* USB_RXCSRH[AUTOCLR] Bits */ +#define USB_RXCSRH_AUTOCLR_OFS (7) /* !< AUTOCLR Offset */ +#define USB_RXCSRH_AUTOCLR_MASK ((uint8_t)0x00000080U) /* !< Auto Clear. If the CPU sets this + bit then the RXRDY bit will be + automatically cleared when a packet + of USBRXMAXP bytes has been unloaded + from the RX FIFO. When packets of + less than the maximum packet size are + unloaded, RXRDY will have to be + cleared manually. When using a DMA to + unload the RX-FIFO, data is read from + the RX-FIFO in 4 byte chunks + regardless of the USBRXMAXP setting. + Note: Device and host mode. */ +#define USB_RXCSRH_AUTOCLR_DSIABLE ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_RXCSRH_AUTOCLR_ENABLE ((uint8_t)0x00000080U) /* !< Enables the RXRDY bit to be + automatically cleared when a packet + of USBRXMAXP[n] bytes has been + unloaded from the receive FIFO. */ + +/* USB_RXCOUNT Bits */ +/* USB_RXCOUNT[COUNT] Bits */ +#define USB_RXCOUNT_COUNT_OFS (0) /* !< COUNT Offset */ +#define USB_RXCOUNT_COUNT_MASK ((uint16_t)0x00001FFFU) /* !< Receive Packet Count indicates the + number of bytes in the receive + packet. */ + +/* USB_TXTYPE Bits */ +/* USB_TXTYPE[TEP] Bits */ +#define USB_TXTYPE_TEP_OFS (0) /* !< TEP Offset */ +#define USB_TXTYPE_TEP_MASK ((uint8_t)0x0000000FU) /* !< Target Endpoint Number. Software + must configure this value to the + endpoint number contained in the + transmit endpoint descriptor returned + to the USB controller during Device + enumeration. */ +/* USB_TXTYPE[PROTO] Bits */ +#define USB_TXTYPE_PROTO_OFS (4) /* !< PROTO Offset */ +#define USB_TXTYPE_PROTO_MASK ((uint8_t)0x00000030U) /* !< Protocol. Software must configure + this bit field to select the required + protocol for the transmit endpoint: */ +#define USB_TXTYPE_PROTO_CTRL ((uint8_t)0x00000000U) /* !< Control */ +#define USB_TXTYPE_PROTO_ISO ((uint8_t)0x00000010U) /* !< isochronous */ +#define USB_TXTYPE_PROTO_BULK ((uint8_t)0x00000020U) /* !< Bulk */ +#define USB_TXTYPE_PROTO_INT ((uint8_t)0x00000030U) /* !< Interrupt */ +/* USB_TXTYPE[SPEED] Bits */ +#define USB_TXTYPE_SPEED_OFS (6) /* !< SPEED Offset */ +#define USB_TXTYPE_SPEED_MASK ((uint8_t)0x000000C0U) /* !< Operating Speed. This bit field + specifies the operating speed of the + target Device: */ +#define USB_TXTYPE_SPEED_DEFAULT ((uint8_t)0x00000000U) /* !< Default. The target is assumed to + be using the same connection speed as + the USB controller. */ +#define USB_TXTYPE_SPEED_FULL ((uint8_t)0x00000080U) /* !< Full speed */ +#define USB_TXTYPE_SPEED_LOW ((uint8_t)0x000000C0U) /* !< Low speed */ + +/* USB_TXINTERVAL Bits */ +/* USB_TXINTERVAL[TXPOLLNAKLMT] Bits */ +#define USB_TXINTERVAL_TXPOLLNAKLMT_OFS (0) /* !< TXPOLLNAKLMT Offset */ +#define USB_TXINTERVAL_TXPOLLNAKLMT_MASK ((uint8_t)0x000000FFU) /* !< TX Polling / NAK Limit The polling + interval for interrupt/isochronous + transfers; the NAK limit for bulk + transfers. */ + +/* USB_RXTYPE Bits */ +/* USB_RXTYPE[TEP] Bits */ +#define USB_RXTYPE_TEP_OFS (0) /* !< TEP Offset */ +#define USB_RXTYPE_TEP_MASK ((uint8_t)0x0000000FU) /* !< Target Endpoint Number. Software + must configure this value to the + endpoint number contained in the + transmit endpoint descriptor returned + to the USB controller during Device + enumeration. */ +/* USB_RXTYPE[PROTO] Bits */ +#define USB_RXTYPE_PROTO_OFS (4) /* !< PROTO Offset */ +#define USB_RXTYPE_PROTO_MASK ((uint8_t)0x00000030U) /* !< Protocol. Software must configure + this bit field to select the required + protocol for the transmit endpoint: */ +#define USB_RXTYPE_PROTO_CTRL ((uint8_t)0x00000000U) /* !< Control */ +#define USB_RXTYPE_PROTO_ISO ((uint8_t)0x00000010U) /* !< isochronous */ +#define USB_RXTYPE_PROTO_BULK ((uint8_t)0x00000020U) /* !< Bulk */ +#define USB_RXTYPE_PROTO_INT ((uint8_t)0x00000030U) /* !< Interrupt */ +/* USB_RXTYPE[SPEED] Bits */ +#define USB_RXTYPE_SPEED_OFS (6) /* !< SPEED Offset */ +#define USB_RXTYPE_SPEED_MASK ((uint8_t)0x000000C0U) /* !< Operating Speed. #br#This bit + field specifies the operating speed + of the target Device: */ +#define USB_RXTYPE_SPEED_DEFAULT ((uint8_t)0x00000000U) /* !< Default. The target is assumed to + be using the same connection speed as + the USB controller. */ +#define USB_RXTYPE_SPEED_FULL ((uint8_t)0x00000080U) /* !< Full speed */ +#define USB_RXTYPE_SPEED_LOW ((uint8_t)0x000000C0U) /* !< Low speed */ + +/* USB_RXINTERVAL Bits */ +/* USB_RXINTERVAL[RXPOLLNAKLMT] Bits */ +#define USB_RXINTERVAL_RXPOLLNAKLMT_OFS (0) /* !< RXPOLLNAKLMT Offset */ +#define USB_RXINTERVAL_RXPOLLNAKLMT_MASK ((uint8_t)0x000000FFU) /* !< RX Polling / NAK Limit The polling + interval for interrupt/isochronous + transfers; the NAK limit for bulk + transfers. */ + +/* USB_FIFOSZ Bits */ +/* USB_FIFOSZ[TXSIZE] Bits */ +#define USB_FIFOSZ_TXSIZE_OFS (0) /* !< TXSIZE Offset */ +#define USB_FIFOSZ_TXSIZE_MASK ((uint8_t)0x0000000FU) /* !< Returns the configured size of the + TX FIFO */ +#define USB_FIFOSZ_TXSIZE_BYTES_8 ((uint8_t)0x00000000U) /* !< FIFO size 8-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_16 ((uint8_t)0x00000001U) /* !< FIFO size 16-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_32 ((uint8_t)0x00000002U) /* !< FIFO size 32-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_64 ((uint8_t)0x00000003U) /* !< FIFO size 64-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_128 ((uint8_t)0x00000004U) /* !< FIFO size 128-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_256 ((uint8_t)0x00000005U) /* !< FIFO size 256-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_512 ((uint8_t)0x00000006U) /* !< FIFO size 512-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_1024 ((uint8_t)0x00000007U) /* !< FIFO size 1024-byte */ +#define USB_FIFOSZ_TXSIZE_BYTES_2048 ((uint8_t)0x00000008U) /* !< FIFO size 2048-byte */ +/* USB_FIFOSZ[RXSIZE] Bits */ +#define USB_FIFOSZ_RXSIZE_OFS (4) /* !< RXSIZE Offset */ +#define USB_FIFOSZ_RXSIZE_MASK ((uint8_t)0x000000F0U) /* !< Returns the configured size of the + RX FIFO */ +#define USB_FIFOSZ_RXSIZE_BYTES_8 ((uint8_t)0x00000000U) /* !< FIFO size 8-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_16 ((uint8_t)0x00000010U) /* !< FIFO size 16-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_32 ((uint8_t)0x00000020U) /* !< FIFO size 32-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_64 ((uint8_t)0x00000030U) /* !< FIFO size 64-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_128 ((uint8_t)0x00000040U) /* !< FIFO size 128-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_256 ((uint8_t)0x00000050U) /* !< FIFO size 256-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_512 ((uint8_t)0x00000060U) /* !< FIFO size 512-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_1024 ((uint8_t)0x00000070U) /* !< FIFO size 1024-byte */ +#define USB_FIFOSZ_RXSIZE_BYTES_2048 ((uint8_t)0x00000080U) /* !< FIFO size 2048-byte */ + +/* USB_TXFUNCADDR Bits */ +/* USB_TXFUNCADDR[ADDR] Bits */ +#define USB_TXFUNCADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_TXFUNCADDR_ADDR_MASK ((uint8_t)0x0000007FU) /* !< Device Address specifies the USB + bus address for the target Device. */ + +/* USB_TXHUBADDR Bits */ +/* USB_TXHUBADDR[ADDR] Bits */ +#define USB_TXHUBADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_TXHUBADDR_ADDR_MASK ((uint8_t)0x0000007FU) /* !< Device Address specifies the USB + bus address for the target Device. */ +/* USB_TXHUBADDR[MULTTRAN] Bits */ +#define USB_TXHUBADDR_MULTTRAN_OFS (7) /* !< MULTTRAN Offset */ +#define USB_TXHUBADDR_MULTTRAN_MASK ((uint8_t)0x00000080U) /* !< Record whether the hub has multiple + transaction translators. */ +#define USB_TXHUBADDR_MULTTRAN_CLEAR ((uint8_t)0x00000000U) /* !< Clear to indicate that the hub has + a single transaction translator. */ +#define USB_TXHUBADDR_MULTTRAN_SET ((uint8_t)0x00000080U) /* !< Set to indicate that the hub has + multiple transaction translators. */ + +/* USB_TXHUBPORT Bits */ +/* USB_TXHUBPORT[ADDR] Bits */ +#define USB_TXHUBPORT_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_TXHUBPORT_ADDR_MASK ((uint8_t)0x0000007FU) /* !< Hub Port specifies the USB hub port + number. */ + +/* USB_RXFUNCADDR Bits */ +/* USB_RXFUNCADDR[ADDR] Bits */ +#define USB_RXFUNCADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_RXFUNCADDR_ADDR_MASK ((uint8_t)0x0000007FU) /* !< Device Address specifies the USB + bus address for the target Device. */ + +/* USB_RXHUBADDR Bits */ +/* USB_RXHUBADDR[ADDR] Bits */ +#define USB_RXHUBADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_RXHUBADDR_ADDR_MASK ((uint8_t)0x0000007FU) /* !< Hub Address */ +/* USB_RXHUBADDR[MULTTRAN] Bits */ +#define USB_RXHUBADDR_MULTTRAN_OFS (7) /* !< MULTTRAN Offset */ +#define USB_RXHUBADDR_MULTTRAN_MASK ((uint8_t)0x00000080U) /* !< Record whether the hub has multiple + transaction translators. */ +#define USB_RXHUBADDR_MULTTRAN_CLEAR ((uint8_t)0x00000000U) /* !< Clear to indicate that the hub has + a single transaction translator. */ +#define USB_RXHUBADDR_MULTTRAN_SET ((uint8_t)0x00000080U) /* !< Set to indicate that the hub has + multiple transaction translators. */ + +/* USB_RXHUBPORT Bits */ +/* USB_RXHUBPORT[ADDR] Bits */ +#define USB_RXHUBPORT_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_RXHUBPORT_ADDR_MASK ((uint8_t)0x0000007FU) /* !< Hub Address */ + +/* USB_FADDR Bits */ +/* USB_FADDR[FUNCADDR] Bits */ +#define USB_FADDR_FUNCADDR_OFS (0) /* !< FUNCADDR Offset */ +#define USB_FADDR_FUNCADDR_MASK ((uint8_t)0x0000007FU) /* !< FAddr is an 8-bit register that + should be written with the 7-bit + address of the peripheral part of the + transaction. When the USB module is + being used in Peripheral mode + (DevCtl.D2=0), this register should + be written with the address received + through a SET_ADDRESS command, which + will then be used for decoding the + function address in subsequent token + packets. Notes: Peripheral Mode + Only!! */ + +/* USB_POWER Bits */ +/* USB_POWER[ENSUSPENDM] Bits */ +#define USB_POWER_ENSUSPENDM_OFS (0) /* !< ENSUSPENDM Offset */ +#define USB_POWER_ENSUSPENDM_MASK ((uint8_t)0x00000001U) /* !< Set by the CPU to enable the + Suspend mode for the USB PHY. */ +#define USB_POWER_ENSUSPENDM_DISABLE ((uint8_t)0x00000000U) /* !< USB PHY is powered */ +#define USB_POWER_ENSUSPENDM_ENABLE ((uint8_t)0x00000001U) /* !< Powers down the internal USB PHY. */ +/* USB_POWER[SUSPEND] Bits */ +#define USB_POWER_SUSPEND_OFS (1) /* !< SUSPEND Offset */ +#define USB_POWER_SUSPEND_MASK ((uint8_t)0x00000002U) /* !< In Host mode, this bit is set by + the CPU to enter Suspend mode. In + Peripheral mode, this bit is set on + entry into Suspend mode. It is + cleared when the CPU reads the + interrupt register, or sets the + Resume bit. */ +#define USB_POWER_SUSPEND_DISABLE ((uint8_t)0x00000000U) /* !< Ends SUSPEND signaling */ +#define USB_POWER_SUSPEND_ENABLE ((uint8_t)0x00000002U) /* !< Enables SUSPEND signaling */ +/* USB_POWER[RESUME] Bits */ +#define USB_POWER_RESUME_OFS (2) /* !< RESUME Offset */ +#define USB_POWER_RESUME_MASK ((uint8_t)0x00000004U) /* !< Set by the CPU to generate Resume + signaling when the device is in + Suspend mode. In Peripheral mode, + the CPU should clear this bit after + 10 ms (a maximum of 15 ms), to end + Resume signaling. In Host mode, the + CPU should clear this bit after 20 + ms. */ +#define USB_POWER_RESUME_DISABLE ((uint8_t)0x00000000U) /* !< Ends RESUME signaling on the bus. */ +#define USB_POWER_RESUME_ENABLE ((uint8_t)0x00000004U) /* !< Enables RESUME signaling when the + Device is in SUSPEND mode. */ +/* USB_POWER[RESET] Bits */ +#define USB_POWER_RESET_OFS (3) /* !< RESET Offset */ +#define USB_POWER_RESET_MASK ((uint8_t)0x00000008U) /* !< This bit is set when Reset + signaling is present on the bus. + Note: This bit is Read/Write from the + CPU in Host Mode but Read-Only in + Peripheral Mode. */ +#define USB_POWER_RESET_DISABLE ((uint8_t)0x00000000U) /* !< Ends RESET signaling on the bus. */ +#define USB_POWER_RESET_ENABLE ((uint8_t)0x00000008U) /* !< Enables RESET signaling on the bus. */ +/* USB_POWER[SOFT_CONN] Bits */ +#define USB_POWER_SOFT_CONN_OFS (6) /* !< SOFT_CONN Offset */ +#define USB_POWER_SOFT_CONN_MASK ((uint8_t)0x00000040U) /* !< Soft Connect/Disconnect feature. + The USB D+/D- lines are enabled when + this bit is set by the CPU and + tri-stated when this bit is cleared + by the CPU. Note: Only valid in + Peripheral Mode. */ +#define USB_POWER_SOFT_CONN_TRISTATE ((uint8_t)0x00000000U) /* !< The USB D+/D- lines are tri-stated. */ +#define USB_POWER_SOFT_CONN_ENABLE ((uint8_t)0x00000040U) /* !< The USB D+/D- lines are enabled. */ +/* USB_POWER[ISOUP] Bits */ +#define USB_POWER_ISOUP_OFS (7) /* !< ISOUP Offset */ +#define USB_POWER_ISOUP_MASK ((uint8_t)0x00000080U) /* !< Isochronous Update. When set by the + CPU, the USB module will wait for an + SOF token from the time TXRDY bit is + set in the USBTXCSRLn before sending + the packet. If an IN token is + received before an SOF token, then a + zero length data packet will be sent. + Note: Only valid in Peripheral Mode. + Also, this bit only affects endpoints + performing Isochronous transfers. */ +#define USB_POWER_ISOUP_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_POWER_ISOUP_WAIT_SOF ((uint8_t)0x00000080U) /* !< The USB controller waits for an SOF + token. */ + +/* USB_TXIS Bits */ +/* USB_TXIS[EP0] Bits */ +#define USB_TXIS_EP0_OFS (0) /* !< EP0 Offset */ +#define USB_TXIS_EP0_MASK ((uint16_t)0x00000001U) /* !< Transmit Endpoint 0 Interrupt */ +#define USB_TXIS_EP0_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP0_INT ((uint16_t)0x00000001U) /* !< The Endpoint 0 transmit and receive + interrupt is asserted. */ +/* USB_TXIS[EP1] Bits */ +#define USB_TXIS_EP1_OFS (1) /* !< EP1 Offset */ +#define USB_TXIS_EP1_MASK ((uint16_t)0x00000002U) /* !< Transmit Endpoint 1 Interrupt */ +#define USB_TXIS_EP1_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP1_INT ((uint16_t)0x00000002U) /* !< The Endpoint 1 transmit interrupt + is asserted. */ +/* USB_TXIS[EP2] Bits */ +#define USB_TXIS_EP2_OFS (2) /* !< EP2 Offset */ +#define USB_TXIS_EP2_MASK ((uint16_t)0x00000004U) /* !< Transmit Endpoint 2 Interrupt */ +#define USB_TXIS_EP2_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP2_INT ((uint16_t)0x00000004U) /* !< The Endpoint 2 transmit interrupt + is asserted. */ +/* USB_TXIS[EP3] Bits */ +#define USB_TXIS_EP3_OFS (3) /* !< EP3 Offset */ +#define USB_TXIS_EP3_MASK ((uint16_t)0x00000008U) /* !< Transmit Endpoint 3 Interrupt */ +#define USB_TXIS_EP3_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP3_INT ((uint16_t)0x00000008U) /* !< The Endpoint 3 transmit interrupt + is asserted. */ +/* USB_TXIS[EP4] Bits */ +#define USB_TXIS_EP4_OFS (4) /* !< EP4 Offset */ +#define USB_TXIS_EP4_MASK ((uint16_t)0x00000010U) /* !< Transmit Endpoint 4 Interrupt */ +#define USB_TXIS_EP4_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP4_INT ((uint16_t)0x00000010U) /* !< The Endpoint 4 transmit interrupt + is asserted. */ +/* USB_TXIS[EP5] Bits */ +#define USB_TXIS_EP5_OFS (5) /* !< EP5 Offset */ +#define USB_TXIS_EP5_MASK ((uint16_t)0x00000020U) /* !< Transmit Endpoint 5 Interrupt */ +#define USB_TXIS_EP5_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP5_INT ((uint16_t)0x00000020U) /* !< The Endpoint 5 transmit interrupt + is asserted. */ +/* USB_TXIS[EP6] Bits */ +#define USB_TXIS_EP6_OFS (6) /* !< EP6 Offset */ +#define USB_TXIS_EP6_MASK ((uint16_t)0x00000040U) /* !< Transmit Endpoint 6 Interrupt */ +#define USB_TXIS_EP6_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP6_INT ((uint16_t)0x00000040U) /* !< The Endpoint 6 transmit interrupt + is asserted. */ +/* USB_TXIS[EP7] Bits */ +#define USB_TXIS_EP7_OFS (7) /* !< EP7 Offset */ +#define USB_TXIS_EP7_MASK ((uint16_t)0x00000080U) /* !< Transmit Endpoint 7 Interrupt */ +#define USB_TXIS_EP7_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_TXIS_EP7_INT ((uint16_t)0x00000080U) /* !< The Endpoint 7 transmit interrupt + is asserted. */ + +/* USB_RXIS Bits */ +/* USB_RXIS[EP1] Bits */ +#define USB_RXIS_EP1_OFS (1) /* !< EP1 Offset */ +#define USB_RXIS_EP1_MASK ((uint16_t)0x00000002U) /* !< Recieve Endpoint 1 Interrupt */ +#define USB_RXIS_EP1_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIS_EP1_INT ((uint16_t)0x00000002U) /* !< The Endpoint 1 transmit interrupt + is asserted. */ +/* USB_RXIS[EP2] Bits */ +#define USB_RXIS_EP2_OFS (2) /* !< EP2 Offset */ +#define USB_RXIS_EP2_MASK ((uint16_t)0x00000004U) /* !< Recieve Endpoint 2 Interrupt */ +#define USB_RXIS_EP2_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIS_EP2_INT ((uint16_t)0x00000004U) /* !< The Endpoint 2 transmit interrupt + is asserted. */ +/* USB_RXIS[EP3] Bits */ +#define USB_RXIS_EP3_OFS (3) /* !< EP3 Offset */ +#define USB_RXIS_EP3_MASK ((uint16_t)0x00000008U) /* !< Recieve Endpoint 3 Interrupt */ +#define USB_RXIS_EP3_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIS_EP3_INT ((uint16_t)0x00000008U) /* !< The Endpoint 3 transmit interrupt + is asserted. */ +/* USB_RXIS[EP4] Bits */ +#define USB_RXIS_EP4_OFS (4) /* !< EP4 Offset */ +#define USB_RXIS_EP4_MASK ((uint16_t)0x00000010U) /* !< Recieve Endpoint 4 Interrupt */ +#define USB_RXIS_EP4_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIS_EP4_INT ((uint16_t)0x00000010U) /* !< The Endpoint 4 transmit interrupt + is asserted. */ +/* USB_RXIS[EP5] Bits */ +#define USB_RXIS_EP5_OFS (5) /* !< EP5 Offset */ +#define USB_RXIS_EP5_MASK ((uint16_t)0x00000020U) /* !< Recieve Endpoint 5 Interrupt */ +#define USB_RXIS_EP5_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIS_EP5_INT ((uint16_t)0x00000020U) /* !< The Endpoint 5 transmit interrupt + is asserted. */ +/* USB_RXIS[EP6] Bits */ +#define USB_RXIS_EP6_OFS (6) /* !< EP6 Offset */ +#define USB_RXIS_EP6_MASK ((uint16_t)0x00000040U) /* !< Recieve Endpoint 6 Interrupt */ +#define USB_RXIS_EP6_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIS_EP6_INT ((uint16_t)0x00000040U) /* !< The Endpoint 6 transmit interrupt + is asserted. */ +/* USB_RXIS[EP7] Bits */ +#define USB_RXIS_EP7_OFS (7) /* !< EP7 Offset */ +#define USB_RXIS_EP7_MASK ((uint16_t)0x00000080U) /* !< Recieve Endpoint 7 Interrupt */ +#define USB_RXIS_EP7_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIS_EP7_INT ((uint16_t)0x00000080U) /* !< The Endpoint 7 transmit interrupt + is asserted. */ + +/* USB_TXIE Bits */ +/* USB_TXIE[EP0] Bits */ +#define USB_TXIE_EP0_OFS (0) /* !< EP0 Offset */ +#define USB_TXIE_EP0_MASK ((uint16_t)0x00000001U) /* !< Transmit Endpoint 0 Interrupt + Enable */ +#define USB_TXIE_EP0_DISABLE ((uint16_t)0x00000000U) /* !< The EP0 transmit and receive + interrupt is suppressed and not sent + to the interupt controller. */ +#define USB_TXIE_EP0_ENABLE ((uint16_t)0x00000001U) /* !< An interrupt is sent to the + interrupt controller when the EP0 bit + in the USBTXIS register is set. */ +/* USB_TXIE[EP1] Bits */ +#define USB_TXIE_EP1_OFS (1) /* !< EP1 Offset */ +#define USB_TXIE_EP1_MASK ((uint16_t)0x00000002U) /* !< Transmit Endpoint 1 Interrupt + Enable */ +#define USB_TXIE_EP1_DISABLE ((uint16_t)0x00000000U) /* !< The EP1 transmit interrupt is + suppressed and not sent to the + interrupt controller. */ +#define USB_TXIE_EP1_ENABLE ((uint16_t)0x00000002U) /* !< An interrupt is sent to the + interrupt controller when the EP1 bit + in the USBTXIS register is set. */ +/* USB_TXIE[EP2] Bits */ +#define USB_TXIE_EP2_OFS (2) /* !< EP2 Offset */ +#define USB_TXIE_EP2_MASK ((uint16_t)0x00000004U) /* !< Transmit Endpoint 2 Interrupt + Enable */ +#define USB_TXIE_EP2_DISABLE ((uint16_t)0x00000000U) /* !< The EP2 transmit interrupt is + suppressed and not sent to the + interrupt controller. */ +#define USB_TXIE_EP2_ENABLE ((uint16_t)0x00000004U) /* !< An interrupt is sent to the + interrupt controller when the EP2 bit + in the USBTXIS register is set. */ +/* USB_TXIE[EP3] Bits */ +#define USB_TXIE_EP3_OFS (3) /* !< EP3 Offset */ +#define USB_TXIE_EP3_MASK ((uint16_t)0x00000008U) /* !< Transmit Endpoint 3 Interrupt + Enable */ +#define USB_TXIE_EP3_DISABLE ((uint16_t)0x00000000U) /* !< The EP3 transmit interrupt is + suppressed and not sent to the + interrupt controller. */ +#define USB_TXIE_EP3_ENABLE ((uint16_t)0x00000008U) /* !< An interrupt is sent to the + interrupt controller when the EP3 bit + in the USBTXIS register is set. */ +/* USB_TXIE[EP4] Bits */ +#define USB_TXIE_EP4_OFS (4) /* !< EP4 Offset */ +#define USB_TXIE_EP4_MASK ((uint16_t)0x00000010U) /* !< Transmit Endpoint 4 Interrupt + Enable */ +#define USB_TXIE_EP4_DISABLE ((uint16_t)0x00000000U) /* !< The EP4 transmit interrupt is + suppressed and not sent to the + interrupt controller. */ +#define USB_TXIE_EP4_ENABLE ((uint16_t)0x00000010U) /* !< An interrupt is sent to the + interrupt controller when the EP4 bit + in the USBTXIS register is set. */ +/* USB_TXIE[EP5] Bits */ +#define USB_TXIE_EP5_OFS (5) /* !< EP5 Offset */ +#define USB_TXIE_EP5_MASK ((uint16_t)0x00000020U) /* !< Transmit Endpoint 5 Interrupt + Enable */ +#define USB_TXIE_EP5_DISABLE ((uint16_t)0x00000000U) /* !< The EP5 transmit interrupt is + suppressed and not sent to the + interrupt controller. */ +#define USB_TXIE_EP5_ENABLE ((uint16_t)0x00000020U) /* !< An interrupt is sent to the + interrupt controller when the EP5 bit + in the USBTXIS register is set. */ +/* USB_TXIE[EP6] Bits */ +#define USB_TXIE_EP6_OFS (6) /* !< EP6 Offset */ +#define USB_TXIE_EP6_MASK ((uint16_t)0x00000040U) /* !< Transmit Endpoint 6 Interrupt + Enable */ +#define USB_TXIE_EP6_DISABLE ((uint16_t)0x00000000U) /* !< The EP6 transmit interrupt is + suppressed and not sent to the + interrupt controller. */ +#define USB_TXIE_EP6_ENABLE ((uint16_t)0x00000040U) /* !< An interrupt is sent to the + interrupt controller when the EP6 bit + in the USBTXIS register is set. */ +/* USB_TXIE[EP7] Bits */ +#define USB_TXIE_EP7_OFS (7) /* !< EP7 Offset */ +#define USB_TXIE_EP7_MASK ((uint16_t)0x00000080U) /* !< Transmit Endpoint 7 Interrupt + Enable */ +#define USB_TXIE_EP7_DISABLE ((uint16_t)0x00000000U) /* !< The EP7 transmit interrupt is + suppressed and not sent to the + interrupt controller. */ +#define USB_TXIE_EP7_ENABLE ((uint16_t)0x00000080U) /* !< An interrupt is sent to the + interrupt controller when the EP7 bit + in the USBTXIS register is set. */ + +/* USB_RXIE Bits */ +/* USB_RXIE[EP1] Bits */ +#define USB_RXIE_EP1_OFS (1) /* !< EP1 Offset */ +#define USB_RXIE_EP1_MASK ((uint16_t)0x00000002U) /* !< Recieve Endpoint 1 Interrupt Enable */ +#define USB_RXIE_EP1_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIE_EP1_INT ((uint16_t)0x00000002U) /* !< The Endpoint 1 transmit interrupt + is asserted. */ +/* USB_RXIE[EP2] Bits */ +#define USB_RXIE_EP2_OFS (2) /* !< EP2 Offset */ +#define USB_RXIE_EP2_MASK ((uint16_t)0x00000004U) /* !< Recieve Endpoint 2 Interrupt Enable */ +#define USB_RXIE_EP2_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIE_EP2_INT ((uint16_t)0x00000004U) /* !< The Endpoint 2 transmit interrupt + is asserted. */ +/* USB_RXIE[EP3] Bits */ +#define USB_RXIE_EP3_OFS (3) /* !< EP3 Offset */ +#define USB_RXIE_EP3_MASK ((uint16_t)0x00000008U) /* !< Recieve Endpoint 3 Interrupt Enable */ +#define USB_RXIE_EP3_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIE_EP3_INT ((uint16_t)0x00000008U) /* !< The Endpoint 3 transmit interrupt + is asserted. */ +/* USB_RXIE[EP4] Bits */ +#define USB_RXIE_EP4_OFS (4) /* !< EP4 Offset */ +#define USB_RXIE_EP4_MASK ((uint16_t)0x00000010U) /* !< Recieve Endpoint 4 Interrupt Enable */ +#define USB_RXIE_EP4_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIE_EP4_INT ((uint16_t)0x00000010U) /* !< The Endpoint 4 transmit interrupt + is asserted. */ +/* USB_RXIE[EP5] Bits */ +#define USB_RXIE_EP5_OFS (5) /* !< EP5 Offset */ +#define USB_RXIE_EP5_MASK ((uint16_t)0x00000020U) /* !< Recieve Endpoint 5 Interrupt Enable */ +#define USB_RXIE_EP5_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIE_EP5_INT ((uint16_t)0x00000020U) /* !< The Endpoint 5 transmit interrupt + is asserted. */ +/* USB_RXIE[EP6] Bits */ +#define USB_RXIE_EP6_OFS (6) /* !< EP6 Offset */ +#define USB_RXIE_EP6_MASK ((uint16_t)0x00000040U) /* !< Recieve Endpoint 6 Interrupt Enable */ +#define USB_RXIE_EP6_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIE_EP6_INT ((uint16_t)0x00000040U) /* !< The Endpoint 6 transmit interrupt + is asserted. */ +/* USB_RXIE[EP7] Bits */ +#define USB_RXIE_EP7_OFS (7) /* !< EP7 Offset */ +#define USB_RXIE_EP7_MASK ((uint16_t)0x00000080U) /* !< Recieve Endpoint 7 Interrupt Enable */ +#define USB_RXIE_EP7_NO_INT ((uint16_t)0x00000000U) /* !< No interrupt */ +#define USB_RXIE_EP7_INT ((uint16_t)0x00000080U) /* !< The Endpoint 7 transmit interrupt + is asserted. */ + +/* USB_USBIS Bits */ +/* USB_USBIS[SUSPEND] Bits */ +#define USB_USBIS_SUSPEND_OFS (0) /* !< SUSPEND Offset */ +#define USB_USBIS_SUSPEND_MASK ((uint8_t)0x00000001U) /* !< Set when Suspend signaling is + detected on the bus. Note: Only valid + in Peripheral mode. */ +#define USB_USBIS_SUSPEND_NO_INT ((uint8_t)0x00000000U) /* !< No interrupt */ +#define USB_USBIS_SUSPEND_INT ((uint8_t)0x00000001U) /* !< SUSPEND signaling has been detected + on the bus. */ +/* USB_USBIS[RESUME] Bits */ +#define USB_USBIS_RESUME_OFS (1) /* !< RESUME Offset */ +#define USB_USBIS_RESUME_MASK ((uint8_t)0x00000002U) /* !< Set when Resume signaling is + detected on the bus while the USB + controller is in Suspend mode. */ +#define USB_USBIS_RESUME_NO_INT ((uint8_t)0x00000000U) /* !< No interrupt */ +#define USB_USBIS_RESUME_INT ((uint8_t)0x00000002U) /* !< RESUME signaling has been detected + on the bus. */ +/* USB_USBIS[RESETBABBLE] Bits */ +#define USB_USBIS_RESETBABBLE_OFS (2) /* !< RESETBABBLE Offset */ +#define USB_USBIS_RESETBABBLE_MASK ((uint8_t)0x00000004U) /* !< Device mode - RESET: Set in + Peripheral mode when Reset signaling + is detected on the bus. Host mode - + BABBLE: Set in Host mode when babble + is detected. Note: Only active after + first SOF has been sent. */ +#define USB_USBIS_RESETBABBLE_NO_INT ((uint8_t)0x00000000U) /* !< No interrupt */ +#define USB_USBIS_RESETBABBLE_INT ((uint8_t)0x00000004U) /* !< RESET / BABBLE signaling has been + detected on the bus. */ +/* USB_USBIS[SOF] Bits */ +#define USB_USBIS_SOF_OFS (3) /* !< SOF Offset */ +#define USB_USBIS_SOF_MASK ((uint8_t)0x00000008U) /* !< Start of frame */ +#define USB_USBIS_SOF_NO_INT ((uint8_t)0x00000000U) /* !< No interrupt */ +#define USB_USBIS_SOF_INT ((uint8_t)0x00000008U) /* !< A new frame has started. */ +/* USB_USBIS[CONN] Bits */ +#define USB_USBIS_CONN_OFS (4) /* !< CONN Offset */ +#define USB_USBIS_CONN_MASK ((uint8_t)0x00000010U) /* !< Set when a device connection is + detected. Note: Only valid in Host + mode. Valid at all transaction + speeds. */ +#define USB_USBIS_CONN_NO_INT ((uint8_t)0x00000000U) /* !< No interrupt */ +#define USB_USBIS_CONN_INT ((uint8_t)0x00000010U) /* !< The device has detected a + connection to the host. */ +/* USB_USBIS[DISCON] Bits */ +#define USB_USBIS_DISCON_OFS (5) /* !< DISCON Offset */ +#define USB_USBIS_DISCON_MASK ((uint8_t)0x00000020U) /* !< Set in Host mode when a device + disconnect is detected. Set in + Peripheral mode when a session ends. + Valid at all transaction speeds. */ +#define USB_USBIS_DISCON_NO_INT ((uint8_t)0x00000000U) /* !< No interrupt */ +#define USB_USBIS_DISCON_INT ((uint8_t)0x00000020U) /* !< The device has been disconnected + from the host. */ + +/* USB_USBIE Bits */ +/* USB_USBIE[SUSPEND] Bits */ +#define USB_USBIE_SUSPEND_OFS (0) /* !< SUSPEND Offset */ +#define USB_USBIE_SUSPEND_MASK ((uint8_t)0x00000001U) /* !< Interrupt enable for SUSPEND + signaling detected. Note: Only valid + in Peripheral mode. */ +#define USB_USBIE_SUSPEND_DISABLE ((uint8_t)0x00000000U) /* !< The SUSPEND interrupt is suppressed + and not sent to the interrupt + controller. */ +#define USB_USBIE_SUSPEND_ENABLE ((uint8_t)0x00000001U) /* !< An interrupt is sent to the + interrupt controller when the DISCON + bit in the USBIS register is set. */ +/* USB_USBIE[RESUME] Bits */ +#define USB_USBIE_RESUME_OFS (1) /* !< RESUME Offset */ +#define USB_USBIE_RESUME_MASK ((uint8_t)0x00000002U) /* !< Interrupt enable for RESUME + signaling detected. */ +#define USB_USBIE_RESUME_DISABLE ((uint8_t)0x00000000U) /* !< The RESUME interrupt is suppressed + and not sent to the interrupt + controller. */ +#define USB_USBIE_RESUME_ENABLE ((uint8_t)0x00000002U) /* !< An interrupt is sent to the + interrupt controller when the RESUME + bit in the USBIS register is set. */ +/* USB_USBIE[RESETBABBLE] Bits */ +#define USB_USBIE_RESETBABBLE_OFS (2) /* !< RESETBABBLE Offset */ +#define USB_USBIE_RESETBABBLE_MASK ((uint8_t)0x00000004U) /* !< Interrupt enable for RESET/BABBLE + signaling detected. */ +#define USB_USBIE_RESETBABBLE_DSIABLE ((uint8_t)0x00000000U) /* !< The RESET interrupt is suppressed + and not sent to the interrupt + controller. */ +#define USB_USBIE_RESETBABBLE_ENABLE ((uint8_t)0x00000004U) /* !< An interrupt is sent to the + interrupt controller when the RESET + bit in the USBIS register is set. */ +/* USB_USBIE[SOF] Bits */ +#define USB_USBIE_SOF_OFS (3) /* !< SOF Offset */ +#define USB_USBIE_SOF_MASK ((uint8_t)0x00000008U) /* !< Interrupt enable for Start of + frame. */ +#define USB_USBIE_SOF_DISABLE ((uint8_t)0x00000000U) /* !< The SOF interrupt is suppressed and + not sent to the interrupt controller. */ +#define USB_USBIE_SOF_ENABLE ((uint8_t)0x00000008U) /* !< An interrupt is sent to the + interrupt controller when the SOF bit + in the USBIS register is set. */ +/* USB_USBIE[CONN] Bits */ +#define USB_USBIE_CONN_OFS (4) /* !< CONN Offset */ +#define USB_USBIE_CONN_MASK ((uint8_t)0x00000010U) /* !< Interrupt enable for connect + detected. Note: Only valid in Host + mode. Valid at all transaction + speeds. */ +#define USB_USBIE_CONN_DISABLE ((uint8_t)0x00000000U) /* !< The CONN interrupt is suppressed + and not sent to the interrupt + controller. */ +#define USB_USBIE_CONN_ENABLE ((uint8_t)0x00000010U) /* !< An interrupt is sent to the + interrupt controller when the CONN + bit in the USBIS register is set. */ +/* USB_USBIE[DISCON] Bits */ +#define USB_USBIE_DISCON_OFS (5) /* !< DISCON Offset */ +#define USB_USBIE_DISCON_MASK ((uint8_t)0x00000020U) /* !< Interrupt enable for session + disconnect. */ +#define USB_USBIE_DISCON_DISABLE ((uint8_t)0x00000000U) /* !< The DISCON interrupt is suppressed + and not sent to the interrupt + controller. */ +#define USB_USBIE_DISCON_ENABLE ((uint8_t)0x00000020U) /* !< An interrupt is sent to the + interrupt controller when the DISCON + bit in the USBIS register is set. */ + +/* USB_FRAME Bits */ +/* USB_FRAME[FRAME] Bits */ +#define USB_FRAME_FRAME_OFS (0) /* !< FRAME Offset */ +#define USB_FRAME_FRAME_MASK ((uint16_t)0x000007FFU) /* !< Frame Number */ + +/* USB_EPINDEX Bits */ +/* USB_EPINDEX[EPIDX] Bits */ +#define USB_EPINDEX_EPIDX_OFS (0) /* !< EPIDX Offset */ +#define USB_EPINDEX_EPIDX_MASK ((uint8_t)0x0000000FU) /* !< Endpoint Index. #br#This bit field + configures which endpoint is accessed + when reading or writing to one of the + USB controller's indexed registers. A + value of 0x0 corresponds to Endpoint + 0 and a value of 0xF corresponds to + Endpoint 15. */ +#define USB_EPINDEX_EPIDX_EP0 ((uint8_t)0x00000000U) /* !< Select EP0 as indexed register */ +#define USB_EPINDEX_EPIDX_EP1 ((uint8_t)0x00000001U) /* !< Select EP1 as indexed register */ +#define USB_EPINDEX_EPIDX_EP2 ((uint8_t)0x00000002U) /* !< Select EP2 as indexed register */ +#define USB_EPINDEX_EPIDX_EP3 ((uint8_t)0x00000003U) /* !< Select EP3 as indexed register */ +#define USB_EPINDEX_EPIDX_EP4 ((uint8_t)0x00000004U) /* !< Select EP4 as indexed register */ +#define USB_EPINDEX_EPIDX_EP5 ((uint8_t)0x00000005U) /* !< Select EP5 as indexed register */ +#define USB_EPINDEX_EPIDX_EP6 ((uint8_t)0x00000006U) /* !< Select EP6 as indexed register */ +#define USB_EPINDEX_EPIDX_EP7 ((uint8_t)0x00000007U) /* !< Select EP7 as indexed register */ + +/* USB_TESTMODE Bits */ +/* USB_TESTMODE[FORCEFS] Bits */ +#define USB_TESTMODE_FORCEFS_OFS (5) /* !< FORCEFS Offset */ +#define USB_TESTMODE_FORCEFS_MASK ((uint8_t)0x00000020U) /* !< Force Full Speed Upon Reset. The + CPU sets this bit either in + conjunction with bit 7 (FORCEH) or to + force the USB controller into + Full-speed mode when it receives a + USB reset. */ +#define USB_TESTMODE_FORCEFS_LOW ((uint8_t)0x00000000U) /* !< The USB controller operates at Low + Speed. */ +#define USB_TESTMODE_FORCEFS_FULL ((uint8_t)0x00000020U) /* !< Forces the USB controller into + Full-Speed mode upon receiving a USB + RESET. */ +/* USB_TESTMODE[FIFOACC] Bits */ +#define USB_TESTMODE_FIFOACC_OFS (6) /* !< FIFOACC Offset */ +#define USB_TESTMODE_FIFOACC_MASK ((uint8_t)0x00000040U) /* !< FIFO Access. The CPU sets this bit + to transfer the packet in the + Endpoint 0 TX FIFO to the Endpoint 0 + Rx FIFO. Note: It is cleared + automatically. */ +#define USB_TESTMODE_FIFOACC_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_TESTMODE_FIFOACC_EFFECT ((uint8_t)0x00000040U) /* !< Transfers the packet in the + endpoint 0 transmit FIFO to the + endpoint 0 receive FIFO. */ +/* USB_TESTMODE[FORCEH] Bits */ +#define USB_TESTMODE_FORCEH_OFS (7) /* !< FORCEH Offset */ +#define USB_TESTMODE_FORCEH_MASK ((uint8_t)0x00000080U) /* !< Force Host Mode. The CPU sets this + bit to instruct the core to enter + Host mode when the Session bit is + set, regardless of whether it is + connected to any peripheral. The + state of the CID input, + HostDisconnect and LineState signals + are ignored. The core will then + remain in Host mode until the Session + bit is cleared, even if a device is + disconnected, and if the Force_Host + bit remains set, will re-enter Host + mode the next time the Session bit is + set. While in this mode, status of + the bus connection may be read using + the DEV bit of the USBDEVCTL + register. The operating speed is + determined from the FORCEFS bit. */ +#define USB_TESTMODE_FORCEH_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_TESTMODE_FORCEH_EFFECT ((uint8_t)0x00000080U) /* !< Forces the USB controller to enter + Host mode when the SESSION bit is + set, regardless ofwhether the USB + controller is connected to any + peripheral. The state of the USB0DP + and USB0DM signals is ignored. The + USB controller then remains in Host + mode until the SESSION #br#bit is + cleared, even if a Device is + disconnected. If the FORCEH bit + remains set, the USB controller + re-enters Host mode the next time the + SESSION bit is set. */ + +/* USB_IDXTXMAXP Bits */ +/* USB_IDXTXMAXP[DATA] Bits */ +#define USB_IDXTXMAXP_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXTXMAXP_DATA_MASK ((uint16_t)0x0000FFFFU) /* !< Control / Status register data. */ + +/* USB_IDXTXCSRL Bits */ +/* USB_IDXTXCSRL[DATA] Bits */ +#define USB_IDXTXCSRL_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXTXCSRL_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXTXCSRH Bits */ +/* USB_IDXTXCSRH[DATA] Bits */ +#define USB_IDXTXCSRH_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXTXCSRH_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXRXMAXP Bits */ +/* USB_IDXRXMAXP[DATA] Bits */ +#define USB_IDXRXMAXP_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXRXMAXP_DATA_MASK ((uint16_t)0x0000FFFFU) /* !< Control / Status register data. */ + +/* USB_IDXRXCSRL Bits */ +/* USB_IDXRXCSRL[DATA] Bits */ +#define USB_IDXRXCSRL_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXRXCSRL_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXRXCSRH Bits */ +/* USB_IDXRXCSRH[DATA] Bits */ +#define USB_IDXRXCSRH_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXRXCSRH_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXRXCOUNT Bits */ +/* USB_IDXRXCOUNT[DATA] Bits */ +#define USB_IDXRXCOUNT_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXRXCOUNT_DATA_MASK ((uint16_t)0x0000FFFFU) /* !< Control / Status register data. */ + +/* USB_IDXTXTYPE Bits */ +/* USB_IDXTXTYPE[DATA] Bits */ +#define USB_IDXTXTYPE_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXTXTYPE_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXTXINTERVAL Bits */ +/* USB_IDXTXINTERVAL[DATA] Bits */ +#define USB_IDXTXINTERVAL_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXTXINTERVAL_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXRXTYPE Bits */ +/* USB_IDXRXTYPE[DATA] Bits */ +#define USB_IDXRXTYPE_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXRXTYPE_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXRXINTERVAL Bits */ +/* USB_IDXRXINTERVAL[DATA] Bits */ +#define USB_IDXRXINTERVAL_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXRXINTERVAL_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_IDXFIFOSZ Bits */ +/* USB_IDXFIFOSZ[DATA] Bits */ +#define USB_IDXFIFOSZ_DATA_OFS (0) /* !< DATA Offset */ +#define USB_IDXFIFOSZ_DATA_MASK ((uint8_t)0x000000FFU) /* !< Control / Status register data. */ + +/* USB_FIFO Bits */ +/* USB_FIFO[EPDATA] Bits */ +#define USB_FIFO_EPDATA_OFS (0) /* !< EPDATA Offset */ +#define USB_FIFO_EPDATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Endpoint Data. Writing to this + register loads the data into the + Transmit FIFO and reading unloads + data from the Receive FIFO. */ + +/* USB_BYTE Bits */ +/* USB_BYTE[EPDATA] Bits */ +#define USB_BYTE_EPDATA_OFS (0) /* !< EPDATA Offset */ +#define USB_BYTE_EPDATA_MASK ((uint32_t)0x000000FFU) /* !< Endpoint Data 8-bit. */ + +/* USB_HALF Bits */ +/* USB_HALF[EPDATA] Bits */ +#define USB_HALF_EPDATA_OFS (0) /* !< EPDATA Offset */ +#define USB_HALF_EPDATA_MASK ((uint32_t)0x0000FFFFU) /* !< Endpoint Data 16-bit. */ + +/* USB_WORD Bits */ +/* USB_WORD[EPDATA] Bits */ +#define USB_WORD_EPDATA_OFS (0) /* !< EPDATA Offset */ +#define USB_WORD_EPDATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Endpoint Data 32-bit. */ + +/* USB_DEVCTL Bits */ +/* USB_DEVCTL[SESSION] Bits */ +#define USB_DEVCTL_SESSION_OFS (0) /* !< SESSION Offset */ +#define USB_DEVCTL_SESSION_MASK ((uint8_t)0x00000001U) /* !< Session Start/End. Host mode: This + bit is set or cleared by the CPU to + start or end a session. Device mode: + This bit is set/cleared by the USB + controller when a session + starts/ends. It is also set by the + CPU to initiate the Session Request + Protocol. When the USB controller is + in Suspend mode, the bit may be + cleared by the CPU to perform a + software disconnect. Note: Clearing + this bit when the core is not + suspended will result in undefined + behavior. */ +#define USB_DEVCTL_SESSION_CLEAR ((uint8_t)0x00000000U) /* !< When operating as a Host: #br#When + cleared by software, this bit ends a + session. #br# #br#When operating as a + Device: #br#The USB controller has + ended a session. When the USB + controller is in SUSPEND mode, this + bit may be cleared by software to + perform a software disconnect. */ +#define USB_DEVCTL_SESSION_SET ((uint8_t)0x00000001U) /* !< When operating as a Host: #br#When + set by software, this bit starts a + session. #br# #br#When operating as a + Device: #br#The USB controller has + started a session. When set by + software, the Session Request + Protocol is initiated. #br# + #br#Clearing this bit when the USB + controller is not suspended results + in undefined behavior. */ +/* USB_DEVCTL[HOSTREQ] Bits */ +#define USB_DEVCTL_HOSTREQ_OFS (1) /* !< HOSTREQ Offset */ +#define USB_DEVCTL_HOSTREQ_MASK ((uint8_t)0x00000002U) /* !< When set, the USB controller will + initiate the Host Negotiation when + Suspend mode is entered. It is + cleared when Host Negotiation is + completed. */ +#define USB_DEVCTL_HOSTREQ_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_DEVCTL_HOSTREQ_EFFECT ((uint8_t)0x00000002U) /* !< Initiates the Host Negotiation when + SUSPENDmode is entered. */ +/* USB_DEVCTL[HOST] Bits */ +#define USB_DEVCTL_HOST_OFS (2) /* !< HOST Offset */ +#define USB_DEVCTL_HOST_MASK ((uint8_t)0x00000004U) /* !< Host Mode. This Read-only bit is + set when the USB controller is acting + as a Host. Note: Only valid while a + session is in progress. */ +#define USB_DEVCTL_HOST_DEVICE ((uint8_t)0x00000000U) /* !< The USB controller is acting as a + Device. */ +#define USB_DEVCTL_HOST_HOST ((uint8_t)0x00000004U) /* !< The USB controller is acting as a + Host. */ +/* USB_DEVCTL[VUSB] Bits */ +#define USB_DEVCTL_VUSB_OFS (3) /* !< VUSB Offset */ +#define USB_DEVCTL_VUSB_MASK ((uint8_t)0x00000018U) /* !< VUSB / USB-PHY is powered. */ +#define USB_DEVCTL_VUSB_NOT_POWERED ((uint8_t)0x00000000U) /* !< VUSB / USB-PHY supply is detected + as under 1.35V. */ +#define USB_DEVCTL_VUSB_POWERED ((uint8_t)0x00000018U) /* !< VUSB / USB-PHY supply is detected + as above 1.35V. */ +/* USB_DEVCTL[LSDEV] Bits */ +#define USB_DEVCTL_LSDEV_OFS (5) /* !< LSDEV Offset */ +#define USB_DEVCTL_LSDEV_MASK ((uint8_t)0x00000020U) /* !< Low Speed Device Detected. This + Read-only bit is set when a low-speed + device has been detected being + connected to the port. Note: Only + valid in Host mode. */ +#define USB_DEVCTL_LSDEV_NO_DETCT ((uint8_t)0x00000000U) /* !< A low-speed Device has not been + detected on the port. */ +#define USB_DEVCTL_LSDEV_DETCT ((uint8_t)0x00000020U) /* !< A low-speed Device has been + detected on the port. */ +/* USB_DEVCTL[FSDEV] Bits */ +#define USB_DEVCTL_FSDEV_OFS (6) /* !< FSDEV Offset */ +#define USB_DEVCTL_FSDEV_MASK ((uint8_t)0x00000040U) /* !< Full Speed Device Detected. This + Read-only bit is set when a + full-speed device has been detected + being connected to the port. Note: + Only valid in Host mode. */ +#define USB_DEVCTL_FSDEV_NO_DETCT ((uint8_t)0x00000000U) /* !< A full-speed Device has not been + detected on the port. */ +#define USB_DEVCTL_FSDEV_DETCT ((uint8_t)0x00000040U) /* !< A full-speed Device has been + detected on the port. */ +/* USB_DEVCTL[DEV] Bits */ +#define USB_DEVCTL_DEV_OFS (7) /* !< DEV Offset */ +#define USB_DEVCTL_DEV_MASK ((uint8_t)0x00000080U) /* !< Device Mode. This Read-only bit + indicates whether the USB controller + is operating as the host mode or + device mode. Note: Only valid while + a session is in progress. */ +#define USB_DEVCTL_DEV_HOST ((uint8_t)0x00000000U) /* !< The USB controller is operating in + host mode. */ +#define USB_DEVCTL_DEV_DEVICE ((uint8_t)0x00000080U) /* !< The USB controller is operating in + device mode. */ + +/* USB_MISC Bits */ +/* USB_MISC[RX_EDMA] Bits */ +#define USB_MISC_RX_EDMA_OFS (0) /* !< RX_EDMA Offset */ +#define USB_MISC_RX_EDMA_MASK ((uint8_t)0x00000001U) /* !< Receive early DMA mode. */ +#define USB_MISC_RX_EDMA_LATE ((uint8_t)0x00000000U) /* !< Late mode: DMA_REQ signal for all + OUT Endpoints will be de-asserted + when MAXP bytes have been read to an + endpoint. */ +#define USB_MISC_RX_EDMA_EARLY ((uint8_t)0x00000001U) /* !< Early Mode: DMA_REQ signal for all + OUT Endpoints will be de-asserted + when MAXP-8 bytes have been read to + an endpoint. */ +/* USB_MISC[TX_EDMA] Bits */ +#define USB_MISC_TX_EDMA_OFS (1) /* !< TX_EDMA Offset */ +#define USB_MISC_TX_EDMA_MASK ((uint8_t)0x00000002U) /* !< Transmit early DMA mode. */ +#define USB_MISC_TX_EDMA_LATE ((uint8_t)0x00000000U) /* !< Late mode: DMA_REQ signal for all + IN Endpoints will be de-asserted when + MAXP bytes have been written to an + endpoint. This is late mode. */ +#define USB_MISC_TX_EDMA_EARLY ((uint8_t)0x00000002U) /* !< Early mode: DMA_REQ signal for all + IN Endpoints will be de-asserted when + MAXP-8 bytes have been written to an + endpoint. This is early mode. */ + +/* USB_IDXTXFIFOSZ Bits */ +/* USB_IDXTXFIFOSZ[SIZE] Bits */ +#define USB_IDXTXFIFOSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define USB_IDXTXFIFOSZ_SIZE_MASK ((uint8_t)0x0000000FU) /* !< Max Packet Size */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_8 ((uint8_t)0x00000000U) /* !< FIFO size 8-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_16 ((uint8_t)0x00000001U) /* !< FIFO size 16-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_32 ((uint8_t)0x00000002U) /* !< FIFO size 32-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_64 ((uint8_t)0x00000003U) /* !< FIFO size 64-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_128 ((uint8_t)0x00000004U) /* !< FIFO size 128-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_256 ((uint8_t)0x00000005U) /* !< FIFO size 256-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_512 ((uint8_t)0x00000006U) /* !< FIFO size 512-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_1024 ((uint8_t)0x00000007U) /* !< FIFO size 1024-byte */ +#define USB_IDXTXFIFOSZ_SIZE_BYTES_2048 ((uint8_t)0x00000008U) /* !< FIFO size 2048-byte */ +/* USB_IDXTXFIFOSZ[DPB] Bits */ +#define USB_IDXTXFIFOSZ_DPB_OFS (4) /* !< DPB Offset */ +#define USB_IDXTXFIFOSZ_DPB_MASK ((uint8_t)0x00000010U) /* !< Double Packet Buffer Support */ +#define USB_IDXTXFIFOSZ_DPB_SIGLE ((uint8_t)0x00000000U) /* !< Single packet buffering is + supported. */ +#define USB_IDXTXFIFOSZ_DPB_DOUBLE ((uint8_t)0x00000010U) /* !< Double packet buffering is enabled. */ + +/* USB_IDXRXFIFOSZ Bits */ +/* USB_IDXRXFIFOSZ[SIZE] Bits */ +#define USB_IDXRXFIFOSZ_SIZE_OFS (0) /* !< SIZE Offset */ +#define USB_IDXRXFIFOSZ_SIZE_MASK ((uint8_t)0x0000000FU) /* !< Maximum packet size to be allowed. + If DPB = 0, the FIFO also is this + size; if DPB = 1, the FIFO is twice + this size. Packet size in bytes: */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_8 ((uint8_t)0x00000000U) /* !< FIFO size 8-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_16 ((uint8_t)0x00000001U) /* !< FIFO size 16-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_32 ((uint8_t)0x00000002U) /* !< FIFO size 32-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_64 ((uint8_t)0x00000003U) /* !< FIFO size 64-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_128 ((uint8_t)0x00000004U) /* !< FIFO size 128-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_256 ((uint8_t)0x00000005U) /* !< FIFO size 256-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_512 ((uint8_t)0x00000006U) /* !< FIFO size 512-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_1024 ((uint8_t)0x00000007U) /* !< FIFO size 1024-byte */ +#define USB_IDXRXFIFOSZ_SIZE_BYTES_2048 ((uint8_t)0x00000008U) /* !< FIFO size 2048-byte */ +/* USB_IDXRXFIFOSZ[DPB] Bits */ +#define USB_IDXRXFIFOSZ_DPB_OFS (4) /* !< DPB Offset */ +#define USB_IDXRXFIFOSZ_DPB_MASK ((uint8_t)0x00000010U) /* !< Double Packet Buffer Support */ +#define USB_IDXRXFIFOSZ_DPB_SIGLE ((uint8_t)0x00000000U) /* !< Single packet buffering is + supported. */ +#define USB_IDXRXFIFOSZ_DPB_DOUBLE ((uint8_t)0x00000010U) /* !< Double packet buffering is enabled. */ + +/* USB_IDXTXFIFOADD Bits */ +/* USB_IDXTXFIFOADD[ADDR] Bits */ +#define USB_IDXTXFIFOADD_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_IDXTXFIFOADD_ADDR_MASK ((uint16_t)0x00003FFFU) /* !< Endpoint Data */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_0 ((uint16_t)0x00000000U) /* !< 0.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_8 ((uint16_t)0x00000001U) /* !< 8.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_16 ((uint16_t)0x00000002U) /* !< 16.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_24 ((uint16_t)0x00000003U) /* !< 24.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_32 ((uint16_t)0x00000004U) /* !< 32.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_40 ((uint16_t)0x00000005U) /* !< 40.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_48 ((uint16_t)0x00000006U) /* !< 48.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_56 ((uint16_t)0x00000007U) /* !< 56.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_64 ((uint16_t)0x00000008U) /* !< 64.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_72 ((uint16_t)0x00000009U) /* !< 72.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_80 ((uint16_t)0x0000000AU) /* !< 80.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_88 ((uint16_t)0x0000000BU) /* !< 88.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_96 ((uint16_t)0x0000000CU) /* !< 96.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_104 ((uint16_t)0x0000000DU) /* !< 104.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_112 ((uint16_t)0x0000000EU) /* !< 112.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_120 ((uint16_t)0x0000000FU) /* !< 120.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_128 ((uint16_t)0x00000010U) /* !< 128.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_136 ((uint16_t)0x00000011U) /* !< 136.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_144 ((uint16_t)0x00000012U) /* !< 144.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_152 ((uint16_t)0x00000013U) /* !< 152.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_160 ((uint16_t)0x00000014U) /* !< 160.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_168 ((uint16_t)0x00000015U) /* !< 168.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_176 ((uint16_t)0x00000016U) /* !< 176.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_184 ((uint16_t)0x00000017U) /* !< 184.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_192 ((uint16_t)0x00000018U) /* !< 192.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_200 ((uint16_t)0x00000019U) /* !< 200.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_208 ((uint16_t)0x0000001AU) /* !< 208.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_216 ((uint16_t)0x0000001BU) /* !< 216.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_224 ((uint16_t)0x0000001CU) /* !< 224.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_232 ((uint16_t)0x0000001DU) /* !< 232.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_240 ((uint16_t)0x0000001EU) /* !< 240.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_248 ((uint16_t)0x0000001FU) /* !< 248.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_256 ((uint16_t)0x00000020U) /* !< 256.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_264 ((uint16_t)0x00000021U) /* !< 264.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_272 ((uint16_t)0x00000022U) /* !< 272.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_280 ((uint16_t)0x00000023U) /* !< 280.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_288 ((uint16_t)0x00000024U) /* !< 288.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_296 ((uint16_t)0x00000025U) /* !< 296.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_304 ((uint16_t)0x00000026U) /* !< 304.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_312 ((uint16_t)0x00000027U) /* !< 312.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_320 ((uint16_t)0x00000028U) /* !< 320.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_328 ((uint16_t)0x00000029U) /* !< 328.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_336 ((uint16_t)0x0000002AU) /* !< 336.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_344 ((uint16_t)0x0000002BU) /* !< 344.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_352 ((uint16_t)0x0000002CU) /* !< 352.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_360 ((uint16_t)0x0000002DU) /* !< 360.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_368 ((uint16_t)0x0000002EU) /* !< 368.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_376 ((uint16_t)0x0000002FU) /* !< 376.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_384 ((uint16_t)0x00000030U) /* !< 384.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_392 ((uint16_t)0x00000031U) /* !< 392.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_400 ((uint16_t)0x00000032U) /* !< 400.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_408 ((uint16_t)0x00000033U) /* !< 408.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_416 ((uint16_t)0x00000034U) /* !< 416.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_424 ((uint16_t)0x00000035U) /* !< 424.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_432 ((uint16_t)0x00000036U) /* !< 432.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_440 ((uint16_t)0x00000037U) /* !< 440.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_448 ((uint16_t)0x00000038U) /* !< 448.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_456 ((uint16_t)0x00000039U) /* !< 456.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_464 ((uint16_t)0x0000003AU) /* !< 464.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_472 ((uint16_t)0x0000003BU) /* !< 472.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_480 ((uint16_t)0x0000003CU) /* !< 480.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_488 ((uint16_t)0x0000003DU) /* !< 488.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_496 ((uint16_t)0x0000003EU) /* !< 496.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_504 ((uint16_t)0x0000003FU) /* !< 504.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_512 ((uint16_t)0x00000040U) /* !< 512.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_520 ((uint16_t)0x00000041U) /* !< 520.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_528 ((uint16_t)0x00000042U) /* !< 528.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_536 ((uint16_t)0x00000043U) /* !< 536.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_544 ((uint16_t)0x00000044U) /* !< 544.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_552 ((uint16_t)0x00000045U) /* !< 552.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_560 ((uint16_t)0x00000046U) /* !< 560.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_568 ((uint16_t)0x00000047U) /* !< 568.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_576 ((uint16_t)0x00000048U) /* !< 576.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_584 ((uint16_t)0x00000049U) /* !< 584.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_592 ((uint16_t)0x0000004AU) /* !< 592.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_600 ((uint16_t)0x0000004BU) /* !< 600.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_608 ((uint16_t)0x0000004CU) /* !< 608.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_616 ((uint16_t)0x0000004DU) /* !< 616.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_624 ((uint16_t)0x0000004EU) /* !< 624.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_632 ((uint16_t)0x0000004FU) /* !< 632.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_640 ((uint16_t)0x00000050U) /* !< 640.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_648 ((uint16_t)0x00000051U) /* !< 648.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_656 ((uint16_t)0x00000052U) /* !< 656.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_664 ((uint16_t)0x00000053U) /* !< 664.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_672 ((uint16_t)0x00000054U) /* !< 672.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_680 ((uint16_t)0x00000055U) /* !< 680.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_688 ((uint16_t)0x00000056U) /* !< 688.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_696 ((uint16_t)0x00000057U) /* !< 696.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_704 ((uint16_t)0x00000058U) /* !< 704.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_712 ((uint16_t)0x00000059U) /* !< 712.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_720 ((uint16_t)0x0000005AU) /* !< 720.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_728 ((uint16_t)0x0000005BU) /* !< 728.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_736 ((uint16_t)0x0000005CU) /* !< 736.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_744 ((uint16_t)0x0000005DU) /* !< 744.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_752 ((uint16_t)0x0000005EU) /* !< 752.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_760 ((uint16_t)0x0000005FU) /* !< 760.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_768 ((uint16_t)0x00000060U) /* !< 768.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_776 ((uint16_t)0x00000061U) /* !< 776.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_784 ((uint16_t)0x00000062U) /* !< 784.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_792 ((uint16_t)0x00000063U) /* !< 792.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_800 ((uint16_t)0x00000064U) /* !< 800.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_808 ((uint16_t)0x00000065U) /* !< 808.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_816 ((uint16_t)0x00000066U) /* !< 816.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_824 ((uint16_t)0x00000067U) /* !< 824.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_832 ((uint16_t)0x00000068U) /* !< 832.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_840 ((uint16_t)0x00000069U) /* !< 840.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_848 ((uint16_t)0x0000006AU) /* !< 848.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_856 ((uint16_t)0x0000006BU) /* !< 856.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_864 ((uint16_t)0x0000006CU) /* !< 864.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_872 ((uint16_t)0x0000006DU) /* !< 872.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_880 ((uint16_t)0x0000006EU) /* !< 880.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_888 ((uint16_t)0x0000006FU) /* !< 888.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_896 ((uint16_t)0x00000070U) /* !< 896.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_904 ((uint16_t)0x00000071U) /* !< 904.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_912 ((uint16_t)0x00000072U) /* !< 912.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_920 ((uint16_t)0x00000073U) /* !< 920.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_928 ((uint16_t)0x00000074U) /* !< 928.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_936 ((uint16_t)0x00000075U) /* !< 936.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_944 ((uint16_t)0x00000076U) /* !< 944.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_952 ((uint16_t)0x00000077U) /* !< 952.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_960 ((uint16_t)0x00000078U) /* !< 960.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_968 ((uint16_t)0x00000079U) /* !< 968.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_976 ((uint16_t)0x0000007AU) /* !< 976.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_984 ((uint16_t)0x0000007BU) /* !< 984.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_992 ((uint16_t)0x0000007CU) /* !< 992.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1000 ((uint16_t)0x0000007DU) /* !< 1000.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1008 ((uint16_t)0x0000007EU) /* !< 1008.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1016 ((uint16_t)0x0000007FU) /* !< 1016.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1024 ((uint16_t)0x00000080U) /* !< 1024.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1032 ((uint16_t)0x00000081U) /* !< 1032.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1040 ((uint16_t)0x00000082U) /* !< 1040.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1048 ((uint16_t)0x00000083U) /* !< 1048.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1056 ((uint16_t)0x00000084U) /* !< 1056.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1064 ((uint16_t)0x00000085U) /* !< 1064.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1072 ((uint16_t)0x00000086U) /* !< 1072.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1080 ((uint16_t)0x00000087U) /* !< 1080.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1088 ((uint16_t)0x00000088U) /* !< 1088.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1096 ((uint16_t)0x00000089U) /* !< 1096.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1104 ((uint16_t)0x0000008AU) /* !< 1104.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1112 ((uint16_t)0x0000008BU) /* !< 1112.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1120 ((uint16_t)0x0000008CU) /* !< 1120.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1128 ((uint16_t)0x0000008DU) /* !< 1128.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1136 ((uint16_t)0x0000008EU) /* !< 1136.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1144 ((uint16_t)0x0000008FU) /* !< 1144.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1152 ((uint16_t)0x00000090U) /* !< 1152.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1160 ((uint16_t)0x00000091U) /* !< 1160.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1168 ((uint16_t)0x00000092U) /* !< 1168.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1176 ((uint16_t)0x00000093U) /* !< 1176.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1184 ((uint16_t)0x00000094U) /* !< 1184.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1192 ((uint16_t)0x00000095U) /* !< 1192.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1200 ((uint16_t)0x00000096U) /* !< 1200.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1208 ((uint16_t)0x00000097U) /* !< 1208.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1216 ((uint16_t)0x00000098U) /* !< 1216.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1224 ((uint16_t)0x00000099U) /* !< 1224.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1232 ((uint16_t)0x0000009AU) /* !< 1232.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1240 ((uint16_t)0x0000009BU) /* !< 1240.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1248 ((uint16_t)0x0000009CU) /* !< 1248.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1256 ((uint16_t)0x0000009DU) /* !< 1256.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1264 ((uint16_t)0x0000009EU) /* !< 1264.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1272 ((uint16_t)0x0000009FU) /* !< 1272.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1280 ((uint16_t)0x000000A0U) /* !< 1280.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1288 ((uint16_t)0x000000A1U) /* !< 1288.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1296 ((uint16_t)0x000000A2U) /* !< 1296.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1304 ((uint16_t)0x000000A3U) /* !< 1304.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1312 ((uint16_t)0x000000A4U) /* !< 1312.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1320 ((uint16_t)0x000000A5U) /* !< 1320.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1328 ((uint16_t)0x000000A6U) /* !< 1328.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1336 ((uint16_t)0x000000A7U) /* !< 1336.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1344 ((uint16_t)0x000000A8U) /* !< 1344.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1352 ((uint16_t)0x000000A9U) /* !< 1352.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1360 ((uint16_t)0x000000AAU) /* !< 1360.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1368 ((uint16_t)0x000000ABU) /* !< 1368.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1376 ((uint16_t)0x000000ACU) /* !< 1376.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1384 ((uint16_t)0x000000ADU) /* !< 1384.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1392 ((uint16_t)0x000000AEU) /* !< 1392.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1400 ((uint16_t)0x000000AFU) /* !< 1400.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1408 ((uint16_t)0x000000B0U) /* !< 1408.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1416 ((uint16_t)0x000000B1U) /* !< 1416.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1424 ((uint16_t)0x000000B2U) /* !< 1424.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1432 ((uint16_t)0x000000B3U) /* !< 1432.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1440 ((uint16_t)0x000000B4U) /* !< 1440.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1448 ((uint16_t)0x000000B5U) /* !< 1448.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1456 ((uint16_t)0x000000B6U) /* !< 1456.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1464 ((uint16_t)0x000000B7U) /* !< 1464.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1472 ((uint16_t)0x000000B8U) /* !< 1472.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1480 ((uint16_t)0x000000B9U) /* !< 1480.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1488 ((uint16_t)0x000000BAU) /* !< 1488.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1496 ((uint16_t)0x000000BBU) /* !< 1496.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1504 ((uint16_t)0x000000BCU) /* !< 1504.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1512 ((uint16_t)0x000000BDU) /* !< 1512.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1520 ((uint16_t)0x000000BEU) /* !< 1520.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1528 ((uint16_t)0x000000BFU) /* !< 1528.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1536 ((uint16_t)0x000000C0U) /* !< 1536.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1544 ((uint16_t)0x000000C1U) /* !< 1544.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1552 ((uint16_t)0x000000C2U) /* !< 1552.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1560 ((uint16_t)0x000000C3U) /* !< 1560.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1568 ((uint16_t)0x000000C4U) /* !< 1568.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1576 ((uint16_t)0x000000C5U) /* !< 1576.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1584 ((uint16_t)0x000000C6U) /* !< 1584.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1592 ((uint16_t)0x000000C7U) /* !< 1592.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1600 ((uint16_t)0x000000C8U) /* !< 1600.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1608 ((uint16_t)0x000000C9U) /* !< 1608.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1616 ((uint16_t)0x000000CAU) /* !< 1616.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1624 ((uint16_t)0x000000CBU) /* !< 1624.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1632 ((uint16_t)0x000000CCU) /* !< 1632.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1640 ((uint16_t)0x000000CDU) /* !< 1640.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1648 ((uint16_t)0x000000CEU) /* !< 1648.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1656 ((uint16_t)0x000000CFU) /* !< 1656.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1664 ((uint16_t)0x000000D0U) /* !< 1664.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1672 ((uint16_t)0x000000D1U) /* !< 1672.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1680 ((uint16_t)0x000000D2U) /* !< 1680.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1688 ((uint16_t)0x000000D3U) /* !< 1688.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1696 ((uint16_t)0x000000D4U) /* !< 1696.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1704 ((uint16_t)0x000000D5U) /* !< 1704.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1712 ((uint16_t)0x000000D6U) /* !< 1712.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1720 ((uint16_t)0x000000D7U) /* !< 1720.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1728 ((uint16_t)0x000000D8U) /* !< 1728.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1736 ((uint16_t)0x000000D9U) /* !< 1736.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1744 ((uint16_t)0x000000DAU) /* !< 1744.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1752 ((uint16_t)0x000000DBU) /* !< 1752.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1760 ((uint16_t)0x000000DCU) /* !< 1760.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1768 ((uint16_t)0x000000DDU) /* !< 1768.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1776 ((uint16_t)0x000000DEU) /* !< 1776.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1784 ((uint16_t)0x000000DFU) /* !< 1784.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1792 ((uint16_t)0x000000E0U) /* !< 1792.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1800 ((uint16_t)0x000000E1U) /* !< 1800.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1808 ((uint16_t)0x000000E2U) /* !< 1808.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1816 ((uint16_t)0x000000E3U) /* !< 1816.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1824 ((uint16_t)0x000000E4U) /* !< 1824.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1832 ((uint16_t)0x000000E5U) /* !< 1832.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1840 ((uint16_t)0x000000E6U) /* !< 1840.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1848 ((uint16_t)0x000000E7U) /* !< 1848.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1856 ((uint16_t)0x000000E8U) /* !< 1856.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1864 ((uint16_t)0x000000E9U) /* !< 1864.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1872 ((uint16_t)0x000000EAU) /* !< 1872.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1880 ((uint16_t)0x000000EBU) /* !< 1880.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1888 ((uint16_t)0x000000ECU) /* !< 1888.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1896 ((uint16_t)0x000000EDU) /* !< 1896.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1904 ((uint16_t)0x000000EEU) /* !< 1904.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1912 ((uint16_t)0x000000EFU) /* !< 1912.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1920 ((uint16_t)0x000000F0U) /* !< 1920.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1928 ((uint16_t)0x000000F1U) /* !< 1928.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1936 ((uint16_t)0x000000F2U) /* !< 1936.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1944 ((uint16_t)0x000000F3U) /* !< 1944.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1952 ((uint16_t)0x000000F4U) /* !< 1952.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1960 ((uint16_t)0x000000F5U) /* !< 1960.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1968 ((uint16_t)0x000000F6U) /* !< 1968.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1976 ((uint16_t)0x000000F7U) /* !< 1976.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1984 ((uint16_t)0x000000F8U) /* !< 1984.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_1992 ((uint16_t)0x000000F9U) /* !< 1992.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_2000 ((uint16_t)0x000000FAU) /* !< 2000.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_2008 ((uint16_t)0x000000FBU) /* !< 2008.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_2016 ((uint16_t)0x000000FCU) /* !< 2016.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_2024 ((uint16_t)0x000000FDU) /* !< 2024.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_2032 ((uint16_t)0x000000FEU) /* !< 2032.0 */ +#define USB_IDXTXFIFOADD_ADDR_ADDR_2040 ((uint16_t)0x000000FFU) /* !< 2040.0 */ + +/* USB_IDXRXFIFOADD Bits */ +/* USB_IDXRXFIFOADD[ADDR] Bits */ +#define USB_IDXRXFIFOADD_ADDR_OFS (0) /* !< ADDR Offset */ +#define USB_IDXRXFIFOADD_ADDR_MASK ((uint16_t)0x00003FFFU) /* !< Endpoint Data */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_0 ((uint16_t)0x00000000U) /* !< 0.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_8 ((uint16_t)0x00000001U) /* !< 8.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_16 ((uint16_t)0x00000002U) /* !< 16.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_24 ((uint16_t)0x00000003U) /* !< 24.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_32 ((uint16_t)0x00000004U) /* !< 32.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_40 ((uint16_t)0x00000005U) /* !< 40.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_48 ((uint16_t)0x00000006U) /* !< 48.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_56 ((uint16_t)0x00000007U) /* !< 56.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_64 ((uint16_t)0x00000008U) /* !< 64.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_72 ((uint16_t)0x00000009U) /* !< 72.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_80 ((uint16_t)0x0000000AU) /* !< 80.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_88 ((uint16_t)0x0000000BU) /* !< 88.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_96 ((uint16_t)0x0000000CU) /* !< 96.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_104 ((uint16_t)0x0000000DU) /* !< 104.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_112 ((uint16_t)0x0000000EU) /* !< 112.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_120 ((uint16_t)0x0000000FU) /* !< 120.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_128 ((uint16_t)0x00000010U) /* !< 128.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_136 ((uint16_t)0x00000011U) /* !< 136.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_144 ((uint16_t)0x00000012U) /* !< 144.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_152 ((uint16_t)0x00000013U) /* !< 152.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_160 ((uint16_t)0x00000014U) /* !< 160.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_168 ((uint16_t)0x00000015U) /* !< 168.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_176 ((uint16_t)0x00000016U) /* !< 176.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_184 ((uint16_t)0x00000017U) /* !< 184.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_192 ((uint16_t)0x00000018U) /* !< 192.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_200 ((uint16_t)0x00000019U) /* !< 200.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_208 ((uint16_t)0x0000001AU) /* !< 208.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_216 ((uint16_t)0x0000001BU) /* !< 216.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_224 ((uint16_t)0x0000001CU) /* !< 224.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_232 ((uint16_t)0x0000001DU) /* !< 232.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_240 ((uint16_t)0x0000001EU) /* !< 240.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_248 ((uint16_t)0x0000001FU) /* !< 248.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_256 ((uint16_t)0x00000020U) /* !< 256.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_264 ((uint16_t)0x00000021U) /* !< 264.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_272 ((uint16_t)0x00000022U) /* !< 272.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_280 ((uint16_t)0x00000023U) /* !< 280.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_288 ((uint16_t)0x00000024U) /* !< 288.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_296 ((uint16_t)0x00000025U) /* !< 296.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_304 ((uint16_t)0x00000026U) /* !< 304.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_312 ((uint16_t)0x00000027U) /* !< 312.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_320 ((uint16_t)0x00000028U) /* !< 320.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_328 ((uint16_t)0x00000029U) /* !< 328.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_336 ((uint16_t)0x0000002AU) /* !< 336.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_344 ((uint16_t)0x0000002BU) /* !< 344.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_352 ((uint16_t)0x0000002CU) /* !< 352.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_360 ((uint16_t)0x0000002DU) /* !< 360.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_368 ((uint16_t)0x0000002EU) /* !< 368.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_376 ((uint16_t)0x0000002FU) /* !< 376.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_384 ((uint16_t)0x00000030U) /* !< 384.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_392 ((uint16_t)0x00000031U) /* !< 392.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_400 ((uint16_t)0x00000032U) /* !< 400.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_408 ((uint16_t)0x00000033U) /* !< 408.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_416 ((uint16_t)0x00000034U) /* !< 416.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_424 ((uint16_t)0x00000035U) /* !< 424.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_432 ((uint16_t)0x00000036U) /* !< 432.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_440 ((uint16_t)0x00000037U) /* !< 440.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_448 ((uint16_t)0x00000038U) /* !< 448.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_456 ((uint16_t)0x00000039U) /* !< 456.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_464 ((uint16_t)0x0000003AU) /* !< 464.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_472 ((uint16_t)0x0000003BU) /* !< 472.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_480 ((uint16_t)0x0000003CU) /* !< 480.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_488 ((uint16_t)0x0000003DU) /* !< 488.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_496 ((uint16_t)0x0000003EU) /* !< 496.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_504 ((uint16_t)0x0000003FU) /* !< 504.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_512 ((uint16_t)0x00000040U) /* !< 512.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_520 ((uint16_t)0x00000041U) /* !< 520.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_528 ((uint16_t)0x00000042U) /* !< 528.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_536 ((uint16_t)0x00000043U) /* !< 536.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_544 ((uint16_t)0x00000044U) /* !< 544.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_552 ((uint16_t)0x00000045U) /* !< 552.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_560 ((uint16_t)0x00000046U) /* !< 560.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_568 ((uint16_t)0x00000047U) /* !< 568.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_576 ((uint16_t)0x00000048U) /* !< 576.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_584 ((uint16_t)0x00000049U) /* !< 584.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_592 ((uint16_t)0x0000004AU) /* !< 592.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_600 ((uint16_t)0x0000004BU) /* !< 600.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_608 ((uint16_t)0x0000004CU) /* !< 608.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_616 ((uint16_t)0x0000004DU) /* !< 616.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_624 ((uint16_t)0x0000004EU) /* !< 624.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_632 ((uint16_t)0x0000004FU) /* !< 632.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_640 ((uint16_t)0x00000050U) /* !< 640.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_648 ((uint16_t)0x00000051U) /* !< 648.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_656 ((uint16_t)0x00000052U) /* !< 656.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_664 ((uint16_t)0x00000053U) /* !< 664.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_672 ((uint16_t)0x00000054U) /* !< 672.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_680 ((uint16_t)0x00000055U) /* !< 680.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_688 ((uint16_t)0x00000056U) /* !< 688.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_696 ((uint16_t)0x00000057U) /* !< 696.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_704 ((uint16_t)0x00000058U) /* !< 704.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_712 ((uint16_t)0x00000059U) /* !< 712.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_720 ((uint16_t)0x0000005AU) /* !< 720.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_728 ((uint16_t)0x0000005BU) /* !< 728.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_736 ((uint16_t)0x0000005CU) /* !< 736.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_744 ((uint16_t)0x0000005DU) /* !< 744.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_752 ((uint16_t)0x0000005EU) /* !< 752.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_760 ((uint16_t)0x0000005FU) /* !< 760.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_768 ((uint16_t)0x00000060U) /* !< 768.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_776 ((uint16_t)0x00000061U) /* !< 776.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_784 ((uint16_t)0x00000062U) /* !< 784.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_792 ((uint16_t)0x00000063U) /* !< 792.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_800 ((uint16_t)0x00000064U) /* !< 800.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_808 ((uint16_t)0x00000065U) /* !< 808.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_816 ((uint16_t)0x00000066U) /* !< 816.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_824 ((uint16_t)0x00000067U) /* !< 824.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_832 ((uint16_t)0x00000068U) /* !< 832.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_840 ((uint16_t)0x00000069U) /* !< 840.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_848 ((uint16_t)0x0000006AU) /* !< 848.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_856 ((uint16_t)0x0000006BU) /* !< 856.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_864 ((uint16_t)0x0000006CU) /* !< 864.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_872 ((uint16_t)0x0000006DU) /* !< 872.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_880 ((uint16_t)0x0000006EU) /* !< 880.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_888 ((uint16_t)0x0000006FU) /* !< 888.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_896 ((uint16_t)0x00000070U) /* !< 896.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_904 ((uint16_t)0x00000071U) /* !< 904.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_912 ((uint16_t)0x00000072U) /* !< 912.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_920 ((uint16_t)0x00000073U) /* !< 920.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_928 ((uint16_t)0x00000074U) /* !< 928.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_936 ((uint16_t)0x00000075U) /* !< 936.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_944 ((uint16_t)0x00000076U) /* !< 944.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_952 ((uint16_t)0x00000077U) /* !< 952.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_960 ((uint16_t)0x00000078U) /* !< 960.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_968 ((uint16_t)0x00000079U) /* !< 968.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_976 ((uint16_t)0x0000007AU) /* !< 976.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_984 ((uint16_t)0x0000007BU) /* !< 984.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_992 ((uint16_t)0x0000007CU) /* !< 992.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1000 ((uint16_t)0x0000007DU) /* !< 1000.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1008 ((uint16_t)0x0000007EU) /* !< 1008.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1016 ((uint16_t)0x0000007FU) /* !< 1016.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1024 ((uint16_t)0x00000080U) /* !< 1024.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1032 ((uint16_t)0x00000081U) /* !< 1032.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1040 ((uint16_t)0x00000082U) /* !< 1040.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1048 ((uint16_t)0x00000083U) /* !< 1048.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1056 ((uint16_t)0x00000084U) /* !< 1056.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1064 ((uint16_t)0x00000085U) /* !< 1064.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1072 ((uint16_t)0x00000086U) /* !< 1072.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1080 ((uint16_t)0x00000087U) /* !< 1080.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1088 ((uint16_t)0x00000088U) /* !< 1088.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1096 ((uint16_t)0x00000089U) /* !< 1096.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1104 ((uint16_t)0x0000008AU) /* !< 1104.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1112 ((uint16_t)0x0000008BU) /* !< 1112.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1120 ((uint16_t)0x0000008CU) /* !< 1120.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1128 ((uint16_t)0x0000008DU) /* !< 1128.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1136 ((uint16_t)0x0000008EU) /* !< 1136.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1144 ((uint16_t)0x0000008FU) /* !< 1144.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1152 ((uint16_t)0x00000090U) /* !< 1152.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1160 ((uint16_t)0x00000091U) /* !< 1160.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1168 ((uint16_t)0x00000092U) /* !< 1168.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1176 ((uint16_t)0x00000093U) /* !< 1176.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1184 ((uint16_t)0x00000094U) /* !< 1184.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1192 ((uint16_t)0x00000095U) /* !< 1192.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1200 ((uint16_t)0x00000096U) /* !< 1200.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1208 ((uint16_t)0x00000097U) /* !< 1208.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1216 ((uint16_t)0x00000098U) /* !< 1216.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1224 ((uint16_t)0x00000099U) /* !< 1224.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1232 ((uint16_t)0x0000009AU) /* !< 1232.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1240 ((uint16_t)0x0000009BU) /* !< 1240.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1248 ((uint16_t)0x0000009CU) /* !< 1248.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1256 ((uint16_t)0x0000009DU) /* !< 1256.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1264 ((uint16_t)0x0000009EU) /* !< 1264.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1272 ((uint16_t)0x0000009FU) /* !< 1272.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1280 ((uint16_t)0x000000A0U) /* !< 1280.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1288 ((uint16_t)0x000000A1U) /* !< 1288.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1296 ((uint16_t)0x000000A2U) /* !< 1296.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1304 ((uint16_t)0x000000A3U) /* !< 1304.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1312 ((uint16_t)0x000000A4U) /* !< 1312.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1320 ((uint16_t)0x000000A5U) /* !< 1320.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1328 ((uint16_t)0x000000A6U) /* !< 1328.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1336 ((uint16_t)0x000000A7U) /* !< 1336.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1344 ((uint16_t)0x000000A8U) /* !< 1344.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1352 ((uint16_t)0x000000A9U) /* !< 1352.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1360 ((uint16_t)0x000000AAU) /* !< 1360.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1368 ((uint16_t)0x000000ABU) /* !< 1368.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1376 ((uint16_t)0x000000ACU) /* !< 1376.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1384 ((uint16_t)0x000000ADU) /* !< 1384.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1392 ((uint16_t)0x000000AEU) /* !< 1392.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1400 ((uint16_t)0x000000AFU) /* !< 1400.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1408 ((uint16_t)0x000000B0U) /* !< 1408.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1416 ((uint16_t)0x000000B1U) /* !< 1416.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1424 ((uint16_t)0x000000B2U) /* !< 1424.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1432 ((uint16_t)0x000000B3U) /* !< 1432.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1440 ((uint16_t)0x000000B4U) /* !< 1440.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1448 ((uint16_t)0x000000B5U) /* !< 1448.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1456 ((uint16_t)0x000000B6U) /* !< 1456.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1464 ((uint16_t)0x000000B7U) /* !< 1464.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1472 ((uint16_t)0x000000B8U) /* !< 1472.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1480 ((uint16_t)0x000000B9U) /* !< 1480.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1488 ((uint16_t)0x000000BAU) /* !< 1488.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1496 ((uint16_t)0x000000BBU) /* !< 1496.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1504 ((uint16_t)0x000000BCU) /* !< 1504.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1512 ((uint16_t)0x000000BDU) /* !< 1512.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1520 ((uint16_t)0x000000BEU) /* !< 1520.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1528 ((uint16_t)0x000000BFU) /* !< 1528.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1536 ((uint16_t)0x000000C0U) /* !< 1536.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1544 ((uint16_t)0x000000C1U) /* !< 1544.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1552 ((uint16_t)0x000000C2U) /* !< 1552.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1560 ((uint16_t)0x000000C3U) /* !< 1560.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1568 ((uint16_t)0x000000C4U) /* !< 1568.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1576 ((uint16_t)0x000000C5U) /* !< 1576.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1584 ((uint16_t)0x000000C6U) /* !< 1584.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1592 ((uint16_t)0x000000C7U) /* !< 1592.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1600 ((uint16_t)0x000000C8U) /* !< 1600.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1608 ((uint16_t)0x000000C9U) /* !< 1608.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1616 ((uint16_t)0x000000CAU) /* !< 1616.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1624 ((uint16_t)0x000000CBU) /* !< 1624.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1632 ((uint16_t)0x000000CCU) /* !< 1632.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1640 ((uint16_t)0x000000CDU) /* !< 1640.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1648 ((uint16_t)0x000000CEU) /* !< 1648.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1656 ((uint16_t)0x000000CFU) /* !< 1656.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1664 ((uint16_t)0x000000D0U) /* !< 1664.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1672 ((uint16_t)0x000000D1U) /* !< 1672.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1680 ((uint16_t)0x000000D2U) /* !< 1680.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1688 ((uint16_t)0x000000D3U) /* !< 1688.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1696 ((uint16_t)0x000000D4U) /* !< 1696.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1704 ((uint16_t)0x000000D5U) /* !< 1704.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1712 ((uint16_t)0x000000D6U) /* !< 1712.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1720 ((uint16_t)0x000000D7U) /* !< 1720.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1728 ((uint16_t)0x000000D8U) /* !< 1728.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1736 ((uint16_t)0x000000D9U) /* !< 1736.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1744 ((uint16_t)0x000000DAU) /* !< 1744.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1752 ((uint16_t)0x000000DBU) /* !< 1752.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1760 ((uint16_t)0x000000DCU) /* !< 1760.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1768 ((uint16_t)0x000000DDU) /* !< 1768.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1776 ((uint16_t)0x000000DEU) /* !< 1776.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1784 ((uint16_t)0x000000DFU) /* !< 1784.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1792 ((uint16_t)0x000000E0U) /* !< 1792.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1800 ((uint16_t)0x000000E1U) /* !< 1800.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1808 ((uint16_t)0x000000E2U) /* !< 1808.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1816 ((uint16_t)0x000000E3U) /* !< 1816.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1824 ((uint16_t)0x000000E4U) /* !< 1824.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1832 ((uint16_t)0x000000E5U) /* !< 1832.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1840 ((uint16_t)0x000000E6U) /* !< 1840.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1848 ((uint16_t)0x000000E7U) /* !< 1848.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1856 ((uint16_t)0x000000E8U) /* !< 1856.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1864 ((uint16_t)0x000000E9U) /* !< 1864.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1872 ((uint16_t)0x000000EAU) /* !< 1872.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1880 ((uint16_t)0x000000EBU) /* !< 1880.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1888 ((uint16_t)0x000000ECU) /* !< 1888.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1896 ((uint16_t)0x000000EDU) /* !< 1896.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1904 ((uint16_t)0x000000EEU) /* !< 1904.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1912 ((uint16_t)0x000000EFU) /* !< 1912.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1920 ((uint16_t)0x000000F0U) /* !< 1920.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1928 ((uint16_t)0x000000F1U) /* !< 1928.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1936 ((uint16_t)0x000000F2U) /* !< 1936.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1944 ((uint16_t)0x000000F3U) /* !< 1944.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1952 ((uint16_t)0x000000F4U) /* !< 1952.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1960 ((uint16_t)0x000000F5U) /* !< 1960.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1968 ((uint16_t)0x000000F6U) /* !< 1968.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1976 ((uint16_t)0x000000F7U) /* !< 1976.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1984 ((uint16_t)0x000000F8U) /* !< 1984.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_1992 ((uint16_t)0x000000F9U) /* !< 1992.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_2000 ((uint16_t)0x000000FAU) /* !< 2000.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_2008 ((uint16_t)0x000000FBU) /* !< 2008.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_2016 ((uint16_t)0x000000FCU) /* !< 2016.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_2024 ((uint16_t)0x000000FDU) /* !< 2024.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_2032 ((uint16_t)0x000000FEU) /* !< 2032.0 */ +#define USB_IDXRXFIFOADD_ADDR_ADDR_2040 ((uint16_t)0x000000FFU) /* !< 2040.0 */ + +/* USB_EPINFO Bits */ +/* USB_EPINFO[TXENDPOINTS] Bits */ +#define USB_EPINFO_TXENDPOINTS_OFS (0) /* !< TXENDPOINTS Offset */ +#define USB_EPINFO_TXENDPOINTS_MASK ((uint8_t)0x0000000FU) /* !< The number of TX endpoints + implemented in the design. */ +/* USB_EPINFO[RXENDPOINTS] Bits */ +#define USB_EPINFO_RXENDPOINTS_OFS (4) /* !< RXENDPOINTS Offset */ +#define USB_EPINFO_RXENDPOINTS_MASK ((uint8_t)0x000000F0U) /* !< The number of Rx endpoints + implemented in the design. */ + +/* USB_RAMINFO Bits */ +/* USB_RAMINFO[RAMBITS] Bits */ +#define USB_RAMINFO_RAMBITS_OFS (0) /* !< RAMBITS Offset */ +#define USB_RAMINFO_RAMBITS_MASK ((uint8_t)0x0000000FU) /* !< The width of the RAM address bus. */ +#define USB_RAMINFO_RAMBITS_RAM_1KB ((uint8_t)0x00000008U) /* !< USB FIFO RAM size is 1kB */ +#define USB_RAMINFO_RAMBITS_RAM_2KB ((uint8_t)0x00000009U) /* !< USB FIFO RAM size is 2kB */ +#define USB_RAMINFO_RAMBITS_RAM_4KB ((uint8_t)0x0000000AU) /* !< USB FIFO RAM size is 4kB */ + +/* USB_CONTIM Bits */ +/* USB_CONTIM[WTID] Bits */ +#define USB_CONTIM_WTID_OFS (0) /* !< WTID Offset */ +#define USB_CONTIM_WTID_MASK ((uint8_t)0x0000000FU) /* !< The wait ID field configures the + delay required from the enable of the + ID detection to when the ID value is + valid, in units of 4.369 ms. Note: + The default corresponds to 52.43 ms. */ +/* USB_CONTIM[WTCON] Bits */ +#define USB_CONTIM_WTCON_OFS (4) /* !< WTCON Offset */ +#define USB_CONTIM_WTCON_MASK ((uint8_t)0x000000F0U) /* !< The connect wait field configures + the wait required to allow for the + user's connect/disconnect filter, in + units of 533.3 ns. Note: The default + corresponds to 2.667 us. */ + +/* USB_FSEOF Bits */ +/* USB_FSEOF[FSEOFG] Bits */ +#define USB_FSEOF_FSEOFG_OFS (0) /* !< FSEOFG Offset */ +#define USB_FSEOF_FSEOFG_MASK ((uint8_t)0x000000FFU) /* !< The full-speed end-of-frame gap + field is used during full-speed + transactions to configure the gap + between the last transaction and the + End-of-Frame (EOF), in units of 533.3 + ns. Note: The default corresponds to + 63.46 us. */ + +/* USB_LSEOF Bits */ +/* USB_LSEOF[LSEOFG] Bits */ +#define USB_LSEOF_LSEOFG_OFS (0) /* !< LSEOFG Offset */ +#define USB_LSEOF_LSEOFG_MASK ((uint8_t)0x000000FFU) /* !< The low-speed end-of-frame gap + field is used during low-speed + transactions to set the gap between + the last transaction and the + End-of-Frame (EOF), in units of 1.067 + us. Note: The default corresponds to + 121.6 us. */ + +/* USB_CSR0L Bits */ +/* USB_CSR0L[RXRDY] Bits */ +#define USB_CSR0L_RXRDY_OFS (0) /* !< RXRDY Offset */ +#define USB_CSR0L_RXRDY_MASK ((uint8_t)0x00000001U) /* !< Receive Packet Ready. Device mode: + This bit is set when a data packet + has been received. An interrupt is + generated when this bit is set. The + CPU clears this bit by setting the + RXRDYC_STATUS bit. Host mode: + Software must clear this bit after he + packet has been read from the FIFO to + acknowledge that the data has been + read from the FIFO. */ +#define USB_CSR0L_RXRDY_NO_PACKET ((uint8_t)0x00000000U) /* !< No receive packet has been + received. */ +#define USB_CSR0L_RXRDY_RECV ((uint8_t)0x00000001U) /* !< Indicates that a data packet has + been received in the RX FIFO. The EP0 + bit in the USBTXIS register is also + set in this situation. */ +/* USB_CSR0L[TXRDY] Bits */ +#define USB_CSR0L_TXRDY_OFS (1) /* !< TXRDY Offset */ +#define USB_CSR0L_TXRDY_MASK ((uint8_t)0x00000002U) /* !< Transmit Packet Ready. Device & + Host mode: The CPU sets this bit + after loading a data packet into the + FIFO. It is cleared automatically + when a data packet has been + transmitted. An interrupt is also + generated at this point (if enabled). + Host mode: If both the TXRDY and + DATAEND_SETUP bits are set, a setup + packet is sent. If just TXRDY is set, + an OUT packet is sent. */ +#define USB_CSR0L_TXRDY_WAIT ((uint8_t)0x00000000U) /* !< No transmit packet is ready. */ +#define USB_CSR0L_TXRDY_READY ((uint8_t)0x00000002U) /* !< Software sets this bit after + loading a data packet into the TX + FIFO. The EP0 bit in the USBTXIS + register is also set in this + situation. */ +/* USB_CSR0L[STALLED] Bits */ +#define USB_CSR0L_STALLED_OFS (2) /* !< STALLED Offset */ +#define USB_CSR0L_STALLED_MASK ((uint8_t)0x00000004U) /* !< Sent Stall / Receive Stall Device + mode: This bit is set when a STALL + handshake is transmitted. The CPU + should clear this bit. Host mode: + This bit is set when a STALL + handshake is received. The CPU should + clear this bit. */ +#define USB_CSR0L_STALLED_NO_HANDSHAKE ((uint8_t)0x00000000U) /* !< No handshake has been received. */ +#define USB_CSR0L_STALLED_HANDSHAKE ((uint8_t)0x00000004U) /* !< A STALL handshake has been received + or transmitted */ +/* USB_CSR0L[DATAEND_SETUP] Bits */ +#define USB_CSR0L_DATAEND_SETUP_OFS (3) /* !< DATAEND_SETUP Offset */ +#define USB_CSR0L_DATAEND_SETUP_MASK ((uint8_t)0x00000008U) /* !< Data end / Setup Packet. Device + mode: Data end bit. The CPU sets this + bit: 1. When setting TXRDY for the + last data packet. 2. When clearing + RXRDY after unloading the last data + packet. 3. When setting TXRDY for a + zero length data packet. Host mode: + Setup packet. The CPU sets this bit, + at the same time as the TXRDY bit is + set, to send a SETUP token instead of + an OUT token for the transaction. + Note: Setting this bit always clears + the DT bit in the USBCSRH0 register. */ +#define USB_CSR0L_DATAEND_SETUP_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +/* USB_CSR0L[SETEND_ERROR] Bits */ +#define USB_CSR0L_SETEND_ERROR_OFS (4) /* !< SETEND_ERROR Offset */ +#define USB_CSR0L_SETEND_ERROR_MASK ((uint8_t)0x00000010U) /* !< Setup end / Error. Device mode: + Setup end. This bit will be set when + a control transaction ends before the + DATAEND_SETUP bit has been set. An + interrupt will be generated and the + FIFO flushed at this time. The bit is + cleared by the CPU writing a 1 to the + SETENDC_NAKTO bit. Host mode: Error + indication. This bit will be set when + three attempts have been made to + perform a transaction with no + response from the peripheral. The CPU + should clear this bit. An interrupt + is generated when this bit is set. */ +#define USB_CSR0L_SETEND_ERROR_NO_EFFECT ((uint8_t)0x00000000U) /* !< Clear Error. Note: Only effective + in host mode. */ +#define USB_CSR0L_SETEND_ERROR_EFFECT ((uint8_t)0x00000010U) /* !< Setup end / Error indication. */ +/* USB_CSR0L[STALL_RQPKT] Bits */ +#define USB_CSR0L_STALL_RQPKT_OFS (5) /* !< STALL_RQPKT Offset */ +#define USB_CSR0L_STALL_RQPKT_MASK ((uint8_t)0x00000020U) /* !< Send Stall / Request Packet. Device + mode: The CPU writes a 1 to this bit + to terminate the current transaction. + The STALL handshake will be + transmitted and then this bit will be + cleared automatically. Host mode: The + CPU sets this bit to request an IN + transaction. It is cleared when RXRDY + bit is set. */ +#define USB_CSR0L_STALL_RQPKT_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_CSR0L_STALL_RQPKT_EFFECT ((uint8_t)0x00000020U) /* !< Send stall request or request + packet is in effect. */ +/* USB_CSR0L[RXRDYC_STATUS] Bits */ +#define USB_CSR0L_RXRDYC_STATUS_OFS (6) /* !< RXRDYC_STATUS Offset */ +#define USB_CSR0L_RXRDYC_STATUS_MASK ((uint8_t)0x00000040U) /* !< Receive ready clear / Status packet + Device mode: Receive ready clear. The + CPU writes a 1 to this bit to clear + the RXRDY bit. It is cleared + automatically Host mode: Status + Packet. The CPU sets this bit at the + same time as the TXRDY or STALL_RQPKT + bit is set, to perform a status stage + transaction. Setting this bit ensures + that the DT bit is set in the + USBCSRH0 register, so that a DATA1 + packet is used for the Status Stage + transaction. Setting this bit + ensures that the DT bit is set in the + USBCSRH0 register so that a DATA1 + packet is used for the STATUS stage + transaction. */ +#define USB_CSR0L_RXRDYC_STATUS_NO_EFFECT ((uint8_t)0x00000000U) /* !< No transaction */ +#define USB_CSR0L_RXRDYC_STATUS_EFFECT ((uint8_t)0x00000040U) /* !< Clear RXRDY or sent status packet. */ +/* USB_CSR0L[SETENDC_NAKTO] Bits */ +#define USB_CSR0L_SETENDC_NAKTO_OFS (7) /* !< SETENDC_NAKTO Offset */ +#define USB_CSR0L_SETENDC_NAKTO_MASK ((uint8_t)0x00000080U) /* !< Setup End Clear / NAK Timeout + Device mode: The CPU writes a 1 to + this bit to clear the SETEND_ERROR + bit. It is cleared automatically. + Host mode: This bit will be set when + Endpoint 0 is halted following the + receipt of NAK responses for longer + than the time set by the USBNAKLMT + register. The CPU should clear this + bit to allow the endpoint to + continue. */ +#define USB_CSR0L_SETENDC_NAKTO_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_CSR0L_SETENDC_NAKTO_EFFECT ((uint8_t)0x00000080U) /* !< Clear SETEND_ERROR or SETENDC_KAKTO */ + +/* USB_CSR0H Bits */ +/* USB_CSR0H[FLUSH] Bits */ +#define USB_CSR0H_FLUSH_OFS (0) /* !< FLUSH Offset */ +#define USB_CSR0H_FLUSH_MASK ((uint8_t)0x00000001U) /* !< Flush FIFO. The CPU writes a 1 to + this bit to flush the next packet to + be transmitted/read from the Endpoint + 0 FIFO. The FIFO pointer is reset and + the TXRDY/RXRDY bit in the USBCSRL0 + register is cleared. Note: FLUSH + should only be used when TXRDY/RXRDY + is set. At other times, it may cause + data to be corrupted. */ +#define USB_CSR0H_FLUSH_NO_EFFECT ((uint8_t)0x00000000U) /* !< No effect */ +#define USB_CSR0H_FLUSH_EFFECT ((uint8_t)0x00000001U) /* !< Flush the FIFO */ +/* USB_CSR0H[DT] Bits */ +#define USB_CSR0H_DT_OFS (1) /* !< DT Offset */ +#define USB_CSR0H_DT_MASK ((uint8_t)0x00000002U) /* !< Data Toggle. When read, this bit + indicates the current state of the + endpoint 0 data toggle. If DTWE is + set, this bit may be written with the + required setting of the data toggle. + If DTWE is Low, this bit cannot be + written. Care should be taken when + writing to this bit as it should only + be changed to RESET USB endpoint 0. + Note: This bit is only effective in + host mode. */ +#define USB_CSR0H_DT_LOW ((uint8_t)0x00000000U) /* !< Data toggle is low */ +#define USB_CSR0H_DT_HIGH ((uint8_t)0x00000002U) /* !< Data toggle is high */ +/* USB_CSR0H[DTWE] Bits */ +#define USB_CSR0H_DTWE_OFS (2) /* !< DTWE Offset */ +#define USB_CSR0H_DTWE_MASK ((uint8_t)0x00000004U) /* !< Data Toggle Write Enable. This bit + is automatically cleared once the new + value is written. Note: This bit is + only effective in host mode. */ +#define USB_CSR0H_DTWE_DISABLE ((uint8_t)0x00000000U) /* !< The DT bit cannot be written. */ +#define USB_CSR0H_DTWE_ENABLE ((uint8_t)0x00000004U) /* !< Enables the current state of the + endpoint 0 data toggle to be written + (see DT bit). */ +/* USB_CSR0H[DISPING] Bits */ +#define USB_CSR0H_DISPING_OFS (3) /* !< DISPING Offset */ +#define USB_CSR0H_DISPING_MASK ((uint8_t)0x00000008U) /* !< Diable PING tokens in data and + status phases of a high-speed Control + transfer. */ +#define USB_CSR0H_DISPING_CLR ((uint8_t)0x00000000U) /* !< Ping is allowed. */ +#define USB_CSR0H_DISPING_SET ((uint8_t)0x00000008U) /* !< Ping is not allowed. */ + +/* USB_COUNT0 Bits */ +/* USB_COUNT0[COUNT] Bits */ +#define USB_COUNT0_COUNT_OFS (0) /* !< COUNT Offset */ +#define USB_COUNT0_COUNT_MASK ((uint8_t)0x0000007FU) /* !< FIFO Count. COUNT is a read-only + value that indicates the number of + received data bytes in the endpoint 0 + FIFO. The value returned changes as + the contents of the FIFO change and + is only valid while RXRDY + (USBCSRL.RXRDY) is set. */ + +/* USB_TYPE0 Bits */ +/* USB_TYPE0[SPEED] Bits */ +#define USB_TYPE0_SPEED_OFS (6) /* !< SPEED Offset */ +#define USB_TYPE0_SPEED_MASK ((uint8_t)0x000000C0U) /* !< Operating Speed specifies the + operating speed of the target Device. + If selected, the target is assumed + #br#to have the same connection speed + as the USB controller. */ +#define USB_TYPE0_SPEED_UNUSED ((uint8_t)0x00000000U) /* !< Unused (Note: If selected, the + target will be assumed to be using + the same connection speed as the USB + controller.) */ +#define USB_TYPE0_SPEED_FULL ((uint8_t)0x00000080U) /* !< Full-speed */ +#define USB_TYPE0_SPEED_LOW ((uint8_t)0x000000C0U) /* !< Low-speed */ + +/* USB_NAKLMT0 Bits */ +/* USB_NAKLMT0[NAKLMT] Bits */ +#define USB_NAKLMT0_NAKLMT_OFS (0) /* !< NAKLMT Offset */ +#define USB_NAKLMT0_NAKLMT_MASK ((uint8_t)0x0000001FU) /* !< EP0 NAK Limit specifies the number + of frames after receiving a stream of + NAK responses. */ + +/* USB_CONFIG Bits */ +/* USB_CONFIG[UTMIDATWDTH] Bits */ +#define USB_CONFIG_UTMIDATWDTH_OFS (0) /* !< UTMIDATWDTH Offset */ +#define USB_CONFIG_UTMIDATWDTH_MASK ((uint8_t)0x00000001U) /* !< Indicates selected UTMI+ data + width. Always 0 indicating 8 bits. */ +/* USB_CONFIG[SOFTCON] Bits */ +#define USB_CONFIG_SOFTCON_OFS (1) /* !< SOFTCON Offset */ +#define USB_CONFIG_SOFTCON_MASK ((uint8_t)0x00000002U) /* !< Always 1 . Indicates Soft + Connect/Disconnect is enabled. */ +/* USB_CONFIG[DYNFIFO] Bits */ +#define USB_CONFIG_DYNFIFO_OFS (2) /* !< DYNFIFO Offset */ +#define USB_CONFIG_DYNFIFO_MASK ((uint8_t)0x00000004U) /* !< When set to 1 indicates Dynamic + FIFO Sizing option selected. */ +/* USB_CONFIG[HBTXE] Bits */ +#define USB_CONFIG_HBTXE_OFS (3) /* !< HBTXE Offset */ +#define USB_CONFIG_HBTXE_MASK ((uint8_t)0x00000008U) /* !< When set to 1 indicates + High-bandwidth TX ISO Endpoint + Support selected. */ +/* USB_CONFIG[HBRXE] Bits */ +#define USB_CONFIG_HBRXE_OFS (4) /* !< HBRXE Offset */ +#define USB_CONFIG_HBRXE_MASK ((uint8_t)0x00000010U) /* !< When set to 1 indicates + High-bandwidth Rx ISO Endpoint + Support selected. */ +/* USB_CONFIG[BIGENDIAN] Bits */ +#define USB_CONFIG_BIGENDIAN_OFS (5) /* !< BIGENDIAN Offset */ +#define USB_CONFIG_BIGENDIAN_MASK ((uint8_t)0x00000020U) /* !< Always '0'. Indicates Little Endian + ordering. */ +/* USB_CONFIG[MPTXE] Bits */ +#define USB_CONFIG_MPTXE_OFS (6) /* !< MPTXE Offset */ +#define USB_CONFIG_MPTXE_MASK ((uint8_t)0x00000040U) /* !< When set to 1, automatic splitting + of bulk packets is selected. */ +/* USB_CONFIG[MPRXE] Bits */ +#define USB_CONFIG_MPRXE_OFS (7) /* !< MPRXE Offset */ +#define USB_CONFIG_MPRXE_MASK ((uint8_t)0x00000080U) /* !< When set to 1, automatic + amalgamation of bulk packets is + selected. */ + +/* USB_RQPKTCOUNT Bits */ +/* USB_RQPKTCOUNT[COUNT] Bits */ +#define USB_RQPKTCOUNT_COUNT_OFS (0) /* !< COUNT Offset */ +#define USB_RQPKTCOUNT_COUNT_MASK ((uint32_t)0x0000FFFFU) /* !< Block Transfer Packet Count sets + the number of packets of the size + defined by the MAXLOAD bit field that + are to be transferred in a block + transfer. Note: This is only used in + Host mode when AUTORQ is set. The bit + has no effect in Device mode or when + AUTORQ is not set. */ + +/* USB_RXDPKTBUFDIS Bits */ +/* USB_RXDPKTBUFDIS[EP1] Bits */ +#define USB_RXDPKTBUFDIS_EP1_OFS (1) /* !< EP1 Offset */ +#define USB_RXDPKTBUFDIS_EP1_MASK ((uint16_t)0x00000002U) /* !< EP1 RX Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS_EP1_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_RXDPKTBUFDIS_EP1_ENABLE ((uint16_t)0x00000002U) /* !< Enables double-packet buffering. */ +/* USB_RXDPKTBUFDIS[EP2] Bits */ +#define USB_RXDPKTBUFDIS_EP2_OFS (2) /* !< EP2 Offset */ +#define USB_RXDPKTBUFDIS_EP2_MASK ((uint16_t)0x00000004U) /* !< EP2 RX Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS_EP2_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_RXDPKTBUFDIS_EP2_ENABLE ((uint16_t)0x00000004U) /* !< Enables double-packet buffering. */ +/* USB_RXDPKTBUFDIS[EP3] Bits */ +#define USB_RXDPKTBUFDIS_EP3_OFS (3) /* !< EP3 Offset */ +#define USB_RXDPKTBUFDIS_EP3_MASK ((uint16_t)0x00000008U) /* !< EP3 RX Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS_EP3_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_RXDPKTBUFDIS_EP3_ENABLE ((uint16_t)0x00000008U) /* !< Enables double-packet buffering. */ +/* USB_RXDPKTBUFDIS[EP4] Bits */ +#define USB_RXDPKTBUFDIS_EP4_OFS (4) /* !< EP4 Offset */ +#define USB_RXDPKTBUFDIS_EP4_MASK ((uint16_t)0x00000010U) /* !< EP4 RX Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS_EP4_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_RXDPKTBUFDIS_EP4_ENABLE ((uint16_t)0x00000010U) /* !< Enables double-packet buffering. */ +/* USB_RXDPKTBUFDIS[EP5] Bits */ +#define USB_RXDPKTBUFDIS_EP5_OFS (5) /* !< EP5 Offset */ +#define USB_RXDPKTBUFDIS_EP5_MASK ((uint16_t)0x00000020U) /* !< EP5 RX Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS_EP5_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_RXDPKTBUFDIS_EP5_ENABLE ((uint16_t)0x00000020U) /* !< Enables double-packet buffering. */ +/* USB_RXDPKTBUFDIS[EP6] Bits */ +#define USB_RXDPKTBUFDIS_EP6_OFS (6) /* !< EP6 Offset */ +#define USB_RXDPKTBUFDIS_EP6_MASK ((uint16_t)0x00000040U) /* !< EP6 RX Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS_EP6_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_RXDPKTBUFDIS_EP6_ENABLE ((uint16_t)0x00000040U) /* !< Enables double-packet buffering. */ +/* USB_RXDPKTBUFDIS[EP7] Bits */ +#define USB_RXDPKTBUFDIS_EP7_OFS (7) /* !< EP7 Offset */ +#define USB_RXDPKTBUFDIS_EP7_MASK ((uint16_t)0x00000080U) /* !< EP7 RX Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS_EP7_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_RXDPKTBUFDIS_EP7_ENABLE ((uint16_t)0x00000080U) /* !< Enables double-packet buffering. */ + +/* USB_TXDPKTBUFDIS Bits */ +/* USB_TXDPKTBUFDIS[EP1] Bits */ +#define USB_TXDPKTBUFDIS_EP1_OFS (1) /* !< EP1 Offset */ +#define USB_TXDPKTBUFDIS_EP1_MASK ((uint16_t)0x00000002U) /* !< EP1 TX Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS_EP1_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_TXDPKTBUFDIS_EP1_ENABLE ((uint16_t)0x00000002U) /* !< Enables double-packet buffering. */ +/* USB_TXDPKTBUFDIS[EP2] Bits */ +#define USB_TXDPKTBUFDIS_EP2_OFS (2) /* !< EP2 Offset */ +#define USB_TXDPKTBUFDIS_EP2_MASK ((uint16_t)0x00000004U) /* !< EP2 TX Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS_EP2_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_TXDPKTBUFDIS_EP2_ENABLE ((uint16_t)0x00000004U) /* !< Enables double-packet buffering. */ +/* USB_TXDPKTBUFDIS[EP3] Bits */ +#define USB_TXDPKTBUFDIS_EP3_OFS (3) /* !< EP3 Offset */ +#define USB_TXDPKTBUFDIS_EP3_MASK ((uint16_t)0x00000008U) /* !< EP3 TX Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS_EP3_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_TXDPKTBUFDIS_EP3_ENABLE ((uint16_t)0x00000008U) /* !< Enables double-packet buffering. */ +/* USB_TXDPKTBUFDIS[EP4] Bits */ +#define USB_TXDPKTBUFDIS_EP4_OFS (4) /* !< EP4 Offset */ +#define USB_TXDPKTBUFDIS_EP4_MASK ((uint16_t)0x00000010U) /* !< EP4 TX Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS_EP4_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_TXDPKTBUFDIS_EP4_ENABLE ((uint16_t)0x00000010U) /* !< Enables double-packet buffering. */ +/* USB_TXDPKTBUFDIS[EP5] Bits */ +#define USB_TXDPKTBUFDIS_EP5_OFS (5) /* !< EP5 Offset */ +#define USB_TXDPKTBUFDIS_EP5_MASK ((uint16_t)0x00000020U) /* !< EP5 TX Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS_EP5_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_TXDPKTBUFDIS_EP5_ENABLE ((uint16_t)0x00000020U) /* !< Enables double-packet buffering. */ +/* USB_TXDPKTBUFDIS[EP6] Bits */ +#define USB_TXDPKTBUFDIS_EP6_OFS (6) /* !< EP6 Offset */ +#define USB_TXDPKTBUFDIS_EP6_MASK ((uint16_t)0x00000040U) /* !< EP6 TX Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS_EP6_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_TXDPKTBUFDIS_EP6_ENABLE ((uint16_t)0x00000040U) /* !< Enables double-packet buffering. */ +/* USB_TXDPKTBUFDIS[EP7] Bits */ +#define USB_TXDPKTBUFDIS_EP7_OFS (7) /* !< EP7 Offset */ +#define USB_TXDPKTBUFDIS_EP7_MASK ((uint16_t)0x00000080U) /* !< EP7 TX Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS_EP7_DISABLE ((uint16_t)0x00000000U) /* !< Disables double-packet buffering. */ +#define USB_TXDPKTBUFDIS_EP7_ENABLE ((uint16_t)0x00000080U) /* !< Enables double-packet buffering. */ + +/* USB_IIDX Bits */ +/* USB_IIDX[STAT] Bits */ +#define USB_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define USB_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */ +#define USB_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No bit is set means there is no + pending interrupt request */ +#define USB_IIDX_STAT_INTRTX ((uint32_t)0x00000001U) /* !< Endpoint 0 and the TX Endpoints + interrupt */ +#define USB_IIDX_STAT_INTRRX ((uint32_t)0x00000002U) /* !< RX Endpoints interrupt */ +#define USB_IIDX_STAT_INTRUSB ((uint32_t)0x00000003U) /* !< USB Interrupts */ +#define USB_IIDX_STAT_VUSBPWRDN ((uint32_t)0x00000004U) /* !< VUSB power down */ +#define USB_IIDX_STAT_DMADONEARX ((uint32_t)0x00000005U) /* !< DMA-Done interrupt for Trigger + USB-A-RX */ +#define USB_IIDX_STAT_DMADONEATX ((uint32_t)0x00000006U) /* !< DMA-Done interrupt for Trigger + USB-A-TX */ +#define USB_IIDX_STAT_DMADONEBRX ((uint32_t)0x00000007U) /* !< DMA-Done interrupt for Trigger + USB-B-RX */ +#define USB_IIDX_STAT_DMADONEBTX ((uint32_t)0x00000008U) /* !< DMA-Done interrupt for Trigger + USB-B-TX */ +#define USB_IIDX_STAT_DMADONECRX ((uint32_t)0x00000009U) /* !< DMA-Done interrupt for Trigger + USB-C-RX */ +#define USB_IIDX_STAT_DMADONECTX ((uint32_t)0x0000000AU) /* !< DMA-Done interrupt for Trigger + USB-C-TX */ +#define USB_IIDX_STAT_DMADONEDRX ((uint32_t)0x0000000BU) /* !< DMA-Done interrupt for Trigger + USB-D-RX */ +#define USB_IIDX_STAT_DMADONEDTX ((uint32_t)0x0000000CU) /* !< DMA-Done interrupt for Trigger + USB-D-TX */ +#define USB_IIDX_STAT_DMAPREARX ((uint32_t)0x0000000DU) /* !< DMA-Pre interrupt for Trigger + USB-A-RX */ +#define USB_IIDX_STAT_DMAPREATX ((uint32_t)0x0000000EU) /* !< DMA-Pre interrupt for Trigger + USB-A-TX */ +#define USB_IIDX_STAT_DMAPREBRX ((uint32_t)0x0000000FU) /* !< DMA-Pre interrupt for Trigger + USB-B-RX */ +#define USB_IIDX_STAT_DMAPREBTX ((uint32_t)0x00000010U) /* !< DMA-Pre interrupt for Trigger + USB-B-TX */ +#define USB_IIDX_STAT_DMAPRECRX ((uint32_t)0x00000011U) /* !< DMA-Pre interrupt for Trigger + USB-C-RX */ +#define USB_IIDX_STAT_DMAPRECTX ((uint32_t)0x00000012U) /* !< DMA-Pre interrupt for Trigger + USB-C-TX */ +#define USB_IIDX_STAT_DMAPREDRX ((uint32_t)0x00000013U) /* !< DMA-Pre interrupt for Trigger + USB-D-RX */ +#define USB_IIDX_STAT_DMAPREDTX ((uint32_t)0x00000014U) /* !< DMA-Pre interrupt for Trigger + USB-D-TX */ + +/* USB_IMASK Bits */ +/* USB_IMASK[INTRTX] Bits */ +#define USB_IMASK_INTRTX_OFS (0) /* !< INTRTX Offset */ +#define USB_IMASK_INTRTX_MASK ((uint32_t)0x00000001U) /* !< Endpoint 0 and the TX Endpoints + interrupt */ +#define USB_IMASK_INTRTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_INTRTX_SET ((uint32_t)0x00000001U) /* !< Interrupt Enabled. */ +/* USB_IMASK[INTRRX] Bits */ +#define USB_IMASK_INTRRX_OFS (1) /* !< INTRRX Offset */ +#define USB_IMASK_INTRRX_MASK ((uint32_t)0x00000002U) /* !< RX Endpoints interrupt */ +#define USB_IMASK_INTRRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_INTRRX_SET ((uint32_t)0x00000002U) /* !< Interrupt Enabled. */ +/* USB_IMASK[INTRUSB] Bits */ +#define USB_IMASK_INTRUSB_OFS (2) /* !< INTRUSB Offset */ +#define USB_IMASK_INTRUSB_MASK ((uint32_t)0x00000004U) /* !< USB Interrupts */ +#define USB_IMASK_INTRUSB_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_INTRUSB_SET ((uint32_t)0x00000004U) /* !< Interrupt Enabled. */ +/* USB_IMASK[VUSBPWRDN] Bits */ +#define USB_IMASK_VUSBPWRDN_OFS (3) /* !< VUSBPWRDN Offset */ +#define USB_IMASK_VUSBPWRDN_MASK ((uint32_t)0x00000008U) /* !< VUSB Power Down */ +#define USB_IMASK_VUSBPWRDN_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_VUSBPWRDN_SET ((uint32_t)0x00000008U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONEARX] Bits */ +#define USB_IMASK_DMADONEARX_OFS (4) /* !< DMADONEARX Offset */ +#define USB_IMASK_DMADONEARX_MASK ((uint32_t)0x00000010U) /* !< DMA-Done interrupt for Trigger + USB-A-RX */ +#define USB_IMASK_DMADONEARX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONEARX_SET ((uint32_t)0x00000010U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONEATX] Bits */ +#define USB_IMASK_DMADONEATX_OFS (5) /* !< DMADONEATX Offset */ +#define USB_IMASK_DMADONEATX_MASK ((uint32_t)0x00000020U) /* !< DMA-Done interrupt for Trigger + USB-A-TX */ +#define USB_IMASK_DMADONEATX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONEATX_SET ((uint32_t)0x00000020U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONEBRX] Bits */ +#define USB_IMASK_DMADONEBRX_OFS (6) /* !< DMADONEBRX Offset */ +#define USB_IMASK_DMADONEBRX_MASK ((uint32_t)0x00000040U) /* !< DMA-Done interrupt for Trigger + USB-B-RX */ +#define USB_IMASK_DMADONEBRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONEBRX_SET ((uint32_t)0x00000040U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONEBTX] Bits */ +#define USB_IMASK_DMADONEBTX_OFS (7) /* !< DMADONEBTX Offset */ +#define USB_IMASK_DMADONEBTX_MASK ((uint32_t)0x00000080U) /* !< DMA-Done interrupt for Trigger + USB-B-TX */ +#define USB_IMASK_DMADONEBTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONEBTX_SET ((uint32_t)0x00000080U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONECRX] Bits */ +#define USB_IMASK_DMADONECRX_OFS (8) /* !< DMADONECRX Offset */ +#define USB_IMASK_DMADONECRX_MASK ((uint32_t)0x00000100U) /* !< DMA-Done interrupt for Trigger + USB-C-RX */ +#define USB_IMASK_DMADONECRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONECRX_SET ((uint32_t)0x00000100U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONECTX] Bits */ +#define USB_IMASK_DMADONECTX_OFS (9) /* !< DMADONECTX Offset */ +#define USB_IMASK_DMADONECTX_MASK ((uint32_t)0x00000200U) /* !< DMA-Done interrupt for Trigger + USB-C-TX */ +#define USB_IMASK_DMADONECTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONECTX_SET ((uint32_t)0x00000200U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONEDRX] Bits */ +#define USB_IMASK_DMADONEDRX_OFS (10) /* !< DMADONEDRX Offset */ +#define USB_IMASK_DMADONEDRX_MASK ((uint32_t)0x00000400U) /* !< DMA-Done interrupt for Trigger + USB-D-RX */ +#define USB_IMASK_DMADONEDRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONEDRX_SET ((uint32_t)0x00000400U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMADONEDTX] Bits */ +#define USB_IMASK_DMADONEDTX_OFS (11) /* !< DMADONEDTX Offset */ +#define USB_IMASK_DMADONEDTX_MASK ((uint32_t)0x00000800U) /* !< DMA-Done interrupt for Trigger + USB-D-TX */ +#define USB_IMASK_DMADONEDTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMADONEDTX_SET ((uint32_t)0x00000800U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPREARX] Bits */ +#define USB_IMASK_DMAPREARX_OFS (12) /* !< DMAPREARX Offset */ +#define USB_IMASK_DMAPREARX_MASK ((uint32_t)0x00001000U) /* !< DMA-Pre interrupt for Trigger + USB-A-RX */ +#define USB_IMASK_DMAPREARX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPREARX_SET ((uint32_t)0x00001000U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPREATX] Bits */ +#define USB_IMASK_DMAPREATX_OFS (13) /* !< DMAPREATX Offset */ +#define USB_IMASK_DMAPREATX_MASK ((uint32_t)0x00002000U) /* !< DMA-Pre interrupt for Trigger + USB-A-TX */ +#define USB_IMASK_DMAPREATX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPREATX_SET ((uint32_t)0x00002000U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPREBRX] Bits */ +#define USB_IMASK_DMAPREBRX_OFS (14) /* !< DMAPREBRX Offset */ +#define USB_IMASK_DMAPREBRX_MASK ((uint32_t)0x00004000U) /* !< DMA-Pre interrupt for Trigger + USB-B-RX */ +#define USB_IMASK_DMAPREBRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPREBRX_SET ((uint32_t)0x00004000U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPREBTX] Bits */ +#define USB_IMASK_DMAPREBTX_OFS (15) /* !< DMAPREBTX Offset */ +#define USB_IMASK_DMAPREBTX_MASK ((uint32_t)0x00008000U) /* !< DMA-Pre interrupt for Trigger + USB-B-TX */ +#define USB_IMASK_DMAPREBTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPREBTX_SET ((uint32_t)0x00008000U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPRECRX] Bits */ +#define USB_IMASK_DMAPRECRX_OFS (16) /* !< DMAPRECRX Offset */ +#define USB_IMASK_DMAPRECRX_MASK ((uint32_t)0x00010000U) /* !< DMA-Pre interrupt for Trigger + USB-C-RX */ +#define USB_IMASK_DMAPRECRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPRECRX_SET ((uint32_t)0x00010000U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPRECTX] Bits */ +#define USB_IMASK_DMAPRECTX_OFS (17) /* !< DMAPRECTX Offset */ +#define USB_IMASK_DMAPRECTX_MASK ((uint32_t)0x00020000U) /* !< DMA-Pre interrupt for Trigger + USB-C-TX */ +#define USB_IMASK_DMAPRECTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPRECTX_SET ((uint32_t)0x00020000U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPREDRX] Bits */ +#define USB_IMASK_DMAPREDRX_OFS (18) /* !< DMAPREDRX Offset */ +#define USB_IMASK_DMAPREDRX_MASK ((uint32_t)0x00040000U) /* !< DMA-Pre interrupt for Trigger + USB-D-RX */ +#define USB_IMASK_DMAPREDRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPREDRX_SET ((uint32_t)0x00040000U) /* !< Interrupt Enabled. */ +/* USB_IMASK[DMAPREDTX] Bits */ +#define USB_IMASK_DMAPREDTX_OFS (19) /* !< DMAPREDTX Offset */ +#define USB_IMASK_DMAPREDTX_MASK ((uint32_t)0x00080000U) /* !< DMA-Pre interrupt for Trigger + USB-D-TX */ +#define USB_IMASK_DMAPREDTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt Disabled. */ +#define USB_IMASK_DMAPREDTX_SET ((uint32_t)0x00080000U) /* !< Interrupt Enabled. */ + +/* USB_RIS Bits */ +/* USB_RIS[INTRTX] Bits */ +#define USB_RIS_INTRTX_OFS (0) /* !< INTRTX Offset */ +#define USB_RIS_INTRTX_MASK ((uint32_t)0x00000001U) /* !< Endpoint 0 and the TX Endpoints + interrupt */ +#define USB_RIS_INTRTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_INTRTX_SET ((uint32_t)0x00000001U) /* !< Interrupt occured */ +/* USB_RIS[INTRRX] Bits */ +#define USB_RIS_INTRRX_OFS (1) /* !< INTRRX Offset */ +#define USB_RIS_INTRRX_MASK ((uint32_t)0x00000002U) /* !< RX Endpoints interrupt */ +#define USB_RIS_INTRRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_INTRRX_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */ +/* USB_RIS[INTRUSB] Bits */ +#define USB_RIS_INTRUSB_OFS (2) /* !< INTRUSB Offset */ +#define USB_RIS_INTRUSB_MASK ((uint32_t)0x00000004U) /* !< USB Interrupts */ +#define USB_RIS_INTRUSB_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_INTRUSB_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */ +/* USB_RIS[VUSBPWRDN] Bits */ +#define USB_RIS_VUSBPWRDN_OFS (3) /* !< VUSBPWRDN Offset */ +#define USB_RIS_VUSBPWRDN_MASK ((uint32_t)0x00000008U) /* !< VUSB Power Down */ +#define USB_RIS_VUSBPWRDN_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_VUSBPWRDN_SET ((uint32_t)0x00000008U) /* !< Interrupt occured */ +/* USB_RIS[DMADONEARX] Bits */ +#define USB_RIS_DMADONEARX_OFS (4) /* !< DMADONEARX Offset */ +#define USB_RIS_DMADONEARX_MASK ((uint32_t)0x00000010U) /* !< DMA-Done interrupt for Trigger + USB-A-RX */ +#define USB_RIS_DMADONEARX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONEARX_SET ((uint32_t)0x00000010U) /* !< Interrupt occured */ +/* USB_RIS[DMADONEATX] Bits */ +#define USB_RIS_DMADONEATX_OFS (5) /* !< DMADONEATX Offset */ +#define USB_RIS_DMADONEATX_MASK ((uint32_t)0x00000020U) /* !< DMA-Done interrupt for Trigger + USB-A-TX */ +#define USB_RIS_DMADONEATX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONEATX_SET ((uint32_t)0x00000020U) /* !< Interrupt occured */ +/* USB_RIS[DMADONEBRX] Bits */ +#define USB_RIS_DMADONEBRX_OFS (6) /* !< DMADONEBRX Offset */ +#define USB_RIS_DMADONEBRX_MASK ((uint32_t)0x00000040U) /* !< DMA-Done interrupt for Trigger + USB-B-RX */ +#define USB_RIS_DMADONEBRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONEBRX_SET ((uint32_t)0x00000040U) /* !< Interrupt occured */ +/* USB_RIS[DMADONEBTX] Bits */ +#define USB_RIS_DMADONEBTX_OFS (7) /* !< DMADONEBTX Offset */ +#define USB_RIS_DMADONEBTX_MASK ((uint32_t)0x00000080U) /* !< DMA-Done interrupt for Trigger + USB-B-TX */ +#define USB_RIS_DMADONEBTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONEBTX_SET ((uint32_t)0x00000080U) /* !< Interrupt occured */ +/* USB_RIS[DMADONECRX] Bits */ +#define USB_RIS_DMADONECRX_OFS (8) /* !< DMADONECRX Offset */ +#define USB_RIS_DMADONECRX_MASK ((uint32_t)0x00000100U) /* !< DMA-Done interrupt for Trigger + USB-C-RX */ +#define USB_RIS_DMADONECRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONECRX_SET ((uint32_t)0x00000100U) /* !< Interrupt occured */ +/* USB_RIS[DMADONECTX] Bits */ +#define USB_RIS_DMADONECTX_OFS (9) /* !< DMADONECTX Offset */ +#define USB_RIS_DMADONECTX_MASK ((uint32_t)0x00000200U) /* !< DMA-Done interrupt for Trigger + USB-C-TX */ +#define USB_RIS_DMADONECTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONECTX_SET ((uint32_t)0x00000200U) /* !< Interrupt occured */ +/* USB_RIS[DMADONEDRX] Bits */ +#define USB_RIS_DMADONEDRX_OFS (10) /* !< DMADONEDRX Offset */ +#define USB_RIS_DMADONEDRX_MASK ((uint32_t)0x00000400U) /* !< DMA-Done interrupt for Trigger + USB-D-RX */ +#define USB_RIS_DMADONEDRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONEDRX_SET ((uint32_t)0x00000400U) /* !< Interrupt occured */ +/* USB_RIS[DMADONEDTX] Bits */ +#define USB_RIS_DMADONEDTX_OFS (11) /* !< DMADONEDTX Offset */ +#define USB_RIS_DMADONEDTX_MASK ((uint32_t)0x00000800U) /* !< DMA-Done interrupt for Trigger + USB-D-TX */ +#define USB_RIS_DMADONEDTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMADONEDTX_SET ((uint32_t)0x00000800U) /* !< Interrupt occured */ +/* USB_RIS[DMAPREARX] Bits */ +#define USB_RIS_DMAPREARX_OFS (12) /* !< DMAPREARX Offset */ +#define USB_RIS_DMAPREARX_MASK ((uint32_t)0x00001000U) /* !< DMA-Pre interrupt for Trigger + USB-A-RX */ +#define USB_RIS_DMAPREARX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPREARX_SET ((uint32_t)0x00001000U) /* !< Interrupt occured */ +/* USB_RIS[DMAPREATX] Bits */ +#define USB_RIS_DMAPREATX_OFS (13) /* !< DMAPREATX Offset */ +#define USB_RIS_DMAPREATX_MASK ((uint32_t)0x00002000U) /* !< DMA-Pre interrupt for Trigger + USB-A-TX */ +#define USB_RIS_DMAPREATX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPREATX_SET ((uint32_t)0x00002000U) /* !< Interrupt occured */ +/* USB_RIS[DMAPREBRX] Bits */ +#define USB_RIS_DMAPREBRX_OFS (14) /* !< DMAPREBRX Offset */ +#define USB_RIS_DMAPREBRX_MASK ((uint32_t)0x00004000U) /* !< DMA-Pre interrupt for Trigger + USB-B-RX */ +#define USB_RIS_DMAPREBRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPREBRX_SET ((uint32_t)0x00004000U) /* !< Interrupt occured */ +/* USB_RIS[DMAPREBTX] Bits */ +#define USB_RIS_DMAPREBTX_OFS (15) /* !< DMAPREBTX Offset */ +#define USB_RIS_DMAPREBTX_MASK ((uint32_t)0x00008000U) /* !< DMA-Pre interrupt for Trigger + USB-B-TX */ +#define USB_RIS_DMAPREBTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPREBTX_SET ((uint32_t)0x00008000U) /* !< Interrupt occured */ +/* USB_RIS[DMAPRECRX] Bits */ +#define USB_RIS_DMAPRECRX_OFS (16) /* !< DMAPRECRX Offset */ +#define USB_RIS_DMAPRECRX_MASK ((uint32_t)0x00010000U) /* !< DMA-Pre interrupt for Trigger + USB-C-RX */ +#define USB_RIS_DMAPRECRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPRECRX_SET ((uint32_t)0x00010000U) /* !< Interrupt occured */ +/* USB_RIS[DMAPRECTX] Bits */ +#define USB_RIS_DMAPRECTX_OFS (17) /* !< DMAPRECTX Offset */ +#define USB_RIS_DMAPRECTX_MASK ((uint32_t)0x00020000U) /* !< DMA-Pre interrupt for Trigger + USB-C-TX */ +#define USB_RIS_DMAPRECTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPRECTX_SET ((uint32_t)0x00020000U) /* !< Interrupt occured */ +/* USB_RIS[DMAPREDRX] Bits */ +#define USB_RIS_DMAPREDRX_OFS (18) /* !< DMAPREDRX Offset */ +#define USB_RIS_DMAPREDRX_MASK ((uint32_t)0x00040000U) /* !< DMA-Pre interrupt for Trigger + USB-D-RX */ +#define USB_RIS_DMAPREDRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPREDRX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* USB_RIS[DMAPREDTX] Bits */ +#define USB_RIS_DMAPREDTX_OFS (19) /* !< DMAPREDTX Offset */ +#define USB_RIS_DMAPREDTX_MASK ((uint32_t)0x00080000U) /* !< DMA-Pre interrupt for Trigger + USB-D-TX */ +#define USB_RIS_DMAPREDTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_RIS_DMAPREDTX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ + +/* USB_MIS Bits */ +/* USB_MIS[INTRTX] Bits */ +#define USB_MIS_INTRTX_OFS (0) /* !< INTRTX Offset */ +#define USB_MIS_INTRTX_MASK ((uint32_t)0x00000001U) /* !< Endpoint 0 and the TX Endpoints + interrupt */ +#define USB_MIS_INTRTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_INTRTX_SET ((uint32_t)0x00000001U) /* !< Interrupt occured */ +/* USB_MIS[INTRRX] Bits */ +#define USB_MIS_INTRRX_OFS (1) /* !< INTRRX Offset */ +#define USB_MIS_INTRRX_MASK ((uint32_t)0x00000002U) /* !< RX Endpoints interrupt */ +#define USB_MIS_INTRRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_INTRRX_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */ +/* USB_MIS[INTRUSB] Bits */ +#define USB_MIS_INTRUSB_OFS (2) /* !< INTRUSB Offset */ +#define USB_MIS_INTRUSB_MASK ((uint32_t)0x00000004U) /* !< USB Interrupts */ +#define USB_MIS_INTRUSB_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_INTRUSB_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */ +/* USB_MIS[VUSBPWRDN] Bits */ +#define USB_MIS_VUSBPWRDN_OFS (3) /* !< VUSBPWRDN Offset */ +#define USB_MIS_VUSBPWRDN_MASK ((uint32_t)0x00000008U) /* !< VUSB Power Down */ +#define USB_MIS_VUSBPWRDN_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_VUSBPWRDN_SET ((uint32_t)0x00000008U) /* !< Interrupt occured */ +/* USB_MIS[DMADONEARX] Bits */ +#define USB_MIS_DMADONEARX_OFS (4) /* !< DMADONEARX Offset */ +#define USB_MIS_DMADONEARX_MASK ((uint32_t)0x00000010U) /* !< DMA-Done interrupt for Trigger + USB-A-RX */ +#define USB_MIS_DMADONEARX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONEARX_SET ((uint32_t)0x00000010U) /* !< Interrupt occured */ +/* USB_MIS[DMADONEATX] Bits */ +#define USB_MIS_DMADONEATX_OFS (5) /* !< DMADONEATX Offset */ +#define USB_MIS_DMADONEATX_MASK ((uint32_t)0x00000020U) /* !< DMA-Done interrupt for Trigger + USB-A-TX */ +#define USB_MIS_DMADONEATX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONEATX_SET ((uint32_t)0x00000020U) /* !< Interrupt occured */ +/* USB_MIS[DMADONEBRX] Bits */ +#define USB_MIS_DMADONEBRX_OFS (6) /* !< DMADONEBRX Offset */ +#define USB_MIS_DMADONEBRX_MASK ((uint32_t)0x00000040U) /* !< DMA-Done interrupt for Trigger + USB-B-RX */ +#define USB_MIS_DMADONEBRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONEBRX_SET ((uint32_t)0x00000040U) /* !< Interrupt occured */ +/* USB_MIS[DMADONEBTX] Bits */ +#define USB_MIS_DMADONEBTX_OFS (7) /* !< DMADONEBTX Offset */ +#define USB_MIS_DMADONEBTX_MASK ((uint32_t)0x00000080U) /* !< DMA-Done interrupt for Trigger + USB-B-TX */ +#define USB_MIS_DMADONEBTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONEBTX_SET ((uint32_t)0x00000080U) /* !< Interrupt occured */ +/* USB_MIS[DMADONECRX] Bits */ +#define USB_MIS_DMADONECRX_OFS (8) /* !< DMADONECRX Offset */ +#define USB_MIS_DMADONECRX_MASK ((uint32_t)0x00000100U) /* !< DMA-Done interrupt for Trigger + USB-C-RX */ +#define USB_MIS_DMADONECRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONECRX_SET ((uint32_t)0x00000100U) /* !< Interrupt occured */ +/* USB_MIS[DMADONECTX] Bits */ +#define USB_MIS_DMADONECTX_OFS (9) /* !< DMADONECTX Offset */ +#define USB_MIS_DMADONECTX_MASK ((uint32_t)0x00000200U) /* !< DMA-Done interrupt for Trigger + USB-C-TX */ +#define USB_MIS_DMADONECTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONECTX_SET ((uint32_t)0x00000200U) /* !< Interrupt occured */ +/* USB_MIS[DMADONEDRX] Bits */ +#define USB_MIS_DMADONEDRX_OFS (10) /* !< DMADONEDRX Offset */ +#define USB_MIS_DMADONEDRX_MASK ((uint32_t)0x00000400U) /* !< DMA-Done interrupt for Trigger + USB-D-RX */ +#define USB_MIS_DMADONEDRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONEDRX_SET ((uint32_t)0x00000400U) /* !< Interrupt occured */ +/* USB_MIS[DMADONEDTX] Bits */ +#define USB_MIS_DMADONEDTX_OFS (11) /* !< DMADONEDTX Offset */ +#define USB_MIS_DMADONEDTX_MASK ((uint32_t)0x00000800U) /* !< DMA-Done interrupt for Trigger + USB-D-TX */ +#define USB_MIS_DMADONEDTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMADONEDTX_SET ((uint32_t)0x00000800U) /* !< Interrupt occured */ +/* USB_MIS[DMAPREARX] Bits */ +#define USB_MIS_DMAPREARX_OFS (12) /* !< DMAPREARX Offset */ +#define USB_MIS_DMAPREARX_MASK ((uint32_t)0x00001000U) /* !< DMA-Pre interrupt for Trigger + USB-A-RX */ +#define USB_MIS_DMAPREARX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPREARX_SET ((uint32_t)0x00001000U) /* !< Interrupt occured */ +/* USB_MIS[DMAPREATX] Bits */ +#define USB_MIS_DMAPREATX_OFS (13) /* !< DMAPREATX Offset */ +#define USB_MIS_DMAPREATX_MASK ((uint32_t)0x00002000U) /* !< DMA-Pre interrupt for Trigger + USB-A-TX */ +#define USB_MIS_DMAPREATX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPREATX_SET ((uint32_t)0x00002000U) /* !< Interrupt occured */ +/* USB_MIS[DMAPREBRX] Bits */ +#define USB_MIS_DMAPREBRX_OFS (14) /* !< DMAPREBRX Offset */ +#define USB_MIS_DMAPREBRX_MASK ((uint32_t)0x00004000U) /* !< DMA-Pre interrupt for Trigger + USB-B-RX */ +#define USB_MIS_DMAPREBRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPREBRX_SET ((uint32_t)0x00004000U) /* !< Interrupt occured */ +/* USB_MIS[DMAPREBTX] Bits */ +#define USB_MIS_DMAPREBTX_OFS (15) /* !< DMAPREBTX Offset */ +#define USB_MIS_DMAPREBTX_MASK ((uint32_t)0x00008000U) /* !< DMA-Pre interrupt for Trigger + USB-B-TX */ +#define USB_MIS_DMAPREBTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPREBTX_SET ((uint32_t)0x00008000U) /* !< Interrupt occured */ +/* USB_MIS[DMAPRECRX] Bits */ +#define USB_MIS_DMAPRECRX_OFS (16) /* !< DMAPRECRX Offset */ +#define USB_MIS_DMAPRECRX_MASK ((uint32_t)0x00010000U) /* !< DMA-Pre interrupt for Trigger + USB-C-RX */ +#define USB_MIS_DMAPRECRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPRECRX_SET ((uint32_t)0x00010000U) /* !< Interrupt occured */ +/* USB_MIS[DMAPRECTX] Bits */ +#define USB_MIS_DMAPRECTX_OFS (17) /* !< DMAPRECTX Offset */ +#define USB_MIS_DMAPRECTX_MASK ((uint32_t)0x00020000U) /* !< DMA-Pre interrupt for Trigger + USB-C-TX */ +#define USB_MIS_DMAPRECTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPRECTX_SET ((uint32_t)0x00020000U) /* !< Interrupt occured */ +/* USB_MIS[DMAPREDRX] Bits */ +#define USB_MIS_DMAPREDRX_OFS (18) /* !< DMAPREDRX Offset */ +#define USB_MIS_DMAPREDRX_MASK ((uint32_t)0x00040000U) /* !< DMA-Pre interrupt for Trigger + USB-D-RX */ +#define USB_MIS_DMAPREDRX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPREDRX_SET ((uint32_t)0x00040000U) /* !< Interrupt occured */ +/* USB_MIS[DMAPREDTX] Bits */ +#define USB_MIS_DMAPREDTX_OFS (19) /* !< DMAPREDTX Offset */ +#define USB_MIS_DMAPREDTX_MASK ((uint32_t)0x00080000U) /* !< DMA-Pre interrupt for Trigger + USB-D-TX */ +#define USB_MIS_DMAPREDTX_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */ +#define USB_MIS_DMAPREDTX_SET ((uint32_t)0x00080000U) /* !< Interrupt occured */ + +/* USB_ISET Bits */ +/* USB_ISET[INTRTX] Bits */ +#define USB_ISET_INTRTX_OFS (0) /* !< INTRTX Offset */ +#define USB_ISET_INTRTX_MASK ((uint32_t)0x00000001U) /* !< Endpoint 0 and the TX Endpoints + interrupt */ +#define USB_ISET_INTRTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_INTRTX_SET ((uint32_t)0x00000001U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[INTRRX] Bits */ +#define USB_ISET_INTRRX_OFS (1) /* !< INTRRX Offset */ +#define USB_ISET_INTRRX_MASK ((uint32_t)0x00000002U) /* !< RX Endpoints interrupt */ +#define USB_ISET_INTRRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_INTRRX_SET ((uint32_t)0x00000002U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[INTRUSB] Bits */ +#define USB_ISET_INTRUSB_OFS (2) /* !< INTRUSB Offset */ +#define USB_ISET_INTRUSB_MASK ((uint32_t)0x00000004U) /* !< USB Interrupts */ +#define USB_ISET_INTRUSB_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_INTRUSB_SET ((uint32_t)0x00000004U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[VUSBPWRDN] Bits */ +#define USB_ISET_VUSBPWRDN_OFS (3) /* !< VUSBPWRDN Offset */ +#define USB_ISET_VUSBPWRDN_MASK ((uint32_t)0x00000008U) /* !< VUSB Power Down */ +#define USB_ISET_VUSBPWRDN_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_VUSBPWRDN_SET ((uint32_t)0x00000008U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONEARX] Bits */ +#define USB_ISET_DMADONEARX_OFS (4) /* !< DMADONEARX Offset */ +#define USB_ISET_DMADONEARX_MASK ((uint32_t)0x00000010U) /* !< DMA-Done interrupt for Trigger + USB-A-RX */ +#define USB_ISET_DMADONEARX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONEARX_SET ((uint32_t)0x00000010U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONEATX] Bits */ +#define USB_ISET_DMADONEATX_OFS (5) /* !< DMADONEATX Offset */ +#define USB_ISET_DMADONEATX_MASK ((uint32_t)0x00000020U) /* !< DMA-Done interrupt for Trigger + USB-A-TX */ +#define USB_ISET_DMADONEATX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONEATX_SET ((uint32_t)0x00000020U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONEBRX] Bits */ +#define USB_ISET_DMADONEBRX_OFS (6) /* !< DMADONEBRX Offset */ +#define USB_ISET_DMADONEBRX_MASK ((uint32_t)0x00000040U) /* !< DMA-Done interrupt for Trigger + USB-B-RX */ +#define USB_ISET_DMADONEBRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONEBRX_SET ((uint32_t)0x00000040U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONEBTX] Bits */ +#define USB_ISET_DMADONEBTX_OFS (7) /* !< DMADONEBTX Offset */ +#define USB_ISET_DMADONEBTX_MASK ((uint32_t)0x00000080U) /* !< DMA-Done interrupt for Trigger + USB-B-TX */ +#define USB_ISET_DMADONEBTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONEBTX_SET ((uint32_t)0x00000080U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONECRX] Bits */ +#define USB_ISET_DMADONECRX_OFS (8) /* !< DMADONECRX Offset */ +#define USB_ISET_DMADONECRX_MASK ((uint32_t)0x00000100U) /* !< DMA-Done interrupt for Trigger + USB-C-RX */ +#define USB_ISET_DMADONECRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONECRX_SET ((uint32_t)0x00000100U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONECTX] Bits */ +#define USB_ISET_DMADONECTX_OFS (9) /* !< DMADONECTX Offset */ +#define USB_ISET_DMADONECTX_MASK ((uint32_t)0x00000200U) /* !< DMA-Done interrupt for Trigger + USB-C-TX */ +#define USB_ISET_DMADONECTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONECTX_SET ((uint32_t)0x00000200U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONEDRX] Bits */ +#define USB_ISET_DMADONEDRX_OFS (10) /* !< DMADONEDRX Offset */ +#define USB_ISET_DMADONEDRX_MASK ((uint32_t)0x00000400U) /* !< DMA-Done interrupt for Trigger + USB-D-RX */ +#define USB_ISET_DMADONEDRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONEDRX_SET ((uint32_t)0x00000400U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMADONEDTX] Bits */ +#define USB_ISET_DMADONEDTX_OFS (11) /* !< DMADONEDTX Offset */ +#define USB_ISET_DMADONEDTX_MASK ((uint32_t)0x00000800U) /* !< DMA-Done interrupt for Trigger + USB-D-TX */ +#define USB_ISET_DMADONEDTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMADONEDTX_SET ((uint32_t)0x00000800U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPREARX] Bits */ +#define USB_ISET_DMAPREARX_OFS (12) /* !< DMAPREARX Offset */ +#define USB_ISET_DMAPREARX_MASK ((uint32_t)0x00001000U) /* !< DMA-Pre interrupt for Trigger + USB-A-RX */ +#define USB_ISET_DMAPREARX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPREARX_SET ((uint32_t)0x00001000U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPREATX] Bits */ +#define USB_ISET_DMAPREATX_OFS (13) /* !< DMAPREATX Offset */ +#define USB_ISET_DMAPREATX_MASK ((uint32_t)0x00002000U) /* !< DMA-Pre interrupt for Trigger + USB-A-TX */ +#define USB_ISET_DMAPREATX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPREATX_SET ((uint32_t)0x00002000U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPREBRX] Bits */ +#define USB_ISET_DMAPREBRX_OFS (14) /* !< DMAPREBRX Offset */ +#define USB_ISET_DMAPREBRX_MASK ((uint32_t)0x00004000U) /* !< DMA-Pre interrupt for Trigger + USB-B-RX */ +#define USB_ISET_DMAPREBRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPREBRX_SET ((uint32_t)0x00004000U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPREBTX] Bits */ +#define USB_ISET_DMAPREBTX_OFS (15) /* !< DMAPREBTX Offset */ +#define USB_ISET_DMAPREBTX_MASK ((uint32_t)0x00008000U) /* !< DMA-Pre interrupt for Trigger + USB-B-TX */ +#define USB_ISET_DMAPREBTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPREBTX_SET ((uint32_t)0x00008000U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPRECRX] Bits */ +#define USB_ISET_DMAPRECRX_OFS (16) /* !< DMAPRECRX Offset */ +#define USB_ISET_DMAPRECRX_MASK ((uint32_t)0x00010000U) /* !< DMA-Pre interrupt for Trigger + USB-C-RX */ +#define USB_ISET_DMAPRECRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPRECRX_SET ((uint32_t)0x00010000U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPRECTX] Bits */ +#define USB_ISET_DMAPRECTX_OFS (17) /* !< DMAPRECTX Offset */ +#define USB_ISET_DMAPRECTX_MASK ((uint32_t)0x00020000U) /* !< DMA-Pre interrupt for Trigger + USB-C-TX */ +#define USB_ISET_DMAPRECTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPRECTX_SET ((uint32_t)0x00020000U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPREDRX] Bits */ +#define USB_ISET_DMAPREDRX_OFS (18) /* !< DMAPREDRX Offset */ +#define USB_ISET_DMAPREDRX_MASK ((uint32_t)0x00040000U) /* !< DMA-Pre interrupt for Trigger + USB-D-RX */ +#define USB_ISET_DMAPREDRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPREDRX_SET ((uint32_t)0x00040000U) /* !< Write 1 to set the interrupt */ +/* USB_ISET[DMAPREDTX] Bits */ +#define USB_ISET_DMAPREDTX_OFS (19) /* !< DMAPREDTX Offset */ +#define USB_ISET_DMAPREDTX_MASK ((uint32_t)0x00080000U) /* !< DMA-Pre interrupt for Trigger + USB-D-TX */ +#define USB_ISET_DMAPREDTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ISET_DMAPREDTX_SET ((uint32_t)0x00080000U) /* !< Write 1 to set the interrupt */ + +/* USB_ICLR Bits */ +/* USB_ICLR[INTRTX] Bits */ +#define USB_ICLR_INTRTX_OFS (0) /* !< INTRTX Offset */ +#define USB_ICLR_INTRTX_MASK ((uint32_t)0x00000001U) /* !< Endpoint 0 and the TX Endpoints + interrupt */ +#define USB_ICLR_INTRTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_INTRTX_CLR ((uint32_t)0x00000001U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[INTRRX] Bits */ +#define USB_ICLR_INTRRX_OFS (1) /* !< INTRRX Offset */ +#define USB_ICLR_INTRRX_MASK ((uint32_t)0x00000002U) /* !< RX Endpoints interrupt */ +#define USB_ICLR_INTRRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_INTRRX_CLR ((uint32_t)0x00000002U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[INTRUSB] Bits */ +#define USB_ICLR_INTRUSB_OFS (2) /* !< INTRUSB Offset */ +#define USB_ICLR_INTRUSB_MASK ((uint32_t)0x00000004U) /* !< USB Interrupts */ +#define USB_ICLR_INTRUSB_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_INTRUSB_CLR ((uint32_t)0x00000004U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[VUSBPWRDN] Bits */ +#define USB_ICLR_VUSBPWRDN_OFS (3) /* !< VUSBPWRDN Offset */ +#define USB_ICLR_VUSBPWRDN_MASK ((uint32_t)0x00000008U) /* !< VUSB Power Down */ +#define USB_ICLR_VUSBPWRDN_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_VUSBPWRDN_CLR ((uint32_t)0x00000008U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONEARX] Bits */ +#define USB_ICLR_DMADONEARX_OFS (4) /* !< DMADONEARX Offset */ +#define USB_ICLR_DMADONEARX_MASK ((uint32_t)0x00000010U) /* !< DMA-Done interrupt for Trigger + USB-A-RX */ +#define USB_ICLR_DMADONEARX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONEARX_CLR ((uint32_t)0x00000010U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONEATX] Bits */ +#define USB_ICLR_DMADONEATX_OFS (5) /* !< DMADONEATX Offset */ +#define USB_ICLR_DMADONEATX_MASK ((uint32_t)0x00000020U) /* !< DMA-Done interrupt for Trigger + USB-A-TX */ +#define USB_ICLR_DMADONEATX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONEATX_CLR ((uint32_t)0x00000020U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONEBRX] Bits */ +#define USB_ICLR_DMADONEBRX_OFS (6) /* !< DMADONEBRX Offset */ +#define USB_ICLR_DMADONEBRX_MASK ((uint32_t)0x00000040U) /* !< DMA-Done interrupt for Trigger + USB-B-RX */ +#define USB_ICLR_DMADONEBRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONEBRX_CLR ((uint32_t)0x00000040U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONEBTX] Bits */ +#define USB_ICLR_DMADONEBTX_OFS (7) /* !< DMADONEBTX Offset */ +#define USB_ICLR_DMADONEBTX_MASK ((uint32_t)0x00000080U) /* !< DMA-Done interrupt for Trigger + USB-B-TX */ +#define USB_ICLR_DMADONEBTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONEBTX_CLR ((uint32_t)0x00000080U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONECRX] Bits */ +#define USB_ICLR_DMADONECRX_OFS (8) /* !< DMADONECRX Offset */ +#define USB_ICLR_DMADONECRX_MASK ((uint32_t)0x00000100U) /* !< DMA-Done interrupt for Trigger + USB-C-RX */ +#define USB_ICLR_DMADONECRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONECRX_CLR ((uint32_t)0x00000100U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONECTX] Bits */ +#define USB_ICLR_DMADONECTX_OFS (9) /* !< DMADONECTX Offset */ +#define USB_ICLR_DMADONECTX_MASK ((uint32_t)0x00000200U) /* !< DMA-Done interrupt for Trigger + USB-C-TX */ +#define USB_ICLR_DMADONECTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONECTX_CLR ((uint32_t)0x00000200U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONEDRX] Bits */ +#define USB_ICLR_DMADONEDRX_OFS (10) /* !< DMADONEDRX Offset */ +#define USB_ICLR_DMADONEDRX_MASK ((uint32_t)0x00000400U) /* !< DMA-Done interrupt for Trigger + USB-D-RX */ +#define USB_ICLR_DMADONEDRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONEDRX_CLR ((uint32_t)0x00000400U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMADONEDTX] Bits */ +#define USB_ICLR_DMADONEDTX_OFS (11) /* !< DMADONEDTX Offset */ +#define USB_ICLR_DMADONEDTX_MASK ((uint32_t)0x00000800U) /* !< DMA-Done interrupt for Trigger + USB-D-TX */ +#define USB_ICLR_DMADONEDTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMADONEDTX_CLR ((uint32_t)0x00000800U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPREARX] Bits */ +#define USB_ICLR_DMAPREARX_OFS (12) /* !< DMAPREARX Offset */ +#define USB_ICLR_DMAPREARX_MASK ((uint32_t)0x00001000U) /* !< DMA-Pre interrupt for Trigger + USB-A-RX */ +#define USB_ICLR_DMAPREARX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPREARX_CLR ((uint32_t)0x00001000U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPREATX] Bits */ +#define USB_ICLR_DMAPREATX_OFS (13) /* !< DMAPREATX Offset */ +#define USB_ICLR_DMAPREATX_MASK ((uint32_t)0x00002000U) /* !< DMA-Pre interrupt for Trigger + USB-A-TX */ +#define USB_ICLR_DMAPREATX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPREATX_CLR ((uint32_t)0x00002000U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPREBRX] Bits */ +#define USB_ICLR_DMAPREBRX_OFS (14) /* !< DMAPREBRX Offset */ +#define USB_ICLR_DMAPREBRX_MASK ((uint32_t)0x00004000U) /* !< DMA-Pre interrupt for Trigger + USB-B-RX */ +#define USB_ICLR_DMAPREBRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPREBRX_CLR ((uint32_t)0x00004000U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPREBTX] Bits */ +#define USB_ICLR_DMAPREBTX_OFS (15) /* !< DMAPREBTX Offset */ +#define USB_ICLR_DMAPREBTX_MASK ((uint32_t)0x00008000U) /* !< DMA-Pre interrupt for Trigger + USB-B-TX */ +#define USB_ICLR_DMAPREBTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPREBTX_CLR ((uint32_t)0x00008000U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPRECRX] Bits */ +#define USB_ICLR_DMAPRECRX_OFS (16) /* !< DMAPRECRX Offset */ +#define USB_ICLR_DMAPRECRX_MASK ((uint32_t)0x00010000U) /* !< DMA-Pre interrupt for Trigger + USB-C-RX */ +#define USB_ICLR_DMAPRECRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPRECRX_CLR ((uint32_t)0x00010000U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPRECTX] Bits */ +#define USB_ICLR_DMAPRECTX_OFS (17) /* !< DMAPRECTX Offset */ +#define USB_ICLR_DMAPRECTX_MASK ((uint32_t)0x00020000U) /* !< DMA-Pre interrupt for Trigger + USB-C-TX */ +#define USB_ICLR_DMAPRECTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPRECTX_CLR ((uint32_t)0x00020000U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPREDRX] Bits */ +#define USB_ICLR_DMAPREDRX_OFS (18) /* !< DMAPREDRX Offset */ +#define USB_ICLR_DMAPREDRX_MASK ((uint32_t)0x00040000U) /* !< DMA-Pre interrupt for Trigger + USB-D-RX */ +#define USB_ICLR_DMAPREDRX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPREDRX_CLR ((uint32_t)0x00040000U) /* !< Write 1 to clear the interrupt */ +/* USB_ICLR[DMAPREDTX] Bits */ +#define USB_ICLR_DMAPREDTX_OFS (19) /* !< DMAPREDTX Offset */ +#define USB_ICLR_DMAPREDTX_MASK ((uint32_t)0x00080000U) /* !< DMA-Pre interrupt for Trigger + USB-D-TX */ +#define USB_ICLR_DMAPREDTX_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has No Effect */ +#define USB_ICLR_DMAPREDTX_CLR ((uint32_t)0x00080000U) /* !< Write 1 to clear the interrupt */ + +/* USB_PWREN Bits */ +/* USB_PWREN[ENABLE] Bits */ +#define USB_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */ +#define USB_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */ +#define USB_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */ +#define USB_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */ +/* USB_PWREN[KEY] Bits */ +#define USB_PWREN_KEY_OFS (24) /* !< KEY Offset */ +#define USB_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */ +#define USB_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this + register */ + +/* USB_RSTCTL Bits */ +/* USB_RSTCTL[RESETSTKYCLR] Bits */ +#define USB_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */ +#define USB_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT + register */ +#define USB_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define USB_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */ +/* USB_RSTCTL[RESETASSERT] Bits */ +#define USB_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */ +#define USB_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */ +#define USB_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */ +#define USB_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */ +/* USB_RSTCTL[KEY] Bits */ +#define USB_RSTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define USB_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */ +#define USB_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this + register */ + +/* USB_CLKCTL Bits */ +/* USB_CLKCTL[CLKDIV] Bits */ +#define USB_CLKCTL_CLKDIV_OFS (0) /* !< CLKDIV Offset */ +#define USB_CLKCTL_CLKDIV_MASK ((uint32_t)0x0000000FU) /* !< Divider settings for the functional + clock */ +#define USB_CLKCTL_CLKDIV_DIV_BY_1 ((uint32_t)0x00000000U) /* !< Divide by 1 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_2 ((uint32_t)0x00000001U) /* !< Divide by 2 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_3 ((uint32_t)0x00000002U) /* !< Divide by 3 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_4 ((uint32_t)0x00000003U) /* !< Divide by 4 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_5 ((uint32_t)0x00000004U) /* !< Divide by 5 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_6 ((uint32_t)0x00000005U) /* !< Divide by 6 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_10 ((uint32_t)0x00000006U) /* !< Divide by 10 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_12 ((uint32_t)0x00000007U) /* !< Divide by 12 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_15 ((uint32_t)0x00000008U) /* !< Divide by 15 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_20 ((uint32_t)0x00000009U) /* !< Divide by 20 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_30 ((uint32_t)0x0000000AU) /* !< Divide by 30 */ +#define USB_CLKCTL_CLKDIV_DIV_BY_60 ((uint32_t)0x0000000BU) /* !< Divide by 60 */ + +/* USB_STAT Bits */ +/* USB_STAT[ENABLE] Bits */ +#define USB_STAT_ENABLE_OFS (8) /* !< ENABLE Offset */ +#define USB_STAT_ENABLE_MASK ((uint32_t)0x00000100U) /* !< Peripheral enable status */ +#define USB_STAT_ENABLE_OFF ((uint32_t)0x00000000U) /* !< Peripheral is disabled */ +#define USB_STAT_ENABLE_ON ((uint32_t)0x00000100U) /* !< Peripheral is enabled */ +/* USB_STAT[RESETSTKY] Bits */ +#define USB_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */ +#define USB_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the + peripheral was reset, since this bit + was cleared by RESETSTKYCLR in the + RSTCTL register */ +#define USB_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset + since this bit was last cleared by + RESETSTKYCLR in the RSTCTL register */ +#define USB_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the + last bit clear */ +/* USB_STAT[SWENABLE] Bits */ +#define USB_STAT_SWENABLE_OFS (0) /* !< SWENABLE Offset */ +#define USB_STAT_SWENABLE_MASK ((uint32_t)0x00000001U) /* !< Software enable status. Shows if + enabled via PWREN.ENABLE bit */ +#define USB_STAT_SWENABLE_DISABLED ((uint32_t)0x00000000U) /* !< Not enabled via PWREN.ENABLE bit */ +#define USB_STAT_SWENABLE_ENABLED ((uint32_t)0x00000001U) /* !< Enabled via PWREN.ENABLE bit */ + +/* USB_EVT_MODE Bits */ +/* USB_EVT_MODE[EVT0_CFG] Bits */ +#define USB_EVT_MODE_EVT0_CFG_OFS (0) /* !< EVT0_CFG Offset */ +#define USB_EVT_MODE_EVT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for event + corresponding to + (IPSTANDARD.INT_EVENT)(0) */ +#define USB_EVT_MODE_EVT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is + disabled. */ +#define USB_EVT_MODE_EVT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in + software mode. Software must clear + the RIS. */ +#define USB_EVT_MODE_EVT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in + hardware mode. The hardware (another + module) clears automatically the + associated RIS flag. */ + +/* USB_DESC Bits */ +/* USB_DESC[MINREV] Bits */ +#define USB_DESC_MINREV_OFS (0) /* !< MINREV Offset */ +#define USB_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */ +#define USB_DESC_MINREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define USB_DESC_MINREV_MAXIMUM ((uint32_t)0x0000000FU) /* !< Highest possible value */ +/* USB_DESC[MAJREV] Bits */ +#define USB_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */ +#define USB_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */ +#define USB_DESC_MAJREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define USB_DESC_MAJREV_MAXIMUM ((uint32_t)0x000000F0U) /* !< Highest possible value */ +/* USB_DESC[FEATUREVER] Bits */ +#define USB_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */ +#define USB_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module + *instance* */ +#define USB_DESC_FEATUREVER_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define USB_DESC_FEATUREVER_MAXIMUM ((uint32_t)0x0000F000U) /* !< Highest possible value */ +/* USB_DESC[MODULEID] Bits */ +#define USB_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */ +#define USB_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a + unique peripheral identification + number. The assignments are + maintained in a central database for + all of the platform modules to ensure + uniqueness. */ +#define USB_DESC_MODULEID_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */ +#define USB_DESC_MODULEID_MAXIMUM ((uint32_t)0xFFFF0000U) /* !< Highest possible value */ + +/* USB_USBMODE Bits */ +/* USB_USBMODE[HOST] Bits */ +#define USB_USBMODE_HOST_OFS (0) /* !< HOST Offset */ +#define USB_USBMODE_HOST_MASK ((uint32_t)0x00000001U) /* !< USB is configured as HOST mode */ +#define USB_USBMODE_HOST_DISABLE ((uint32_t)0x00000000U) /* !< USB is configured as DEVICE or + HOST. */ +#define USB_USBMODE_HOST_ENABLE ((uint32_t)0x00000001U) /* !< USB is configured as HOST */ +/* USB_USBMODE[DEVICEONLY] Bits */ +#define USB_USBMODE_DEVICEONLY_OFS (1) /* !< DEVICEONLY Offset */ +#define USB_USBMODE_DEVICEONLY_MASK ((uint32_t)0x00000002U) /* !< USB is configured as DEVICE_ONLY + mode */ +#define USB_USBMODE_DEVICEONLY_DISABLE ((uint32_t)0x00000000U) /* !< USB is configured as DEVICE or + HOST. */ +#define USB_USBMODE_DEVICEONLY_ENABLE ((uint32_t)0x00000002U) /* !< USB is configured as DEVICE only + mode. */ +/* USB_USBMODE[PHYMODE] Bits */ +#define USB_USBMODE_PHYMODE_OFS (4) /* !< PHYMODE Offset */ +#define USB_USBMODE_PHYMODE_MASK ((uint32_t)0x00000010U) /* !< USB PHY mode. Defines whether + DP/DM pins are controled by USB + module or IOMUX/GPIO module. */ +#define USB_USBMODE_PHYMODE_GPIO ((uint32_t)0x00000000U) /* !< The DP/DM pins are assighed to + IOMUX/GPIO module, */ +#define USB_USBMODE_PHYMODE_USB ((uint32_t)0x00000010U) /* !< The DP/DM pins are assighed to USB + module. */ + +/* USB_USBMONITOR Bits */ +/* USB_USBMONITOR[VUSBEN] Bits */ +#define USB_USBMONITOR_VUSBEN_OFS (0) /* !< VUSBEN Offset */ +#define USB_USBMONITOR_VUSBEN_MASK ((uint32_t)0x00000001U) /* !< Enable the 1/3 resistor divider for + VUSB supply. Set this bit to monitor + the VUSB supply with the ADC. */ +#define USB_USBMONITOR_VUSBEN_DISABLE ((uint32_t)0x00000000U) /* !< VUSB monitor disabled */ +#define USB_USBMONITOR_VUSBEN_ENABLE ((uint32_t)0x00000001U) /* !< VUSB monitor enabled */ + +/* USB_USBDMASEL Bits */ +/* USB_USBDMASEL[TRIGARX] Bits */ +#define USB_USBDMASEL_TRIGARX_OFS (0) /* !< TRIGARX Offset */ +#define USB_USBDMASEL_TRIGARX_MASK ((uint32_t)0x00000007U) /* !< TRIG A RX select specifies the RX + mapping of the USB endpoint on DMA + trigger USB-A-RX */ +#define USB_USBDMASEL_TRIGARX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGARX_EP1 ((uint32_t)0x00000001U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGARX_EP2 ((uint32_t)0x00000002U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGARX_EP3 ((uint32_t)0x00000003U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGARX_EP4 ((uint32_t)0x00000004U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGARX_EP5 ((uint32_t)0x00000005U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGARX_EP6 ((uint32_t)0x00000006U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGARX_EP7 ((uint32_t)0x00000007U) /* !< Endpoint 7 */ +/* USB_USBDMASEL[TRIGATX] Bits */ +#define USB_USBDMASEL_TRIGATX_OFS (4) /* !< TRIGATX Offset */ +#define USB_USBDMASEL_TRIGATX_MASK ((uint32_t)0x00000070U) /* !< TRIG A TX select specifies the TX + mapping of the USB endpoint on DMA + trigger USB-A-TX */ +#define USB_USBDMASEL_TRIGATX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGATX_EP1 ((uint32_t)0x00000010U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGATX_EP2 ((uint32_t)0x00000020U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGATX_EP3 ((uint32_t)0x00000030U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGATX_EP4 ((uint32_t)0x00000040U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGATX_EP5 ((uint32_t)0x00000050U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGATX_EP6 ((uint32_t)0x00000060U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGATX_EP7 ((uint32_t)0x00000070U) /* !< Endpoint 7 */ +/* USB_USBDMASEL[TRIGBRX] Bits */ +#define USB_USBDMASEL_TRIGBRX_OFS (8) /* !< TRIGBRX Offset */ +#define USB_USBDMASEL_TRIGBRX_MASK ((uint32_t)0x00000700U) /* !< TRIG B RX select specifies the RX + mapping of the USB endpoint on DMA + trigger USB-B-RX */ +#define USB_USBDMASEL_TRIGBRX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGBRX_EP1 ((uint32_t)0x00000100U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGBRX_EP2 ((uint32_t)0x00000200U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGBRX_EP3 ((uint32_t)0x00000300U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGBRX_EP4 ((uint32_t)0x00000400U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGBRX_EP5 ((uint32_t)0x00000500U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGBRX_EP6 ((uint32_t)0x00000600U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGBRX_EP7 ((uint32_t)0x00000700U) /* !< Endpoint 7 */ +/* USB_USBDMASEL[TRIGBTX] Bits */ +#define USB_USBDMASEL_TRIGBTX_OFS (12) /* !< TRIGBTX Offset */ +#define USB_USBDMASEL_TRIGBTX_MASK ((uint32_t)0x00007000U) /* !< TRIG B TX select specifies the TX + mapping of the USB endpoint on DMA + trigger USB-B-TX */ +#define USB_USBDMASEL_TRIGBTX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGBTX_EP1 ((uint32_t)0x00001000U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGBTX_EP2 ((uint32_t)0x00002000U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGBTX_EP3 ((uint32_t)0x00003000U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGBTX_EP4 ((uint32_t)0x00004000U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGBTX_EP5 ((uint32_t)0x00005000U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGBTX_EP6 ((uint32_t)0x00006000U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGBTX_EP7 ((uint32_t)0x00007000U) /* !< Endpoint 7 */ +/* USB_USBDMASEL[TRIGCRX] Bits */ +#define USB_USBDMASEL_TRIGCRX_OFS (16) /* !< TRIGCRX Offset */ +#define USB_USBDMASEL_TRIGCRX_MASK ((uint32_t)0x00070000U) /* !< TRIG C RX select specifies the RX + mapping of the USB endpoint on DMA + trigger USB-C-RX */ +#define USB_USBDMASEL_TRIGCRX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGCRX_EP1 ((uint32_t)0x00010000U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGCRX_EP2 ((uint32_t)0x00020000U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGCRX_EP3 ((uint32_t)0x00030000U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGCRX_EP4 ((uint32_t)0x00040000U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGCRX_EP5 ((uint32_t)0x00050000U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGCRX_EP6 ((uint32_t)0x00060000U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGCRX_EP7 ((uint32_t)0x00070000U) /* !< Endpoint 7 */ +/* USB_USBDMASEL[TRIGCTX] Bits */ +#define USB_USBDMASEL_TRIGCTX_OFS (20) /* !< TRIGCTX Offset */ +#define USB_USBDMASEL_TRIGCTX_MASK ((uint32_t)0x00700000U) /* !< TRIG C TX select specifies the TX + mapping of the USB endpoint on DMA + trigger USB-C-TX */ +#define USB_USBDMASEL_TRIGCTX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGCTX_EP1 ((uint32_t)0x00100000U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGCTX_EP2 ((uint32_t)0x00200000U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGCTX_EP3 ((uint32_t)0x00300000U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGCTX_EP4 ((uint32_t)0x00400000U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGCTX_EP5 ((uint32_t)0x00500000U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGCTX_EP6 ((uint32_t)0x00600000U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGCTX_EP7 ((uint32_t)0x00700000U) /* !< Endpoint 7 */ +/* USB_USBDMASEL[TRIGDRX] Bits */ +#define USB_USBDMASEL_TRIGDRX_OFS (24) /* !< TRIGDRX Offset */ +#define USB_USBDMASEL_TRIGDRX_MASK ((uint32_t)0x07000000U) /* !< TRIG D RX select specifies the RX + mapping of the USB endpoint on DMA + trigger USB-D-RX */ +#define USB_USBDMASEL_TRIGDRX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGDRX_EP1 ((uint32_t)0x01000000U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGDRX_EP2 ((uint32_t)0x02000000U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGDRX_EP3 ((uint32_t)0x03000000U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGDRX_EP4 ((uint32_t)0x04000000U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGDRX_EP5 ((uint32_t)0x05000000U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGDRX_EP6 ((uint32_t)0x06000000U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGDRX_EP7 ((uint32_t)0x07000000U) /* !< Endpoint 7 */ +/* USB_USBDMASEL[TRIGDTX] Bits */ +#define USB_USBDMASEL_TRIGDTX_OFS (28) /* !< TRIGDTX Offset */ +#define USB_USBDMASEL_TRIGDTX_MASK ((uint32_t)0x70000000U) /* !< TRIG D TX select specifies the TX + mapping of the USB endpoint on DMA + trigger USB-D-TX */ +#define USB_USBDMASEL_TRIGDTX_DIS ((uint32_t)0x00000000U) /* !< Disabled */ +#define USB_USBDMASEL_TRIGDTX_EP1 ((uint32_t)0x10000000U) /* !< Endpoint 1 */ +#define USB_USBDMASEL_TRIGDTX_EP2 ((uint32_t)0x20000000U) /* !< Endpoint 2 */ +#define USB_USBDMASEL_TRIGDTX_EP3 ((uint32_t)0x30000000U) /* !< Endpoint 3 */ +#define USB_USBDMASEL_TRIGDTX_EP4 ((uint32_t)0x40000000U) /* !< Endpoint 4 */ +#define USB_USBDMASEL_TRIGDTX_EP5 ((uint32_t)0x50000000U) /* !< Endpoint 5 */ +#define USB_USBDMASEL_TRIGDTX_EP6 ((uint32_t)0x60000000U) /* !< Endpoint 6 */ +#define USB_USBDMASEL_TRIGDTX_EP7 ((uint32_t)0x70000000U) /* !< Endpoint 7 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_hw_usb__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/hw_vref.h b/mspm0/source/ti/devices/msp/peripherals/hw_vref.h index 6f6671f..64f9b6a 100644 --- a/mspm0/source/ti/devices/msp/peripherals/hw_vref.h +++ b/mspm0/source/ti/devices/msp/peripherals/hw_vref.h @@ -1,33 +1,33 @@ /***************************************************************************** - Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright + Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ @@ -36,8 +36,8 @@ #define ti_devices_msp_peripherals_hw_vref__include /* Filename: hw_vref.h */ -/* Revised: 2023-05-10 21:34:47 */ -/* Revision: 346daa750fb9270ab4d9c503b44addb19c7cc8cc */ +/* Revised: 2025-09-02 22:58:34 */ +/* Revision: 46c5772b5c087a3277379fbff0316007e1d65e70 */ #ifndef __CORTEX_M #ifdef __cplusplus @@ -178,11 +178,12 @@ typedef struct { enabled */ /* VREF_CTL0 Bits */ -/* VREF_CTL0[ENABLE] Bits */ -#define VREF_CTL0_ENABLE_OFS (0) /* !< ENABLE Offset */ -#define VREF_CTL0_ENABLE_MASK ((uint32_t)0x00000001U) /* !< This bit enables the VREF module. */ -#define VREF_CTL0_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< VREF is disabled */ -#define VREF_CTL0_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< VREF is enabled */ + +/* VREF_CTL0[ENABLE0] Bits */ +#define VREF_CTL0_ENABLE0_OFS (0) /* !< ENABLE0 Offset */ +#define VREF_CTL0_ENABLE0_MASK ((uint32_t)0x00000001U) /* !< This bit enables the VREF0 */ +#define VREF_CTL0_ENABLE0_DISABLE ((uint32_t)0x00000000U) /* !< VREF0 is disabled */ +#define VREF_CTL0_ENABLE0_ENABLE ((uint32_t)0x00000001U) /* !< VREF0 is enabled */ /* VREF_CTL0[BUFCONFIG] Bits */ #define VREF_CTL0_BUFCONFIG_OFS (7) /* !< BUFCONFIG Offset */ #define VREF_CTL0_BUFCONFIG_MASK ((uint32_t)0x00000080U) /* !< These bits configure output buffer. */ @@ -194,18 +195,33 @@ typedef struct { mode */ #define VREF_CTL0_SHMODE_DISABLE ((uint32_t)0x00000000U) /* !< Sample and hold mode is disable */ #define VREF_CTL0_SHMODE_ENABLE ((uint32_t)0x00000100U) /* !< Sample and hold mode is enable */ -/* VREF_CTL0[COMP_VREF_ENABLE] Bits */ -#define VREF_CTL0_COMP_VREF_ENABLE_OFS (1) /* !< COMP_VREF_ENABLE Offset */ -#define VREF_CTL0_COMP_VREF_ENABLE_MASK ((uint32_t)0x00000002U) /* !< Comparator Vref Enable */ -#define VREF_CTL0_COMP_VREF_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< COMP VREF is disabled */ -#define VREF_CTL0_COMP_VREF_ENABLE_ENABLE ((uint32_t)0x00000002U) /* !< COMP VREF is enabled */ +/* VREF_CTL0[ENABLE1] Bits */ +#define VREF_CTL0_ENABLE1_OFS (1) /* !< ENABLE1 Offset */ +#define VREF_CTL0_ENABLE1_MASK ((uint32_t)0x00000002U) /* !< This bit enables the VREF1 */ +#define VREF_CTL0_ENABLE1_DISABLE ((uint32_t)0x00000000U) /* !< VREF1 is disabled */ +#define VREF_CTL0_ENABLE1_ENABLE ((uint32_t)0x00000002U) /* !< VREF1 is enabled */ +/* VREF_CTL0[ENABLE2] Bits */ +#define VREF_CTL0_ENABLE2_OFS (2) /* !< ENABLE2 Offset */ +#define VREF_CTL0_ENABLE2_MASK ((uint32_t)0x00000004U) /* !< This bit enables the VREF2 */ +#define VREF_CTL0_ENABLE2_DISABLE ((uint32_t)0x00000000U) /* !< VREF2 is disabled */ +#define VREF_CTL0_ENABLE2_ENABLE ((uint32_t)0x00000004U) /* !< VREF2 is enabled */ /* VREF_CTL1 Bits */ -/* VREF_CTL1[READY] Bits */ -#define VREF_CTL1_READY_OFS (0) /* !< READY Offset */ -#define VREF_CTL1_READY_MASK ((uint32_t)0x00000001U) /* !< These bits defines status of VREF */ -#define VREF_CTL1_READY_NOTRDY ((uint32_t)0x00000000U) /* !< VREF output is not ready */ -#define VREF_CTL1_READY_RDY ((uint32_t)0x00000001U) /* !< VREF output is ready */ +/* VREF_CTL1[READY0] Bits */ +#define VREF_CTL1_READY0_OFS (0) /* !< READY0 Offset */ +#define VREF_CTL1_READY0_MASK ((uint32_t)0x00000001U) /* !< These bits defines status of VREF0 */ +#define VREF_CTL1_READY0_NOTRDY ((uint32_t)0x00000000U) /* !< VREF0 not ready */ +#define VREF_CTL1_READY0_RDY ((uint32_t)0x00000001U) /* !< VREF ready */ +/* VREF_CTL1[READY1] Bits */ +#define VREF_CTL1_READY1_OFS (2) /* !< READY1 Offset */ +#define VREF_CTL1_READY1_MASK ((uint32_t)0x00000004U) /* !< These bits defines status of VREF1 */ +#define VREF_CTL1_READY1_NOTRDY ((uint32_t)0x00000000U) /* !< VREF1 not Ready */ +#define VREF_CTL1_READY1_RDY ((uint32_t)0x00000004U) /* !< VREF1 ready */ +/* VREF_CTL1[READY2] Bits */ +#define VREF_CTL1_READY2_OFS (3) /* !< READY2 Offset */ +#define VREF_CTL1_READY2_MASK ((uint32_t)0x00000008U) /* !< These bits defines status of VREF2 */ +#define VREF_CTL1_READY2_NOTRDY ((uint32_t)0x00000000U) /* !< VREF2 not Ready */ +#define VREF_CTL1_READY2_RDY ((uint32_t)0x00000008U) /* !< VREF2 Ready */ /* VREF_CTL2 Bits */ /* VREF_CTL2[SHCYCLE] Bits */ @@ -237,6 +253,33 @@ typedef struct { #define VREF_CTL2_HCYCLE_MAXIMUM ((uint32_t)0xFFFF0000U) /* !< largest hold cycle */ +/****************************************************************************** +* VREF Register Backwards Compatible Control Bits +******************************************************************************/ +/* VREF_CTL1[READY] Bits */ +#define VREF_CTL1_READY_OFS VREF_CTL1_READY0_OFS /* !< READY Offset */ +#define VREF_CTL1_READY_MASK VREF_CTL1_READY0_MASK /* !< These bits defines status of VREF */ +#define VREF_CTL1_READY_NOTRDY VREF_CTL1_READY0_NOTRDY /* !< VREF output is not ready */ +#define VREF_CTL1_READY_RDY VREF_CTL1_READY0_RDY /* !< VREF output is ready */ + +/* VREF_CTL0[ENABLE] Bits */ +#define VREF_CTL0_ENABLE_OFS VREF_CTL0_ENABLE0_OFS /* !< ENABLE Offset */ +#define VREF_CTL0_ENABLE_MASK VREF_CTL0_ENABLE0_MASK /* !< This bit enables the VREF module. */ +#define VREF_CTL0_ENABLE_DISABLE VREF_CTL0_ENABLE0_DISABLE /* !< VREF is disabled */ +#define VREF_CTL0_ENABLE_ENABLE VREF_CTL0_ENABLE0_ENABLE /* !< VREF is enabled */ + +/* VREF_CTL0[COMP_VREF_ENABLE] Bits */ +#define VREF_CTL0_COMP_VREF_ENABLE_OFS VREF_CTL0_ENABLE1_OFS /* !< COMP_VREF_ENABLE Offset */ +#define VREF_CTL0_COMP_VREF_ENABLE_MASK VREF_CTL0_ENABLE1_MASK /* !< Comparator Vref Enable */ +#define VREF_CTL0_COMP_VREF_ENABLE_DISABLE VREF_CTL0_ENABLE1_DISABLE /* !< COMP VREF is disabled */ +#define VREF_CTL0_COMP_VREF_ENABLE_ENABLE VREF_CTL0_ENABLE1_ENABLE /* !< COMP VREF is enabled */ + +/* VREF_CTL0[ADC_VREF_ENABLE] Bits */ +#define VREF_CTL0_ADC_VREF_ENABLE_OFS VREF_CTL0_ENABLE2_OFS /* !< ADC_VREF_ENABLE Offset */ +#define VREF_CTL0_ADC_VREF_ENABLE_MASK VREF_CTL0_ENABLE2_MASK /* !< ADC Vref Enable */ +#define VREF_CTL0_ADC_VREF_ENABLE_DISABLE VREF_CTL0_ENABLE2_DISABLE /* !< ADC VREF is disabled */ +#define VREF_CTL0_ADC_VREF_ENABLE_ENABLE VREF_CTL0_ENABLE2_ENABLE /* !< ADC VREF is enabled */ + #ifdef __cplusplus } #endif diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/hw_factoryregion.h b/mspm0/source/ti/devices/msp/peripherals/m0p/hw_factoryregion.h index 59f2c32..ee3fb7b 100644 --- a/mspm0/source/ti/devices/msp/peripherals/m0p/hw_factoryregion.h +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/hw_factoryregion.h @@ -78,10 +78,18 @@ */ typedef struct { +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X) + __I uint32_t USERID; /* !< (@ 0x41C40000) Defined by TI, depending on device spin */ +#else __I uint32_t TRACEID; /* !< (@ 0x41C40000) Defined by TI, during ATE, based on wafer */ +#endif __I uint32_t DEVICEID; /* !< (@ 0x41C40004) This is the JTAGIDCODE that comes from the Ramp system */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X) + __I uint32_t TRACEID; /* !< (@ 0x41C40008) Defined by TI, during ATE, based on wafer */ +#else __I uint32_t USERID; /* !< (@ 0x41C40008) Defined by TI, depending on device spin */ +#endif __I uint32_t BSLPIN_UART; /* !< (@ 0x41C4000C) BSL UART Pin Configuration */ __I uint32_t BSLPIN_I2C; /* !< (@ 0x41C40010) BSL I2C Pin Configuration */ __I uint32_t BSLPIN_INVOKE; /* !< (@ 0x41C40014) BSL Pin Invocation Configuration */ diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/hw_sysctl.h b/mspm0/source/ti/devices/msp/peripherals/m0p/hw_sysctl.h index 0dae7e4..010e39a 100644 --- a/mspm0/source/ti/devices/msp/peripherals/m0p/hw_sysctl.h +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/hw_sysctl.h @@ -56,10 +56,20 @@ #include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X) #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X) +#include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X) #include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X) #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C1105_C1106) +#include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G511X) +#include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G518X) +#include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L211X_L112X) +#include /******************************************************************** * ********************************************************************/ diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0c1105_c1106.h b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0c1105_c1106.h new file mode 100644 index 0000000..bdfcc10 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0c1105_c1106.h @@ -0,0 +1,1405 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c1105_c1106__include +#define ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c1105_c1106__include + +/* Filename: hw_sysctl_mspm0c1105_c1106.h */ +/* Revised: 2024-09-26 16:14:17 */ +/* Revision: 7df7b58d4d629d02f0e180265303985d8e32c137 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* SYSCTL Registers +******************************************************************************/ +#define SYSCTL_SECCFG_OFS ((uint32_t)0x00003000U) +#define SYSCTL_SOCLOCK_OFS ((uint32_t)0x00001000U) + + +/** @addtogroup SYSCTL_SECCFG + @{ +*/ + +typedef struct { + __IO uint32_t FWEPROTMAIN; /* !< (@ 0x00003000) 1 Sector Write-Erase per bit starting at address + 0x0 of flash */ + uint32_t RESERVED0[5]; + __IO uint32_t FRXPROTMAINSTART; /* !< (@ 0x00003018) Flash RX Protection Start Address */ + __IO uint32_t FRXPROTMAINEND; /* !< (@ 0x0000301C) Flash RX Protection End Address */ + __IO uint32_t FIPPROTMAINSTART; /* !< (@ 0x00003020) Flash IP Protection Start Address */ + __IO uint32_t FIPPROTMAINEND; /* !< (@ 0x00003024) Flash IP Protection End Address */ + uint32_t RESERVED1[7]; + __O uint32_t FWENABLE; /* !< (@ 0x00003044) Security Firewall Enable Register */ + __I uint32_t SECSTATUS; /* !< (@ 0x00003048) Security Configuration status */ + uint32_t RESERVED2[5]; + __O uint32_t INITDONE; /* !< (@ 0x00003060) INITCODE PASS */ +} SYSCTL_SECCFG_Regs; + +/*@}*/ /* end of group SYSCTL_SECCFG */ + +/** @addtogroup SYSCTL_SOCLOCK + @{ +*/ + +typedef struct { + uint32_t RESERVED0[8]; + __I uint32_t IIDX; /* !< (@ 0x00001020) SYSCTL interrupt index */ + uint32_t RESERVED1; + __IO uint32_t IMASK; /* !< (@ 0x00001028) SYSCTL interrupt mask */ + uint32_t RESERVED2; + __I uint32_t RIS; /* !< (@ 0x00001030) SYSCTL raw interrupt status */ + uint32_t RESERVED3; + __I uint32_t MIS; /* !< (@ 0x00001038) SYSCTL masked interrupt status */ + uint32_t RESERVED4; + __O uint32_t ISET; /* !< (@ 0x00001040) SYSCTL interrupt set */ + uint32_t RESERVED5; + __O uint32_t ICLR; /* !< (@ 0x00001048) SYSCTL interrupt clear */ + uint32_t RESERVED6; + __I uint32_t NMIIIDX; /* !< (@ 0x00001050) NMI interrupt index */ + uint32_t RESERVED7[3]; + __I uint32_t NMIRIS; /* !< (@ 0x00001060) NMI raw interrupt status */ + uint32_t RESERVED8[3]; + __O uint32_t NMIISET; /* !< (@ 0x00001070) NMI interrupt set */ + uint32_t RESERVED9; + __O uint32_t NMIICLR; /* !< (@ 0x00001078) NMI interrupt clear */ + uint32_t RESERVED10[33]; + __IO uint32_t SYSOSCCFG; /* !< (@ 0x00001100) SYSOSC configuration */ + __IO uint32_t MCLKCFG; /* !< (@ 0x00001104) Main clock (MCLK) configuration */ + __IO uint32_t HSCLKEN; /* !< (@ 0x00001108) High-speed clock (HSCLK) source enable/disable */ + __IO uint32_t HSCLKCFG; /* !< (@ 0x0000110C) High-speed clock (HSCLK) source selection */ + __IO uint32_t HFCLKCLKCFG; /* !< (@ 0x00001110) High-frequency clock (HFCLK) configuration */ + __IO uint32_t LFCLKCFG; /* !< (@ 0x00001114) Low frequency crystal oscillator (LFXT) + configuration */ + uint32_t RESERVED11[8]; + __IO uint32_t GENCLKCFG; /* !< (@ 0x00001138) General clock configuration */ + __IO uint32_t GENCLKEN; /* !< (@ 0x0000113C) General clock enable control */ + __IO uint32_t PMODECFG; /* !< (@ 0x00001140) Power mode configuration */ + uint32_t RESERVED12[3]; + __I uint32_t FCC; /* !< (@ 0x00001150) Frequency clock counter (FCC) count */ + uint32_t RESERVED13[9]; + __IO uint32_t SRAMBOUNDARY; /* !< (@ 0x00001178) SRAM Write Boundary */ + uint32_t RESERVED14; + __IO uint32_t SYSTEMCFG; /* !< (@ 0x00001180) System configuration */ + uint32_t RESERVED15[3]; + __IO uint32_t BEEPCFG; /* !< (@ 0x00001190) BEEPER Configuration */ + uint32_t RESERVED16[27]; + __IO uint32_t WRITELOCK; /* !< (@ 0x00001200) SYSCTL register write lockout */ + __I uint32_t CLKSTATUS; /* !< (@ 0x00001204) Clock module (CKM) status */ + __I uint32_t SYSSTATUS; /* !< (@ 0x00001208) System status information */ + uint32_t RESERVED17[5]; + __I uint32_t RSTCAUSE; /* !< (@ 0x00001220) Reset cause */ + uint32_t RESERVED18[55]; + __IO uint32_t RESETLEVEL; /* !< (@ 0x00001300) Reset level for application-triggered reset + command */ + __O uint32_t RESETCMD; /* !< (@ 0x00001304) Execute an application-triggered reset command */ + __IO uint32_t BORTHRESHOLD; /* !< (@ 0x00001308) BOR threshold selection */ + __O uint32_t BORCLRCMD; /* !< (@ 0x0000130C) Set the BOR threshold */ + __O uint32_t SYSOSCFCLCTL; /* !< (@ 0x00001310) SYSOSC frequency correction loop (FCL) ROSC enable */ + __O uint32_t LFXTCTL; /* !< (@ 0x00001314) LFXT and LFCLK control */ + __O uint32_t EXLFCTL; /* !< (@ 0x00001318) LFCLK_IN and LFCLK control */ + __O uint32_t SHDNIOREL; /* !< (@ 0x0000131C) SHUTDOWN IO release control */ + __O uint32_t EXRSTPIN; /* !< (@ 0x00001320) Disable the reset function of the NRST pin */ + __O uint32_t SYSSTATUSCLR; /* !< (@ 0x00001324) Clear sticky bits of SYSSTATUS */ + __O uint32_t SWDCFG; /* !< (@ 0x00001328) Disable the SWD function on the SWD pins */ + __O uint32_t FCCCMD; /* !< (@ 0x0000132C) Frequency clock counter start capture */ + uint32_t RESERVED19[52]; + __IO uint32_t SHUTDNSTORE0; /* !< (@ 0x00001400) Shutdown storage memory (byte 0) */ + __IO uint32_t SHUTDNSTORE1; /* !< (@ 0x00001404) Shutdown storage memory (byte 1) */ + __IO uint32_t SHUTDNSTORE2; /* !< (@ 0x00001408) Shutdown storage memory (byte 2) */ + __IO uint32_t SHUTDNSTORE3; /* !< (@ 0x0000140C) Shutdown storage memory (byte 3) */ +} SYSCTL_SOCLOCK_Regs; + +/*@}*/ /* end of group SYSCTL_SOCLOCK */ + +/** @addtogroup SYSCTL + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + SYSCTL_SOCLOCK_Regs SOCLOCK; /* !< (@ 0x00001000) SYSCTL SOCLOCK Region */ + uint32_t RESERVED1[1788]; + SYSCTL_SECCFG_Regs SECCFG; /* !< (@ 0x00003000) SYSCTL SECCFG Region */ +} SYSCTL_Regs; + +/*@}*/ /* end of group SYSCTL */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* SYSCTL Register Control Bits +******************************************************************************/ + +/* SYSCTL_FWEPROTMAIN Bits */ +/* SYSCTL_FWEPROTMAIN[DATA] Bits */ +#define SYSCTL_FWEPROTMAIN_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWEPROTMAIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< 1 Sector Write Erase protection 1: + prohibits write-erase, 0: allows */ + +/* SYSCTL_FRXPROTMAINSTART Bits */ +/* SYSCTL_FRXPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection Start Address + 64B granularity */ + +/* SYSCTL_FRXPROTMAINEND Bits */ +/* SYSCTL_FRXPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection End Address 64B + granularity */ + +/* SYSCTL_FIPPROTMAINSTART Bits */ +/* SYSCTL_FIPPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection Start Address + 64B granularity */ + +/* SYSCTL_FIPPROTMAINEND Bits */ +/* SYSCTL_FIPPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection End Address 64B + granularity */ + +/* SYSCTL_FWENABLE Bits */ +/* SYSCTL_FWENABLE[KEY] Bits */ +#define SYSCTL_FWENABLE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FWENABLE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x76(118) for write */ +#define SYSCTL_FWENABLE_KEY_VALUE ((uint32_t)0x76000000U) /* !< Write Key */ +/* SYSCTL_FWENABLE[FLIPPROT] Bits */ +#define SYSCTL_FWENABLE_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_FWENABLE_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash Read IP ProtectionActive */ +#define SYSCTL_FWENABLE_FLIPPROT_ENABLE ((uint32_t)0x00000040U) /* !< Turn On Flash IP Protection */ +/* SYSCTL_FWENABLE[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: Blocks Writes from Changing + SRAMBOUNDARY MMR */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE ((uint32_t)0x00000100U) /* !< SRAMBOUNDARY MMR Locked */ +/* SYSCTL_FWENABLE[FLRXPROT] Bits */ +#define SYSCTL_FWENABLE_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_FWENABLE_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_FWENABLE_FLRXPROT_ENABLE ((uint32_t)0x00000010U) /* !< Turn On Flash Read-eXecute + Protection */ + +/* SYSCTL_SECSTATUS Bits */ +/* SYSCTL_SECSTATUS[FLIPPROT] Bits */ +#define SYSCTL_SECSTATUS_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_SECSTATUS_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash IP Protection Active */ +#define SYSCTL_SECSTATUS_FLIPPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLIPPROT_ENABLED ((uint32_t)0x00000040U) +/* SYSCTL_SECSTATUS[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: SRAM Boundary MMR Locked */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED ((uint32_t)0x00000100U) +/* SYSCTL_SECSTATUS[FLRXPROT] Bits */ +#define SYSCTL_SECSTATUS_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_SECSTATUS_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_SECSTATUS_FLRXPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLRXPROT_ENABLED ((uint32_t)0x00000010U) +/* SYSCTL_SECSTATUS[INITDONE] Bits */ +#define SYSCTL_SECSTATUS_INITDONE_OFS (0) /* !< INITDONE Offset */ +#define SYSCTL_SECSTATUS_INITDONE_MASK ((uint32_t)0x00000001U) /* !< 1: CSC has been completed */ +#define SYSCTL_SECSTATUS_INITDONE_NO ((uint32_t)0x00000000U) /* !< INIT is not yet done */ +#define SYSCTL_SECSTATUS_INITDONE_YES ((uint32_t)0x00000001U) /* !< INIT is done */ +/* SYSCTL_SECSTATUS[CSCEXISTS] Bits */ +#define SYSCTL_SECSTATUS_CSCEXISTS_OFS (2) /* !< CSCEXISTS Offset */ +#define SYSCTL_SECSTATUS_CSCEXISTS_MASK ((uint32_t)0x00000004U) /* !< 1: CSC Exists in the system */ +#define SYSCTL_SECSTATUS_CSCEXISTS_NO ((uint32_t)0x00000000U) /* !< System does not have a CSC */ +#define SYSCTL_SECSTATUS_CSCEXISTS_YES ((uint32_t)0x00000004U) /* !< System does have a CSC */ + +/* SYSCTL_INITDONE Bits */ +/* SYSCTL_INITDONE[KEY] Bits */ +#define SYSCTL_INITDONE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_INITDONE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x9D(157) for write */ +#define SYSCTL_INITDONE_KEY_VALUE ((uint32_t)0x9D000000U) /* !< Issue Reset */ +/* SYSCTL_INITDONE[PASS] Bits */ +#define SYSCTL_INITDONE_PASS_OFS (0) /* !< PASS Offset */ +#define SYSCTL_INITDONE_PASS_MASK ((uint32_t)0x00000001U) /* !< INITCODE writes 1 for PASS, left + unwritten a timeout will occur if not + blocked */ +#define SYSCTL_INITDONE_PASS_TRUE ((uint32_t)0x00000001U) /* !< INITCODE PASS */ + +/* SYSCTL_IIDX Bits */ +/* SYSCTL_IIDX[STAT] Bits */ +#define SYSCTL_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_IIDX_STAT_MASK ((uint32_t)0x00000007U) /* !< The SYSCTL interrupt index (IIDX) + register generates a value + corresponding to the highest priority + pending interrupt source. This value + may be used as an address offset for + fast, deterministic handling in the + interrupt service routine. A read of + the IIDX register will clear the + corresponding interrupt status in the + RIS and MIS registers. */ +#define SYSCTL_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_IIDX_STAT_LFOSCGOOD ((uint32_t)0x00000001U) /* !< LFOSCGOOD interrupt pending */ +#define SYSCTL_IIDX_STAT_ANACLKERR ((uint32_t)0x00000002U) +#define SYSCTL_IIDX_STAT_LFXTGOOD ((uint32_t)0x00000003U) +#define SYSCTL_IIDX_STAT_HFCLKGOOD ((uint32_t)0x00000004U) +#define SYSCTL_IIDX_STAT_HSCLKGOOD ((uint32_t)0x00000005U) + +/* SYSCTL_IMASK Bits */ +/* SYSCTL_IMASK[LFOSCGOOD] Bits */ +#define SYSCTL_IMASK_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_IMASK_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Enable or disable the LFOSCGOOD + interrupt. LFOSCGOOD indicates that + the LFOSC has started successfully. */ +#define SYSCTL_IMASK_LFOSCGOOD_DISABLE ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define SYSCTL_IMASK_LFOSCGOOD_ENABLE ((uint32_t)0x00000001U) /* !< Interrupt enabled */ +/* SYSCTL_IMASK[HFCLKGOOD] Bits */ +#define SYSCTL_IMASK_HFCLKGOOD_OFS (3) /* !< HFCLKGOOD Offset */ +#define SYSCTL_IMASK_HFCLKGOOD_MASK ((uint32_t)0x00000008U) /* !< HFCLK GOOD */ +#define SYSCTL_IMASK_HFCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HFCLKGOOD_ENABLE ((uint32_t)0x00000008U) +/* SYSCTL_IMASK[HSCLKGOOD] Bits */ +#define SYSCTL_IMASK_HSCLKGOOD_OFS (4) /* !< HSCLKGOOD Offset */ +#define SYSCTL_IMASK_HSCLKGOOD_MASK ((uint32_t)0x00000010U) /* !< HSCLK GOOD */ +#define SYSCTL_IMASK_HSCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HSCLKGOOD_ENABLE ((uint32_t)0x00000010U) +/* SYSCTL_IMASK[ANACLKERR] Bits */ +#define SYSCTL_IMASK_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_IMASK_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_IMASK_ANACLKERR_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_ANACLKERR_ENABLE ((uint32_t)0x00000002U) +/* SYSCTL_IMASK[LFXTGOOD] Bits */ +#define SYSCTL_IMASK_LFXTGOOD_OFS (2) /* !< LFXTGOOD Offset */ +#define SYSCTL_IMASK_LFXTGOOD_MASK ((uint32_t)0x00000004U) /* !< LFXT GOOD */ +#define SYSCTL_IMASK_LFXTGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_LFXTGOOD_ENABLE ((uint32_t)0x00000004U) + +/* SYSCTL_RIS Bits */ +/* SYSCTL_RIS[LFOSCGOOD] Bits */ +#define SYSCTL_RIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_RIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Raw status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_RIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_RIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_RIS[HFCLKGOOD] Bits */ +#define SYSCTL_RIS_HFCLKGOOD_OFS (3) /* !< HFCLKGOOD Offset */ +#define SYSCTL_RIS_HFCLKGOOD_MASK ((uint32_t)0x00000008U) /* !< HFCLK GOOD */ +#define SYSCTL_RIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HFCLKGOOD_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_RIS[HSCLKGOOD] Bits */ +#define SYSCTL_RIS_HSCLKGOOD_OFS (4) /* !< HSCLKGOOD Offset */ +#define SYSCTL_RIS_HSCLKGOOD_MASK ((uint32_t)0x00000010U) /* !< HSCLK GOOD */ +#define SYSCTL_RIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HSCLKGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_RIS[ANACLKERR] Bits */ +#define SYSCTL_RIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_RIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_RIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_RIS[LFXTGOOD] Bits */ +#define SYSCTL_RIS_LFXTGOOD_OFS (2) /* !< LFXTGOOD Offset */ +#define SYSCTL_RIS_LFXTGOOD_MASK ((uint32_t)0x00000004U) /* !< LFXT GOOD */ +#define SYSCTL_RIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_LFXTGOOD_TRUE ((uint32_t)0x00000004U) + +/* SYSCTL_MIS Bits */ +/* SYSCTL_MIS[LFOSCGOOD] Bits */ +#define SYSCTL_MIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_MIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Masked status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_MIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_MIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_MIS[HFCLKGOOD] Bits */ +#define SYSCTL_MIS_HFCLKGOOD_OFS (3) /* !< HFCLKGOOD Offset */ +#define SYSCTL_MIS_HFCLKGOOD_MASK ((uint32_t)0x00000008U) /* !< HFCLK GOOD */ +#define SYSCTL_MIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HFCLKGOOD_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_MIS[HSCLKGOOD] Bits */ +#define SYSCTL_MIS_HSCLKGOOD_OFS (4) /* !< HSCLKGOOD Offset */ +#define SYSCTL_MIS_HSCLKGOOD_MASK ((uint32_t)0x00000010U) /* !< HSCLK GOOD */ +#define SYSCTL_MIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HSCLKGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_MIS[ANACLKERR] Bits */ +#define SYSCTL_MIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_MIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_MIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_MIS[LFXTGOOD] Bits */ +#define SYSCTL_MIS_LFXTGOOD_OFS (2) /* !< LFXTGOOD Offset */ +#define SYSCTL_MIS_LFXTGOOD_MASK ((uint32_t)0x00000004U) /* !< LFXT GOOD */ +#define SYSCTL_MIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_LFXTGOOD_TRUE ((uint32_t)0x00000004U) + +/* SYSCTL_ISET Bits */ +/* SYSCTL_ISET[LFOSCGOOD] Bits */ +#define SYSCTL_ISET_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ISET_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Set the LFOSCGOOD interrupt. */ +#define SYSCTL_ISET_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_ISET_LFOSCGOOD_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_ISET[HFCLKGOOD] Bits */ +#define SYSCTL_ISET_HFCLKGOOD_OFS (3) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ISET_HFCLKGOOD_MASK ((uint32_t)0x00000008U) /* !< HFCLK GOOD */ +#define SYSCTL_ISET_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HFCLKGOOD_SET ((uint32_t)0x00000008U) +/* SYSCTL_ISET[HSCLKGOOD] Bits */ +#define SYSCTL_ISET_HSCLKGOOD_OFS (4) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ISET_HSCLKGOOD_MASK ((uint32_t)0x00000010U) /* !< HSCLK GOOD */ +#define SYSCTL_ISET_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HSCLKGOOD_SET ((uint32_t)0x00000010U) +/* SYSCTL_ISET[ANACLKERR] Bits */ +#define SYSCTL_ISET_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ISET_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ISET_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_ANACLKERR_SET ((uint32_t)0x00000002U) +/* SYSCTL_ISET[LFXTGOOD] Bits */ +#define SYSCTL_ISET_LFXTGOOD_OFS (2) /* !< LFXTGOOD Offset */ +#define SYSCTL_ISET_LFXTGOOD_MASK ((uint32_t)0x00000004U) /* !< LFXT GOOD */ +#define SYSCTL_ISET_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_LFXTGOOD_SET ((uint32_t)0x00000004U) + +/* SYSCTL_ICLR Bits */ +/* SYSCTL_ICLR[LFOSCGOOD] Bits */ +#define SYSCTL_ICLR_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ICLR_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Clear the LFOSCGOOD interrupt. */ +#define SYSCTL_ICLR_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h has no effect */ +#define SYSCTL_ICLR_LFOSCGOOD_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_ICLR[HFCLKGOOD] Bits */ +#define SYSCTL_ICLR_HFCLKGOOD_OFS (3) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ICLR_HFCLKGOOD_MASK ((uint32_t)0x00000008U) /* !< HFCLK GOOD */ +#define SYSCTL_ICLR_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HFCLKGOOD_CLR ((uint32_t)0x00000008U) +/* SYSCTL_ICLR[HSCLKGOOD] Bits */ +#define SYSCTL_ICLR_HSCLKGOOD_OFS (4) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ICLR_HSCLKGOOD_MASK ((uint32_t)0x00000010U) /* !< HSCLK GOOD */ +#define SYSCTL_ICLR_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HSCLKGOOD_CLR ((uint32_t)0x00000010U) +/* SYSCTL_ICLR[ANACLKERR] Bits */ +#define SYSCTL_ICLR_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ICLR_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ICLR_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_ANACLKERR_CLR ((uint32_t)0x00000002U) +/* SYSCTL_ICLR[LFXTGOOD] Bits */ +#define SYSCTL_ICLR_LFXTGOOD_OFS (2) /* !< LFXTGOOD Offset */ +#define SYSCTL_ICLR_LFXTGOOD_MASK ((uint32_t)0x00000004U) /* !< LFXT GOOD */ +#define SYSCTL_ICLR_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_LFXTGOOD_CLR ((uint32_t)0x00000004U) + +/* SYSCTL_NMIIIDX Bits */ +/* SYSCTL_NMIIIDX[STAT] Bits */ +#define SYSCTL_NMIIIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_NMIIIDX_STAT_MASK ((uint32_t)0x00000007U) /* !< The NMI interrupt index (NMIIIDX) + register generates a value + corresponding to the highest priority + pending NMI source. This value may + be used as an address offset for + fast, deterministic handling in the + NMI service routine. A read of the + NMIIIDX register will clear the + corresponding interrupt status in the + NMIRIS register. */ +#define SYSCTL_NMIIIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No NMI pending */ +#define SYSCTL_NMIIIDX_STAT_BORLVL ((uint32_t)0x00000001U) /* !< BOR Threshold NMI pending */ +#define SYSCTL_NMIIIDX_STAT_WWDT0 ((uint32_t)0x00000002U) +#define SYSCTL_NMIIIDX_STAT_LFCLKFAIL ((uint32_t)0x00000003U) + +/* SYSCTL_NMIRIS Bits */ +/* SYSCTL_NMIRIS[BORLVL] Bits */ +#define SYSCTL_NMIRIS_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIRIS_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Raw status of the BORLVL NMI */ +#define SYSCTL_NMIRIS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_NMIRIS_BORLVL_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_NMIRIS[WWDT0] Bits */ +#define SYSCTL_NMIRIS_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIRIS_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT0_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT0_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_NMIRIS[LFCLKFAIL] Bits */ +#define SYSCTL_NMIRIS_LFCLKFAIL_OFS (2) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIRIS_LFCLKFAIL_MASK ((uint32_t)0x00000004U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIRIS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_LFCLKFAIL_TRUE ((uint32_t)0x00000004U) + +/* SYSCTL_NMIISET Bits */ +/* SYSCTL_NMIISET[BORLVL] Bits */ +#define SYSCTL_NMIISET_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIISET_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Set the BORLVL NMI */ +#define SYSCTL_NMIISET_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIISET_BORLVL_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_NMIISET[WWDT0] Bits */ +#define SYSCTL_NMIISET_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIISET_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT0_SET ((uint32_t)0x00000002U) +/* SYSCTL_NMIISET[LFCLKFAIL] Bits */ +#define SYSCTL_NMIISET_LFCLKFAIL_OFS (2) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIISET_LFCLKFAIL_MASK ((uint32_t)0x00000004U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIISET_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_LFCLKFAIL_SET ((uint32_t)0x00000004U) + +/* SYSCTL_NMIICLR Bits */ +/* SYSCTL_NMIICLR[BORLVL] Bits */ +#define SYSCTL_NMIICLR_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIICLR_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Clr the BORLVL NMI */ +#define SYSCTL_NMIICLR_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIICLR_BORLVL_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_NMIICLR[WWDT0] Bits */ +#define SYSCTL_NMIICLR_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIICLR_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT0_CLR ((uint32_t)0x00000002U) +/* SYSCTL_NMIICLR[LFCLKFAIL] Bits */ +#define SYSCTL_NMIICLR_LFCLKFAIL_OFS (2) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIICLR_LFCLKFAIL_MASK ((uint32_t)0x00000004U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIICLR_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_LFCLKFAIL_CLR ((uint32_t)0x00000004U) + +/* SYSCTL_SYSOSCCFG Bits */ +/* SYSCTL_SYSOSCCFG[DISABLESTOP] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_OFS (9) /* !< DISABLESTOP Offset */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_MASK ((uint32_t)0x00000200U) /* !< DISABLESTOP sets the SYSOSC stop + mode enable/disable policy. When + operating in STOP mode, the SYSOSC + may be automatically disabled. When + set, ULPCLK will run from LFCLK in + STOP mode and SYSOSC will be disabled + to reduce power consumption. */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC in STOP mode */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE ((uint32_t)0x00000200U) /* !< Disable SYSOSC in STOP mode and + source ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[BLOCKASYNCALL] Bits */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_OFS (16) /* !< BLOCKASYNCALL Offset */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_MASK ((uint32_t)0x00010000U) /* !< BLOCKASYNCALL may be used to mask + block all asynchronous fast clock + requests, preventing hardware from + dynamically changing the active clock + configuration when operating in a + given mode. */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_DISABLE ((uint32_t)0x00000000U) /* !< Asynchronous fast clock requests + are controlled by the requesting + peripheral */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE ((uint32_t)0x00010000U) /* !< All asynchronous fast clock + requests are blocked */ +/* SYSCTL_SYSOSCCFG[DISABLE] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLE_OFS (10) /* !< DISABLE Offset */ +#define SYSCTL_SYSOSCCFG_DISABLE_MASK ((uint32_t)0x00000400U) /* !< DISABLE sets the SYSOSC + enable/disable policy. SYSOSC may be + powered off in RUN, SLEEP, and STOP + modes to reduce power consumption. + When SYSOSC is disabled, MCLK and + ULPCLK are sourced from LFCLK. */ +#define SYSCTL_SYSOSCCFG_DISABLE_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC */ +#define SYSCTL_SYSOSCCFG_DISABLE_ENABLE ((uint32_t)0x00000400U) /* !< Disable SYSOSC immediately and + source MCLK and ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[FASTCPUEVENT] Bits */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_OFS (17) /* !< FASTCPUEVENT Offset */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_MASK ((uint32_t)0x00020000U) /* !< FASTCPUEVENT may be used to assert + a fast clock request when an + interrupt is asserted to the CPU, + reducing interrupt latency. */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_DISABLE ((uint32_t)0x00000000U) /* !< An interrupt to the CPU will not + assert a fast clock request */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE ((uint32_t)0x00020000U) /* !< An interrupt to the CPU will assert + a fast clock request */ +/* SYSCTL_SYSOSCCFG[FREQ] Bits */ +#define SYSCTL_SYSOSCCFG_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCCFG_FREQ_MASK ((uint32_t)0x00000003U) /* !< Target operating frequency for the + system oscillator (SYSOSC) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE ((uint32_t)0x00000000U) /* !< Base frequency (32MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< Low frequency (4MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< User-trimmed frequency (16 or 24 + MHz) */ + +/* SYSCTL_MCLKCFG Bits */ +/* SYSCTL_MCLKCFG[USEMFTICK] Bits */ +#define SYSCTL_MCLKCFG_USEMFTICK_OFS (12) /* !< USEMFTICK Offset */ +#define SYSCTL_MCLKCFG_USEMFTICK_MASK ((uint32_t)0x00001000U) /* !< USEMFTICK specifies whether the + 4MHz constant-rate clock (MFCLK) to + peripherals is enabled or disabled. + When enabled, MDIV must be disabled + (set to 0h=/1). */ +#define SYSCTL_MCLKCFG_USEMFTICK_DISABLE ((uint32_t)0x00000000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled */ +#define SYSCTL_MCLKCFG_USEMFTICK_ENABLE ((uint32_t)0x00001000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled. */ +/* SYSCTL_MCLKCFG[MDIV] Bits */ +#define SYSCTL_MCLKCFG_MDIV_OFS (0) /* !< MDIV Offset */ +#define SYSCTL_MCLKCFG_MDIV_MASK ((uint32_t)0x0000000FU) /* !< MDIV may be used to divide the MCLK + frequency when MCLK is sourced from + SYSOSC. MDIV=0h corresponds to /1 + (no divider). MDIV=1h corresponds to + /2 (divide-by-2). MDIV=Fh + corresponds to /16 (divide-by-16). + MDIV may be set between /1 and /16 on + an integer basis. */ +/* SYSCTL_MCLKCFG[USEHSCLK] Bits */ +#define SYSCTL_MCLKCFG_USEHSCLK_OFS (16) /* !< USEHSCLK Offset */ +#define SYSCTL_MCLKCFG_USEHSCLK_MASK ((uint32_t)0x00010000U) /* !< USEHSCLK, together with USELFCLK, + sets the MCLK source policy. Set + USEHSCLK to use HSCLK (HFCLK or + SYSPLL) as the MCLK source in RUN and + SLEEP modes. */ +#define SYSCTL_MCLKCFG_USEHSCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the high speed + clock (HSCLK) */ +#define SYSCTL_MCLKCFG_USEHSCLK_ENABLE ((uint32_t)0x00010000U) /* !< MCLK will use the high speed clock + (HSCLK) in RUN and SLEEP mode */ +/* SYSCTL_MCLKCFG[USELFCLK] Bits */ +#define SYSCTL_MCLKCFG_USELFCLK_OFS (20) /* !< USELFCLK Offset */ +#define SYSCTL_MCLKCFG_USELFCLK_MASK ((uint32_t)0x00100000U) /* !< USELFCLK sets the MCLK source + policy. Set USELFCLK to use LFCLK as + the MCLK source. Note that setting + USELFCLK does not disable SYSOSC, and + SYSOSC remains available for direct + use by analog modules. */ +#define SYSCTL_MCLKCFG_USELFCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the low frequency + clock (LFCLK) */ +#define SYSCTL_MCLKCFG_USELFCLK_ENABLE ((uint32_t)0x00100000U) /* !< MCLK will use the low frequency + clock (LFCLK) */ +/* SYSCTL_MCLKCFG[STOPCLKSTBY] Bits */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_OFS (21) /* !< STOPCLKSTBY Offset */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_MASK ((uint32_t)0x00200000U) /* !< STOPCLKSTBY sets the STANDBY mode + policy (STANDBY0 or STANDBY1). When + set, ULPCLK and LFCLK are disabled to + all peripherals in STANDBY mode, with + the exception of TIMG0 and TIMG1 + which continue to run. Wake-up is + only possible via an asynchronous + fast clock request. */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_DISABLE ((uint32_t)0x00000000U) /* !< ULPCLK/LFCLK runs to all PD0 + peripherals in STANDBY mode */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE ((uint32_t)0x00200000U) /* !< ULPCLK/LFCLK is disabled to all + peripherals in STANDBY mode except + TIMG0 and TIMG1 */ +/* SYSCTL_MCLKCFG[FLASHWAIT] Bits */ +#define SYSCTL_MCLKCFG_FLASHWAIT_OFS (8) /* !< FLASHWAIT Offset */ +#define SYSCTL_MCLKCFG_FLASHWAIT_MASK ((uint32_t)0x00000F00U) /* !< FLASHWAIT specifies the number of + flash wait states when MCLK is + sourced from HSCLK. FLASHWAIT has no + effect when MCLK is sourced from + SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT0 ((uint32_t)0x00000000U) /* !< No flash wait states are applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT1 ((uint32_t)0x00000100U) /* !< One flash wait state is applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT2 ((uint32_t)0x00000200U) /* !< 2 flash wait states are applied */ +/* SYSCTL_MCLKCFG[MCLKDEADCHK] Bits */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_OFS (22) /* !< MCLKDEADCHK Offset */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_MASK ((uint32_t)0x00400000U) /* !< MCLKDEADCHK enables or disables the + continuous MCLK dead check monitor. + LFCLK must be running before + MCLKDEADCHK is enabled. */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_DISABLE ((uint32_t)0x00000000U) /* !< The MCLK dead check monitor is + disabled */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_ENABLE ((uint32_t)0x00400000U) /* !< The MCLK dead check monitor is + enabled */ + +/* SYSCTL_HSCLKEN Bits */ +/* SYSCTL_HSCLKEN[HFXTEN] Bits */ +#define SYSCTL_HSCLKEN_HFXTEN_OFS (0) /* !< HFXTEN Offset */ +#define SYSCTL_HSCLKEN_HFXTEN_MASK ((uint32_t)0x00000001U) /* !< HFXTEN enables or disables the high + frequency crystal oscillator (HFXT). */ +#define SYSCTL_HSCLKEN_HFXTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the HFXT */ +#define SYSCTL_HSCLKEN_HFXTEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable the HFXT */ +/* SYSCTL_HSCLKEN[USEEXTHFCLK] Bits */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_OFS (16) /* !< USEEXTHFCLK Offset */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_MASK ((uint32_t)0x00010000U) /* !< USEEXTHFCLK selects the HFCLK_IN + digital clock input to be the source + for HFCLK. When disabled, HFXT is + the HFCLK source and HFXTEN may be + set. Do not set HFXTEN and + USEEXTHFCLK simultaneously. */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_DISABLE ((uint32_t)0x00000000U) /* !< Use HFXT as the HFCLK source */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE ((uint32_t)0x00010000U) /* !< Use the HFCLK_IN digital clock + input as the HFCLK source */ + +/* SYSCTL_HSCLKCFG Bits */ +/* SYSCTL_HSCLKCFG[HSCLKSEL] Bits */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_OFS (0) /* !< HSCLKSEL Offset */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_MASK ((uint32_t)0x00000001U) /* !< HSCLKSEL selects the HSCLK source + (SYSPLL or HFCLK). */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK ((uint32_t)0x00000001U) /* !< HSCLK is sourced from the HFCLK */ + +/* SYSCTL_HFCLKCLKCFG Bits */ +/* SYSCTL_HFCLKCLKCFG[HFXTTIME] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_OFS (0) /* !< HFXTTIME Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK ((uint32_t)0x000000FFU) /* !< HFXTTIME specifies the HFXT startup + time in 64us resolution. If the + HFCLK startup monitor is enabled + (HFCLKFLTCHK), HFXT will be checked + after this time expires. */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MINSTARTTIME ((uint32_t)0x00000000U) /* !< Minimum startup time (approximatly + zero) */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MAXSTARTTIME ((uint32_t)0x000000FFU) /* !< Maximum startup time (approximatly + 16.32ms) */ +/* SYSCTL_HFCLKCLKCFG[HFCLKFLTCHK] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_OFS (28) /* !< HFCLKFLTCHK Offset */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK ((uint32_t)0x10000000U) /* !< HFCLKFLTCHK enables or disables the + HFCLK startup monitor. */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_DISABLE ((uint32_t)0x00000000U) /* !< HFCLK startup is not checked */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE ((uint32_t)0x10000000U) /* !< HFCLK startup is checked */ +/* SYSCTL_HFCLKCLKCFG[HFXTRSEL] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS (12) /* !< HFXTRSEL Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK ((uint32_t)0x00003000U) /* !< HFXT Range Select */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8 ((uint32_t)0x00000000U) /* !< 4MHz <= HFXT frequency <= 8MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16 ((uint32_t)0x00001000U) /* !< 8MHz < HFXT frequency <= 16MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32 ((uint32_t)0x00002000U) /* !< 16MHz < HFXT frequency <= 32MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48 ((uint32_t)0x00003000U) /* !< 32MHz < HFXT frequency <= 48MHz */ + +/* SYSCTL_LFCLKCFG Bits */ +/* SYSCTL_LFCLKCFG[XT1DRIVE] Bits */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_OFS (0) /* !< XT1DRIVE Offset */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_MASK ((uint32_t)0x00000003U) /* !< XT1DRIVE selects the low frequency + crystal oscillator (LFXT) drive + strength. */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV ((uint32_t)0x00000000U) /* !< Lowest drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV ((uint32_t)0x00000001U) /* !< Lower drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV ((uint32_t)0x00000002U) /* !< Higher drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV ((uint32_t)0x00000003U) /* !< Highest drive and current */ +/* SYSCTL_LFCLKCFG[MONITOR] Bits */ +#define SYSCTL_LFCLKCFG_MONITOR_OFS (4) /* !< MONITOR Offset */ +#define SYSCTL_LFCLKCFG_MONITOR_MASK ((uint32_t)0x00000010U) /* !< MONITOR enables or disables the + LFCLK monitor, which continuously + checks LFXT or LFCLK_IN for a clock + stuck fault. */ +#define SYSCTL_LFCLKCFG_MONITOR_DISABLE ((uint32_t)0x00000000U) /* !< Clock monitor is disabled */ +#define SYSCTL_LFCLKCFG_MONITOR_ENABLE ((uint32_t)0x00000010U) /* !< Clock monitor is enabled */ +/* SYSCTL_LFCLKCFG[LOWCAP] Bits */ +#define SYSCTL_LFCLKCFG_LOWCAP_OFS (8) /* !< LOWCAP Offset */ +#define SYSCTL_LFCLKCFG_LOWCAP_MASK ((uint32_t)0x00000100U) /* !< LOWCAP controls the low-power LFXT + mode. When the LFXT load capacitance + is less than 3pf, LOWCAP may be set + for reduced power consumption. */ +#define SYSCTL_LFCLKCFG_LOWCAP_DISABLE ((uint32_t)0x00000000U) /* !< LFXT low capacitance mode is + disabled */ +#define SYSCTL_LFCLKCFG_LOWCAP_ENABLE ((uint32_t)0x00000100U) /* !< LFXT low capacitance mode is + enabled */ + +/* SYSCTL_GENCLKCFG Bits */ +/* SYSCTL_GENCLKCFG[HFCLK4MFPCLKDIV] Bits */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS (12) /* !< HFCLK4MFPCLKDIV Offset */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK ((uint32_t)0x0000F000U) /* !< HFCLK4MFPCLKDIV selects the divider + applied to HFCLK when HFCLK is used + as the MFPCLK source. Integer + dividers from /1 to /16 may be + selected. */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV1 ((uint32_t)0x00000000U) /* !< HFCLK is not divided before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV2 ((uint32_t)0x00001000U) /* !< HFCLK is divided by 2 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV3 ((uint32_t)0x00002000U) /* !< HFCLK is divided by 3 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV4 ((uint32_t)0x00003000U) /* !< HFCLK is divided by 4 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV5 ((uint32_t)0x00004000U) /* !< HFCLK is divided by 5 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV6 ((uint32_t)0x00005000U) /* !< HFCLK is divided by 6 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV7 ((uint32_t)0x00006000U) /* !< HFCLK is divided by 7 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV8 ((uint32_t)0x00007000U) /* !< HFCLK is divided by 8 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV9 ((uint32_t)0x00008000U) /* !< HFCLK is divided by 9 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV10 ((uint32_t)0x00009000U) /* !< HFCLK is divided by 10 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV11 ((uint32_t)0x0000A000U) /* !< HFCLK is divided by 11 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV12 ((uint32_t)0x0000B000U) /* !< HFCLK is divided by 12 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV13 ((uint32_t)0x0000C000U) /* !< HFCLK is divided by 13 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV14 ((uint32_t)0x0000D000U) /* !< HFCLK is divided by 14 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV15 ((uint32_t)0x0000E000U) /* !< HFCLK is divided by 15 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV16 ((uint32_t)0x0000F000U) /* !< HFCLK is divided by 16 before being + used for MFPCLK */ +/* SYSCTL_GENCLKCFG[MFPCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_OFS (9) /* !< MFPCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_MASK ((uint32_t)0x00000200U) /* !< MFPCLKSRC selects the MFPCLK + (middle frequency precision clock) + source. */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< MFPCLK is sourced from SYSOSC */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK ((uint32_t)0x00000200U) /* !< MFPCLK is sourced from HFCLK */ +/* SYSCTL_GENCLKCFG[FCCLFCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_OFS (29) /* !< FCCLFCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_MASK ((uint32_t)0x20000000U) /* !< FCCLFCLKSRC selects between SYSTEM + LFCLK and EXTERNAL SOURCED LFCLK. */ +/* SYSCTL_GENCLKCFG[FCCTRIGCNT] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS (24) /* !< FCCTRIGCNT Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK ((uint32_t)0x1F000000U) /* !< FCCTRIGCNT specifies the number of + trigger clock periods in the trigger + window. FCCTRIGCNT=0h (one trigger + clock period) up to 1Fh (32 trigger + clock periods) may be specified. */ +/* SYSCTL_GENCLKCFG[ANACPUMPCFG] Bits */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_OFS (22) /* !< ANACPUMPCFG Offset */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK ((uint32_t)0x00C00000U) /* !< ANACPUMPCFG selects the analog mux + charge pump (VBOOST) enable method. */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND ((uint32_t)0x00000000U) /* !< VBOOST is enabled on request from a + COMP, GPAMP, or OPA */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE ((uint32_t)0x00400000U) /* !< VBOOST is enabled when the device + is in RUN or SLEEP mode, or when a + COMP/GPAMP/OPA is enabled */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS ((uint32_t)0x00800000U) /* !< VBOOST is always enabled */ +/* SYSCTL_GENCLKCFG[FCCSELCLK] Bits */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_OFS (16) /* !< FCCSELCLK Offset */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MASK ((uint32_t)0x000F0000U) /* !< FCCSELCLK selectes the frequency + clock counter (FCC) clock source. */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MCLK ((uint32_t)0x00000000U) /* !< FCC clock is MCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC ((uint32_t)0x00010000U) /* !< FCC clock is SYSOSC */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK ((uint32_t)0x00020000U) /* !< FCC clock is HFCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK ((uint32_t)0x00030000U) /* !< FCC clock is the CLK_OUT selection */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN ((uint32_t)0x00070000U) /* !< FCC clock is the FCCIN external + input */ +/* SYSCTL_GENCLKCFG[FCCTRIGSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_OFS (20) /* !< FCCTRIGSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK ((uint32_t)0x00100000U) /* !< FCCTRIGSRC selects the frequency + clock counter (FCC) trigger source. */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN ((uint32_t)0x00000000U) /* !< FCC trigger is the external pin */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK ((uint32_t)0x00100000U) /* !< FCC trigger is the LFCLK */ +/* SYSCTL_GENCLKCFG[FCCLVLTRIG] Bits */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_OFS (21) /* !< FCCLVLTRIG Offset */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK ((uint32_t)0x00200000U) /* !< FCCLVLTRIG selects the frequency + clock counter (FCC) trigger mode. */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE ((uint32_t)0x00000000U) /* !< Rising edge to rising edge + triggered */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL ((uint32_t)0x00200000U) /* !< Level triggered */ +/* SYSCTL_GENCLKCFG[EXCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_OFS (0) /* !< EXCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MASK ((uint32_t)0x00000007U) /* !< EXCLKSRC selects the source for the + CLK_OUT external clock output block. + ULPCLK and MFPCLK require the CLK_OUT + divider (EXCLKDIVEN) to be enabled */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< CLK_OUT is SYSOSC */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK ((uint32_t)0x00000001U) /* !< CLK_OUT is ULPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK ((uint32_t)0x00000002U) /* !< CLK_OUT is LFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK ((uint32_t)0x00000003U) /* !< CLK_OUT is MFPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK ((uint32_t)0x00000004U) /* !< CLK_OUT is HFCLK */ +/* SYSCTL_GENCLKCFG[EXCLKDIVVAL] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_OFS (4) /* !< EXCLKDIVVAL Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK ((uint32_t)0x00000070U) /* !< EXCLKDIVVAL selects the divider + value for the divider in the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2 ((uint32_t)0x00000000U) /* !< CLK_OUT source is divided by 2 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4 ((uint32_t)0x00000010U) /* !< CLK_OUT source is divided by 4 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6 ((uint32_t)0x00000020U) /* !< CLK_OUT source is divided by 6 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8 ((uint32_t)0x00000030U) /* !< CLK_OUT source is divided by 8 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10 ((uint32_t)0x00000040U) /* !< CLK_OUT source is divided by 10 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12 ((uint32_t)0x00000050U) /* !< CLK_OUT source is divided by 12 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14 ((uint32_t)0x00000060U) /* !< CLK_OUT source is divided by 14 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16 ((uint32_t)0x00000070U) /* !< CLK_OUT source is divided by 16 */ +/* SYSCTL_GENCLKCFG[EXCLKDIVEN] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_OFS (7) /* !< EXCLKDIVEN Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK ((uint32_t)0x00000080U) /* !< EXCLKDIVEN enables or disables the + divider function of the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU ((uint32_t)0x00000000U) /* !< CLock divider is disabled + (passthrough, EXCLKDIVVAL is not + applied) */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE ((uint32_t)0x00000080U) /* !< Clock divider is enabled + (EXCLKDIVVAL is applied) */ + +/* SYSCTL_GENCLKEN Bits */ +/* SYSCTL_GENCLKEN[EXCLKEN] Bits */ +#define SYSCTL_GENCLKEN_EXCLKEN_OFS (0) /* !< EXCLKEN Offset */ +#define SYSCTL_GENCLKEN_EXCLKEN_MASK ((uint32_t)0x00000001U) /* !< EXCLKEN enables the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKEN_EXCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< CLK_OUT block is disabled */ +#define SYSCTL_GENCLKEN_EXCLKEN_ENABLE ((uint32_t)0x00000001U) /* !< CLK_OUT block is enabled */ +/* SYSCTL_GENCLKEN[MFPCLKEN] Bits */ +#define SYSCTL_GENCLKEN_MFPCLKEN_OFS (4) /* !< MFPCLKEN Offset */ +#define SYSCTL_GENCLKEN_MFPCLKEN_MASK ((uint32_t)0x00000010U) /* !< MFPCLKEN enables the middle + frequency precision clock (MFPCLK). */ +#define SYSCTL_GENCLKEN_MFPCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< MFPCLK is disabled */ +#define SYSCTL_GENCLKEN_MFPCLKEN_ENABLE ((uint32_t)0x00000010U) /* !< MFPCLK is enabled */ + +/* SYSCTL_PMODECFG Bits */ +/* SYSCTL_PMODECFG[DSLEEP] Bits */ +#define SYSCTL_PMODECFG_DSLEEP_OFS (0) /* !< DSLEEP Offset */ +#define SYSCTL_PMODECFG_DSLEEP_MASK ((uint32_t)0x00000003U) /* !< DSLEEP selects the operating mode + to enter upon a DEEPSLEEP request + from the CPU. */ +#define SYSCTL_PMODECFG_DSLEEP_STOP ((uint32_t)0x00000000U) /* !< STOP mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_STANDBY ((uint32_t)0x00000001U) /* !< STANDBY mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_SHUTDOWN ((uint32_t)0x00000002U) /* !< SHUTDOWN mode is entered */ + +/* SYSCTL_FCC Bits */ +/* SYSCTL_FCC[DATA] Bits */ +#define SYSCTL_FCC_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FCC_DATA_MASK ((uint32_t)0x003FFFFFU) /* !< Frequency clock counter (FCC) count + value. */ + +/* SYSCTL_SRAMBOUNDARY Bits */ +/* SYSCTL_SRAMBOUNDARY[ADDR] Bits */ +#define SYSCTL_SRAMBOUNDARY_ADDR_OFS (5) /* !< ADDR Offset */ +#define SYSCTL_SRAMBOUNDARY_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary configuration. The + value configured into this acts such + that: SRAM accesses to addresses less + than or equal value will be RW only. + SRAM accesses to addresses greater + than value will be RX only. Value of + 0 is not valid (system will have no + stack). If set to 0, the system acts + as if the entire SRAM is RWX. Any + non-zero value can be configured, + including a value = SRAM size. */ + +/* SYSCTL_SYSTEMCFG Bits */ +/* SYSCTL_SYSTEMCFG[KEY] Bits */ +#define SYSCTL_SYSTEMCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSTEMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 1Bh (27) must be + written to KEY together with contents + to be updated. Reads as 0 */ +#define SYSCTL_SYSTEMCFG_KEY_VALUE ((uint32_t)0x1B000000U) /* !< Issue write */ +/* SYSCTL_SYSTEMCFG[WWDTLP0RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS (0) /* !< WWDTLP0RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK ((uint32_t)0x00000001U) /* !< WWDTLP0RSTDIS specifies whether a + WWDT Error Event will trigger a + BOOTRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP0 Error Event will trigger a + BOOTRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_TRUE ((uint32_t)0x00000001U) /* !< WWDTLP0 Error Event will trigger an + NMI */ + +/* SYSCTL_BEEPCFG Bits */ +/* SYSCTL_BEEPCFG[FREQ] Bits */ +#define SYSCTL_BEEPCFG_FREQ_OFS (4) /* !< FREQ Offset */ +#define SYSCTL_BEEPCFG_FREQ_MASK ((uint32_t)0x00000030U) /* !< Beeper Output Frequency + Configuration */ +#define SYSCTL_BEEPCFG_FREQ_8KHZ ((uint32_t)0x00000000U) /* !< Beeper runs at 8KHz */ +#define SYSCTL_BEEPCFG_FREQ_4KHZ ((uint32_t)0x00000010U) /* !< Beeper runs at 4KHz */ +#define SYSCTL_BEEPCFG_FREQ_2KHZ ((uint32_t)0x00000020U) /* !< Beeper runs at 2KHz */ +#define SYSCTL_BEEPCFG_FREQ_1KHZ ((uint32_t)0x00000030U) /* !< Beeper runs at 1KHz */ +/* SYSCTL_BEEPCFG[EN] Bits */ +#define SYSCTL_BEEPCFG_EN_OFS (0) /* !< EN Offset */ +#define SYSCTL_BEEPCFG_EN_MASK ((uint32_t)0x00000001U) /* !< Beeper Output Enable */ +#define SYSCTL_BEEPCFG_EN_DISABLE ((uint32_t)0x00000000U) /* !< Beeper Output Disabled */ +#define SYSCTL_BEEPCFG_EN_ENABLE ((uint32_t)0x00000001U) /* !< Beeper Output Enabled */ + +/* SYSCTL_WRITELOCK Bits */ +/* SYSCTL_WRITELOCK[ACTIVE] Bits */ +#define SYSCTL_WRITELOCK_ACTIVE_OFS (0) /* !< ACTIVE Offset */ +#define SYSCTL_WRITELOCK_ACTIVE_MASK ((uint32_t)0x00000001U) /* !< ACTIVE controls whether critical + SYSCTL registers are write protected + or not. */ +#define SYSCTL_WRITELOCK_ACTIVE_DISABLE ((uint32_t)0x00000000U) /* !< Allow writes to lockable registers */ +#define SYSCTL_WRITELOCK_ACTIVE_ENABLE ((uint32_t)0x00000001U) /* !< Disallow writes to lockable + registers */ + +/* SYSCTL_CLKSTATUS Bits */ +/* SYSCTL_CLKSTATUS[LFOSCGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_OFS (11) /* !< LFOSCGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_MASK ((uint32_t)0x00000800U) /* !< LFOSCGOOD indicates when the LFOSC + startup has completed and the LFOSC + is ready for use. */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFOSC is not ready */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE ((uint32_t)0x00000800U) /* !< LFOSC is ready */ +/* SYSCTL_CLKSTATUS[HFCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_OFS (8) /* !< HFCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_MASK ((uint32_t)0x00000100U) /* !< HFCLKGOOD indicates that the HFCLK + started correctly. When the HFXT is + started or HFCLK_IN is selected as + the HFCLK source, this bit will be + set by hardware if a valid HFCLK is + detected, and cleared if HFCLK is not + operating within the expected range. */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< HFCLK did not start correctly */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE ((uint32_t)0x00000100U) /* !< HFCLK started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKDEAD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_OFS (20) /* !< HSCLKDEAD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_MASK ((uint32_t)0x00100000U) /* !< HSCLKDEAD is set by hardware if the + selected source for HSCLK was started + but did not start successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source was not started or + started correctly */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE ((uint32_t)0x00100000U) /* !< The HSCLK source did not start + correctly */ +/* SYSCTL_CLKSTATUS[HFCLKOFF] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_OFS (13) /* !< HFCLKOFF Offset */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_MASK ((uint32_t)0x00002000U) /* !< HFCLKOFF indicates if the HFCLK is + disabled or was dead at startup. + When the HFCLK is started, HFCLKOFF + is cleared by hardware. Following + startup of the HFCLK, if the HFCLK + startup monitor determines that the + HFCLK was not started correctly, + HFCLKOFF is set. */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_FALSE ((uint32_t)0x00000000U) /* !< HFCLK started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_TRUE ((uint32_t)0x00002000U) /* !< HFCLK is disabled or was dead at + startup */ +/* SYSCTL_CLKSTATUS[HFCLKBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_OFS (28) /* !< HFCLKBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_MASK ((uint32_t)0x10000000U) /* !< HFCLKBLKUPD indicates when writes + to the HFCLKCLKCFG register are + blocked. */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< Writes to HFCLKCLKCFG are allowed */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE ((uint32_t)0x10000000U) /* !< Writes to HFCLKCLKCFG are blocked */ +/* SYSCTL_CLKSTATUS[HSCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_OFS (21) /* !< HSCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_MASK ((uint32_t)0x00200000U) /* !< HSCLKGOOD is set by hardware if the + selected clock source for HSCLK + started successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source did not start + correctly */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE ((uint32_t)0x00200000U) /* !< The HSCLK source started correctly */ +/* SYSCTL_CLKSTATUS[ANACLKERR] Bits */ +#define SYSCTL_CLKSTATUS_ANACLKERR_OFS (31) /* !< ANACLKERR Offset */ +#define SYSCTL_CLKSTATUS_ANACLKERR_MASK ((uint32_t)0x80000000U) /* !< ANACLKERR is set when the device + clock configuration does not support + an enabled analog peripheral mode and + the analog peripheral may not be + functioning as expected. */ +#define SYSCTL_CLKSTATUS_ANACLKERR_FALSE ((uint32_t)0x00000000U) /* !< No analog clock errors detected */ +#define SYSCTL_CLKSTATUS_ANACLKERR_TRUE ((uint32_t)0x80000000U) /* !< Analog clock error detected */ +/* SYSCTL_CLKSTATUS[HSCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_OFS (4) /* !< HSCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_MASK ((uint32_t)0x00000010U) /* !< HSCLKMUX indicates if MCLK is + currently sourced from the high-speed + clock (HSCLK). */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_SYSOSC ((uint32_t)0x00000000U) /* !< MCLK is not sourced from HSCLK */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK ((uint32_t)0x00000010U) /* !< MCLK is sourced from HSCLK */ +/* SYSCTL_CLKSTATUS[LFCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_OFS (6) /* !< LFCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_MASK ((uint32_t)0x000000C0U) /* !< LFCLKMUX indicates if LFCLK is + sourced from the internal LFOSC, the + low frequency crystal (LFXT), or the + LFCLK_IN digital clock input. */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFOSC ((uint32_t)0x00000000U) /* !< LFCLK is sourced from the internal + LFOSC */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFXT ((uint32_t)0x00000040U) /* !< LFCLK is sourced from the LFXT + (crystal) */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_EXLF ((uint32_t)0x00000080U) /* !< LFCLK is sourced from LFCLK_IN + (external digital clock input) */ +/* SYSCTL_CLKSTATUS[SYSOSCFREQ] Bits */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_OFS (0) /* !< SYSOSCFREQ Offset */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK ((uint32_t)0x00000003U) /* !< SYSOSCFREQ indicates the current + SYSOSC operating frequency. */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC32M ((uint32_t)0x00000000U) /* !< SYSOSC is at base frequency (32MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< SYSOSC is at low frequency (4MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< SYSOSC is at the user-trimmed + frequency (16 or 24MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCTURBO ((uint32_t)0x00000003U) /* !< Reserved */ +/* SYSCTL_CLKSTATUS[LFXTGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_OFS (10) /* !< LFXTGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_MASK ((uint32_t)0x00000400U) /* !< LFXTGOOD indicates if the LFXT + started correctly. When the LFXT is + started, LFXTGOOD is cleared by + hardware. After the startup settling + time has expired, the LFXT status is + tested. If the LFXT started + successfully the LFXTGOOD bit is set, + else it is left cleared. */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFXT did not start correctly */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_TRUE ((uint32_t)0x00000400U) /* !< LFXT started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKSOFF] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_OFS (12) /* !< HSCLKSOFF Offset */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_MASK ((uint32_t)0x00001000U) /* !< HSCLKSOFF is set when the high + speed clock sources (SYSPLL, HFCLK) + are disabled or dead. It is the + logical AND of HFCLKOFF and + SYSPLLOFF. */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL, HFCLK, or both were started + correctly and remain enabled */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE ((uint32_t)0x00001000U) /* !< SYSPLL and HFCLK are both either + off or dead */ +/* SYSCTL_CLKSTATUS[FCLMODE] Bits */ +#define SYSCTL_CLKSTATUS_FCLMODE_OFS (24) /* !< FCLMODE Offset */ +#define SYSCTL_CLKSTATUS_FCLMODE_MASK ((uint32_t)0x01000000U) /* !< FCLMODE indicates if the SYSOSC + frequency correction loop (FCL) is + enabled. */ +#define SYSCTL_CLKSTATUS_FCLMODE_DISABLED ((uint32_t)0x00000000U) /* !< SYSOSC FCL is disabled */ +#define SYSCTL_CLKSTATUS_FCLMODE_ENABLED ((uint32_t)0x01000000U) /* !< SYSOSC FCL is enabled */ +/* SYSCTL_CLKSTATUS[CURHSCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_OFS (16) /* !< CURHSCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_MASK ((uint32_t)0x00010000U) /* !< CURHSCLKSEL indicates the current + clock source for HSCLK. */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is currently sourced from the + SYSPLL */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK ((uint32_t)0x00010000U) /* !< HSCLK is currently sourced from the + HFCLK */ +/* SYSCTL_CLKSTATUS[CURMCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_OFS (17) /* !< CURMCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_MASK ((uint32_t)0x00020000U) /* !< CURMCLKSEL indicates if MCLK is + currently sourced from LFCLK. */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_NOTLFCLK ((uint32_t)0x00000000U) /* !< MCLK is not sourced from LFCLK */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK ((uint32_t)0x00020000U) /* !< MCLK is sourced from LFCLK */ +/* SYSCTL_CLKSTATUS[FCCDONE] Bits */ +#define SYSCTL_CLKSTATUS_FCCDONE_OFS (25) /* !< FCCDONE Offset */ +#define SYSCTL_CLKSTATUS_FCCDONE_MASK ((uint32_t)0x02000000U) /* !< FCCDONE indicates when a frequency + clock counter capture is complete. */ +#define SYSCTL_CLKSTATUS_FCCDONE_NOTDONE ((uint32_t)0x00000000U) /* !< FCC capture is not done */ +#define SYSCTL_CLKSTATUS_FCCDONE_DONE ((uint32_t)0x02000000U) /* !< FCC capture is done */ +/* SYSCTL_CLKSTATUS[LFCLKFAIL] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_OFS (23) /* !< LFCLKFAIL Offset */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_MASK ((uint32_t)0x00800000U) /* !< LFCLKFAIL indicates when the + continous LFCLK monitor detects a + LFXT or LFCLK_IN clock stuck failure. */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) /* !< No LFCLK fault detected */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE ((uint32_t)0x00800000U) /* !< LFCLK stuck fault detected */ + +/* SYSCTL_SYSSTATUS Bits */ +/* SYSCTL_SYSSTATUS[SHDNIOLOCK] Bits */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_OFS (14) /* !< SHDNIOLOCK Offset */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_MASK ((uint32_t)0x00004000U) /* !< SHDNIOLOCK indicates when IO is + locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_FALSE ((uint32_t)0x00000000U) /* !< IO IS NOT Locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE ((uint32_t)0x00004000U) /* !< IO IS Locked due to SHUTDOWN */ +/* SYSCTL_SYSSTATUS[EXTRSTPINDIS] Bits */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_OFS (12) /* !< EXTRSTPINDIS Offset */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_MASK ((uint32_t)0x00001000U) /* !< EXTRSTPINDIS indicates when user + has disabled the use of external + reset pin */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_FALSE ((uint32_t)0x00000000U) /* !< External Reset Pin Enabled */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE ((uint32_t)0x00001000U) /* !< External Reset Pin Disabled */ +/* SYSCTL_SYSSTATUS[PMUIREFGOOD] Bits */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_OFS (6) /* !< PMUIREFGOOD Offset */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_MASK ((uint32_t)0x00000040U) /* !< PMUIREFGOOD is set by hardware when + the PMU current reference is ready. */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_FALSE ((uint32_t)0x00000000U) /* !< IREF is not ready */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE ((uint32_t)0x00000040U) /* !< IREF is ready */ +/* SYSCTL_SYSSTATUS[SWDCFGDIS] Bits */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_OFS (13) /* !< SWDCFGDIS Offset */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_MASK ((uint32_t)0x00002000U) /* !< SWDCFGDIS indicates when user has + disabled the use of SWD Port */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_FALSE ((uint32_t)0x00000000U) /* !< SWD Port Enabled */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE ((uint32_t)0x00002000U) /* !< SWD Port Disabled */ +/* SYSCTL_SYSSTATUS[ANACPUMPGOOD] Bits */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_OFS (5) /* !< ANACPUMPGOOD Offset */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_MASK ((uint32_t)0x00000020U) /* !< ANACPUMPGOOD is set by hardware + when the VBOOST analog mux charge + pump is ready. */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_FALSE ((uint32_t)0x00000000U) /* !< VBOOST is not ready */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE ((uint32_t)0x00000020U) /* !< VBOOST is ready */ +/* SYSCTL_SYSSTATUS[REBOOTATTEMPTS] Bits */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_OFS (30) /* !< REBOOTATTEMPTS Offset */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_MASK ((uint32_t)0xC0000000U) /* !< REBOOTATTEMPTS indicates the number + of boot attempts taken before the + user application starts. */ +/* SYSCTL_SYSSTATUS[SWALTSELEN] Bits */ +#define SYSCTL_SYSSTATUS_SWALTSELEN_OFS (15) /* !< SWALTSELEN Offset */ +#define SYSCTL_SYSSTATUS_SWALTSELEN_MASK ((uint32_t)0x00008000U) /* !< SWALTSELEN indicates when user has + enabled the use of alternate + SWD/SWCLK pins */ +#define SYSCTL_SYSSTATUS_SWALTSELEN_FALSE ((uint32_t)0x00000000U) /* !< Alternate SWD/SWCLK pins are + disabled */ +#define SYSCTL_SYSSTATUS_SWALTSELEN_TRUE ((uint32_t)0x00008000U) /* !< Alternate SWD/SWCLK pins are + enabled */ +/* SYSCTL_SYSSTATUS[BORLVL] Bits */ +#define SYSCTL_SYSSTATUS_BORLVL_OFS (4) /* !< BORLVL Offset */ +#define SYSCTL_SYSSTATUS_BORLVL_MASK ((uint32_t)0x00000010U) /* !< BORLVL indicates if a BOR event + occured and the BOR threshold was + switched to BOR0 by hardware. */ +#define SYSCTL_SYSSTATUS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No BOR violation occured */ +#define SYSCTL_SYSSTATUS_BORLVL_TRUE ((uint32_t)0x00000010U) /* !< A BOR violation occured and the BOR + threshold was switched to BOR0 */ +/* SYSCTL_SYSSTATUS[BORCURTHRESHOLD] Bits */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_OFS (2) /* !< BORCURTHRESHOLD Offset */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_MASK ((uint32_t)0x0000000CU) /* !< BORCURTHRESHOLD indicates the + active brown-out reset supply monitor + configuration. */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1 ((uint32_t)0x00000004U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2 ((uint32_t)0x00000008U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3 ((uint32_t)0x0000000CU) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_RSTCAUSE Bits */ +/* SYSCTL_RSTCAUSE[ID] Bits */ +#define SYSCTL_RSTCAUSE_ID_OFS (0) /* !< ID Offset */ +#define SYSCTL_RSTCAUSE_ID_MASK ((uint32_t)0x0000001FU) /* !< ID is a read-to-clear field which + indicates the lowest level reset + cause since the last read. */ +#define SYSCTL_RSTCAUSE_ID_NORST ((uint32_t)0x00000000U) /* !< No reset since last read */ +#define SYSCTL_RSTCAUSE_ID_PORHWFAIL ((uint32_t)0x00000001U) /* !< POR- violation, SHUTDNSTOREx or PMU + trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_POREXNRST ((uint32_t)0x00000002U) /* !< NRST triggered POR (>1s hold) */ +#define SYSCTL_RSTCAUSE_ID_PORSW ((uint32_t)0x00000003U) /* !< Software triggered POR */ +#define SYSCTL_RSTCAUSE_ID_BORSUPPLY ((uint32_t)0x00000004U) /* !< BOR0- violation */ +#define SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN ((uint32_t)0x00000005U) /* !< SHUTDOWN mode exit */ +#define SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY ((uint32_t)0x00000008U) /* !< Non-PMU trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL ((uint32_t)0x00000009U) /* !< Fatal clock failure */ +#define SYSCTL_RSTCAUSE_ID_BOOTEXNRST ((uint32_t)0x0000000CU) /* !< NRST triggered BOOTRST (<1s hold) */ +#define SYSCTL_RSTCAUSE_ID_BOOTSW ((uint32_t)0x0000000DU) /* !< Software triggered BOOTRST */ +#define SYSCTL_RSTCAUSE_ID_BOOTWWDT0 ((uint32_t)0x0000000EU) /* !< WWDT0 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLEXIT ((uint32_t)0x00000010U) /* !< BSL exit */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLENTRY ((uint32_t)0x00000011U) /* !< BSL entry */ +#define SYSCTL_RSTCAUSE_ID_SYSWWDT1 ((uint32_t)0x00000013U) /* !< WWDT1 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSFLASHECC ((uint32_t)0x00000014U) /* !< Flash uncorrectable ECC error */ +#define SYSCTL_RSTCAUSE_ID_SYSCPULOCK ((uint32_t)0x00000015U) /* !< CPULOCK violation */ +#define SYSCTL_RSTCAUSE_ID_SYSDBG ((uint32_t)0x0000001AU) /* !< Debug triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_SYSSW ((uint32_t)0x0000001BU) /* !< Software triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_CPUDBG ((uint32_t)0x0000001CU) /* !< Debug triggered CPURST */ +#define SYSCTL_RSTCAUSE_ID_CPUSW ((uint32_t)0x0000001DU) /* !< Software triggered CPURST */ + +/* SYSCTL_RESETLEVEL Bits */ +/* SYSCTL_RESETLEVEL[LEVEL] Bits */ +#define SYSCTL_RESETLEVEL_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_RESETLEVEL_LEVEL_MASK ((uint32_t)0x00000007U) /* !< LEVEL is used to specify the type + of reset to be issued when RESETCMD + is set to generate a software + triggered reset. */ +#define SYSCTL_RESETLEVEL_LEVEL_CPU ((uint32_t)0x00000000U) /* !< Issue a SYSRST (CPU plus + peripherals only) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOT ((uint32_t)0x00000001U) /* !< Issue a BOOTRST (CPU, peripherals, + and boot configuration routine) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY ((uint32_t)0x00000002U) /* !< Issue a SYSRST and enter the boot + strap loader (BSL) */ +#define SYSCTL_RESETLEVEL_LEVEL_POR ((uint32_t)0x00000003U) /* !< Issue a power-on reset (POR) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT ((uint32_t)0x00000004U) /* !< Issue a SYSRST and exit the boot + strap loader (BSL) */ + +/* SYSCTL_RESETCMD Bits */ +/* SYSCTL_RESETCMD[KEY] Bits */ +#define SYSCTL_RESETCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_RESETCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of E4h (228) must be + written to KEY together with GO to + trigger the reset. */ +#define SYSCTL_RESETCMD_KEY_VALUE ((uint32_t)0xE4000000U) /* !< Issue reset */ +/* SYSCTL_RESETCMD[GO] Bits */ +#define SYSCTL_RESETCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_RESETCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Execute the reset specified in + RESETLEVEL.LEVEL. Must be written + together with the KEY. */ +#define SYSCTL_RESETCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue reset */ + +/* SYSCTL_BORTHRESHOLD Bits */ +/* SYSCTL_BORTHRESHOLD[LEVEL] Bits */ +#define SYSCTL_BORTHRESHOLD_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_BORTHRESHOLD_LEVEL_MASK ((uint32_t)0x00000003U) /* !< LEVEL specifies the desired BOR + threshold and BOR mode. */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1 ((uint32_t)0x00000001U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2 ((uint32_t)0x00000002U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3 ((uint32_t)0x00000003U) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_BORCLRCMD Bits */ +/* SYSCTL_BORCLRCMD[KEY] Bits */ +#define SYSCTL_BORCLRCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_BORCLRCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of C7h (199) must be + written to KEY together with GO to + trigger the clear and BOR threshold + change. */ +#define SYSCTL_BORCLRCMD_KEY_VALUE ((uint32_t)0xC7000000U) /* !< Issue clear */ +/* SYSCTL_BORCLRCMD[GO] Bits */ +#define SYSCTL_BORCLRCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_BORCLRCMD_GO_MASK ((uint32_t)0x00000001U) /* !< GO clears any prior BOR violation + status indications and attempts to + change the active BOR mode to that + specified in the LEVEL field of the + BORTHRESHOLD register. */ +#define SYSCTL_BORCLRCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue clear */ + +/* SYSCTL_SYSOSCFCLCTL Bits */ +/* SYSCTL_SYSOSCFCLCTL[KEY] Bits */ +#define SYSCTL_SYSOSCFCLCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSOSCFCLCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 2Ah (42) must be + written to KEY together with + SETUSEFCL to enable the FCL. */ +#define SYSCTL_SYSOSCFCLCTL_KEY_VALUE ((uint32_t)0x2A000000U) /* !< Issue Command */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEFCL] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_OFS (0) /* !< SETUSEFCL Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEFCL to enable the + frequency correction loop in SYSOSC. + Once enabled, this state is locked + until the next BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */ + +/* SYSCTL_LFXTCTL Bits */ +/* SYSCTL_LFXTCTL[KEY] Bits */ +#define SYSCTL_LFXTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_LFXTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 91h (145) must be + written to KEY together with either + STARTLFXT or SETUSELFXT to set the + corresponding bit. */ +#define SYSCTL_LFXTCTL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_LFXTCTL[SETUSELFXT] Bits */ +#define SYSCTL_LFXTCTL_SETUSELFXT_OFS (1) /* !< SETUSELFXT Offset */ +#define SYSCTL_LFXTCTL_SETUSELFXT_MASK ((uint32_t)0x00000002U) /* !< Set SETUSELFXT to switch LFCLK to + LFXT. Once set, SETUSELFXT remains + set until the next BOOTRST. */ +#define SYSCTL_LFXTCTL_SETUSELFXT_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_LFXTCTL_SETUSELFXT_TRUE ((uint32_t)0x00000002U) /* !< Use LFXT as the LFCLK source */ +/* SYSCTL_LFXTCTL[STARTLFXT] Bits */ +#define SYSCTL_LFXTCTL_STARTLFXT_OFS (0) /* !< STARTLFXT Offset */ +#define SYSCTL_LFXTCTL_STARTLFXT_MASK ((uint32_t)0x00000001U) /* !< Set STARTLFXT to start the low + frequency crystal oscillator (LFXT). + Once set, STARTLFXT remains set until + the next BOOTRST. */ +#define SYSCTL_LFXTCTL_STARTLFXT_FALSE ((uint32_t)0x00000000U) /* !< LFXT not started */ +#define SYSCTL_LFXTCTL_STARTLFXT_TRUE ((uint32_t)0x00000001U) /* !< Start LFXT */ + +/* SYSCTL_EXLFCTL Bits */ +/* SYSCTL_EXLFCTL[KEY] Bits */ +#define SYSCTL_EXLFCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXLFCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 36h (54) must be + written to KEY together with + SETUSEEXLF to set SETUSEEXLF. */ +#define SYSCTL_EXLFCTL_KEY_VALUE ((uint32_t)0x36000000U) /* !< Issue command */ +/* SYSCTL_EXLFCTL[SETUSEEXLF] Bits */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_OFS (0) /* !< SETUSEEXLF Offset */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEEXLF to switch LFCLK to + the LFCLK_IN digital clock input. + Once set, SETUSEEXLF remains set + until the next BOOTRST. */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_TRUE ((uint32_t)0x00000001U) /* !< Use LFCLK_IN as the LFCLK source */ + +/* SYSCTL_SHDNIOREL Bits */ +/* SYSCTL_SHDNIOREL[KEY] Bits */ +#define SYSCTL_SHDNIOREL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SHDNIOREL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 91h must be written + to KEY together with RELEASE to set + RELEASE. */ +#define SYSCTL_SHDNIOREL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_SHDNIOREL[RELEASE] Bits */ +#define SYSCTL_SHDNIOREL_RELEASE_OFS (0) /* !< RELEASE Offset */ +#define SYSCTL_SHDNIOREL_RELEASE_MASK ((uint32_t)0x00000001U) /* !< Set RELEASE to release the IO after + a SHUTDOWN mode exit. */ +#define SYSCTL_SHDNIOREL_RELEASE_TRUE ((uint32_t)0x00000001U) /* !< Release IO */ + +/* SYSCTL_EXRSTPIN Bits */ +/* SYSCTL_EXRSTPIN[KEY] Bits */ +#define SYSCTL_EXRSTPIN_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXRSTPIN_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 1Eh must be written + together with DISABLE to disable the + reset function. */ +#define SYSCTL_EXRSTPIN_KEY_VALUE ((uint32_t)0x1E000000U) /* !< Issue command */ +/* SYSCTL_EXRSTPIN[DISABLE] Bits */ +#define SYSCTL_EXRSTPIN_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_EXRSTPIN_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the reset + function of the NRST pin. Once set, + this configuration is locked until + the next POR. */ +#define SYSCTL_EXRSTPIN_DISABLE_FALSE ((uint32_t)0x00000000U) /* !< Reset function of NRST pin is + enabled */ +#define SYSCTL_EXRSTPIN_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Reset function of NRST pin is + disabled */ + +/* SYSCTL_SYSSTATUSCLR Bits */ +/* SYSCTL_SYSSTATUSCLR[KEY] Bits */ +#define SYSCTL_SYSSTATUSCLR_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSSTATUSCLR_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value CEh (206) must be + written to KEY together with ALLECC + to clear the ECC state. */ +#define SYSCTL_SYSSTATUSCLR_KEY_VALUE ((uint32_t)0xCE000000U) /* !< Issue command */ +/* SYSCTL_SYSSTATUSCLR[ALLECC] Bits */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_OFS (0) /* !< ALLECC Offset */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_MASK ((uint32_t)0x00000001U) /* !< Set ALLECC to clear all ECC related + SYSSTATUS indicators. */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR ((uint32_t)0x00000001U) /* !< Clear ECC error state */ + +/* SYSCTL_SWDCFG Bits */ +/* SYSCTL_SWDCFG[KEY] Bits */ +#define SYSCTL_SWDCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SWDCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 62h (98) must be + written to KEY together with DISBALE + to disable the SWD functions. */ +#define SYSCTL_SWDCFG_KEY_VALUE ((uint32_t)0x62000000U) /* !< Issue command */ +/* SYSCTL_SWDCFG[DISABLE] Bits */ +#define SYSCTL_SWDCFG_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_SWDCFG_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the SWD + function on SWD pins, allowing the + SWD pins to be used as GPIO. */ +#define SYSCTL_SWDCFG_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disable SWD function on SWD pins */ + +/* SYSCTL_FCCCMD Bits */ +/* SYSCTL_FCCCMD[KEY] Bits */ +#define SYSCTL_FCCCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FCCCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 0Eh (14) must be + written with GO to start a capture. */ +#define SYSCTL_FCCCMD_KEY_VALUE ((uint32_t)0x0E000000U) /* !< Issue command */ +/* SYSCTL_FCCCMD[GO] Bits */ +#define SYSCTL_FCCCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_FCCCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Set GO to start a capture with the + frequency clock counter (FCC). */ +#define SYSCTL_FCCCMD_GO_TRUE ((uint32_t)0x00000001U) + +/* SYSCTL_SHUTDNSTORE0 Bits */ +/* SYSCTL_SHUTDNSTORE0[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE0_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE0_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 0 */ + +/* SYSCTL_SHUTDNSTORE1 Bits */ +/* SYSCTL_SHUTDNSTORE1[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE1_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE1_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 1 */ + +/* SYSCTL_SHUTDNSTORE2 Bits */ +/* SYSCTL_SHUTDNSTORE2[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE2_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE2_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 2 */ + +/* SYSCTL_SHUTDNSTORE3 Bits */ +/* SYSCTL_SHUTDNSTORE3[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE3_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE3_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 3 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c1105_c1106__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g352x.h b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g352x.h new file mode 100644 index 0000000..c98759d --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g352x.h @@ -0,0 +1,1907 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g352x__include +#define ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g352x__include + +/* Filename: hw_sysctl_mspm0g352x.h */ +/* Revised: 2024-05-27 03:28:21 */ +/* Revision: 0dba7a68171db09903ab463afe222c4acffc539f */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* SYSCTL Registers +******************************************************************************/ +#define SYSCTL_SECCFG_OFS ((uint32_t)0x00003000U) +#define SYSCTL_SOCLOCK_OFS ((uint32_t)0x00001000U) + + +/** @addtogroup SYSCTL_SECCFG + @{ +*/ + +typedef struct { + __IO uint32_t FWEPROTMAIN; /* !< (@ 0x00003000) 1 Sector Write-Erase per bit starting at address + 0x0 of flash */ + uint32_t RESERVED0[4]; + __IO uint32_t FWPROTMAINDATA; /* !< (@ 0x00003014) Read-Write Protection for first 4 Sectors of Data + Bank */ + __IO uint32_t FRXPROTMAINSTART; /* !< (@ 0x00003018) Flash RX Protection Start Address */ + __IO uint32_t FRXPROTMAINEND; /* !< (@ 0x0000301C) Flash RX Protection End Address */ + __IO uint32_t FIPPROTMAINSTART; /* !< (@ 0x00003020) Flash IP Protection Start Address */ + __IO uint32_t FIPPROTMAINEND; /* !< (@ 0x00003024) Flash IP Protection End Address */ + uint32_t RESERVED1[4]; + __O uint32_t FLBANKSWPPOLICY; /* !< (@ 0x00003038) Flash Bank Swap Policy */ + __O uint32_t FLBANKSWP; /* !< (@ 0x0000303C) Flash MAIN bank address swap */ + uint32_t RESERVED2; + __O uint32_t FWENABLE; /* !< (@ 0x00003044) Security Firewall Enable Register */ + __I uint32_t SECSTATUS; /* !< (@ 0x00003048) Security Configuration status */ + uint32_t RESERVED3[5]; + __O uint32_t INITDONE; /* !< (@ 0x00003060) INITCODE PASS */ +} SYSCTL_SECCFG_Regs; + +/*@}*/ /* end of group SYSCTL_SECCFG */ + +/** @addtogroup SYSCTL_SOCLOCK + @{ +*/ + +typedef struct { + uint32_t RESERVED0[8]; + __I uint32_t IIDX; /* !< (@ 0x00001020) SYSCTL interrupt index */ + uint32_t RESERVED1; + __IO uint32_t IMASK; /* !< (@ 0x00001028) SYSCTL interrupt mask */ + uint32_t RESERVED2; + __I uint32_t RIS; /* !< (@ 0x00001030) SYSCTL raw interrupt status */ + uint32_t RESERVED3; + __I uint32_t MIS; /* !< (@ 0x00001038) SYSCTL masked interrupt status */ + uint32_t RESERVED4; + __O uint32_t ISET; /* !< (@ 0x00001040) SYSCTL interrupt set */ + uint32_t RESERVED5; + __O uint32_t ICLR; /* !< (@ 0x00001048) SYSCTL interrupt clear */ + uint32_t RESERVED6; + __I uint32_t NMIIIDX; /* !< (@ 0x00001050) NMI interrupt index */ + uint32_t RESERVED7[3]; + __I uint32_t NMIRIS; /* !< (@ 0x00001060) NMI raw interrupt status */ + uint32_t RESERVED8[3]; + __O uint32_t NMIISET; /* !< (@ 0x00001070) NMI interrupt set */ + uint32_t RESERVED9; + __O uint32_t NMIICLR; /* !< (@ 0x00001078) NMI interrupt clear */ + uint32_t RESERVED10[33]; + __IO uint32_t SYSOSCCFG; /* !< (@ 0x00001100) SYSOSC configuration */ + __IO uint32_t MCLKCFG; /* !< (@ 0x00001104) Main clock (MCLK) configuration */ + __IO uint32_t HSCLKEN; /* !< (@ 0x00001108) High-speed clock (HSCLK) source enable/disable */ + __IO uint32_t HSCLKCFG; /* !< (@ 0x0000110C) High-speed clock (HSCLK) source selection */ + __IO uint32_t HFCLKCLKCFG; /* !< (@ 0x00001110) High-frequency clock (HFCLK) configuration */ + __IO uint32_t LFCLKCFG; /* !< (@ 0x00001114) Low frequency crystal oscillator (LFXT) + configuration */ + uint32_t RESERVED11[2]; + __IO uint32_t SYSPLLCFG0; /* !< (@ 0x00001120) SYSPLL reference and output configuration */ + __IO uint32_t SYSPLLCFG1; /* !< (@ 0x00001124) SYSPLL reference and feedback divider */ + __IO uint32_t SYSPLLPARAM0; /* !< (@ 0x00001128) SYSPLL PARAM0 (load from FACTORY region) */ + __IO uint32_t SYSPLLPARAM1; /* !< (@ 0x0000112C) SYSPLL PARAM1 (load from FACTORY region) */ + uint32_t RESERVED12[2]; + __IO uint32_t GENCLKCFG; /* !< (@ 0x00001138) General clock configuration */ + __IO uint32_t GENCLKEN; /* !< (@ 0x0000113C) General clock enable control */ + __IO uint32_t PMODECFG; /* !< (@ 0x00001140) Power mode configuration */ + uint32_t RESERVED13[3]; + __I uint32_t FCC; /* !< (@ 0x00001150) Frequency clock counter (FCC) count */ + uint32_t RESERVED14[7]; + __IO uint32_t SYSOSCTRIMUSER; /* !< (@ 0x00001170) SYSOSC user-specified trim */ + uint32_t RESERVED15; + __IO uint32_t SRAMBOUNDARY; /* !< (@ 0x00001178) SRAM Write Boundary */ + __IO uint32_t SRAMBOUNDARYHIGH; /* !< (@ 0x0000117C) SRAM Write Boundary High */ + __IO uint32_t SYSTEMCFG; /* !< (@ 0x00001180) System configuration */ + __IO uint32_t SRAMCFG; /* !< (@ 0x00001184) System SRAM configuration */ + uint32_t RESERVED16[30]; + __IO uint32_t WRITELOCK; /* !< (@ 0x00001200) SYSCTL register write lockout */ + __I uint32_t CLKSTATUS; /* !< (@ 0x00001204) Clock module (CKM) status */ + __I uint32_t SYSSTATUS; /* !< (@ 0x00001208) System status information */ + __I uint32_t DEDERRADDR; /* !< (@ 0x0000120C) Memory DED Address */ + uint32_t RESERVED17[4]; + __I uint32_t RSTCAUSE; /* !< (@ 0x00001220) Reset cause */ + uint32_t RESERVED18[55]; + __IO uint32_t RESETLEVEL; /* !< (@ 0x00001300) Reset level for application-triggered reset + command */ + __O uint32_t RESETCMD; /* !< (@ 0x00001304) Execute an application-triggered reset command */ + __IO uint32_t BORTHRESHOLD; /* !< (@ 0x00001308) BOR threshold selection */ + __O uint32_t BORCLRCMD; /* !< (@ 0x0000130C) Set the BOR threshold */ + __O uint32_t SYSOSCFCLCTL; /* !< (@ 0x00001310) SYSOSC frequency correction loop (FCL) ROSC enable */ + __O uint32_t LFXTCTL; /* !< (@ 0x00001314) LFXT and LFCLK control */ + __O uint32_t EXLFCTL; /* !< (@ 0x00001318) LFCLK_IN and LFCLK control */ + __O uint32_t SHDNIOREL; /* !< (@ 0x0000131C) SHUTDOWN IO release control */ + __O uint32_t EXRSTPIN; /* !< (@ 0x00001320) Disable the reset function of the NRST pin */ + __O uint32_t SYSSTATUSCLR; /* !< (@ 0x00001324) Clear sticky bits of SYSSTATUS */ + __O uint32_t SWDCFG; /* !< (@ 0x00001328) Disable the SWD function on the SWD pins */ + __O uint32_t FCCCMD; /* !< (@ 0x0000132C) Frequency clock counter start capture */ + uint32_t RESERVED19[52]; + __IO uint32_t SHUTDNSTORE0; /* !< (@ 0x00001400) Shutdown storage memory (byte 0) */ + __IO uint32_t SHUTDNSTORE1; /* !< (@ 0x00001404) Shutdown storage memory (byte 1) */ + __IO uint32_t SHUTDNSTORE2; /* !< (@ 0x00001408) Shutdown storage memory (byte 2) */ + __IO uint32_t SHUTDNSTORE3; /* !< (@ 0x0000140C) Shutdown storage memory (byte 3) */ +} SYSCTL_SOCLOCK_Regs; + +/*@}*/ /* end of group SYSCTL_SOCLOCK */ + +/** @addtogroup SYSCTL + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + SYSCTL_SOCLOCK_Regs SOCLOCK; /* !< (@ 0x00001000) SYSCTL SOCLOCK Region */ + uint32_t RESERVED1[1788]; + SYSCTL_SECCFG_Regs SECCFG; /* !< (@ 0x00003000) SYSCTL SECCFG Region */ +} SYSCTL_Regs; + +/*@}*/ /* end of group SYSCTL */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* SYSCTL Register Control Bits +******************************************************************************/ + +/* SYSCTL_FWEPROTMAIN Bits */ +/* SYSCTL_FWEPROTMAIN[DATA] Bits */ +#define SYSCTL_FWEPROTMAIN_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWEPROTMAIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< 1 Sector Write Erase protection 1: + prohibits write-erase, 0: allows */ + +/* SYSCTL_FWPROTMAINDATA Bits */ +/* SYSCTL_FWPROTMAINDATA[DATA] Bits */ +#define SYSCTL_FWPROTMAINDATA_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWPROTMAINDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< 00: Both RW allowed 01: Read Only + 10: No Read No Write 11: No Read No + Write - Not Used */ + +/* SYSCTL_FRXPROTMAINSTART Bits */ +/* SYSCTL_FRXPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection Start Address + 64B granularity */ + +/* SYSCTL_FRXPROTMAINEND Bits */ +/* SYSCTL_FRXPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection End Address 64B + granularity */ + +/* SYSCTL_FIPPROTMAINSTART Bits */ +/* SYSCTL_FIPPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection Start Address + 64B granularity */ + +/* SYSCTL_FIPPROTMAINEND Bits */ +/* SYSCTL_FIPPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection End Address 64B + granularity */ + +/* SYSCTL_FLBANKSWPPOLICY Bits */ +/* SYSCTL_FLBANKSWPPOLICY[KEY] Bits */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0xCA(202) for write */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_VALUE ((uint32_t)0xCA000000U) /* !< Write Key */ +/* SYSCTL_FLBANKSWPPOLICY[DISABLE] Bits */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_MASK ((uint32_t)0x00000001U) /* !< 1: Disables Policy To Allow Flash + Bank Swapping */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disallow Bank Swap */ + +/* SYSCTL_FLBANKSWP Bits */ +/* SYSCTL_FLBANKSWP[KEY] Bits */ +#define SYSCTL_FLBANKSWP_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FLBANKSWP_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 58h (88) must be + written with USEUPPER to change the + bank swap configuration. */ +#define SYSCTL_FLBANKSWP_KEY_VALUE ((uint32_t)0x58000000U) /* !< Issue write */ +/* SYSCTL_FLBANKSWP[USEUPPER] Bits */ +#define SYSCTL_FLBANKSWP_USEUPPER_OFS (0) /* !< USEUPPER Offset */ +#define SYSCTL_FLBANKSWP_USEUPPER_MASK ((uint32_t)0x00000001U) /* !< 1: Use Upper Bank as Logical 0 */ +#define SYSCTL_FLBANKSWP_USEUPPER_DISABLE ((uint32_t)0x00000000U) /* !< Normal (default) memory map + addressing scheme */ +#define SYSCTL_FLBANKSWP_USEUPPER_ENABLE ((uint32_t)0x00000001U) /* !< Flash upper region address space + swapped with lower region */ + +/* SYSCTL_FWENABLE Bits */ +/* SYSCTL_FWENABLE[KEY] Bits */ +#define SYSCTL_FWENABLE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FWENABLE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x76(118) for write */ +#define SYSCTL_FWENABLE_KEY_VALUE ((uint32_t)0x76000000U) /* !< Write Key */ +/* SYSCTL_FWENABLE[FLIPPROT] Bits */ +#define SYSCTL_FWENABLE_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_FWENABLE_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash Read IP ProtectionActive */ +#define SYSCTL_FWENABLE_FLIPPROT_ENABLE ((uint32_t)0x00000040U) /* !< Turn On Flash IP Protection */ +/* SYSCTL_FWENABLE[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: Blocks Writes from Changing + SRAMBOUNDARY MMR */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE ((uint32_t)0x00000100U) /* !< SRAMBOUNDARY MMR Locked */ +/* SYSCTL_FWENABLE[FLRXPROT] Bits */ +#define SYSCTL_FWENABLE_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_FWENABLE_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_FWENABLE_FLRXPROT_ENABLE ((uint32_t)0x00000010U) /* !< Turn On Flash Read-eXecute + Protection */ + +/* SYSCTL_SECSTATUS Bits */ +/* SYSCTL_SECSTATUS[FLBANKSWPPOLICY] Bits */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_OFS (10) /* !< FLBANKSWPPOLICY Offset */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_MASK ((uint32_t)0x00000400U) /* !< 1: Upper and Lower Banks allowed to + be swapped */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED ((uint32_t)0x00000400U) +/* SYSCTL_SECSTATUS[FLIPPROT] Bits */ +#define SYSCTL_SECSTATUS_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_SECSTATUS_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash IP Protection Active */ +#define SYSCTL_SECSTATUS_FLIPPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLIPPROT_ENABLED ((uint32_t)0x00000040U) +/* SYSCTL_SECSTATUS[FLBANKSWP] Bits */ +#define SYSCTL_SECSTATUS_FLBANKSWP_OFS (12) /* !< FLBANKSWP Offset */ +#define SYSCTL_SECSTATUS_FLBANKSWP_MASK ((uint32_t)0x00001000U) /* !< 1: Upper and Lower Banks have been + swapped */ +/* SYSCTL_SECSTATUS[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: SRAM Boundary MMR Locked */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED ((uint32_t)0x00000100U) +/* SYSCTL_SECSTATUS[FLRXPROT] Bits */ +#define SYSCTL_SECSTATUS_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_SECSTATUS_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_SECSTATUS_FLRXPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLRXPROT_ENABLED ((uint32_t)0x00000010U) +/* SYSCTL_SECSTATUS[INITDONE] Bits */ +#define SYSCTL_SECSTATUS_INITDONE_OFS (0) /* !< INITDONE Offset */ +#define SYSCTL_SECSTATUS_INITDONE_MASK ((uint32_t)0x00000001U) /* !< 1: CSC has been completed */ +#define SYSCTL_SECSTATUS_INITDONE_NO ((uint32_t)0x00000000U) /* !< INIT is not yet done */ +#define SYSCTL_SECSTATUS_INITDONE_YES ((uint32_t)0x00000001U) /* !< INIT is done */ +/* SYSCTL_SECSTATUS[CSCEXISTS] Bits */ +#define SYSCTL_SECSTATUS_CSCEXISTS_OFS (2) /* !< CSCEXISTS Offset */ +#define SYSCTL_SECSTATUS_CSCEXISTS_MASK ((uint32_t)0x00000004U) /* !< 1: CSC Exists in the system */ +#define SYSCTL_SECSTATUS_CSCEXISTS_NO ((uint32_t)0x00000000U) /* !< System does not have a CSC */ +#define SYSCTL_SECSTATUS_CSCEXISTS_YES ((uint32_t)0x00000004U) /* !< System does have a CSC */ + +/* SYSCTL_INITDONE Bits */ +/* SYSCTL_INITDONE[KEY] Bits */ +#define SYSCTL_INITDONE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_INITDONE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x9D(157) for write */ +#define SYSCTL_INITDONE_KEY_VALUE ((uint32_t)0x9D000000U) /* !< Issue Reset */ +/* SYSCTL_INITDONE[PASS] Bits */ +#define SYSCTL_INITDONE_PASS_OFS (0) /* !< PASS Offset */ +#define SYSCTL_INITDONE_PASS_MASK ((uint32_t)0x00000001U) /* !< INITCODE writes 1 for PASS, left + unwritten a timeout will occur if not + blocked */ +#define SYSCTL_INITDONE_PASS_TRUE ((uint32_t)0x00000001U) /* !< INITCODE PASS */ + +/* SYSCTL_IIDX Bits */ +/* SYSCTL_IIDX[STAT] Bits */ +#define SYSCTL_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_IIDX_STAT_MASK ((uint32_t)0x0000000FU) /* !< The SYSCTL interrupt index (IIDX) + register generates a value + corresponding to the highest priority + pending interrupt source. This value + may be used as an address offset for + fast, deterministic handling in the + interrupt service routine. A read of + the IIDX register will clear the + corresponding interrupt status in the + RIS and MIS registers. */ +#define SYSCTL_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_IIDX_STAT_LFOSCGOOD ((uint32_t)0x00000001U) /* !< LFOSCGOOD interrupt pending */ +#define SYSCTL_IIDX_STAT_ANACLKERR ((uint32_t)0x00000002U) +#define SYSCTL_IIDX_STAT_FLASHSEC ((uint32_t)0x00000003U) +#define SYSCTL_IIDX_STAT_SRAMSEC ((uint32_t)0x00000004U) +#define SYSCTL_IIDX_STAT_LFXTGOOD ((uint32_t)0x00000005U) +#define SYSCTL_IIDX_STAT_HFCLKGOOD ((uint32_t)0x00000006U) +#define SYSCTL_IIDX_STAT_SYSPLLGOOD ((uint32_t)0x00000007U) +#define SYSCTL_IIDX_STAT_HSCLKGOOD ((uint32_t)0x00000008U) + +/* SYSCTL_IMASK Bits */ +/* SYSCTL_IMASK[LFOSCGOOD] Bits */ +#define SYSCTL_IMASK_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_IMASK_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Enable or disable the LFOSCGOOD + interrupt. LFOSCGOOD indicates that + the LFOSC has started successfully. */ +#define SYSCTL_IMASK_LFOSCGOOD_DISABLE ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define SYSCTL_IMASK_LFOSCGOOD_ENABLE ((uint32_t)0x00000001U) /* !< Interrupt enabled */ +/* SYSCTL_IMASK[HFCLKGOOD] Bits */ +#define SYSCTL_IMASK_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_IMASK_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_IMASK_HFCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HFCLKGOOD_ENABLE ((uint32_t)0x00000020U) +/* SYSCTL_IMASK[SRAMSEC] Bits */ +#define SYSCTL_IMASK_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_IMASK_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_IMASK_SRAMSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_SRAMSEC_ENABLE ((uint32_t)0x00000008U) +/* SYSCTL_IMASK[LFXTGOOD] Bits */ +#define SYSCTL_IMASK_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_IMASK_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_IMASK_LFXTGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_LFXTGOOD_ENABLE ((uint32_t)0x00000010U) +/* SYSCTL_IMASK[HSCLKGOOD] Bits */ +#define SYSCTL_IMASK_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_IMASK_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_IMASK_HSCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HSCLKGOOD_ENABLE ((uint32_t)0x00000080U) +/* SYSCTL_IMASK[SYSPLLGOOD] Bits */ +#define SYSCTL_IMASK_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_IMASK_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_IMASK_SYSPLLGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_SYSPLLGOOD_ENABLE ((uint32_t)0x00000040U) +/* SYSCTL_IMASK[ANACLKERR] Bits */ +#define SYSCTL_IMASK_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_IMASK_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_IMASK_ANACLKERR_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_ANACLKERR_ENABLE ((uint32_t)0x00000002U) +/* SYSCTL_IMASK[FLASHSEC] Bits */ +#define SYSCTL_IMASK_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_IMASK_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_IMASK_FLASHSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_FLASHSEC_ENABLE ((uint32_t)0x00000004U) + +/* SYSCTL_RIS Bits */ +/* SYSCTL_RIS[LFOSCGOOD] Bits */ +#define SYSCTL_RIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_RIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Raw status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_RIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_RIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_RIS[HFCLKGOOD] Bits */ +#define SYSCTL_RIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_RIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_RIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_RIS[SRAMSEC] Bits */ +#define SYSCTL_RIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_RIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_RIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_RIS[LFXTGOOD] Bits */ +#define SYSCTL_RIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_RIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_RIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_RIS[HSCLKGOOD] Bits */ +#define SYSCTL_RIS_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_RIS_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_RIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HSCLKGOOD_TRUE ((uint32_t)0x00000080U) +/* SYSCTL_RIS[SYSPLLGOOD] Bits */ +#define SYSCTL_RIS_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_RIS_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_RIS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_SYSPLLGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_RIS[ANACLKERR] Bits */ +#define SYSCTL_RIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_RIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_RIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_RIS[FLASHSEC] Bits */ +#define SYSCTL_RIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_RIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_RIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) + +/* SYSCTL_MIS Bits */ +/* SYSCTL_MIS[LFOSCGOOD] Bits */ +#define SYSCTL_MIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_MIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Masked status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_MIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_MIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_MIS[HFCLKGOOD] Bits */ +#define SYSCTL_MIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_MIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_MIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_MIS[SRAMSEC] Bits */ +#define SYSCTL_MIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_MIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_MIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_MIS[LFXTGOOD] Bits */ +#define SYSCTL_MIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_MIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_MIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_MIS[HSCLKGOOD] Bits */ +#define SYSCTL_MIS_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_MIS_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_MIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HSCLKGOOD_TRUE ((uint32_t)0x00000080U) +/* SYSCTL_MIS[SYSPLLGOOD] Bits */ +#define SYSCTL_MIS_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_MIS_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_MIS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_SYSPLLGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_MIS[ANACLKERR] Bits */ +#define SYSCTL_MIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_MIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_MIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_MIS[FLASHSEC] Bits */ +#define SYSCTL_MIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_MIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_MIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) + +/* SYSCTL_ISET Bits */ +/* SYSCTL_ISET[LFOSCGOOD] Bits */ +#define SYSCTL_ISET_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ISET_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Set the LFOSCGOOD interrupt. */ +#define SYSCTL_ISET_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_ISET_LFOSCGOOD_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_ISET[HFCLKGOOD] Bits */ +#define SYSCTL_ISET_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ISET_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ISET_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HFCLKGOOD_SET ((uint32_t)0x00000020U) +/* SYSCTL_ISET[SRAMSEC] Bits */ +#define SYSCTL_ISET_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ISET_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ISET_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_SRAMSEC_SET ((uint32_t)0x00000008U) +/* SYSCTL_ISET[LFXTGOOD] Bits */ +#define SYSCTL_ISET_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ISET_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ISET_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_LFXTGOOD_SET ((uint32_t)0x00000010U) +/* SYSCTL_ISET[HSCLKGOOD] Bits */ +#define SYSCTL_ISET_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ISET_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_ISET_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HSCLKGOOD_SET ((uint32_t)0x00000080U) +/* SYSCTL_ISET[SYSPLLGOOD] Bits */ +#define SYSCTL_ISET_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_ISET_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_ISET_SYSPLLGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_SYSPLLGOOD_SET ((uint32_t)0x00000040U) +/* SYSCTL_ISET[ANACLKERR] Bits */ +#define SYSCTL_ISET_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ISET_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ISET_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_ANACLKERR_SET ((uint32_t)0x00000002U) +/* SYSCTL_ISET[FLASHSEC] Bits */ +#define SYSCTL_ISET_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ISET_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ISET_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_FLASHSEC_SET ((uint32_t)0x00000004U) + +/* SYSCTL_ICLR Bits */ +/* SYSCTL_ICLR[LFOSCGOOD] Bits */ +#define SYSCTL_ICLR_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ICLR_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Clear the LFOSCGOOD interrupt. */ +#define SYSCTL_ICLR_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h has no effect */ +#define SYSCTL_ICLR_LFOSCGOOD_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_ICLR[HFCLKGOOD] Bits */ +#define SYSCTL_ICLR_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ICLR_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ICLR_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HFCLKGOOD_CLR ((uint32_t)0x00000020U) +/* SYSCTL_ICLR[SRAMSEC] Bits */ +#define SYSCTL_ICLR_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ICLR_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ICLR_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_SRAMSEC_CLR ((uint32_t)0x00000008U) +/* SYSCTL_ICLR[LFXTGOOD] Bits */ +#define SYSCTL_ICLR_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ICLR_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ICLR_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_LFXTGOOD_CLR ((uint32_t)0x00000010U) +/* SYSCTL_ICLR[HSCLKGOOD] Bits */ +#define SYSCTL_ICLR_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ICLR_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_ICLR_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HSCLKGOOD_CLR ((uint32_t)0x00000080U) +/* SYSCTL_ICLR[SYSPLLGOOD] Bits */ +#define SYSCTL_ICLR_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_ICLR_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_ICLR_SYSPLLGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_SYSPLLGOOD_CLR ((uint32_t)0x00000040U) +/* SYSCTL_ICLR[ANACLKERR] Bits */ +#define SYSCTL_ICLR_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ICLR_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ICLR_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_ANACLKERR_CLR ((uint32_t)0x00000002U) +/* SYSCTL_ICLR[FLASHSEC] Bits */ +#define SYSCTL_ICLR_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ICLR_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ICLR_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_FLASHSEC_CLR ((uint32_t)0x00000004U) + +/* SYSCTL_NMIIIDX Bits */ +/* SYSCTL_NMIIIDX[STAT] Bits */ +#define SYSCTL_NMIIIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_NMIIIDX_STAT_MASK ((uint32_t)0x0000000FU) /* !< The NMI interrupt index (NMIIIDX) + register generates a value + corresponding to the highest priority + pending NMI source. This value may + be used as an address offset for + fast, deterministic handling in the + NMI service routine. A read of the + NMIIIDX register will clear the + corresponding interrupt status in the + NMIRIS register. */ +#define SYSCTL_NMIIIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No NMI pending */ +#define SYSCTL_NMIIIDX_STAT_BORLVL ((uint32_t)0x00000001U) /* !< BOR Threshold NMI pending */ +#define SYSCTL_NMIIIDX_STAT_WWDT0 ((uint32_t)0x00000002U) +#define SYSCTL_NMIIIDX_STAT_WWDT1 ((uint32_t)0x00000003U) +#define SYSCTL_NMIIIDX_STAT_LFCLKFAIL ((uint32_t)0x00000004U) +#define SYSCTL_NMIIIDX_STAT_FLASHDED ((uint32_t)0x00000005U) +#define SYSCTL_NMIIIDX_STAT_SRAMDED ((uint32_t)0x00000006U) + +/* SYSCTL_NMIRIS Bits */ +/* SYSCTL_NMIRIS[WWDT1] Bits */ +#define SYSCTL_NMIRIS_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIRIS_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT1_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT1_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_NMIRIS[SRAMDED] Bits */ +#define SYSCTL_NMIRIS_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIRIS_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIRIS_SRAMDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_SRAMDED_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_NMIRIS[BORLVL] Bits */ +#define SYSCTL_NMIRIS_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIRIS_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Raw status of the BORLVL NMI */ +#define SYSCTL_NMIRIS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_NMIRIS_BORLVL_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_NMIRIS[FLASHDED] Bits */ +#define SYSCTL_NMIRIS_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIRIS_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIRIS_FLASHDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_FLASHDED_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_NMIRIS[WWDT0] Bits */ +#define SYSCTL_NMIRIS_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIRIS_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT0_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT0_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_NMIRIS[LFCLKFAIL] Bits */ +#define SYSCTL_NMIRIS_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIRIS_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIRIS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_LFCLKFAIL_TRUE ((uint32_t)0x00000008U) + +/* SYSCTL_NMIISET Bits */ +/* SYSCTL_NMIISET[WWDT1] Bits */ +#define SYSCTL_NMIISET_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIISET_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT1_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT1_SET ((uint32_t)0x00000004U) +/* SYSCTL_NMIISET[SRAMDED] Bits */ +#define SYSCTL_NMIISET_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIISET_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIISET_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_SRAMDED_SET ((uint32_t)0x00000020U) +/* SYSCTL_NMIISET[BORLVL] Bits */ +#define SYSCTL_NMIISET_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIISET_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Set the BORLVL NMI */ +#define SYSCTL_NMIISET_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIISET_BORLVL_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_NMIISET[FLASHDED] Bits */ +#define SYSCTL_NMIISET_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIISET_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIISET_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_FLASHDED_SET ((uint32_t)0x00000010U) +/* SYSCTL_NMIISET[WWDT0] Bits */ +#define SYSCTL_NMIISET_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIISET_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT0_SET ((uint32_t)0x00000002U) +/* SYSCTL_NMIISET[LFCLKFAIL] Bits */ +#define SYSCTL_NMIISET_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIISET_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIISET_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_LFCLKFAIL_SET ((uint32_t)0x00000008U) + +/* SYSCTL_NMIICLR Bits */ +/* SYSCTL_NMIICLR[WWDT1] Bits */ +#define SYSCTL_NMIICLR_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIICLR_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT1_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT1_CLR ((uint32_t)0x00000004U) +/* SYSCTL_NMIICLR[SRAMDED] Bits */ +#define SYSCTL_NMIICLR_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIICLR_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIICLR_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_SRAMDED_CLR ((uint32_t)0x00000020U) +/* SYSCTL_NMIICLR[BORLVL] Bits */ +#define SYSCTL_NMIICLR_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIICLR_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Clr the BORLVL NMI */ +#define SYSCTL_NMIICLR_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIICLR_BORLVL_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_NMIICLR[FLASHDED] Bits */ +#define SYSCTL_NMIICLR_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIICLR_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIICLR_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_FLASHDED_CLR ((uint32_t)0x00000010U) +/* SYSCTL_NMIICLR[WWDT0] Bits */ +#define SYSCTL_NMIICLR_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIICLR_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT0_CLR ((uint32_t)0x00000002U) +/* SYSCTL_NMIICLR[LFCLKFAIL] Bits */ +#define SYSCTL_NMIICLR_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIICLR_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIICLR_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_LFCLKFAIL_CLR ((uint32_t)0x00000008U) + +/* SYSCTL_SYSOSCCFG Bits */ +/* SYSCTL_SYSOSCCFG[USE4MHZSTOP] Bits */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_OFS (8) /* !< USE4MHZSTOP Offset */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK ((uint32_t)0x00000100U) /* !< USE4MHZSTOP sets the SYSOSC stop + mode frequency policy. When entering + STOP mode, the SYSOSC frequency may + be automatically switched to 4MHz to + reduce SYSOSC power consumption. */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not gear shift the SYSOSC to + 4MHz in STOP mode */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE ((uint32_t)0x00000100U) /* !< Gear shift SYSOSC to 4MHz in STOP + mode */ +/* SYSCTL_SYSOSCCFG[DISABLESTOP] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_OFS (9) /* !< DISABLESTOP Offset */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_MASK ((uint32_t)0x00000200U) /* !< DISABLESTOP sets the SYSOSC stop + mode enable/disable policy. When + operating in STOP mode, the SYSOSC + may be automatically disabled. When + set, ULPCLK will run from LFCLK in + STOP mode and SYSOSC will be disabled + to reduce power consumption. */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC in STOP mode */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE ((uint32_t)0x00000200U) /* !< Disable SYSOSC in STOP mode and + source ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[BLOCKASYNCALL] Bits */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_OFS (16) /* !< BLOCKASYNCALL Offset */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_MASK ((uint32_t)0x00010000U) /* !< BLOCKASYNCALL may be used to mask + block all asynchronous fast clock + requests, preventing hardware from + dynamically changing the active clock + configuration when operating in a + given mode. */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_DISABLE ((uint32_t)0x00000000U) /* !< Asynchronous fast clock requests + are controlled by the requesting + peripheral */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE ((uint32_t)0x00010000U) /* !< All asynchronous fast clock + requests are blocked */ +/* SYSCTL_SYSOSCCFG[DISABLE] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLE_OFS (10) /* !< DISABLE Offset */ +#define SYSCTL_SYSOSCCFG_DISABLE_MASK ((uint32_t)0x00000400U) /* !< DISABLE sets the SYSOSC + enable/disable policy. SYSOSC may be + powered off in RUN, SLEEP, and STOP + modes to reduce power consumption. + When SYSOSC is disabled, MCLK and + ULPCLK are sourced from LFCLK. */ +#define SYSCTL_SYSOSCCFG_DISABLE_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC */ +#define SYSCTL_SYSOSCCFG_DISABLE_ENABLE ((uint32_t)0x00000400U) /* !< Disable SYSOSC immediately and + source MCLK and ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[FASTCPUEVENT] Bits */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_OFS (17) /* !< FASTCPUEVENT Offset */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_MASK ((uint32_t)0x00020000U) /* !< FASTCPUEVENT may be used to assert + a fast clock request when an + interrupt is asserted to the CPU, + reducing interrupt latency. */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_DISABLE ((uint32_t)0x00000000U) /* !< An interrupt to the CPU will not + assert a fast clock request */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE ((uint32_t)0x00020000U) /* !< An interrupt to the CPU will assert + a fast clock request */ +/* SYSCTL_SYSOSCCFG[FREQ] Bits */ +#define SYSCTL_SYSOSCCFG_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCCFG_FREQ_MASK ((uint32_t)0x00000003U) /* !< Target operating frequency for the + system oscillator (SYSOSC) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE ((uint32_t)0x00000000U) /* !< Base frequency (32MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< Low frequency (4MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< User-trimmed frequency (16 or 24 + MHz) */ + +/* SYSCTL_MCLKCFG Bits */ +/* SYSCTL_MCLKCFG[USEMFTICK] Bits */ +#define SYSCTL_MCLKCFG_USEMFTICK_OFS (12) /* !< USEMFTICK Offset */ +#define SYSCTL_MCLKCFG_USEMFTICK_MASK ((uint32_t)0x00001000U) /* !< USEMFTICK specifies whether the + 4MHz constant-rate clock (MFCLK) to + peripherals is enabled or disabled. + When enabled, MDIV must be disabled + (set to 0h=/1). */ +#define SYSCTL_MCLKCFG_USEMFTICK_DISABLE ((uint32_t)0x00000000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled */ +#define SYSCTL_MCLKCFG_USEMFTICK_ENABLE ((uint32_t)0x00001000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled. */ +/* SYSCTL_MCLKCFG[MDIV] Bits */ +#define SYSCTL_MCLKCFG_MDIV_OFS (0) /* !< MDIV Offset */ +#define SYSCTL_MCLKCFG_MDIV_MASK ((uint32_t)0x0000000FU) /* !< MDIV may be used to divide the MCLK + frequency when MCLK is sourced from + SYSOSC. MDIV=0h corresponds to /1 + (no divider). MDIV=1h corresponds to + /2 (divide-by-2). MDIV=Fh + corresponds to /16 (divide-by-16). + MDIV may be set between /1 and /16 on + an integer basis. */ +/* SYSCTL_MCLKCFG[USEHSCLK] Bits */ +#define SYSCTL_MCLKCFG_USEHSCLK_OFS (16) /* !< USEHSCLK Offset */ +#define SYSCTL_MCLKCFG_USEHSCLK_MASK ((uint32_t)0x00010000U) /* !< USEHSCLK, together with USELFCLK, + sets the MCLK source policy. Set + USEHSCLK to use HSCLK (HFCLK or + SYSPLL) as the MCLK source in RUN and + SLEEP modes. */ +#define SYSCTL_MCLKCFG_USEHSCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the high speed + clock (HSCLK) */ +#define SYSCTL_MCLKCFG_USEHSCLK_ENABLE ((uint32_t)0x00010000U) /* !< MCLK will use the high speed clock + (HSCLK) in RUN and SLEEP mode */ +/* SYSCTL_MCLKCFG[USELFCLK] Bits */ +#define SYSCTL_MCLKCFG_USELFCLK_OFS (20) /* !< USELFCLK Offset */ +#define SYSCTL_MCLKCFG_USELFCLK_MASK ((uint32_t)0x00100000U) /* !< USELFCLK sets the MCLK source + policy. Set USELFCLK to use LFCLK as + the MCLK source. Note that setting + USELFCLK does not disable SYSOSC, and + SYSOSC remains available for direct + use by analog modules. */ +#define SYSCTL_MCLKCFG_USELFCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the low frequency + clock (LFCLK) */ +#define SYSCTL_MCLKCFG_USELFCLK_ENABLE ((uint32_t)0x00100000U) /* !< MCLK will use the low frequency + clock (LFCLK) */ +/* SYSCTL_MCLKCFG[STOPCLKSTBY] Bits */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_OFS (21) /* !< STOPCLKSTBY Offset */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_MASK ((uint32_t)0x00200000U) /* !< STOPCLKSTBY sets the STANDBY mode + policy (STANDBY0 or STANDBY1). When + set, ULPCLK and LFCLK are disabled to + all peripherals in STANDBY mode, with + the exception of TIMG0 and TIMG1 + which continue to run. Wake-up is + only possible via an asynchronous + fast clock request. */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_DISABLE ((uint32_t)0x00000000U) /* !< ULPCLK/LFCLK runs to all PD0 + peripherals in STANDBY mode */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE ((uint32_t)0x00200000U) /* !< ULPCLK/LFCLK is disabled to all + peripherals in STANDBY mode except + TIMG0 and TIMG1 */ +/* SYSCTL_MCLKCFG[FLASHWAIT] Bits */ +#define SYSCTL_MCLKCFG_FLASHWAIT_OFS (8) /* !< FLASHWAIT Offset */ +#define SYSCTL_MCLKCFG_FLASHWAIT_MASK ((uint32_t)0x00000F00U) /* !< FLASHWAIT specifies the number of + flash wait states when MCLK is + sourced from HSCLK. FLASHWAIT has no + effect when MCLK is sourced from + SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT0 ((uint32_t)0x00000000U) /* !< No flash wait states are applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT1 ((uint32_t)0x00000100U) /* !< One flash wait state is applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT2 ((uint32_t)0x00000200U) /* !< 2 flash wait states are applied */ +/* SYSCTL_MCLKCFG[MCLKDEADCHK] Bits */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_OFS (22) /* !< MCLKDEADCHK Offset */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_MASK ((uint32_t)0x00400000U) /* !< MCLKDEADCHK enables or disables the + continuous MCLK dead check monitor. + LFCLK must be running before + MCLKDEADCHK is enabled. */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_DISABLE ((uint32_t)0x00000000U) /* !< The MCLK dead check monitor is + disabled */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_ENABLE ((uint32_t)0x00400000U) /* !< The MCLK dead check monitor is + enabled */ +/* SYSCTL_MCLKCFG[UDIV] Bits */ +#define SYSCTL_MCLKCFG_UDIV_OFS (4) /* !< UDIV Offset */ +#define SYSCTL_MCLKCFG_UDIV_MASK ((uint32_t)0x00000030U) /* !< UDIV specifies the ULPCLK divider + when MCLK is sourced from HSCLK. + UDIV has no effect when MCLK is + sourced from SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_UDIV_NODIVIDE ((uint32_t)0x00000000U) /* !< ULPCLK is not divided and is equal + to MCLK */ +#define SYSCTL_MCLKCFG_UDIV_DIVIDE2 ((uint32_t)0x00000010U) /* !< ULPCLK is MCLK/2 (divided-by-2) */ + +/* SYSCTL_HSCLKEN Bits */ +/* SYSCTL_HSCLKEN[HFXTEN] Bits */ +#define SYSCTL_HSCLKEN_HFXTEN_OFS (0) /* !< HFXTEN Offset */ +#define SYSCTL_HSCLKEN_HFXTEN_MASK ((uint32_t)0x00000001U) /* !< HFXTEN enables or disables the high + frequency crystal oscillator (HFXT). */ +#define SYSCTL_HSCLKEN_HFXTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the HFXT */ +#define SYSCTL_HSCLKEN_HFXTEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable the HFXT */ +/* SYSCTL_HSCLKEN[USEEXTHFCLK] Bits */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_OFS (16) /* !< USEEXTHFCLK Offset */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_MASK ((uint32_t)0x00010000U) /* !< USEEXTHFCLK selects the HFCLK_IN + digital clock input to be the source + for HFCLK. When disabled, HFXT is + the HFCLK source and HFXTEN may be + set. Do not set HFXTEN and + USEEXTHFCLK simultaneously. */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_DISABLE ((uint32_t)0x00000000U) /* !< Use HFXT as the HFCLK source */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE ((uint32_t)0x00010000U) /* !< Use the HFCLK_IN digital clock + input as the HFCLK source */ +/* SYSCTL_HSCLKEN[SYSPLLEN] Bits */ +#define SYSCTL_HSCLKEN_SYSPLLEN_OFS (8) /* !< SYSPLLEN Offset */ +#define SYSCTL_HSCLKEN_SYSPLLEN_MASK ((uint32_t)0x00000100U) /* !< SYSPLLEN enables or disables the + system phase-lock loop (SYSPLL). */ +#define SYSCTL_HSCLKEN_SYSPLLEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the SYSPLL */ +#define SYSCTL_HSCLKEN_SYSPLLEN_ENABLE ((uint32_t)0x00000100U) /* !< Enable the SYSPLL */ + +/* SYSCTL_HSCLKCFG Bits */ +/* SYSCTL_HSCLKCFG[HSCLKSEL] Bits */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_OFS (0) /* !< HSCLKSEL Offset */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_MASK ((uint32_t)0x00000001U) /* !< HSCLKSEL selects the HSCLK source + (SYSPLL or HFCLK). */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is sourced from the SYSPLL */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK ((uint32_t)0x00000001U) /* !< HSCLK is sourced from the HFCLK */ + +/* SYSCTL_HFCLKCLKCFG Bits */ +/* SYSCTL_HFCLKCLKCFG[HFXTTIME] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_OFS (0) /* !< HFXTTIME Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK ((uint32_t)0x000000FFU) /* !< HFXTTIME specifies the HFXT startup + time in 64us resolution. If the + HFCLK startup monitor is enabled + (HFCLKFLTCHK), HFXT will be checked + after this time expires. */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MINSTARTTIME ((uint32_t)0x00000000U) /* !< Minimum startup time (approximatly + zero) */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MAXSTARTTIME ((uint32_t)0x000000FFU) /* !< Maximum startup time (approximatly + 16.32ms) */ +/* SYSCTL_HFCLKCLKCFG[HFCLKFLTCHK] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_OFS (28) /* !< HFCLKFLTCHK Offset */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK ((uint32_t)0x10000000U) /* !< HFCLKFLTCHK enables or disables the + HFCLK startup monitor. */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_DISABLE ((uint32_t)0x00000000U) /* !< HFCLK startup is not checked */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE ((uint32_t)0x10000000U) /* !< HFCLK startup is checked */ +/* SYSCTL_HFCLKCLKCFG[HFXTRSEL] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS (12) /* !< HFXTRSEL Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK ((uint32_t)0x00003000U) /* !< HFXT Range Select */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8 ((uint32_t)0x00000000U) /* !< 4MHz <= HFXT frequency <= 8MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16 ((uint32_t)0x00001000U) /* !< 8MHz < HFXT frequency <= 16MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32 ((uint32_t)0x00002000U) /* !< 16MHz < HFXT frequency <= 32MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48 ((uint32_t)0x00003000U) /* !< 32MHz < HFXT frequency <= 48MHz */ + +/* SYSCTL_LFCLKCFG Bits */ +/* SYSCTL_LFCLKCFG[XT1DRIVE] Bits */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_OFS (0) /* !< XT1DRIVE Offset */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_MASK ((uint32_t)0x00000003U) /* !< XT1DRIVE selects the low frequency + crystal oscillator (LFXT) drive + strength. */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV ((uint32_t)0x00000000U) /* !< Lowest drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV ((uint32_t)0x00000001U) /* !< Lower drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV ((uint32_t)0x00000002U) /* !< Higher drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV ((uint32_t)0x00000003U) /* !< Highest drive and current */ +/* SYSCTL_LFCLKCFG[MONITOR] Bits */ +#define SYSCTL_LFCLKCFG_MONITOR_OFS (4) /* !< MONITOR Offset */ +#define SYSCTL_LFCLKCFG_MONITOR_MASK ((uint32_t)0x00000010U) /* !< MONITOR enables or disables the + LFCLK monitor, which continuously + checks LFXT or LFCLK_IN for a clock + stuck fault. */ +#define SYSCTL_LFCLKCFG_MONITOR_DISABLE ((uint32_t)0x00000000U) /* !< Clock monitor is disabled */ +#define SYSCTL_LFCLKCFG_MONITOR_ENABLE ((uint32_t)0x00000010U) /* !< Clock monitor is enabled */ +/* SYSCTL_LFCLKCFG[LOWCAP] Bits */ +#define SYSCTL_LFCLKCFG_LOWCAP_OFS (8) /* !< LOWCAP Offset */ +#define SYSCTL_LFCLKCFG_LOWCAP_MASK ((uint32_t)0x00000100U) /* !< LOWCAP controls the low-power LFXT + mode. When the LFXT load capacitance + is less than 3pf, LOWCAP may be set + for reduced power consumption. */ +#define SYSCTL_LFCLKCFG_LOWCAP_DISABLE ((uint32_t)0x00000000U) /* !< LFXT low capacitance mode is + disabled */ +#define SYSCTL_LFCLKCFG_LOWCAP_ENABLE ((uint32_t)0x00000100U) /* !< LFXT low capacitance mode is + enabled */ + +/* SYSCTL_SYSPLLCFG0 Bits */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK0] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_OFS (4) /* !< ENABLECLK0 Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK ((uint32_t)0x00000010U) /* !< ENABLECLK0 enables or disables the + SYSPLLCLK0 output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK0 is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_ENABLE ((uint32_t)0x00000010U) /* !< SYSPLLCLK0 is enabled */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK1] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_OFS (5) /* !< ENABLECLK1 Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK ((uint32_t)0x00000020U) /* !< ENABLECLK1 enables or disables the + SYSPLLCLK1 output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_ENABLE ((uint32_t)0x00000020U) /* !< SYSPLLCLK1 is enabled */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK1] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS (12) /* !< RDIVCLK1 Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK ((uint32_t)0x0000F000U) /* !< RDIVCLK1 sets the final divider for + the SYSPLLCLK1 output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV2 ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV4 ((uint32_t)0x00001000U) /* !< SYSPLLCLK1 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV6 ((uint32_t)0x00002000U) /* !< SYSPLLCLK1 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV8 ((uint32_t)0x00003000U) /* !< SYSPLLCLK1 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV10 ((uint32_t)0x00004000U) /* !< SYSPLLCLK1 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV12 ((uint32_t)0x00005000U) /* !< SYSPLLCLK1 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV14 ((uint32_t)0x00006000U) /* !< SYSPLLCLK1 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV16 ((uint32_t)0x00007000U) /* !< SYSPLLCLK1 is divided by 16 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV18 ((uint32_t)0x00008000U) /* !< SYSPLLCLK1 is divided by 18 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV20 ((uint32_t)0x00009000U) /* !< SYSPLLCLK1 is divided by 20 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV22 ((uint32_t)0x0000A000U) /* !< SYSPLLCLK1 is divided by 22 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV24 ((uint32_t)0x0000B000U) /* !< SYSPLLCLK1 is divided by 24 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV26 ((uint32_t)0x0000C000U) /* !< SYSPLLCLK1 is divided by 26 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV28 ((uint32_t)0x0000D000U) /* !< SYSPLLCLK1 is divided by 28 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV30 ((uint32_t)0x0000E000U) /* !< SYSPLLCLK1 is divided by 30 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV32 ((uint32_t)0x0000F000U) /* !< SYSPLLCLK1 is divided by 32 */ +/* SYSCTL_SYSPLLCFG0[MCLK2XVCO] Bits */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_OFS (1) /* !< MCLK2XVCO Offset */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK ((uint32_t)0x00000002U) /* !< MCLK2XVCO selects the SYSPLL output + which is sent to the HSCLK mux for + use by MCLK. */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_DISABLE ((uint32_t)0x00000000U) /* !< The SYSPLLCLK0 output is sent to + the HSCLK mux */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_ENABLE ((uint32_t)0x00000002U) /* !< The SYSPLLCLK2X output is sent to + the HSCLK mux */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK2X] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS (16) /* !< RDIVCLK2X Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK ((uint32_t)0x000F0000U) /* !< RDIVCLK2X sets the final divider + for the SYSPLLCLK2X output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV1 ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is divided by 1 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV2 ((uint32_t)0x00010000U) /* !< SYSPLLCLK1 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV3 ((uint32_t)0x00020000U) /* !< SYSPLLCLK1 is divided by 3 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV4 ((uint32_t)0x00030000U) /* !< SYSPLLCLK1 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV5 ((uint32_t)0x00040000U) /* !< SYSPLLCLK1 is divided by 5 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV6 ((uint32_t)0x00050000U) /* !< SYSPLLCLK1 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV7 ((uint32_t)0x00060000U) /* !< SYSPLLCLK1 is divided by 7 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV8 ((uint32_t)0x00070000U) /* !< SYSPLLCLK1 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV9 ((uint32_t)0x00080000U) /* !< SYSPLLCLK1 is divided by 9 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV10 ((uint32_t)0x00090000U) /* !< SYSPLLCLK1 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV11 ((uint32_t)0x000A0000U) /* !< SYSPLLCLK1 is divided by 11 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV12 ((uint32_t)0x000B0000U) /* !< SYSPLLCLK1 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV13 ((uint32_t)0x000C0000U) /* !< SYSPLLCLK1 is divided by 13 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV14 ((uint32_t)0x000D0000U) /* !< SYSPLLCLK1 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV15 ((uint32_t)0x000E0000U) /* !< SYSPLLCLK1 is divided by 15 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV16 ((uint32_t)0x000F0000U) /* !< SYSPLLCLK1 is divided by 16 */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK0] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS (8) /* !< RDIVCLK0 Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK ((uint32_t)0x00000F00U) /* !< RDIVCLK0 sets the final divider for + the SYSPLLCLK0 output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV2 ((uint32_t)0x00000000U) /* !< SYSPLLCLK0 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV4 ((uint32_t)0x00000100U) /* !< SYSPLLCLK0 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV6 ((uint32_t)0x00000200U) /* !< SYSPLLCLK0 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV8 ((uint32_t)0x00000300U) /* !< SYSPLLCLK0 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV10 ((uint32_t)0x00000400U) /* !< SYSPLLCLK0 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV12 ((uint32_t)0x00000500U) /* !< SYSPLLCLK0 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV14 ((uint32_t)0x00000600U) /* !< SYSPLLCLK0 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV16 ((uint32_t)0x00000700U) /* !< SYSPLLCLK0 is divided by 16 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV18 ((uint32_t)0x00000800U) /* !< SYSPLLCLK0 is divided by 18 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV20 ((uint32_t)0x00000900U) /* !< SYSPLLCLK0 is divided by 20 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV22 ((uint32_t)0x00000A00U) /* !< SYSPLLCLK0 is divided by 22 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV24 ((uint32_t)0x00000B00U) /* !< SYSPLLCLK0 is divided by 24 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV26 ((uint32_t)0x00000C00U) /* !< SYSPLLCLK0 is divided by 26 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV28 ((uint32_t)0x00000D00U) /* !< SYSPLLCLK0 is divided by 28 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV30 ((uint32_t)0x00000E00U) /* !< SYSPLLCLK0 is divided by 30 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV32 ((uint32_t)0x00000F00U) /* !< SYSPLLCLK0 is divided by 32 */ +/* SYSCTL_SYSPLLCFG0[SYSPLLREF] Bits */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_OFS (0) /* !< SYSPLLREF Offset */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK ((uint32_t)0x00000001U) /* !< SYSPLLREF selects the system PLL + (SYSPLL) reference clock source. */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_SYSOSC ((uint32_t)0x00000000U) /* !< SYSPLL reference is SYSOSC */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_HFCLK ((uint32_t)0x00000001U) /* !< SYSPLL reference is HFCLK */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK2X] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_OFS (6) /* !< ENABLECLK2X Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK ((uint32_t)0x00000040U) /* !< ENABLECLK2X enables or disables the + SYSPLLCLK2X output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK2X is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_ENABLE ((uint32_t)0x00000040U) /* !< SYSPLLCLK2X is enabled */ + +/* SYSCTL_SYSPLLCFG1 Bits */ +/* SYSCTL_SYSPLLCFG1[PDIV] Bits */ +#define SYSCTL_SYSPLLCFG1_PDIV_OFS (0) /* !< PDIV Offset */ +#define SYSCTL_SYSPLLCFG1_PDIV_MASK ((uint32_t)0x00000003U) /* !< PDIV selects the SYSPLL reference + clock prescale divider. */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV1 ((uint32_t)0x00000000U) /* !< SYSPLLREF is not divided */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV2 ((uint32_t)0x00000001U) /* !< SYSPLLREF is divided by 2 */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV4 ((uint32_t)0x00000002U) /* !< SYSPLLREF is divided by 4 */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV8 ((uint32_t)0x00000003U) /* !< SYSPLLREF is divided by 8 */ +/* SYSCTL_SYSPLLCFG1[QDIV] Bits */ +#define SYSCTL_SYSPLLCFG1_QDIV_OFS (8) /* !< QDIV Offset */ +#define SYSCTL_SYSPLLCFG1_QDIV_MASK ((uint32_t)0x00007F00U) /* !< QDIV selects the SYSPLL feedback + path divider. */ +#define SYSCTL_SYSPLLCFG1_QDIV_INVALID ((uint32_t)0x00000000U) /* !< Divide-by-one is not a valid QDIV + option */ +#define SYSCTL_SYSPLLCFG1_QDIV_QDIVMIN ((uint32_t)0x00000100U) /* !< Feedback path is divided by 2 */ +#define SYSCTL_SYSPLLCFG1_QDIV_QDIVMAX ((uint32_t)0x00007E00U) /* !< Feedback path is divided by 127 + (0x7E) */ + +/* SYSCTL_SYSPLLPARAM0 Bits */ +/* SYSCTL_SYSPLLPARAM0[CPCURRENT] Bits */ +#define SYSCTL_SYSPLLPARAM0_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */ +#define SYSCTL_SYSPLLPARAM0_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge pump current */ +/* SYSCTL_SYSPLLPARAM0[CAPBOVERRIDE] Bits */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< CAPBOVERRIDE controls the override + for Cap B */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U) /* !< Cap B override disabled */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U) /* !< Cap B override enabled */ +/* SYSCTL_SYSPLLPARAM0[STARTTIME] Bits */ +#define SYSCTL_SYSPLLPARAM0_STARTTIME_OFS (0) /* !< STARTTIME Offset */ +#define SYSCTL_SYSPLLPARAM0_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from enable to locked + clock, in 1us resolution */ +/* SYSCTL_SYSPLLPARAM0[CAPBVAL] Bits */ +#define SYSCTL_SYSPLLPARAM0_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */ +#define SYSCTL_SYSPLLPARAM0_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override value for Cap B */ +/* SYSCTL_SYSPLLPARAM0[STARTTIMELP] Bits */ +#define SYSCTL_SYSPLLPARAM0_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */ +#define SYSCTL_SYSPLLPARAM0_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from low power mode + exit to locked clock, in 1us + resolution */ + +/* SYSCTL_SYSPLLPARAM1 Bits */ +/* SYSCTL_SYSPLLPARAM1[LPFCAPA] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop filter Cap A */ +/* SYSCTL_SYSPLLPARAM1[LPFRESC] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFRESC_OFS (24) /* !< LPFRESC Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop filter Res C */ +/* SYSCTL_SYSPLLPARAM1[LPFRESA] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFRESA_OFS (8) /* !< LPFRESA Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop filter Res A */ + +/* SYSCTL_GENCLKCFG Bits */ +/* SYSCTL_GENCLKCFG[HFCLK4MFPCLKDIV] Bits */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS (12) /* !< HFCLK4MFPCLKDIV Offset */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK ((uint32_t)0x0000F000U) /* !< HFCLK4MFPCLKDIV selects the divider + applied to HFCLK when HFCLK is used + as the MFPCLK source. Integer + dividers from /1 to /16 may be + selected. */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV1 ((uint32_t)0x00000000U) /* !< HFCLK is not divided before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV2 ((uint32_t)0x00001000U) /* !< HFCLK is divided by 2 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV3 ((uint32_t)0x00002000U) /* !< HFCLK is divided by 3 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV4 ((uint32_t)0x00003000U) /* !< HFCLK is divided by 4 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV5 ((uint32_t)0x00004000U) /* !< HFCLK is divided by 5 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV6 ((uint32_t)0x00005000U) /* !< HFCLK is divided by 6 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV7 ((uint32_t)0x00006000U) /* !< HFCLK is divided by 7 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV8 ((uint32_t)0x00007000U) /* !< HFCLK is divided by 8 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV9 ((uint32_t)0x00008000U) /* !< HFCLK is divided by 9 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV10 ((uint32_t)0x00009000U) /* !< HFCLK is divided by 10 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV11 ((uint32_t)0x0000A000U) /* !< HFCLK is divided by 11 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV12 ((uint32_t)0x0000B000U) /* !< HFCLK is divided by 12 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV13 ((uint32_t)0x0000C000U) /* !< HFCLK is divided by 13 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV14 ((uint32_t)0x0000D000U) /* !< HFCLK is divided by 14 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV15 ((uint32_t)0x0000E000U) /* !< HFCLK is divided by 15 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV16 ((uint32_t)0x0000F000U) /* !< HFCLK is divided by 16 before being + used for MFPCLK */ +/* SYSCTL_GENCLKCFG[MFPCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_OFS (9) /* !< MFPCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_MASK ((uint32_t)0x00000200U) /* !< MFPCLKSRC selects the MFPCLK + (middle frequency precision clock) + source. */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< MFPCLK is sourced from SYSOSC */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK ((uint32_t)0x00000200U) /* !< MFPCLK is sourced from HFCLK */ +/* SYSCTL_GENCLKCFG[CANCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_CANCLKSRC_OFS (8) /* !< CANCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_CANCLKSRC_MASK ((uint32_t)0x00000100U) /* !< CANCLKSRC selects the CANCLK + source. */ +#define SYSCTL_GENCLKCFG_CANCLKSRC_HFCLK ((uint32_t)0x00000000U) /* !< CANCLK source is HFCLK */ +#define SYSCTL_GENCLKCFG_CANCLKSRC_SYSPLLOUT1 ((uint32_t)0x00000100U) /* !< CANCLK source is SYSPLLCLK1 */ +/* SYSCTL_GENCLKCFG[FCCTRIGCNT] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS (24) /* !< FCCTRIGCNT Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK ((uint32_t)0x1F000000U) /* !< FCCTRIGCNT specifies the number of + trigger clock periods in the trigger + window. FCCTRIGCNT=0h (one trigger + clock period) up to 1Fh (32 trigger + clock periods) may be specified. */ +/* SYSCTL_GENCLKCFG[ANACPUMPCFG] Bits */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_OFS (22) /* !< ANACPUMPCFG Offset */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK ((uint32_t)0x00C00000U) /* !< ANACPUMPCFG selects the analog mux + charge pump (VBOOST) enable method. */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND ((uint32_t)0x00000000U) /* !< VBOOST is enabled on request from a + COMP, GPAMP, or OPA */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE ((uint32_t)0x00400000U) /* !< VBOOST is enabled when the device + is in RUN or SLEEP mode, or when a + COMP/GPAMP/OPA is enabled */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS ((uint32_t)0x00800000U) /* !< VBOOST is always enabled */ +/* SYSCTL_GENCLKCFG[FCCSELCLK] Bits */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_OFS (16) /* !< FCCSELCLK Offset */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MASK ((uint32_t)0x000F0000U) /* !< FCCSELCLK selectes the frequency + clock counter (FCC) clock source. */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MCLK ((uint32_t)0x00000000U) /* !< FCC clock is MCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC ((uint32_t)0x00010000U) /* !< FCC clock is SYSOSC */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK ((uint32_t)0x00020000U) /* !< FCC clock is HFCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK ((uint32_t)0x00030000U) /* !< FCC clock is the CLK_OUT selection */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK0 ((uint32_t)0x00040000U) /* !< FCC clock is SYSPLLCLK0 */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK1 ((uint32_t)0x00050000U) /* !< FCC clock is SYSPLLCLK1 */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK2X ((uint32_t)0x00060000U) /* !< FCC clock is SYSPLLCLK2X */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN ((uint32_t)0x00070000U) /* !< FCC clock is the FCCIN external + input */ +/* SYSCTL_GENCLKCFG[FCCTRIGSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_OFS (20) /* !< FCCTRIGSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK ((uint32_t)0x00100000U) /* !< FCCTRIGSRC selects the frequency + clock counter (FCC) trigger source. */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN ((uint32_t)0x00000000U) /* !< FCC trigger is the external pin */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK ((uint32_t)0x00100000U) /* !< FCC trigger is the LFCLK */ +/* SYSCTL_GENCLKCFG[FCCLVLTRIG] Bits */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_OFS (21) /* !< FCCLVLTRIG Offset */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK ((uint32_t)0x00200000U) /* !< FCCLVLTRIG selects the frequency + clock counter (FCC) trigger mode. */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE ((uint32_t)0x00000000U) /* !< Rising edge to rising edge + triggered */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL ((uint32_t)0x00200000U) /* !< Level triggered */ +/* SYSCTL_GENCLKCFG[EXCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_OFS (0) /* !< EXCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MASK ((uint32_t)0x00000007U) /* !< EXCLKSRC selects the source for the + CLK_OUT external clock output block. + ULPCLK and MFPCLK require the CLK_OUT + divider (EXCLKDIVEN) to be enabled */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< CLK_OUT is SYSOSC */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK ((uint32_t)0x00000001U) /* !< CLK_OUT is ULPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK ((uint32_t)0x00000002U) /* !< CLK_OUT is LFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK ((uint32_t)0x00000003U) /* !< CLK_OUT is MFPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK ((uint32_t)0x00000004U) /* !< CLK_OUT is HFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSPLLOUT1 ((uint32_t)0x00000005U) /* !< CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 + must be <=48MHz) */ +/* SYSCTL_GENCLKCFG[EXCLKDIVVAL] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_OFS (4) /* !< EXCLKDIVVAL Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK ((uint32_t)0x00000070U) /* !< EXCLKDIVVAL selects the divider + value for the divider in the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2 ((uint32_t)0x00000000U) /* !< CLK_OUT source is divided by 2 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4 ((uint32_t)0x00000010U) /* !< CLK_OUT source is divided by 4 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6 ((uint32_t)0x00000020U) /* !< CLK_OUT source is divided by 6 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8 ((uint32_t)0x00000030U) /* !< CLK_OUT source is divided by 8 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10 ((uint32_t)0x00000040U) /* !< CLK_OUT source is divided by 10 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12 ((uint32_t)0x00000050U) /* !< CLK_OUT source is divided by 12 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14 ((uint32_t)0x00000060U) /* !< CLK_OUT source is divided by 14 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16 ((uint32_t)0x00000070U) /* !< CLK_OUT source is divided by 16 */ +/* SYSCTL_GENCLKCFG[EXCLKDIVEN] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_OFS (7) /* !< EXCLKDIVEN Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK ((uint32_t)0x00000080U) /* !< EXCLKDIVEN enables or disables the + divider function of the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU ((uint32_t)0x00000000U) /* !< CLock divider is disabled + (passthrough, EXCLKDIVVAL is not + applied) */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE ((uint32_t)0x00000080U) /* !< Clock divider is enabled + (EXCLKDIVVAL is applied) */ + +/* SYSCTL_GENCLKEN Bits */ +/* SYSCTL_GENCLKEN[EXCLKEN] Bits */ +#define SYSCTL_GENCLKEN_EXCLKEN_OFS (0) /* !< EXCLKEN Offset */ +#define SYSCTL_GENCLKEN_EXCLKEN_MASK ((uint32_t)0x00000001U) /* !< EXCLKEN enables the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKEN_EXCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< CLK_OUT block is disabled */ +#define SYSCTL_GENCLKEN_EXCLKEN_ENABLE ((uint32_t)0x00000001U) /* !< CLK_OUT block is enabled */ +/* SYSCTL_GENCLKEN[MFPCLKEN] Bits */ +#define SYSCTL_GENCLKEN_MFPCLKEN_OFS (4) /* !< MFPCLKEN Offset */ +#define SYSCTL_GENCLKEN_MFPCLKEN_MASK ((uint32_t)0x00000010U) /* !< MFPCLKEN enables the middle + frequency precision clock (MFPCLK). */ +#define SYSCTL_GENCLKEN_MFPCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< MFPCLK is disabled */ +#define SYSCTL_GENCLKEN_MFPCLKEN_ENABLE ((uint32_t)0x00000010U) /* !< MFPCLK is enabled */ + +/* SYSCTL_PMODECFG Bits */ +/* SYSCTL_PMODECFG[DSLEEP] Bits */ +#define SYSCTL_PMODECFG_DSLEEP_OFS (0) /* !< DSLEEP Offset */ +#define SYSCTL_PMODECFG_DSLEEP_MASK ((uint32_t)0x00000003U) /* !< DSLEEP selects the operating mode + to enter upon a DEEPSLEEP request + from the CPU. */ +#define SYSCTL_PMODECFG_DSLEEP_STOP ((uint32_t)0x00000000U) /* !< STOP mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_STANDBY ((uint32_t)0x00000001U) /* !< STANDBY mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_SHUTDOWN ((uint32_t)0x00000002U) /* !< SHUTDOWN mode is entered */ + +/* SYSCTL_FCC Bits */ +/* SYSCTL_FCC[DATA] Bits */ +#define SYSCTL_FCC_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FCC_DATA_MASK ((uint32_t)0x003FFFFFU) /* !< Frequency clock counter (FCC) count + value. */ + +/* SYSCTL_SYSOSCTRIMUSER Bits */ +/* SYSCTL_SYSOSCTRIMUSER[RESCOARSE] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RESCOARSE_OFS (8) /* !< RESCOARSE Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RESCOARSE_MASK ((uint32_t)0x00003F00U) /* !< RESCOARSE specifies the resister + coarse trim. This value changes with + the target frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[RESFINE] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RESFINE_OFS (16) /* !< RESFINE Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RESFINE_MASK ((uint32_t)0x000F0000U) /* !< RESFINE specifies the resister fine + trim. This value changes with the + target frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[RDIV] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RDIV_OFS (20) /* !< RDIV Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RDIV_MASK ((uint32_t)0x1FF00000U) /* !< RDIV specifies the frequency + correction loop (FCL) resistor trim. + This value changes with the target + frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[FREQ] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_MASK ((uint32_t)0x00000003U) /* !< FREQ specifies the target + user-trimmed frequency for SYSOSC. */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC16M ((uint32_t)0x00000001U) /* !< 16MHz user frequency */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC24M ((uint32_t)0x00000002U) /* !< 24MHz user frequency */ +/* SYSCTL_SYSOSCTRIMUSER[CAP] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_CAP_OFS (4) /* !< CAP Offset */ +#define SYSCTL_SYSOSCTRIMUSER_CAP_MASK ((uint32_t)0x00000070U) /* !< CAP specifies the SYSOSC capacitor + trim. This value changes with the + target frequency. */ + +/* SYSCTL_SRAMBOUNDARY Bits */ +/* SYSCTL_SRAMBOUNDARY[ADDR] Bits */ +#define SYSCTL_SRAMBOUNDARY_ADDR_OFS (5) /* !< ADDR Offset */ +#define SYSCTL_SRAMBOUNDARY_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary configuration. The + value configured into this acts such + that: SRAM accesses to addresses less + than or equal value will be RW only. + SRAM accesses to addresses greater + than value will be RX only. Value of + 0 is not valid (system will have no + stack). If set to 0, the system acts + as if the entire SRAM is RWX. Any + non-zero value can be configured, + including a value = SRAM size. */ + +/* SYSCTL_SRAMBOUNDARYHIGH Bits */ +/* SYSCTL_SRAMBOUNDARYHIGH[ADDR] Bits */ +#define SYSCTL_SRAMBOUNDARYHIGH_ADDR_OFS (5) /* !< ADDR Offset */ +#define SYSCTL_SRAMBOUNDARYHIGH_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary high configuration. + The value configured into this acts + such that: SRAM accesses to greater + than value will be RW only. SRAM + accesses to addresses less than or + equal to value will be RX until + meeting SRAMBOUNDARY MMR Value. Value + of 0 is default. If value set to less + than or equal to SRAMBOUNDARY MMR, + the system will only use the + SRAMBOUNDARY MMR as criteria. */ + +/* SYSCTL_SYSTEMCFG Bits */ +/* SYSCTL_SYSTEMCFG[KEY] Bits */ +#define SYSCTL_SYSTEMCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSTEMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 1Bh (27) must be + written to KEY together with contents + to be updated. Reads as 0 */ +#define SYSCTL_SYSTEMCFG_KEY_VALUE ((uint32_t)0x1B000000U) /* !< Issue write */ +/* SYSCTL_SYSTEMCFG[FLASHECCRSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS (2) /* !< FLASHECCRSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK ((uint32_t)0x00000004U) /* !< FLASHECCRSTDIS specifies whether a + flash ECC double error detect (DED) + will trigger a SYSRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_FALSE ((uint32_t)0x00000000U) /* !< Flash ECC DED will trigger a SYSRST */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_TRUE ((uint32_t)0x00000004U) /* !< Flash ECC DED will trigger a NMI */ +/* SYSCTL_SYSTEMCFG[WWDTLP0RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS (0) /* !< WWDTLP0RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK ((uint32_t)0x00000001U) /* !< WWDTLP0RSTDIS specifies whether a + WWDT Error Event will trigger a + BOOTRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP0 Error Event will trigger a + BOOTRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_TRUE ((uint32_t)0x00000001U) /* !< WWDTLP0 Error Event will trigger an + NMI */ +/* SYSCTL_SYSTEMCFG[WWDTLP1RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS (1) /* !< WWDTLP1RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK ((uint32_t)0x00000002U) /* !< WWDTLP1RSTDIS specifies whether a + WWDT Error Event will trigger a + SYSRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP1 Error Event will trigger a + SYSRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_TRUE ((uint32_t)0x00000002U) /* !< WWDTLP1 Error Event will trigger an + NMI */ + +/* SYSCTL_SRAMCFG Bits */ +/* SYSCTL_SRAMCFG[KEY] Bits */ +#define SYSCTL_SRAMCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SRAMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of B5h (181) must be + written to KEY together with contents + to be updated. Reads as 0 */ +#define SYSCTL_SRAMCFG_KEY_VALUE ((uint32_t)0xB5000000U) /* !< Issue write */ +/* SYSCTL_SRAMCFG[BANKSTOP1] Bits */ +#define SYSCTL_SRAMCFG_BANKSTOP1_OFS (9) /* !< BANKSTOP1 Offset */ +#define SYSCTL_SRAMCFG_BANKSTOP1_MASK ((uint32_t)0x00000200U) /* !< SRAM BANK1 power level for STOP + mode */ +#define SYSCTL_SRAMCFG_BANKSTOP1_FALSE ((uint32_t)0x00000000U) /* !< SRAM BANK1 power OFF for STOP mode */ +#define SYSCTL_SRAMCFG_BANKSTOP1_TRUE ((uint32_t)0x00000200U) /* !< SRAM BANK1 power RETAIN for STOP + mode */ +/* SYSCTL_SRAMCFG[BANKOFF1] Bits */ +#define SYSCTL_SRAMCFG_BANKOFF1_OFS (1) /* !< BANKOFF1 Offset */ +#define SYSCTL_SRAMCFG_BANKOFF1_MASK ((uint32_t)0x00000002U) /* !< SRAM BANK1 power level for RUN mode */ +#define SYSCTL_SRAMCFG_BANKOFF1_FALSE ((uint32_t)0x00000000U) /* !< SRAM BANK1 power ON for RUN mode */ +#define SYSCTL_SRAMCFG_BANKOFF1_TRUE ((uint32_t)0x00000002U) /* !< SRAM BANK1 power OFF for RUN mode */ + +/* SYSCTL_WRITELOCK Bits */ +/* SYSCTL_WRITELOCK[ACTIVE] Bits */ +#define SYSCTL_WRITELOCK_ACTIVE_OFS (0) /* !< ACTIVE Offset */ +#define SYSCTL_WRITELOCK_ACTIVE_MASK ((uint32_t)0x00000001U) /* !< ACTIVE controls whether critical + SYSCTL registers are write protected + or not. */ +#define SYSCTL_WRITELOCK_ACTIVE_DISABLE ((uint32_t)0x00000000U) /* !< Allow writes to lockable registers */ +#define SYSCTL_WRITELOCK_ACTIVE_ENABLE ((uint32_t)0x00000001U) /* !< Disallow writes to lockable + registers */ + +/* SYSCTL_CLKSTATUS Bits */ +/* SYSCTL_CLKSTATUS[LFOSCGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_OFS (11) /* !< LFOSCGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_MASK ((uint32_t)0x00000800U) /* !< LFOSCGOOD indicates when the LFOSC + startup has completed and the LFOSC + is ready for use. */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFOSC is not ready */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE ((uint32_t)0x00000800U) /* !< LFOSC is ready */ +/* SYSCTL_CLKSTATUS[HFCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_OFS (8) /* !< HFCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_MASK ((uint32_t)0x00000100U) /* !< HFCLKGOOD indicates that the HFCLK + started correctly. When the HFXT is + started or HFCLK_IN is selected as + the HFCLK source, this bit will be + set by hardware if a valid HFCLK is + detected, and cleared if HFCLK is not + operating within the expected range. */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< HFCLK did not start correctly */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE ((uint32_t)0x00000100U) /* !< HFCLK started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKDEAD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_OFS (20) /* !< HSCLKDEAD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_MASK ((uint32_t)0x00100000U) /* !< HSCLKDEAD is set by hardware if the + selected source for HSCLK was started + but did not start successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source was not started or + started correctly */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE ((uint32_t)0x00100000U) /* !< The HSCLK source did not start + correctly */ +/* SYSCTL_CLKSTATUS[SYSPLLBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_OFS (29) /* !< SYSPLLBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_MASK ((uint32_t)0x20000000U) /* !< SYSPLLBLKUPD indicates when writes + to SYSPLLCFG0/1 and SYSPLLPARAM0/1 + are blocked. */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< writes to SYSPLLCFG0/1 and + SYSPLLPARAM0/1 are allowed */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_TRUE ((uint32_t)0x20000000U) /* !< writes to SYSPLLCFG0/1 and + SYSPLLPARAM0/1 are blocked */ +/* SYSCTL_CLKSTATUS[HFCLKOFF] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_OFS (13) /* !< HFCLKOFF Offset */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_MASK ((uint32_t)0x00002000U) /* !< HFCLKOFF indicates if the HFCLK is + disabled or was dead at startup. + When the HFCLK is started, HFCLKOFF + is cleared by hardware. Following + startup of the HFCLK, if the HFCLK + startup monitor determines that the + HFCLK was not started correctly, + HFCLKOFF is set. */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_FALSE ((uint32_t)0x00000000U) /* !< HFCLK started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_TRUE ((uint32_t)0x00002000U) /* !< HFCLK is disabled or was dead at + startup */ +/* SYSCTL_CLKSTATUS[HFCLKBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_OFS (28) /* !< HFCLKBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_MASK ((uint32_t)0x10000000U) /* !< HFCLKBLKUPD indicates when writes + to the HFCLKCLKCFG register are + blocked. */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< Writes to HFCLKCLKCFG are allowed */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE ((uint32_t)0x10000000U) /* !< Writes to HFCLKCLKCFG are blocked */ +/* SYSCTL_CLKSTATUS[HSCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_OFS (21) /* !< HSCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_MASK ((uint32_t)0x00200000U) /* !< HSCLKGOOD is set by hardware if the + selected clock source for HSCLK + started successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source did not start + correctly */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE ((uint32_t)0x00200000U) /* !< The HSCLK source started correctly */ +/* SYSCTL_CLKSTATUS[SYSPLLGOOD] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_OFS (9) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK ((uint32_t)0x00000200U) /* !< SYSPLLGOOD indicates if the SYSPLL + started correctly. When the SYSPLL + is started, SYSPLLGOOD is cleared by + hardware. After the startup settling + time has expired, the SYSPLL status + is tested. If the SYSPLL started + successfully the SYSPLLGOOD bit is + set, else it is left cleared. */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL did not start correctly */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_TRUE ((uint32_t)0x00000200U) /* !< SYSPLL started correctly */ +/* SYSCTL_CLKSTATUS[ANACLKERR] Bits */ +#define SYSCTL_CLKSTATUS_ANACLKERR_OFS (31) /* !< ANACLKERR Offset */ +#define SYSCTL_CLKSTATUS_ANACLKERR_MASK ((uint32_t)0x80000000U) /* !< ANACLKERR is set when the device + clock configuration does not support + an enabled analog peripheral mode and + the analog peripheral may not be + functioning as expected. */ +#define SYSCTL_CLKSTATUS_ANACLKERR_FALSE ((uint32_t)0x00000000U) /* !< No analog clock errors detected */ +#define SYSCTL_CLKSTATUS_ANACLKERR_TRUE ((uint32_t)0x80000000U) /* !< Analog clock error detected */ +/* SYSCTL_CLKSTATUS[HSCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_OFS (4) /* !< HSCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_MASK ((uint32_t)0x00000010U) /* !< HSCLKMUX indicates if MCLK is + currently sourced from the high-speed + clock (HSCLK). */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_SYSOSC ((uint32_t)0x00000000U) /* !< MCLK is not sourced from HSCLK */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK ((uint32_t)0x00000010U) /* !< MCLK is sourced from HSCLK */ +/* SYSCTL_CLKSTATUS[LFCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_OFS (6) /* !< LFCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_MASK ((uint32_t)0x000000C0U) /* !< LFCLKMUX indicates if LFCLK is + sourced from the internal LFOSC, the + low frequency crystal (LFXT), or the + LFCLK_IN digital clock input. */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFOSC ((uint32_t)0x00000000U) /* !< LFCLK is sourced from the internal + LFOSC */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFXT ((uint32_t)0x00000040U) /* !< LFCLK is sourced from the LFXT + (crystal) */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_EXLF ((uint32_t)0x00000080U) /* !< LFCLK is sourced from LFCLK_IN + (external digital clock input) */ +/* SYSCTL_CLKSTATUS[SYSOSCFREQ] Bits */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_OFS (0) /* !< SYSOSCFREQ Offset */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK ((uint32_t)0x00000003U) /* !< SYSOSCFREQ indicates the current + SYSOSC operating frequency. */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC32M ((uint32_t)0x00000000U) /* !< SYSOSC is at base frequency (32MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< SYSOSC is at low frequency (4MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< SYSOSC is at the user-trimmed + frequency (16 or 24MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCTURBO ((uint32_t)0x00000003U) /* !< Reserved */ +/* SYSCTL_CLKSTATUS[LFXTGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_OFS (10) /* !< LFXTGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_MASK ((uint32_t)0x00000400U) /* !< LFXTGOOD indicates if the LFXT + started correctly. When the LFXT is + started, LFXTGOOD is cleared by + hardware. After the startup settling + time has expired, the LFXT status is + tested. If the LFXT started + successfully the LFXTGOOD bit is set, + else it is left cleared. */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFXT did not start correctly */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_TRUE ((uint32_t)0x00000400U) /* !< LFXT started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKSOFF] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_OFS (12) /* !< HSCLKSOFF Offset */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_MASK ((uint32_t)0x00001000U) /* !< HSCLKSOFF is set when the high + speed clock sources (SYSPLL, HFCLK) + are disabled or dead. It is the + logical AND of HFCLKOFF and + SYSPLLOFF. */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL, HFCLK, or both were started + correctly and remain enabled */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE ((uint32_t)0x00001000U) /* !< SYSPLL and HFCLK are both either + off or dead */ +/* SYSCTL_CLKSTATUS[FCLMODE] Bits */ +#define SYSCTL_CLKSTATUS_FCLMODE_OFS (24) /* !< FCLMODE Offset */ +#define SYSCTL_CLKSTATUS_FCLMODE_MASK ((uint32_t)0x01000000U) /* !< FCLMODE indicates if the SYSOSC + frequency correction loop (FCL) is + enabled. */ +#define SYSCTL_CLKSTATUS_FCLMODE_DISABLED ((uint32_t)0x00000000U) /* !< SYSOSC FCL is disabled */ +#define SYSCTL_CLKSTATUS_FCLMODE_ENABLED ((uint32_t)0x01000000U) /* !< SYSOSC FCL is enabled */ +/* SYSCTL_CLKSTATUS[CURHSCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_OFS (16) /* !< CURHSCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_MASK ((uint32_t)0x00010000U) /* !< CURHSCLKSEL indicates the current + clock source for HSCLK. */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is currently sourced from the + SYSPLL */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK ((uint32_t)0x00010000U) /* !< HSCLK is currently sourced from the + HFCLK */ +/* SYSCTL_CLKSTATUS[CURMCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_OFS (17) /* !< CURMCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_MASK ((uint32_t)0x00020000U) /* !< CURMCLKSEL indicates if MCLK is + currently sourced from LFCLK. */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_NOTLFCLK ((uint32_t)0x00000000U) /* !< MCLK is not sourced from LFCLK */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK ((uint32_t)0x00020000U) /* !< MCLK is sourced from LFCLK */ +/* SYSCTL_CLKSTATUS[FCCDONE] Bits */ +#define SYSCTL_CLKSTATUS_FCCDONE_OFS (25) /* !< FCCDONE Offset */ +#define SYSCTL_CLKSTATUS_FCCDONE_MASK ((uint32_t)0x02000000U) /* !< FCCDONE indicates when a frequency + clock counter capture is complete. */ +#define SYSCTL_CLKSTATUS_FCCDONE_NOTDONE ((uint32_t)0x00000000U) /* !< FCC capture is not done */ +#define SYSCTL_CLKSTATUS_FCCDONE_DONE ((uint32_t)0x02000000U) /* !< FCC capture is done */ +/* SYSCTL_CLKSTATUS[SYSPLLOFF] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_OFS (14) /* !< SYSPLLOFF Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_MASK ((uint32_t)0x00004000U) /* !< SYSPLLOFF indicates if the SYSPLL + is disabled or was dead at startup. + When the SYSPLL is started, SYSPLLOFF + is cleared by hardware. Following + startup of the SYSPLL, if the SYSPLL + startup monitor determines that the + SYSPLL was not started correctly, + SYSPLLOFF is set. */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_TRUE ((uint32_t)0x00004000U) /* !< SYSPLL is disabled or was dead + startup */ +/* SYSCTL_CLKSTATUS[LFCLKFAIL] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_OFS (23) /* !< LFCLKFAIL Offset */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_MASK ((uint32_t)0x00800000U) /* !< LFCLKFAIL indicates when the + continous LFCLK monitor detects a + LFXT or LFCLK_IN clock stuck failure. */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) /* !< No LFCLK fault detected */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE ((uint32_t)0x00800000U) /* !< LFCLK stuck fault detected */ + +/* SYSCTL_SYSSTATUS Bits */ +/* SYSCTL_SYSSTATUS[SHDNIOLOCK] Bits */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_OFS (14) /* !< SHDNIOLOCK Offset */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_MASK ((uint32_t)0x00004000U) /* !< SHDNIOLOCK indicates when IO is + locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_FALSE ((uint32_t)0x00000000U) /* !< IO IS NOT Locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE ((uint32_t)0x00004000U) /* !< IO IS Locked due to SHUTDOWN */ +/* SYSCTL_SYSSTATUS[EXTRSTPINDIS] Bits */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_OFS (12) /* !< EXTRSTPINDIS Offset */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_MASK ((uint32_t)0x00001000U) /* !< EXTRSTPINDIS indicates when user + has disabled the use of external + reset pin */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_FALSE ((uint32_t)0x00000000U) /* !< External Reset Pin Enabled */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE ((uint32_t)0x00001000U) /* !< External Reset Pin Disabled */ +/* SYSCTL_SYSSTATUS[PMUIREFGOOD] Bits */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_OFS (6) /* !< PMUIREFGOOD Offset */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_MASK ((uint32_t)0x00000040U) /* !< PMUIREFGOOD is set by hardware when + the PMU current reference is ready. */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_FALSE ((uint32_t)0x00000000U) /* !< IREF is not ready */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE ((uint32_t)0x00000040U) /* !< IREF is ready */ +/* SYSCTL_SYSSTATUS[SWDCFGDIS] Bits */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_OFS (13) /* !< SWDCFGDIS Offset */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_MASK ((uint32_t)0x00002000U) /* !< SWDCFGDIS indicates when user has + disabled the use of SWD Port */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_FALSE ((uint32_t)0x00000000U) /* !< SWD Port Enabled */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE ((uint32_t)0x00002000U) /* !< SWD Port Disabled */ +/* SYSCTL_SYSSTATUS[ANACPUMPGOOD] Bits */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_OFS (5) /* !< ANACPUMPGOOD Offset */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_MASK ((uint32_t)0x00000020U) /* !< ANACPUMPGOOD is set by hardware + when the VBOOST analog mux charge + pump is ready. */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_FALSE ((uint32_t)0x00000000U) /* !< VBOOST is not ready */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE ((uint32_t)0x00000020U) /* !< VBOOST is ready */ +/* SYSCTL_SYSSTATUS[REBOOTATTEMPTS] Bits */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_OFS (30) /* !< REBOOTATTEMPTS Offset */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_MASK ((uint32_t)0xC0000000U) /* !< REBOOTATTEMPTS indicates the number + of boot attempts taken before the + user application starts. */ +/* SYSCTL_SYSSTATUS[BORLVL] Bits */ +#define SYSCTL_SYSSTATUS_BORLVL_OFS (4) /* !< BORLVL Offset */ +#define SYSCTL_SYSSTATUS_BORLVL_MASK ((uint32_t)0x00000010U) /* !< BORLVL indicates if a BOR event + occured and the BOR threshold was + switched to BOR0 by hardware. */ +#define SYSCTL_SYSSTATUS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No BOR violation occured */ +#define SYSCTL_SYSSTATUS_BORLVL_TRUE ((uint32_t)0x00000010U) /* !< A BOR violation occured and the BOR + threshold was switched to BOR0 */ +/* SYSCTL_SYSSTATUS[MCAN1READY] Bits */ +#define SYSCTL_SYSSTATUS_MCAN1READY_OFS (9) /* !< MCAN1READY Offset */ +#define SYSCTL_SYSSTATUS_MCAN1READY_MASK ((uint32_t)0x00000200U) /* !< MCAN1READY indicates when the MCAN1 + peripheral is ready. */ +#define SYSCTL_SYSSTATUS_MCAN1READY_FALSE ((uint32_t)0x00000000U) /* !< MCAN1 is not ready */ +#define SYSCTL_SYSSTATUS_MCAN1READY_TRUE ((uint32_t)0x00000200U) /* !< MCAN1 is ready */ +/* SYSCTL_SYSSTATUS[MCAN0READY] Bits */ +#define SYSCTL_SYSSTATUS_MCAN0READY_OFS (8) /* !< MCAN0READY Offset */ +#define SYSCTL_SYSSTATUS_MCAN0READY_MASK ((uint32_t)0x00000100U) /* !< MCAN0READY indicates when the MCAN0 + peripheral is ready. */ +#define SYSCTL_SYSSTATUS_MCAN0READY_FALSE ((uint32_t)0x00000000U) /* !< MCAN0 is not ready */ +#define SYSCTL_SYSSTATUS_MCAN0READY_TRUE ((uint32_t)0x00000100U) /* !< MCAN0 is ready */ +/* SYSCTL_SYSSTATUS[FLASHDED] Bits */ +#define SYSCTL_SYSSTATUS_FLASHDED_OFS (0) /* !< FLASHDED Offset */ +#define SYSCTL_SYSSTATUS_FLASHDED_MASK ((uint32_t)0x00000001U) /* !< FLASHDED indicates if a flash ECC + double bit error was detected (DED). */ +#define SYSCTL_SYSSTATUS_FLASHDED_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC double bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHDED_TRUE ((uint32_t)0x00000001U) /* !< Flash ECC double bit error detected */ +/* SYSCTL_SYSSTATUS[FLASHSEC] Bits */ +#define SYSCTL_SYSSTATUS_FLASHSEC_OFS (1) /* !< FLASHSEC Offset */ +#define SYSCTL_SYSSTATUS_FLASHSEC_MASK ((uint32_t)0x00000002U) /* !< FLASHSEC indicates if a flash ECC + single bit error was detected and + corrected (SEC). */ +#define SYSCTL_SYSSTATUS_FLASHSEC_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC single bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHSEC_TRUE ((uint32_t)0x00000002U) /* !< Flash ECC single bit error was + detected and corrected */ +/* SYSCTL_SYSSTATUS[SRAMBANK1READY] Bits */ +#define SYSCTL_SYSSTATUS_SRAMBANK1READY_OFS (17) /* !< SRAMBANK1READY Offset */ +#define SYSCTL_SYSSTATUS_SRAMBANK1READY_MASK ((uint32_t)0x00020000U) /* !< SRAM BANK1 READY STATE */ +#define SYSCTL_SYSSTATUS_SRAMBANK1READY_FALSE ((uint32_t)0x00000000U) /* !< SRAM BANK1 is NOT READY for access */ +#define SYSCTL_SYSSTATUS_SRAMBANK1READY_TRUE ((uint32_t)0x00020000U) /* !< SRAM BANK1 is READY for access */ +/* SYSCTL_SYSSTATUS[BORCURTHRESHOLD] Bits */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_OFS (2) /* !< BORCURTHRESHOLD Offset */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_MASK ((uint32_t)0x0000000CU) /* !< BORCURTHRESHOLD indicates the + active brown-out reset supply monitor + configuration. */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1 ((uint32_t)0x00000004U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2 ((uint32_t)0x00000008U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3 ((uint32_t)0x0000000CU) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_DEDERRADDR Bits */ +/* SYSCTL_DEDERRADDR[ADDR] Bits */ +#define SYSCTL_DEDERRADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define SYSCTL_DEDERRADDR_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< Address of MEMORY DED Error. */ + +/* SYSCTL_RSTCAUSE Bits */ +/* SYSCTL_RSTCAUSE[ID] Bits */ +#define SYSCTL_RSTCAUSE_ID_OFS (0) /* !< ID Offset */ +#define SYSCTL_RSTCAUSE_ID_MASK ((uint32_t)0x0000001FU) /* !< ID is a read-to-clear field which + indicates the lowest level reset + cause since the last read. */ +#define SYSCTL_RSTCAUSE_ID_NORST ((uint32_t)0x00000000U) /* !< No reset since last read */ +#define SYSCTL_RSTCAUSE_ID_PORHWFAIL ((uint32_t)0x00000001U) /* !< POR- violation, SHUTDNSTOREx or PMU + trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_POREXNRST ((uint32_t)0x00000002U) /* !< NRST triggered POR (>1s hold) */ +#define SYSCTL_RSTCAUSE_ID_PORSW ((uint32_t)0x00000003U) /* !< Software triggered POR */ +#define SYSCTL_RSTCAUSE_ID_BORSUPPLY ((uint32_t)0x00000004U) /* !< BOR0- violation */ +#define SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN ((uint32_t)0x00000005U) /* !< SHUTDOWN mode exit */ +#define SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY ((uint32_t)0x00000008U) /* !< Non-PMU trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL ((uint32_t)0x00000009U) /* !< Fatal clock failure */ +#define SYSCTL_RSTCAUSE_ID_BOOTEXNRST ((uint32_t)0x0000000CU) /* !< NRST triggered BOOTRST (<1s hold) */ +#define SYSCTL_RSTCAUSE_ID_BOOTSW ((uint32_t)0x0000000DU) /* !< Software triggered BOOTRST */ +#define SYSCTL_RSTCAUSE_ID_BOOTWWDT0 ((uint32_t)0x0000000EU) /* !< WWDT0 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLEXIT ((uint32_t)0x00000010U) /* !< BSL exit */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLENTRY ((uint32_t)0x00000011U) /* !< BSL entry */ +#define SYSCTL_RSTCAUSE_ID_SYSWWDT1 ((uint32_t)0x00000013U) /* !< WWDT1 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSFLASHECC ((uint32_t)0x00000014U) /* !< Flash uncorrectable ECC error */ +#define SYSCTL_RSTCAUSE_ID_SYSCPULOCK ((uint32_t)0x00000015U) /* !< CPULOCK violation */ +#define SYSCTL_RSTCAUSE_ID_SYSDBG ((uint32_t)0x0000001AU) /* !< Debug triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_SYSSW ((uint32_t)0x0000001BU) /* !< Software triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_CPUDBG ((uint32_t)0x0000001CU) /* !< Debug triggered CPURST */ +#define SYSCTL_RSTCAUSE_ID_CPUSW ((uint32_t)0x0000001DU) /* !< Software triggered CPURST */ + +/* SYSCTL_RESETLEVEL Bits */ +/* SYSCTL_RESETLEVEL[LEVEL] Bits */ +#define SYSCTL_RESETLEVEL_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_RESETLEVEL_LEVEL_MASK ((uint32_t)0x00000007U) /* !< LEVEL is used to specify the type + of reset to be issued when RESETCMD + is set to generate a software + triggered reset. */ +#define SYSCTL_RESETLEVEL_LEVEL_CPU ((uint32_t)0x00000000U) /* !< Issue a SYSRST (CPU plus + peripherals only) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOT ((uint32_t)0x00000001U) /* !< Issue a BOOTRST (CPU, peripherals, + and boot configuration routine) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY ((uint32_t)0x00000002U) /* !< Issue a SYSRST and enter the boot + strap loader (BSL) */ +#define SYSCTL_RESETLEVEL_LEVEL_POR ((uint32_t)0x00000003U) /* !< Issue a power-on reset (POR) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT ((uint32_t)0x00000004U) /* !< Issue a SYSRST and exit the boot + strap loader (BSL) */ + +/* SYSCTL_RESETCMD Bits */ +/* SYSCTL_RESETCMD[KEY] Bits */ +#define SYSCTL_RESETCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_RESETCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of E4h (228) must be + written to KEY together with GO to + trigger the reset. */ +#define SYSCTL_RESETCMD_KEY_VALUE ((uint32_t)0xE4000000U) /* !< Issue reset */ +/* SYSCTL_RESETCMD[GO] Bits */ +#define SYSCTL_RESETCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_RESETCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Execute the reset specified in + RESETLEVEL.LEVEL. Must be written + together with the KEY. */ +#define SYSCTL_RESETCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue reset */ + +/* SYSCTL_BORTHRESHOLD Bits */ +/* SYSCTL_BORTHRESHOLD[LEVEL] Bits */ +#define SYSCTL_BORTHRESHOLD_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_BORTHRESHOLD_LEVEL_MASK ((uint32_t)0x00000003U) /* !< LEVEL specifies the desired BOR + threshold and BOR mode. */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1 ((uint32_t)0x00000001U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2 ((uint32_t)0x00000002U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3 ((uint32_t)0x00000003U) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_BORCLRCMD Bits */ +/* SYSCTL_BORCLRCMD[KEY] Bits */ +#define SYSCTL_BORCLRCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_BORCLRCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of C7h (199) must be + written to KEY together with GO to + trigger the clear and BOR threshold + change. */ +#define SYSCTL_BORCLRCMD_KEY_VALUE ((uint32_t)0xC7000000U) /* !< Issue clear */ +/* SYSCTL_BORCLRCMD[GO] Bits */ +#define SYSCTL_BORCLRCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_BORCLRCMD_GO_MASK ((uint32_t)0x00000001U) /* !< GO clears any prior BOR violation + status indications and attempts to + change the active BOR mode to that + specified in the LEVEL field of the + BORTHRESHOLD register. */ +#define SYSCTL_BORCLRCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue clear */ + +/* SYSCTL_SYSOSCFCLCTL Bits */ +/* SYSCTL_SYSOSCFCLCTL[KEY] Bits */ +#define SYSCTL_SYSOSCFCLCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSOSCFCLCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 2Ah (42) must be + written to KEY together with + SETUSEFCL to enable the FCL. */ +#define SYSCTL_SYSOSCFCLCTL_KEY_VALUE ((uint32_t)0x2A000000U) /* !< Issue Command */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEFCL] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_OFS (0) /* !< SETUSEFCL Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEFCL to enable the + frequency correction loop in SYSOSC. + Once enabled, this state is locked + until the next BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEEXRES] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_OFS (1) /* !< SETUSEEXRES Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_MASK ((uint32_t)0x00000002U) /* !< Set SETUSEEXRES to specify that an + external resistor will be used for + the FCL. An appropriate resistor + must be populated on the ROSC pin. + This state is locked until the next + BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE ((uint32_t)0x00000002U) /* !< Enable the SYSOSC external Resistor */ + +/* SYSCTL_LFXTCTL Bits */ +/* SYSCTL_LFXTCTL[KEY] Bits */ +#define SYSCTL_LFXTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_LFXTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 91h (145) must be + written to KEY together with either + STARTLFXT or SETUSELFXT to set the + corresponding bit. */ +#define SYSCTL_LFXTCTL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_LFXTCTL[SETUSELFXT] Bits */ +#define SYSCTL_LFXTCTL_SETUSELFXT_OFS (1) /* !< SETUSELFXT Offset */ +#define SYSCTL_LFXTCTL_SETUSELFXT_MASK ((uint32_t)0x00000002U) /* !< Set SETUSELFXT to switch LFCLK to + LFXT. Once set, SETUSELFXT remains + set until the next BOOTRST. */ +#define SYSCTL_LFXTCTL_SETUSELFXT_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_LFXTCTL_SETUSELFXT_TRUE ((uint32_t)0x00000002U) /* !< Use LFXT as the LFCLK source */ +/* SYSCTL_LFXTCTL[STARTLFXT] Bits */ +#define SYSCTL_LFXTCTL_STARTLFXT_OFS (0) /* !< STARTLFXT Offset */ +#define SYSCTL_LFXTCTL_STARTLFXT_MASK ((uint32_t)0x00000001U) /* !< Set STARTLFXT to start the low + frequency crystal oscillator (LFXT). + Once set, STARTLFXT remains set until + the next BOOTRST. */ +#define SYSCTL_LFXTCTL_STARTLFXT_FALSE ((uint32_t)0x00000000U) /* !< LFXT not started */ +#define SYSCTL_LFXTCTL_STARTLFXT_TRUE ((uint32_t)0x00000001U) /* !< Start LFXT */ + +/* SYSCTL_EXLFCTL Bits */ +/* SYSCTL_EXLFCTL[KEY] Bits */ +#define SYSCTL_EXLFCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXLFCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 36h (54) must be + written to KEY together with + SETUSEEXLF to set SETUSEEXLF. */ +#define SYSCTL_EXLFCTL_KEY_VALUE ((uint32_t)0x36000000U) /* !< Issue command */ +/* SYSCTL_EXLFCTL[SETUSEEXLF] Bits */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_OFS (0) /* !< SETUSEEXLF Offset */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEEXLF to switch LFCLK to + the LFCLK_IN digital clock input. + Once set, SETUSEEXLF remains set + until the next BOOTRST. */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_TRUE ((uint32_t)0x00000001U) /* !< Use LFCLK_IN as the LFCLK source */ + +/* SYSCTL_SHDNIOREL Bits */ +/* SYSCTL_SHDNIOREL[KEY] Bits */ +#define SYSCTL_SHDNIOREL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SHDNIOREL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 91h must be written + to KEY together with RELEASE to set + RELEASE. */ +#define SYSCTL_SHDNIOREL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_SHDNIOREL[RELEASE] Bits */ +#define SYSCTL_SHDNIOREL_RELEASE_OFS (0) /* !< RELEASE Offset */ +#define SYSCTL_SHDNIOREL_RELEASE_MASK ((uint32_t)0x00000001U) /* !< Set RELEASE to release the IO after + a SHUTDOWN mode exit. */ +#define SYSCTL_SHDNIOREL_RELEASE_TRUE ((uint32_t)0x00000001U) /* !< Release IO */ + +/* SYSCTL_EXRSTPIN Bits */ +/* SYSCTL_EXRSTPIN[KEY] Bits */ +#define SYSCTL_EXRSTPIN_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXRSTPIN_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 1Eh must be written + together with DISABLE to disable the + reset function. */ +#define SYSCTL_EXRSTPIN_KEY_VALUE ((uint32_t)0x1E000000U) /* !< Issue command */ +/* SYSCTL_EXRSTPIN[DISABLE] Bits */ +#define SYSCTL_EXRSTPIN_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_EXRSTPIN_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the reset + function of the NRST pin. Once set, + this configuration is locked until + the next POR. */ +#define SYSCTL_EXRSTPIN_DISABLE_FALSE ((uint32_t)0x00000000U) /* !< Reset function of NRST pin is + enabled */ +#define SYSCTL_EXRSTPIN_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Reset function of NRST pin is + disabled */ + +/* SYSCTL_SYSSTATUSCLR Bits */ +/* SYSCTL_SYSSTATUSCLR[KEY] Bits */ +#define SYSCTL_SYSSTATUSCLR_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSSTATUSCLR_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value CEh (206) must be + written to KEY together with ALLECC + to clear the ECC state. */ +#define SYSCTL_SYSSTATUSCLR_KEY_VALUE ((uint32_t)0xCE000000U) /* !< Issue command */ +/* SYSCTL_SYSSTATUSCLR[ALLECC] Bits */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_OFS (0) /* !< ALLECC Offset */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_MASK ((uint32_t)0x00000001U) /* !< Set ALLECC to clear all ECC related + SYSSTATUS indicators. */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR ((uint32_t)0x00000001U) /* !< Clear ECC error state */ + +/* SYSCTL_SWDCFG Bits */ +/* SYSCTL_SWDCFG[KEY] Bits */ +#define SYSCTL_SWDCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SWDCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 62h (98) must be + written to KEY together with DISBALE + to disable the SWD functions. */ +#define SYSCTL_SWDCFG_KEY_VALUE ((uint32_t)0x62000000U) /* !< Issue command */ +/* SYSCTL_SWDCFG[DISABLE] Bits */ +#define SYSCTL_SWDCFG_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_SWDCFG_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the SWD + function on SWD pins, allowing the + SWD pins to be used as GPIO. */ +#define SYSCTL_SWDCFG_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disable SWD function on SWD pins */ + +/* SYSCTL_FCCCMD Bits */ +/* SYSCTL_FCCCMD[KEY] Bits */ +#define SYSCTL_FCCCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FCCCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 0Eh (14) must be + written with GO to start a capture. */ +#define SYSCTL_FCCCMD_KEY_VALUE ((uint32_t)0x0E000000U) /* !< Issue command */ +/* SYSCTL_FCCCMD[GO] Bits */ +#define SYSCTL_FCCCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_FCCCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Set GO to start a capture with the + frequency clock counter (FCC). */ +#define SYSCTL_FCCCMD_GO_TRUE ((uint32_t)0x00000001U) + +/* SYSCTL_SHUTDNSTORE0 Bits */ +/* SYSCTL_SHUTDNSTORE0[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE0_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE0_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 0 */ + +/* SYSCTL_SHUTDNSTORE1 Bits */ +/* SYSCTL_SHUTDNSTORE1[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE1_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE1_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 1 */ + +/* SYSCTL_SHUTDNSTORE2 Bits */ +/* SYSCTL_SHUTDNSTORE2[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE2_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE2_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 2 */ + +/* SYSCTL_SHUTDNSTORE3 Bits */ +/* SYSCTL_SHUTDNSTORE3[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE3_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE3_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 3 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g352x__include */ + diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g511x.h b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g511x.h new file mode 100644 index 0000000..73e0745 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g511x.h @@ -0,0 +1,1966 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g511x__include +#define ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g511x__include + +/* Filename: hw_sysctl_mspm0g511x.h */ +/* Revised: 2024-12-23 19:16:39 */ +/* Revision: 7689f773d1f3e94bdd42e4fda8b3557bbed5f247 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* SYSCTL Registers +******************************************************************************/ +#define SYSCTL_SECCFG_OFS ((uint32_t)0x00003000U) +#define SYSCTL_SOCLOCK_OFS ((uint32_t)0x00001000U) + + +/** @addtogroup SYSCTL_SECCFG + @{ +*/ + +typedef struct { + __IO uint32_t FWEPROTMAIN; /* !< (@ 0x00003000) 1 Sector Write-Erase per bit starting at address + 0x0 of flash */ + uint32_t RESERVED0[4]; + __IO uint32_t FWPROTMAINDATA; /* !< (@ 0x00003014) Read-Write Protection for first 4 Sectors of Data + Bank */ + __IO uint32_t FRXPROTMAINSTART; /* !< (@ 0x00003018) Flash RX Protection Start Address */ + __IO uint32_t FRXPROTMAINEND; /* !< (@ 0x0000301C) Flash RX Protection End Address */ + __IO uint32_t FIPPROTMAINSTART; /* !< (@ 0x00003020) Flash IP Protection Start Address */ + __IO uint32_t FIPPROTMAINEND; /* !< (@ 0x00003024) Flash IP Protection End Address */ + uint32_t RESERVED1[4]; + __O uint32_t FLBANKSWPPOLICY; /* !< (@ 0x00003038) Flash Bank Swap Policy */ + __O uint32_t FLBANKSWP; /* !< (@ 0x0000303C) Flash MAIN bank address swap */ + uint32_t RESERVED2; + __O uint32_t FWENABLE; /* !< (@ 0x00003044) Security Firewall Enable Register */ + __I uint32_t SECSTATUS; /* !< (@ 0x00003048) Security Configuration status */ + uint32_t RESERVED3[5]; + __O uint32_t INITDONE; /* !< (@ 0x00003060) INITCODE PASS */ +} SYSCTL_SECCFG_Regs; + +/*@}*/ /* end of group SYSCTL_SECCFG */ + +/** @addtogroup SYSCTL_SOCLOCK + @{ +*/ + +typedef struct { + uint32_t RESERVED0[8]; + __I uint32_t IIDX; /* !< (@ 0x00001020) SYSCTL interrupt index */ + uint32_t RESERVED1; + __IO uint32_t IMASK; /* !< (@ 0x00001028) SYSCTL interrupt mask */ + uint32_t RESERVED2; + __I uint32_t RIS; /* !< (@ 0x00001030) SYSCTL raw interrupt status */ + uint32_t RESERVED3; + __I uint32_t MIS; /* !< (@ 0x00001038) SYSCTL masked interrupt status */ + uint32_t RESERVED4; + __O uint32_t ISET; /* !< (@ 0x00001040) SYSCTL interrupt set */ + uint32_t RESERVED5; + __O uint32_t ICLR; /* !< (@ 0x00001048) SYSCTL interrupt clear */ + uint32_t RESERVED6; + __I uint32_t NMIIIDX; /* !< (@ 0x00001050) NMI interrupt index */ + uint32_t RESERVED7[3]; + __I uint32_t NMIRIS; /* !< (@ 0x00001060) NMI raw interrupt status */ + uint32_t RESERVED8[3]; + __O uint32_t NMIISET; /* !< (@ 0x00001070) NMI interrupt set */ + uint32_t RESERVED9; + __O uint32_t NMIICLR; /* !< (@ 0x00001078) NMI interrupt clear */ + uint32_t RESERVED10[33]; + __IO uint32_t SYSOSCCFG; /* !< (@ 0x00001100) SYSOSC configuration */ + __IO uint32_t MCLKCFG; /* !< (@ 0x00001104) Main clock (MCLK) configuration */ + __IO uint32_t HSCLKEN; /* !< (@ 0x00001108) High-speed clock (HSCLK) source enable/disable */ + __IO uint32_t HSCLKCFG; /* !< (@ 0x0000110C) High-speed clock (HSCLK) source selection */ + __IO uint32_t HFCLKCLKCFG; /* !< (@ 0x00001110) High-frequency clock (HFCLK) configuration */ + __IO uint32_t LFCLKCFG; /* !< (@ 0x00001114) Low frequency crystal oscillator (LFXT) + configuration */ + uint32_t RESERVED11[2]; + __IO uint32_t SYSPLLCFG0; /* !< (@ 0x00001120) SYSPLL reference and output configuration */ + __IO uint32_t SYSPLLCFG1; /* !< (@ 0x00001124) SYSPLL reference and feedback divider */ + __IO uint32_t SYSPLLPARAM0; /* !< (@ 0x00001128) SYSPLL PARAM0 (load from FACTORY region) */ + __IO uint32_t SYSPLLPARAM1; /* !< (@ 0x0000112C) SYSPLL PARAM1 (load from FACTORY region) */ + uint32_t RESERVED12[2]; + __IO uint32_t GENCLKCFG; /* !< (@ 0x00001138) General clock configuration */ + __IO uint32_t GENCLKEN; /* !< (@ 0x0000113C) General clock enable control */ + __IO uint32_t PMODECFG; /* !< (@ 0x00001140) Power mode configuration */ + uint32_t RESERVED13[3]; + __I uint32_t FCC; /* !< (@ 0x00001150) Frequency clock counter (FCC) count */ + uint32_t RESERVED14[7]; + __IO uint32_t SYSOSCTRIMUSER; /* !< (@ 0x00001170) SYSOSC user-specified trim */ + uint32_t RESERVED15; + __IO uint32_t SRAMBOUNDARY; /* !< (@ 0x00001178) SRAM Write Boundary */ + uint32_t RESERVED16; + __IO uint32_t SYSTEMCFG; /* !< (@ 0x00001180) System configuration */ + uint32_t RESERVED17[31]; + __IO uint32_t WRITELOCK; /* !< (@ 0x00001200) SYSCTL register write lockout */ + __I uint32_t CLKSTATUS; /* !< (@ 0x00001204) Clock module (CKM) status */ + __I uint32_t SYSSTATUS; /* !< (@ 0x00001208) System status information */ + __I uint32_t DEDERRADDR; /* !< (@ 0x0000120C) Memory DED Address */ + uint32_t RESERVED18[4]; + __I uint32_t RSTCAUSE; /* !< (@ 0x00001220) Reset cause */ + uint32_t RESERVED19[55]; + __IO uint32_t RESETLEVEL; /* !< (@ 0x00001300) Reset level for application-triggered reset + command */ + __O uint32_t RESETCMD; /* !< (@ 0x00001304) Execute an application-triggered reset command */ + __IO uint32_t BORTHRESHOLD; /* !< (@ 0x00001308) BOR threshold selection */ + __O uint32_t BORCLRCMD; /* !< (@ 0x0000130C) Set the BOR threshold */ + __O uint32_t SYSOSCFCLCTL; /* !< (@ 0x00001310) SYSOSC frequency correction loop (FCL) ROSC enable */ + __O uint32_t LFXTCTL; /* !< (@ 0x00001314) LFXT and LFCLK control */ + __O uint32_t EXLFCTL; /* !< (@ 0x00001318) LFCLK_IN and LFCLK control */ + __O uint32_t SHDNIOREL; /* !< (@ 0x0000131C) SHUTDOWN IO release control */ + __O uint32_t EXRSTPIN; /* !< (@ 0x00001320) Disable the reset function of the NRST pin */ + __O uint32_t SYSSTATUSCLR; /* !< (@ 0x00001324) Clear sticky bits of SYSSTATUS */ + __O uint32_t SWDCFG; /* !< (@ 0x00001328) Disable the SWD function on the SWD pins */ + __O uint32_t FCCCMD; /* !< (@ 0x0000132C) Frequency clock counter start capture */ + uint32_t RESERVED20[4]; + __IO uint32_t USBFLLCTL; /* !< (@ 0x00001340) USB FLL Control Register */ + __IO uint32_t USBFLLADJ; /* !< (@ 0x00001344) USB FLL Manual Adjustment Register */ + __I uint32_t USBFLLSTAT; /* !< (@ 0x00001348) USB FLL Status Register */ + uint32_t RESERVED21[45]; + __IO uint32_t SHUTDNSTORE0; /* !< (@ 0x00001400) Shutdown storage memory (byte 0) */ + __IO uint32_t SHUTDNSTORE1; /* !< (@ 0x00001404) Shutdown storage memory (byte 1) */ + __IO uint32_t SHUTDNSTORE2; /* !< (@ 0x00001408) Shutdown storage memory (byte 2) */ + __IO uint32_t SHUTDNSTORE3; /* !< (@ 0x0000140C) Shutdown storage memory (byte 3) */ +} SYSCTL_SOCLOCK_Regs; + +/*@}*/ /* end of group SYSCTL_SOCLOCK */ + +/** @addtogroup SYSCTL + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + SYSCTL_SOCLOCK_Regs SOCLOCK; /* !< (@ 0x00001000) SYSCTL SOCLOCK Region */ + uint32_t RESERVED1[1788]; + SYSCTL_SECCFG_Regs SECCFG; /* !< (@ 0x00003000) SYSCTL SECCFG Region */ +} SYSCTL_Regs; + +/*@}*/ /* end of group SYSCTL */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* SYSCTL Register Control Bits +******************************************************************************/ + +/* SYSCTL_FWEPROTMAIN Bits */ +/* SYSCTL_FWEPROTMAIN[DATA] Bits */ +#define SYSCTL_FWEPROTMAIN_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWEPROTMAIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< 1 Sector Write Erase protection 1: + prohibits write-erase, 0: allows */ + +/* SYSCTL_FWPROTMAINDATA Bits */ +/* SYSCTL_FWPROTMAINDATA[DATA] Bits */ +#define SYSCTL_FWPROTMAINDATA_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWPROTMAINDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< 00: Both RW allowed 01: Read Only + 10: No Read No Write 11: No Read No + Write - Not Used */ + +/* SYSCTL_FRXPROTMAINSTART Bits */ +/* SYSCTL_FRXPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection Start Address + 64B granularity */ + +/* SYSCTL_FRXPROTMAINEND Bits */ +/* SYSCTL_FRXPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection End Address 64B + granularity */ + +/* SYSCTL_FIPPROTMAINSTART Bits */ +/* SYSCTL_FIPPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection Start Address + 64B granularity */ + +/* SYSCTL_FIPPROTMAINEND Bits */ +/* SYSCTL_FIPPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection End Address 64B + granularity */ + +/* SYSCTL_FLBANKSWPPOLICY Bits */ +/* SYSCTL_FLBANKSWPPOLICY[KEY] Bits */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0xCA(202) for write */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_VALUE ((uint32_t)0xCA000000U) /* !< Write Key */ +/* SYSCTL_FLBANKSWPPOLICY[DISABLE] Bits */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_MASK ((uint32_t)0x00000001U) /* !< 1: Disables Policy To Allow Flash + Bank Swapping */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disallow Bank Swap */ + +/* SYSCTL_FLBANKSWP Bits */ +/* SYSCTL_FLBANKSWP[KEY] Bits */ +#define SYSCTL_FLBANKSWP_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FLBANKSWP_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 58h (88) must be + written with USEUPPER to change the + bank swap configuration. */ +#define SYSCTL_FLBANKSWP_KEY_VALUE ((uint32_t)0x58000000U) /* !< Issue write */ +/* SYSCTL_FLBANKSWP[USEUPPER] Bits */ +#define SYSCTL_FLBANKSWP_USEUPPER_OFS (0) /* !< USEUPPER Offset */ +#define SYSCTL_FLBANKSWP_USEUPPER_MASK ((uint32_t)0x00000001U) /* !< 1: Use Upper Bank as Logical 0 */ +#define SYSCTL_FLBANKSWP_USEUPPER_DISABLE ((uint32_t)0x00000000U) /* !< Normal (default) memory map + addressing scheme */ +#define SYSCTL_FLBANKSWP_USEUPPER_ENABLE ((uint32_t)0x00000001U) /* !< Flash upper region address space + swapped with lower region */ + +/* SYSCTL_FWENABLE Bits */ +/* SYSCTL_FWENABLE[KEY] Bits */ +#define SYSCTL_FWENABLE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FWENABLE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x76(118) for write */ +#define SYSCTL_FWENABLE_KEY_VALUE ((uint32_t)0x76000000U) /* !< Write Key */ +/* SYSCTL_FWENABLE[FLIPPROT] Bits */ +#define SYSCTL_FWENABLE_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_FWENABLE_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash Read IP ProtectionActive */ +#define SYSCTL_FWENABLE_FLIPPROT_ENABLE ((uint32_t)0x00000040U) /* !< Turn On Flash IP Protection */ +/* SYSCTL_FWENABLE[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: Blocks Writes from Changing + SRAMBOUNDARY MMR */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE ((uint32_t)0x00000100U) /* !< SRAMBOUNDARY MMR Locked */ +/* SYSCTL_FWENABLE[FLRXPROT] Bits */ +#define SYSCTL_FWENABLE_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_FWENABLE_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_FWENABLE_FLRXPROT_ENABLE ((uint32_t)0x00000010U) /* !< Turn On Flash Read-eXecute + Protection */ + +/* SYSCTL_SECSTATUS Bits */ +/* SYSCTL_SECSTATUS[FLBANKSWPPOLICY] Bits */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_OFS (10) /* !< FLBANKSWPPOLICY Offset */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_MASK ((uint32_t)0x00000400U) /* !< 1: Upper and Lower Banks allowed to + be swapped */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED ((uint32_t)0x00000400U) +/* SYSCTL_SECSTATUS[FLIPPROT] Bits */ +#define SYSCTL_SECSTATUS_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_SECSTATUS_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash IP Protection Active */ +#define SYSCTL_SECSTATUS_FLIPPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLIPPROT_ENABLED ((uint32_t)0x00000040U) +/* SYSCTL_SECSTATUS[FLBANKSWP] Bits */ +#define SYSCTL_SECSTATUS_FLBANKSWP_OFS (12) /* !< FLBANKSWP Offset */ +#define SYSCTL_SECSTATUS_FLBANKSWP_MASK ((uint32_t)0x00001000U) /* !< 1: Upper and Lower Banks have been + swapped */ +/* SYSCTL_SECSTATUS[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: SRAM Boundary MMR Locked */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED ((uint32_t)0x00000100U) +/* SYSCTL_SECSTATUS[FLRXPROT] Bits */ +#define SYSCTL_SECSTATUS_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_SECSTATUS_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_SECSTATUS_FLRXPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLRXPROT_ENABLED ((uint32_t)0x00000010U) +/* SYSCTL_SECSTATUS[INITDONE] Bits */ +#define SYSCTL_SECSTATUS_INITDONE_OFS (0) /* !< INITDONE Offset */ +#define SYSCTL_SECSTATUS_INITDONE_MASK ((uint32_t)0x00000001U) /* !< 1: CSC has been completed */ +#define SYSCTL_SECSTATUS_INITDONE_NO ((uint32_t)0x00000000U) /* !< INIT is not yet done */ +#define SYSCTL_SECSTATUS_INITDONE_YES ((uint32_t)0x00000001U) /* !< INIT is done */ +/* SYSCTL_SECSTATUS[CSCEXISTS] Bits */ +#define SYSCTL_SECSTATUS_CSCEXISTS_OFS (2) /* !< CSCEXISTS Offset */ +#define SYSCTL_SECSTATUS_CSCEXISTS_MASK ((uint32_t)0x00000004U) /* !< 1: CSC Exists in the system */ +#define SYSCTL_SECSTATUS_CSCEXISTS_NO ((uint32_t)0x00000000U) /* !< System does not have a CSC */ +#define SYSCTL_SECSTATUS_CSCEXISTS_YES ((uint32_t)0x00000004U) /* !< System does have a CSC */ + +/* SYSCTL_INITDONE Bits */ +/* SYSCTL_INITDONE[KEY] Bits */ +#define SYSCTL_INITDONE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_INITDONE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x9D(157) for write */ +#define SYSCTL_INITDONE_KEY_VALUE ((uint32_t)0x9D000000U) /* !< Issue Reset */ +/* SYSCTL_INITDONE[PASS] Bits */ +#define SYSCTL_INITDONE_PASS_OFS (0) /* !< PASS Offset */ +#define SYSCTL_INITDONE_PASS_MASK ((uint32_t)0x00000001U) /* !< INITCODE writes 1 for PASS, left + unwritten a timeout will occur if not + blocked */ +#define SYSCTL_INITDONE_PASS_TRUE ((uint32_t)0x00000001U) /* !< INITCODE PASS */ + +/* SYSCTL_IIDX Bits */ +/* SYSCTL_IIDX[STAT] Bits */ +#define SYSCTL_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_IIDX_STAT_MASK ((uint32_t)0x0000000FU) /* !< The SYSCTL interrupt index (IIDX) + register generates a value + corresponding to the highest priority + pending interrupt source. This value + may be used as an address offset for + fast, deterministic handling in the + interrupt service routine. A read of + the IIDX register will clear the + corresponding interrupt status in the + RIS and MIS registers. */ +#define SYSCTL_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_IIDX_STAT_LFOSCGOOD ((uint32_t)0x00000001U) /* !< LFOSCGOOD interrupt pending */ +#define SYSCTL_IIDX_STAT_ANACLKERR ((uint32_t)0x00000002U) +#define SYSCTL_IIDX_STAT_FLASHSEC ((uint32_t)0x00000003U) +#define SYSCTL_IIDX_STAT_SRAMSEC ((uint32_t)0x00000004U) +#define SYSCTL_IIDX_STAT_LFXTGOOD ((uint32_t)0x00000005U) +#define SYSCTL_IIDX_STAT_HFCLKGOOD ((uint32_t)0x00000006U) +#define SYSCTL_IIDX_STAT_SYSPLLGOOD ((uint32_t)0x00000007U) +#define SYSCTL_IIDX_STAT_HSCLKGOOD ((uint32_t)0x00000008U) +#define SYSCTL_IIDX_STAT_USBFLLERR ((uint32_t)0x00000009U) + +/* SYSCTL_IMASK Bits */ +/* SYSCTL_IMASK[LFOSCGOOD] Bits */ +#define SYSCTL_IMASK_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_IMASK_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Enable or disable the LFOSCGOOD + interrupt. LFOSCGOOD indicates that + the LFOSC has started successfully. */ +#define SYSCTL_IMASK_LFOSCGOOD_DISABLE ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define SYSCTL_IMASK_LFOSCGOOD_ENABLE ((uint32_t)0x00000001U) /* !< Interrupt enabled */ +/* SYSCTL_IMASK[HFCLKGOOD] Bits */ +#define SYSCTL_IMASK_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_IMASK_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_IMASK_HFCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HFCLKGOOD_ENABLE ((uint32_t)0x00000020U) +/* SYSCTL_IMASK[SRAMSEC] Bits */ +#define SYSCTL_IMASK_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_IMASK_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_IMASK_SRAMSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_SRAMSEC_ENABLE ((uint32_t)0x00000008U) +/* SYSCTL_IMASK[LFXTGOOD] Bits */ +#define SYSCTL_IMASK_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_IMASK_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_IMASK_LFXTGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_LFXTGOOD_ENABLE ((uint32_t)0x00000010U) +/* SYSCTL_IMASK[HSCLKGOOD] Bits */ +#define SYSCTL_IMASK_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_IMASK_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_IMASK_HSCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HSCLKGOOD_ENABLE ((uint32_t)0x00000080U) +/* SYSCTL_IMASK[SYSPLLGOOD] Bits */ +#define SYSCTL_IMASK_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_IMASK_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_IMASK_SYSPLLGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_SYSPLLGOOD_ENABLE ((uint32_t)0x00000040U) +/* SYSCTL_IMASK[ANACLKERR] Bits */ +#define SYSCTL_IMASK_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_IMASK_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_IMASK_ANACLKERR_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_ANACLKERR_ENABLE ((uint32_t)0x00000002U) +/* SYSCTL_IMASK[FLASHSEC] Bits */ +#define SYSCTL_IMASK_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_IMASK_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_IMASK_FLASHSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_FLASHSEC_ENABLE ((uint32_t)0x00000004U) +/* SYSCTL_IMASK[USBFLLERR] Bits */ +#define SYSCTL_IMASK_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_IMASK_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_IMASK_USBFLLERR_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_USBFLLERR_ENABLE ((uint32_t)0x00000100U) + +/* SYSCTL_RIS Bits */ +/* SYSCTL_RIS[LFOSCGOOD] Bits */ +#define SYSCTL_RIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_RIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Raw status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_RIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_RIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_RIS[HFCLKGOOD] Bits */ +#define SYSCTL_RIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_RIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_RIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_RIS[SRAMSEC] Bits */ +#define SYSCTL_RIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_RIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_RIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_RIS[LFXTGOOD] Bits */ +#define SYSCTL_RIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_RIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_RIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_RIS[HSCLKGOOD] Bits */ +#define SYSCTL_RIS_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_RIS_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_RIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HSCLKGOOD_TRUE ((uint32_t)0x00000080U) +/* SYSCTL_RIS[SYSPLLGOOD] Bits */ +#define SYSCTL_RIS_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_RIS_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_RIS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_SYSPLLGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_RIS[ANACLKERR] Bits */ +#define SYSCTL_RIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_RIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_RIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_RIS[FLASHSEC] Bits */ +#define SYSCTL_RIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_RIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_RIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_RIS[USBFLLERR] Bits */ +#define SYSCTL_RIS_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_RIS_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_RIS_USBFLLERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_USBFLLERR_TRUE ((uint32_t)0x00000100U) + +/* SYSCTL_MIS Bits */ +/* SYSCTL_MIS[LFOSCGOOD] Bits */ +#define SYSCTL_MIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_MIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Masked status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_MIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_MIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_MIS[HFCLKGOOD] Bits */ +#define SYSCTL_MIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_MIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_MIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_MIS[SRAMSEC] Bits */ +#define SYSCTL_MIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_MIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_MIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_MIS[LFXTGOOD] Bits */ +#define SYSCTL_MIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_MIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_MIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_MIS[HSCLKGOOD] Bits */ +#define SYSCTL_MIS_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_MIS_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_MIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HSCLKGOOD_TRUE ((uint32_t)0x00000080U) +/* SYSCTL_MIS[SYSPLLGOOD] Bits */ +#define SYSCTL_MIS_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_MIS_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_MIS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_SYSPLLGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_MIS[ANACLKERR] Bits */ +#define SYSCTL_MIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_MIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_MIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_MIS[FLASHSEC] Bits */ +#define SYSCTL_MIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_MIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_MIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_MIS[USBFLLERR] Bits */ +#define SYSCTL_MIS_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_MIS_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_MIS_USBFLLERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_USBFLLERR_TRUE ((uint32_t)0x00000100U) + +/* SYSCTL_ISET Bits */ +/* SYSCTL_ISET[LFOSCGOOD] Bits */ +#define SYSCTL_ISET_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ISET_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Set the LFOSCGOOD interrupt. */ +#define SYSCTL_ISET_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_ISET_LFOSCGOOD_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_ISET[HFCLKGOOD] Bits */ +#define SYSCTL_ISET_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ISET_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ISET_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HFCLKGOOD_SET ((uint32_t)0x00000020U) +/* SYSCTL_ISET[SRAMSEC] Bits */ +#define SYSCTL_ISET_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ISET_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ISET_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_SRAMSEC_SET ((uint32_t)0x00000008U) +/* SYSCTL_ISET[LFXTGOOD] Bits */ +#define SYSCTL_ISET_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ISET_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ISET_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_LFXTGOOD_SET ((uint32_t)0x00000010U) +/* SYSCTL_ISET[HSCLKGOOD] Bits */ +#define SYSCTL_ISET_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ISET_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_ISET_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HSCLKGOOD_SET ((uint32_t)0x00000080U) +/* SYSCTL_ISET[SYSPLLGOOD] Bits */ +#define SYSCTL_ISET_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_ISET_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_ISET_SYSPLLGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_SYSPLLGOOD_SET ((uint32_t)0x00000040U) +/* SYSCTL_ISET[ANACLKERR] Bits */ +#define SYSCTL_ISET_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ISET_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ISET_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_ANACLKERR_SET ((uint32_t)0x00000002U) +/* SYSCTL_ISET[FLASHSEC] Bits */ +#define SYSCTL_ISET_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ISET_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ISET_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_FLASHSEC_SET ((uint32_t)0x00000004U) +/* SYSCTL_ISET[USBFLLERR] Bits */ +#define SYSCTL_ISET_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_ISET_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_ISET_USBFLLERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_USBFLLERR_SET ((uint32_t)0x00000100U) + +/* SYSCTL_ICLR Bits */ +/* SYSCTL_ICLR[LFOSCGOOD] Bits */ +#define SYSCTL_ICLR_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ICLR_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Clear the LFOSCGOOD interrupt. */ +#define SYSCTL_ICLR_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h has no effect */ +#define SYSCTL_ICLR_LFOSCGOOD_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_ICLR[HFCLKGOOD] Bits */ +#define SYSCTL_ICLR_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ICLR_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ICLR_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HFCLKGOOD_CLR ((uint32_t)0x00000020U) +/* SYSCTL_ICLR[SRAMSEC] Bits */ +#define SYSCTL_ICLR_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ICLR_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ICLR_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_SRAMSEC_CLR ((uint32_t)0x00000008U) +/* SYSCTL_ICLR[LFXTGOOD] Bits */ +#define SYSCTL_ICLR_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ICLR_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ICLR_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_LFXTGOOD_CLR ((uint32_t)0x00000010U) +/* SYSCTL_ICLR[HSCLKGOOD] Bits */ +#define SYSCTL_ICLR_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ICLR_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_ICLR_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HSCLKGOOD_CLR ((uint32_t)0x00000080U) +/* SYSCTL_ICLR[SYSPLLGOOD] Bits */ +#define SYSCTL_ICLR_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_ICLR_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_ICLR_SYSPLLGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_SYSPLLGOOD_CLR ((uint32_t)0x00000040U) +/* SYSCTL_ICLR[ANACLKERR] Bits */ +#define SYSCTL_ICLR_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ICLR_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ICLR_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_ANACLKERR_CLR ((uint32_t)0x00000002U) +/* SYSCTL_ICLR[FLASHSEC] Bits */ +#define SYSCTL_ICLR_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ICLR_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ICLR_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_FLASHSEC_CLR ((uint32_t)0x00000004U) +/* SYSCTL_ICLR[USBFLLERR] Bits */ +#define SYSCTL_ICLR_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_ICLR_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_ICLR_USBFLLERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_USBFLLERR_CLR ((uint32_t)0x00000100U) + +/* SYSCTL_NMIIIDX Bits */ +/* SYSCTL_NMIIIDX[STAT] Bits */ +#define SYSCTL_NMIIIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_NMIIIDX_STAT_MASK ((uint32_t)0x0000000FU) /* !< The NMI interrupt index (NMIIIDX) + register generates a value + corresponding to the highest priority + pending NMI source. This value may + be used as an address offset for + fast, deterministic handling in the + NMI service routine. A read of the + NMIIIDX register will clear the + corresponding interrupt status in the + NMIRIS register. */ +#define SYSCTL_NMIIIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No NMI pending */ +#define SYSCTL_NMIIIDX_STAT_BORLVL ((uint32_t)0x00000001U) /* !< BOR Threshold NMI pending */ +#define SYSCTL_NMIIIDX_STAT_WWDT0 ((uint32_t)0x00000002U) +#define SYSCTL_NMIIIDX_STAT_WWDT1 ((uint32_t)0x00000003U) +#define SYSCTL_NMIIIDX_STAT_LFCLKFAIL ((uint32_t)0x00000004U) +#define SYSCTL_NMIIIDX_STAT_FLASHDED ((uint32_t)0x00000005U) +#define SYSCTL_NMIIIDX_STAT_SRAMDED ((uint32_t)0x00000006U) + +/* SYSCTL_NMIRIS Bits */ +/* SYSCTL_NMIRIS[WWDT1] Bits */ +#define SYSCTL_NMIRIS_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIRIS_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT1_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT1_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_NMIRIS[SRAMDED] Bits */ +#define SYSCTL_NMIRIS_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIRIS_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIRIS_SRAMDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_SRAMDED_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_NMIRIS[BORLVL] Bits */ +#define SYSCTL_NMIRIS_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIRIS_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Raw status of the BORLVL NMI */ +#define SYSCTL_NMIRIS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_NMIRIS_BORLVL_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_NMIRIS[FLASHDED] Bits */ +#define SYSCTL_NMIRIS_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIRIS_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIRIS_FLASHDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_FLASHDED_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_NMIRIS[WWDT0] Bits */ +#define SYSCTL_NMIRIS_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIRIS_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT0_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT0_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_NMIRIS[LFCLKFAIL] Bits */ +#define SYSCTL_NMIRIS_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIRIS_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIRIS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_LFCLKFAIL_TRUE ((uint32_t)0x00000008U) + +/* SYSCTL_NMIISET Bits */ +/* SYSCTL_NMIISET[WWDT1] Bits */ +#define SYSCTL_NMIISET_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIISET_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT1_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT1_SET ((uint32_t)0x00000004U) +/* SYSCTL_NMIISET[SRAMDED] Bits */ +#define SYSCTL_NMIISET_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIISET_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIISET_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_SRAMDED_SET ((uint32_t)0x00000020U) +/* SYSCTL_NMIISET[BORLVL] Bits */ +#define SYSCTL_NMIISET_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIISET_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Set the BORLVL NMI */ +#define SYSCTL_NMIISET_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIISET_BORLVL_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_NMIISET[FLASHDED] Bits */ +#define SYSCTL_NMIISET_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIISET_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIISET_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_FLASHDED_SET ((uint32_t)0x00000010U) +/* SYSCTL_NMIISET[WWDT0] Bits */ +#define SYSCTL_NMIISET_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIISET_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT0_SET ((uint32_t)0x00000002U) +/* SYSCTL_NMIISET[LFCLKFAIL] Bits */ +#define SYSCTL_NMIISET_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIISET_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIISET_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_LFCLKFAIL_SET ((uint32_t)0x00000008U) + +/* SYSCTL_NMIICLR Bits */ +/* SYSCTL_NMIICLR[WWDT1] Bits */ +#define SYSCTL_NMIICLR_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIICLR_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT1_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT1_CLR ((uint32_t)0x00000004U) +/* SYSCTL_NMIICLR[SRAMDED] Bits */ +#define SYSCTL_NMIICLR_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIICLR_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIICLR_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_SRAMDED_CLR ((uint32_t)0x00000020U) +/* SYSCTL_NMIICLR[BORLVL] Bits */ +#define SYSCTL_NMIICLR_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIICLR_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Clr the BORLVL NMI */ +#define SYSCTL_NMIICLR_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIICLR_BORLVL_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_NMIICLR[FLASHDED] Bits */ +#define SYSCTL_NMIICLR_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIICLR_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIICLR_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_FLASHDED_CLR ((uint32_t)0x00000010U) +/* SYSCTL_NMIICLR[WWDT0] Bits */ +#define SYSCTL_NMIICLR_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIICLR_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT0_CLR ((uint32_t)0x00000002U) +/* SYSCTL_NMIICLR[LFCLKFAIL] Bits */ +#define SYSCTL_NMIICLR_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIICLR_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIICLR_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_LFCLKFAIL_CLR ((uint32_t)0x00000008U) + +/* SYSCTL_SYSOSCCFG Bits */ +/* SYSCTL_SYSOSCCFG[USE4MHZSTOP] Bits */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_OFS (8) /* !< USE4MHZSTOP Offset */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK ((uint32_t)0x00000100U) /* !< USE4MHZSTOP sets the SYSOSC stop + mode frequency policy. When entering + STOP mode, the SYSOSC frequency may + be automatically switched to 4MHz to + reduce SYSOSC power consumption. */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not gear shift the SYSOSC to + 4MHz in STOP mode */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE ((uint32_t)0x00000100U) /* !< Gear shift SYSOSC to 4MHz in STOP + mode */ +/* SYSCTL_SYSOSCCFG[DISABLESTOP] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_OFS (9) /* !< DISABLESTOP Offset */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_MASK ((uint32_t)0x00000200U) /* !< DISABLESTOP sets the SYSOSC stop + mode enable/disable policy. When + operating in STOP mode, the SYSOSC + may be automatically disabled. When + set, ULPCLK will run from LFCLK in + STOP mode and SYSOSC will be disabled + to reduce power consumption. */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC in STOP mode */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE ((uint32_t)0x00000200U) /* !< Disable SYSOSC in STOP mode and + source ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[BLOCKASYNCALL] Bits */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_OFS (16) /* !< BLOCKASYNCALL Offset */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_MASK ((uint32_t)0x00010000U) /* !< BLOCKASYNCALL may be used to mask + block all asynchronous fast clock + requests, preventing hardware from + dynamically changing the active clock + configuration when operating in a + given mode. */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_DISABLE ((uint32_t)0x00000000U) /* !< Asynchronous fast clock requests + are controlled by the requesting + peripheral */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE ((uint32_t)0x00010000U) /* !< All asynchronous fast clock + requests are blocked */ +/* SYSCTL_SYSOSCCFG[DISABLE] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLE_OFS (10) /* !< DISABLE Offset */ +#define SYSCTL_SYSOSCCFG_DISABLE_MASK ((uint32_t)0x00000400U) /* !< DISABLE sets the SYSOSC + enable/disable policy. SYSOSC may be + powered off in RUN, SLEEP, and STOP + modes to reduce power consumption. + When SYSOSC is disabled, MCLK and + ULPCLK are sourced from LFCLK. */ +#define SYSCTL_SYSOSCCFG_DISABLE_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC */ +#define SYSCTL_SYSOSCCFG_DISABLE_ENABLE ((uint32_t)0x00000400U) /* !< Disable SYSOSC immediately and + source MCLK and ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[FASTCPUEVENT] Bits */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_OFS (17) /* !< FASTCPUEVENT Offset */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_MASK ((uint32_t)0x00020000U) /* !< FASTCPUEVENT may be used to assert + a fast clock request when an + interrupt is asserted to the CPU, + reducing interrupt latency. */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_DISABLE ((uint32_t)0x00000000U) /* !< An interrupt to the CPU will not + assert a fast clock request */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE ((uint32_t)0x00020000U) /* !< An interrupt to the CPU will assert + a fast clock request */ +/* SYSCTL_SYSOSCCFG[FREQ] Bits */ +#define SYSCTL_SYSOSCCFG_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCCFG_FREQ_MASK ((uint32_t)0x00000003U) /* !< Target operating frequency for the + system oscillator (SYSOSC) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE ((uint32_t)0x00000000U) /* !< Base frequency (32MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< Low frequency (4MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< User-trimmed frequency (16 or 24 + MHz) */ + +/* SYSCTL_MCLKCFG Bits */ +/* SYSCTL_MCLKCFG[USEMFTICK] Bits */ +#define SYSCTL_MCLKCFG_USEMFTICK_OFS (12) /* !< USEMFTICK Offset */ +#define SYSCTL_MCLKCFG_USEMFTICK_MASK ((uint32_t)0x00001000U) /* !< USEMFTICK specifies whether the + 4MHz constant-rate clock (MFCLK) to + peripherals is enabled or disabled. + When enabled, MDIV must be disabled + (set to 0h=/1). */ +#define SYSCTL_MCLKCFG_USEMFTICK_DISABLE ((uint32_t)0x00000000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled */ +#define SYSCTL_MCLKCFG_USEMFTICK_ENABLE ((uint32_t)0x00001000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled. */ +/* SYSCTL_MCLKCFG[MDIV] Bits */ +#define SYSCTL_MCLKCFG_MDIV_OFS (0) /* !< MDIV Offset */ +#define SYSCTL_MCLKCFG_MDIV_MASK ((uint32_t)0x0000000FU) /* !< MDIV may be used to divide the MCLK + frequency when MCLK is sourced from + SYSOSC. MDIV=0h corresponds to /1 + (no divider). MDIV=1h corresponds to + /2 (divide-by-2). MDIV=Fh + corresponds to /16 (divide-by-16). + MDIV may be set between /1 and /16 on + an integer basis. */ +/* SYSCTL_MCLKCFG[USEHSCLK] Bits */ +#define SYSCTL_MCLKCFG_USEHSCLK_OFS (16) /* !< USEHSCLK Offset */ +#define SYSCTL_MCLKCFG_USEHSCLK_MASK ((uint32_t)0x00010000U) /* !< USEHSCLK, together with USELFCLK, + sets the MCLK source policy. Set + USEHSCLK to use HSCLK (HFCLK or + SYSPLL) as the MCLK source in RUN and + SLEEP modes. */ +#define SYSCTL_MCLKCFG_USEHSCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the high speed + clock (HSCLK) */ +#define SYSCTL_MCLKCFG_USEHSCLK_ENABLE ((uint32_t)0x00010000U) /* !< MCLK will use the high speed clock + (HSCLK) in RUN and SLEEP mode */ +/* SYSCTL_MCLKCFG[USELFCLK] Bits */ +#define SYSCTL_MCLKCFG_USELFCLK_OFS (20) /* !< USELFCLK Offset */ +#define SYSCTL_MCLKCFG_USELFCLK_MASK ((uint32_t)0x00100000U) /* !< USELFCLK sets the MCLK source + policy. Set USELFCLK to use LFCLK as + the MCLK source. Note that setting + USELFCLK does not disable SYSOSC, and + SYSOSC remains available for direct + use by analog modules. */ +#define SYSCTL_MCLKCFG_USELFCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the low frequency + clock (LFCLK) */ +#define SYSCTL_MCLKCFG_USELFCLK_ENABLE ((uint32_t)0x00100000U) /* !< MCLK will use the low frequency + clock (LFCLK) */ +/* SYSCTL_MCLKCFG[STOPCLKSTBY] Bits */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_OFS (21) /* !< STOPCLKSTBY Offset */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_MASK ((uint32_t)0x00200000U) /* !< STOPCLKSTBY sets the STANDBY mode + policy (STANDBY0 or STANDBY1). When + set, ULPCLK and LFCLK are disabled to + all peripherals in STANDBY mode, with + the exception of TIMG0 and TIMG1 + which continue to run. Wake-up is + only possible via an asynchronous + fast clock request. */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_DISABLE ((uint32_t)0x00000000U) /* !< ULPCLK/LFCLK runs to all PD0 + peripherals in STANDBY mode */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE ((uint32_t)0x00200000U) /* !< ULPCLK/LFCLK is disabled to all + peripherals in STANDBY mode except + TIMG0 and TIMG1 */ +/* SYSCTL_MCLKCFG[FLASHWAIT] Bits */ +#define SYSCTL_MCLKCFG_FLASHWAIT_OFS (8) /* !< FLASHWAIT Offset */ +#define SYSCTL_MCLKCFG_FLASHWAIT_MASK ((uint32_t)0x00000F00U) /* !< FLASHWAIT specifies the number of + flash wait states when MCLK is + sourced from HSCLK. FLASHWAIT has no + effect when MCLK is sourced from + SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT0 ((uint32_t)0x00000000U) /* !< No flash wait states are applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT1 ((uint32_t)0x00000100U) /* !< One flash wait state is applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT2 ((uint32_t)0x00000200U) /* !< 2 flash wait states are applied */ +/* SYSCTL_MCLKCFG[MCLKDEADCHK] Bits */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_OFS (22) /* !< MCLKDEADCHK Offset */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_MASK ((uint32_t)0x00400000U) /* !< MCLKDEADCHK enables or disables the + continuous MCLK dead check monitor. + LFCLK must be running before + MCLKDEADCHK is enabled. */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_DISABLE ((uint32_t)0x00000000U) /* !< The MCLK dead check monitor is + disabled */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_ENABLE ((uint32_t)0x00400000U) /* !< The MCLK dead check monitor is + enabled */ +/* SYSCTL_MCLKCFG[UDIV] Bits */ +#define SYSCTL_MCLKCFG_UDIV_OFS (4) /* !< UDIV Offset */ +#define SYSCTL_MCLKCFG_UDIV_MASK ((uint32_t)0x00000030U) /* !< UDIV specifies the ULPCLK divider + when MCLK is sourced from HSCLK. + UDIV has no effect when MCLK is + sourced from SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_UDIV_NODIVIDE ((uint32_t)0x00000000U) /* !< ULPCLK is not divided and is equal + to MCLK */ +#define SYSCTL_MCLKCFG_UDIV_DIVIDE2 ((uint32_t)0x00000010U) /* !< ULPCLK is MCLK/2 (divided-by-2) */ + +/* SYSCTL_HSCLKEN Bits */ +/* SYSCTL_HSCLKEN[HFXTEN] Bits */ +#define SYSCTL_HSCLKEN_HFXTEN_OFS (0) /* !< HFXTEN Offset */ +#define SYSCTL_HSCLKEN_HFXTEN_MASK ((uint32_t)0x00000001U) /* !< HFXTEN enables or disables the high + frequency crystal oscillator (HFXT). */ +#define SYSCTL_HSCLKEN_HFXTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the HFXT */ +#define SYSCTL_HSCLKEN_HFXTEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable the HFXT */ +/* SYSCTL_HSCLKEN[USEEXTHFCLK] Bits */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_OFS (16) /* !< USEEXTHFCLK Offset */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_MASK ((uint32_t)0x00010000U) /* !< USEEXTHFCLK selects the HFCLK_IN + digital clock input to be the source + for HFCLK. When disabled, HFXT is + the HFCLK source and HFXTEN may be + set. Do not set HFXTEN and + USEEXTHFCLK simultaneously. */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_DISABLE ((uint32_t)0x00000000U) /* !< Use HFXT as the HFCLK source */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE ((uint32_t)0x00010000U) /* !< Use the HFCLK_IN digital clock + input as the HFCLK source */ +/* SYSCTL_HSCLKEN[SYSPLLEN] Bits */ +#define SYSCTL_HSCLKEN_SYSPLLEN_OFS (8) /* !< SYSPLLEN Offset */ +#define SYSCTL_HSCLKEN_SYSPLLEN_MASK ((uint32_t)0x00000100U) /* !< SYSPLLEN enables or disables the + system phase-lock loop (SYSPLL). */ +#define SYSCTL_HSCLKEN_SYSPLLEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the SYSPLL */ +#define SYSCTL_HSCLKEN_SYSPLLEN_ENABLE ((uint32_t)0x00000100U) /* !< Enable the SYSPLL */ + +/* SYSCTL_HSCLKCFG Bits */ +/* SYSCTL_HSCLKCFG[USBFLL4HSCLK] Bits */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_OFS (1) /* !< USBFLL4HSCLK Offset */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_MASK ((uint32_t)0x00000002U) /* !< USBFLL4HSCLK selects the USBFLL as + High Speed clock source */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_SYSPLL_HFCLK ((uint32_t)0x00000000U) /* !< HSCLK is sourced from the + HSCLKCFG.HSCLKSEL */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_USBFLL ((uint32_t)0x00000002U) /* !< HSCLK is sourced from the USBFLL */ +/* SYSCTL_HSCLKCFG[HSCLKSEL] Bits */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_OFS (0) /* !< HSCLKSEL Offset */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_MASK ((uint32_t)0x00000001U) /* !< HSCLKSEL selects the HSCLK source + (SYSPLL or HFCLK). */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is sourced from the SYSPLL */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK ((uint32_t)0x00000001U) /* !< HSCLK is sourced from the HFCLK */ + +/* SYSCTL_HFCLKCLKCFG Bits */ +/* SYSCTL_HFCLKCLKCFG[HFXTTIME] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_OFS (0) /* !< HFXTTIME Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK ((uint32_t)0x000000FFU) /* !< HFXTTIME specifies the HFXT startup + time in 64us resolution. If the + HFCLK startup monitor is enabled + (HFCLKFLTCHK), HFXT will be checked + after this time expires. */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MINSTARTTIME ((uint32_t)0x00000000U) /* !< Minimum startup time (approximatly + zero) */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MAXSTARTTIME ((uint32_t)0x000000FFU) /* !< Maximum startup time (approximatly + 16.32ms) */ +/* SYSCTL_HFCLKCLKCFG[HFCLKFLTCHK] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_OFS (28) /* !< HFCLKFLTCHK Offset */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK ((uint32_t)0x10000000U) /* !< HFCLKFLTCHK enables or disables the + HFCLK startup monitor. */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_DISABLE ((uint32_t)0x00000000U) /* !< HFCLK startup is not checked */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE ((uint32_t)0x10000000U) /* !< HFCLK startup is checked */ +/* SYSCTL_HFCLKCLKCFG[HFXTRSEL] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS (12) /* !< HFXTRSEL Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK ((uint32_t)0x00003000U) /* !< HFXT Range Select */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8 ((uint32_t)0x00000000U) /* !< 4MHz <= HFXT frequency <= 8MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16 ((uint32_t)0x00001000U) /* !< 8MHz < HFXT frequency <= 16MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32 ((uint32_t)0x00002000U) /* !< 16MHz < HFXT frequency <= 32MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48 ((uint32_t)0x00003000U) /* !< 32MHz < HFXT frequency <= 48MHz */ + +/* SYSCTL_LFCLKCFG Bits */ +/* SYSCTL_LFCLKCFG[XT1DRIVE] Bits */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_OFS (0) /* !< XT1DRIVE Offset */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_MASK ((uint32_t)0x00000003U) /* !< XT1DRIVE selects the low frequency + crystal oscillator (LFXT) drive + strength. */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV ((uint32_t)0x00000000U) /* !< Lowest drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV ((uint32_t)0x00000001U) /* !< Lower drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV ((uint32_t)0x00000002U) /* !< Higher drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV ((uint32_t)0x00000003U) /* !< Highest drive and current */ +/* SYSCTL_LFCLKCFG[MONITOR] Bits */ +#define SYSCTL_LFCLKCFG_MONITOR_OFS (4) /* !< MONITOR Offset */ +#define SYSCTL_LFCLKCFG_MONITOR_MASK ((uint32_t)0x00000010U) /* !< MONITOR enables or disables the + LFCLK monitor, which continuously + checks LFXT or LFCLK_IN for a clock + stuck fault. */ +#define SYSCTL_LFCLKCFG_MONITOR_DISABLE ((uint32_t)0x00000000U) /* !< Clock monitor is disabled */ +#define SYSCTL_LFCLKCFG_MONITOR_ENABLE ((uint32_t)0x00000010U) /* !< Clock monitor is enabled */ +/* SYSCTL_LFCLKCFG[LOWCAP] Bits */ +#define SYSCTL_LFCLKCFG_LOWCAP_OFS (8) /* !< LOWCAP Offset */ +#define SYSCTL_LFCLKCFG_LOWCAP_MASK ((uint32_t)0x00000100U) /* !< LOWCAP controls the low-power LFXT + mode. When the LFXT load capacitance + is less than 3pf, LOWCAP may be set + for reduced power consumption. */ +#define SYSCTL_LFCLKCFG_LOWCAP_DISABLE ((uint32_t)0x00000000U) /* !< LFXT low capacitance mode is + disabled */ +#define SYSCTL_LFCLKCFG_LOWCAP_ENABLE ((uint32_t)0x00000100U) /* !< LFXT low capacitance mode is + enabled */ + +/* SYSCTL_SYSPLLCFG0 Bits */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK0] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_OFS (4) /* !< ENABLECLK0 Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK ((uint32_t)0x00000010U) /* !< ENABLECLK0 enables or disables the + SYSPLLCLK0 output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK0 is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_ENABLE ((uint32_t)0x00000010U) /* !< SYSPLLCLK0 is enabled */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK1] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_OFS (5) /* !< ENABLECLK1 Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK ((uint32_t)0x00000020U) /* !< ENABLECLK1 enables or disables the + SYSPLLCLK1 output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_ENABLE ((uint32_t)0x00000020U) /* !< SYSPLLCLK1 is enabled */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK1] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS (12) /* !< RDIVCLK1 Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK ((uint32_t)0x0000F000U) /* !< RDIVCLK1 sets the final divider for + the SYSPLLCLK1 output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV2 ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV4 ((uint32_t)0x00001000U) /* !< SYSPLLCLK1 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV6 ((uint32_t)0x00002000U) /* !< SYSPLLCLK1 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV8 ((uint32_t)0x00003000U) /* !< SYSPLLCLK1 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV10 ((uint32_t)0x00004000U) /* !< SYSPLLCLK1 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV12 ((uint32_t)0x00005000U) /* !< SYSPLLCLK1 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV14 ((uint32_t)0x00006000U) /* !< SYSPLLCLK1 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV16 ((uint32_t)0x00007000U) /* !< SYSPLLCLK1 is divided by 16 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV18 ((uint32_t)0x00008000U) /* !< SYSPLLCLK1 is divided by 18 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV20 ((uint32_t)0x00009000U) /* !< SYSPLLCLK1 is divided by 20 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV22 ((uint32_t)0x0000A000U) /* !< SYSPLLCLK1 is divided by 22 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV24 ((uint32_t)0x0000B000U) /* !< SYSPLLCLK1 is divided by 24 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV26 ((uint32_t)0x0000C000U) /* !< SYSPLLCLK1 is divided by 26 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV28 ((uint32_t)0x0000D000U) /* !< SYSPLLCLK1 is divided by 28 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV30 ((uint32_t)0x0000E000U) /* !< SYSPLLCLK1 is divided by 30 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV32 ((uint32_t)0x0000F000U) /* !< SYSPLLCLK1 is divided by 32 */ +/* SYSCTL_SYSPLLCFG0[MCLK2XVCO] Bits */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_OFS (1) /* !< MCLK2XVCO Offset */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK ((uint32_t)0x00000002U) /* !< MCLK2XVCO selects the SYSPLL output + which is sent to the HSCLK mux for + use by MCLK. */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_DISABLE ((uint32_t)0x00000000U) /* !< The SYSPLLCLK0 output is sent to + the HSCLK mux */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_ENABLE ((uint32_t)0x00000002U) /* !< The SYSPLLCLK2X output is sent to + the HSCLK mux */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK2X] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS (16) /* !< RDIVCLK2X Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK ((uint32_t)0x000F0000U) /* !< RDIVCLK2X sets the final divider + for the SYSPLLCLK2X output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV1 ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is divided by 1 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV2 ((uint32_t)0x00010000U) /* !< SYSPLLCLK1 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV3 ((uint32_t)0x00020000U) /* !< SYSPLLCLK1 is divided by 3 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV4 ((uint32_t)0x00030000U) /* !< SYSPLLCLK1 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV5 ((uint32_t)0x00040000U) /* !< SYSPLLCLK1 is divided by 5 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV6 ((uint32_t)0x00050000U) /* !< SYSPLLCLK1 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV7 ((uint32_t)0x00060000U) /* !< SYSPLLCLK1 is divided by 7 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV8 ((uint32_t)0x00070000U) /* !< SYSPLLCLK1 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV9 ((uint32_t)0x00080000U) /* !< SYSPLLCLK1 is divided by 9 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV10 ((uint32_t)0x00090000U) /* !< SYSPLLCLK1 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV11 ((uint32_t)0x000A0000U) /* !< SYSPLLCLK1 is divided by 11 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV12 ((uint32_t)0x000B0000U) /* !< SYSPLLCLK1 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV13 ((uint32_t)0x000C0000U) /* !< SYSPLLCLK1 is divided by 13 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV14 ((uint32_t)0x000D0000U) /* !< SYSPLLCLK1 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV15 ((uint32_t)0x000E0000U) /* !< SYSPLLCLK1 is divided by 15 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV16 ((uint32_t)0x000F0000U) /* !< SYSPLLCLK1 is divided by 16 */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK0] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS (8) /* !< RDIVCLK0 Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK ((uint32_t)0x00000F00U) /* !< RDIVCLK0 sets the final divider for + the SYSPLLCLK0 output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV2 ((uint32_t)0x00000000U) /* !< SYSPLLCLK0 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV4 ((uint32_t)0x00000100U) /* !< SYSPLLCLK0 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV6 ((uint32_t)0x00000200U) /* !< SYSPLLCLK0 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV8 ((uint32_t)0x00000300U) /* !< SYSPLLCLK0 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV10 ((uint32_t)0x00000400U) /* !< SYSPLLCLK0 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV12 ((uint32_t)0x00000500U) /* !< SYSPLLCLK0 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV14 ((uint32_t)0x00000600U) /* !< SYSPLLCLK0 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV16 ((uint32_t)0x00000700U) /* !< SYSPLLCLK0 is divided by 16 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV18 ((uint32_t)0x00000800U) /* !< SYSPLLCLK0 is divided by 18 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV20 ((uint32_t)0x00000900U) /* !< SYSPLLCLK0 is divided by 20 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV22 ((uint32_t)0x00000A00U) /* !< SYSPLLCLK0 is divided by 22 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV24 ((uint32_t)0x00000B00U) /* !< SYSPLLCLK0 is divided by 24 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV26 ((uint32_t)0x00000C00U) /* !< SYSPLLCLK0 is divided by 26 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV28 ((uint32_t)0x00000D00U) /* !< SYSPLLCLK0 is divided by 28 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV30 ((uint32_t)0x00000E00U) /* !< SYSPLLCLK0 is divided by 30 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV32 ((uint32_t)0x00000F00U) /* !< SYSPLLCLK0 is divided by 32 */ +/* SYSCTL_SYSPLLCFG0[SYSPLLREF] Bits */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_OFS (0) /* !< SYSPLLREF Offset */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK ((uint32_t)0x00000001U) /* !< SYSPLLREF selects the system PLL + (SYSPLL) reference clock source. */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_SYSOSC ((uint32_t)0x00000000U) /* !< SYSPLL reference is SYSOSC */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_HFCLK ((uint32_t)0x00000001U) /* !< SYSPLL reference is HFCLK */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK2X] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_OFS (6) /* !< ENABLECLK2X Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK ((uint32_t)0x00000040U) /* !< ENABLECLK2X enables or disables the + SYSPLLCLK2X output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK2X is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_ENABLE ((uint32_t)0x00000040U) /* !< SYSPLLCLK2X is enabled */ + +/* SYSCTL_SYSPLLCFG1 Bits */ +/* SYSCTL_SYSPLLCFG1[PDIV] Bits */ +#define SYSCTL_SYSPLLCFG1_PDIV_OFS (0) /* !< PDIV Offset */ +#define SYSCTL_SYSPLLCFG1_PDIV_MASK ((uint32_t)0x00000003U) /* !< PDIV selects the SYSPLL reference + clock prescale divider. */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV1 ((uint32_t)0x00000000U) /* !< SYSPLLREF is not divided */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV2 ((uint32_t)0x00000001U) /* !< SYSPLLREF is divided by 2 */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV4 ((uint32_t)0x00000002U) /* !< SYSPLLREF is divided by 4 */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV8 ((uint32_t)0x00000003U) /* !< SYSPLLREF is divided by 8 */ +/* SYSCTL_SYSPLLCFG1[QDIV] Bits */ +#define SYSCTL_SYSPLLCFG1_QDIV_OFS (8) /* !< QDIV Offset */ +#define SYSCTL_SYSPLLCFG1_QDIV_MASK ((uint32_t)0x00007F00U) /* !< QDIV selects the SYSPLL feedback + path divider. */ +#define SYSCTL_SYSPLLCFG1_QDIV_INVALID ((uint32_t)0x00000000U) /* !< Divide-by-one is not a valid QDIV + option */ +#define SYSCTL_SYSPLLCFG1_QDIV_QDIVMIN ((uint32_t)0x00000100U) /* !< Feedback path is divided by 2 */ +#define SYSCTL_SYSPLLCFG1_QDIV_QDIVMAX ((uint32_t)0x00007E00U) /* !< Feedback path is divided by 127 + (0x7E) */ + +/* SYSCTL_SYSPLLPARAM0 Bits */ +/* SYSCTL_SYSPLLPARAM0[CPCURRENT] Bits */ +#define SYSCTL_SYSPLLPARAM0_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */ +#define SYSCTL_SYSPLLPARAM0_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge pump current */ +/* SYSCTL_SYSPLLPARAM0[CAPBOVERRIDE] Bits */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< CAPBOVERRIDE controls the override + for Cap B */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U) /* !< Cap B override disabled */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U) /* !< Cap B override enabled */ +/* SYSCTL_SYSPLLPARAM0[STARTTIME] Bits */ +#define SYSCTL_SYSPLLPARAM0_STARTTIME_OFS (0) /* !< STARTTIME Offset */ +#define SYSCTL_SYSPLLPARAM0_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from enable to locked + clock, in 1us resolution */ +/* SYSCTL_SYSPLLPARAM0[CAPBVAL] Bits */ +#define SYSCTL_SYSPLLPARAM0_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */ +#define SYSCTL_SYSPLLPARAM0_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override value for Cap B */ +/* SYSCTL_SYSPLLPARAM0[STARTTIMELP] Bits */ +#define SYSCTL_SYSPLLPARAM0_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */ +#define SYSCTL_SYSPLLPARAM0_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from low power mode + exit to locked clock, in 1us + resolution */ + +/* SYSCTL_SYSPLLPARAM1 Bits */ +/* SYSCTL_SYSPLLPARAM1[LPFCAPA] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop filter Cap A */ +/* SYSCTL_SYSPLLPARAM1[LPFRESC] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFRESC_OFS (24) /* !< LPFRESC Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop filter Res C */ +/* SYSCTL_SYSPLLPARAM1[LPFRESA] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFRESA_OFS (8) /* !< LPFRESA Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop filter Res A */ + +/* SYSCTL_GENCLKCFG Bits */ +/* SYSCTL_GENCLKCFG[HFCLK4MFPCLKDIV] Bits */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS (12) /* !< HFCLK4MFPCLKDIV Offset */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK ((uint32_t)0x0000F000U) /* !< HFCLK4MFPCLKDIV selects the divider + applied to HFCLK when HFCLK is used + as the MFPCLK source. Integer + dividers from /1 to /16 may be + selected. */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV1 ((uint32_t)0x00000000U) /* !< HFCLK is not divided before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV2 ((uint32_t)0x00001000U) /* !< HFCLK is divided by 2 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV3 ((uint32_t)0x00002000U) /* !< HFCLK is divided by 3 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV4 ((uint32_t)0x00003000U) /* !< HFCLK is divided by 4 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV5 ((uint32_t)0x00004000U) /* !< HFCLK is divided by 5 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV6 ((uint32_t)0x00005000U) /* !< HFCLK is divided by 6 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV7 ((uint32_t)0x00006000U) /* !< HFCLK is divided by 7 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV8 ((uint32_t)0x00007000U) /* !< HFCLK is divided by 8 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV9 ((uint32_t)0x00008000U) /* !< HFCLK is divided by 9 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV10 ((uint32_t)0x00009000U) /* !< HFCLK is divided by 10 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV11 ((uint32_t)0x0000A000U) /* !< HFCLK is divided by 11 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV12 ((uint32_t)0x0000B000U) /* !< HFCLK is divided by 12 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV13 ((uint32_t)0x0000C000U) /* !< HFCLK is divided by 13 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV14 ((uint32_t)0x0000D000U) /* !< HFCLK is divided by 14 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV15 ((uint32_t)0x0000E000U) /* !< HFCLK is divided by 15 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV16 ((uint32_t)0x0000F000U) /* !< HFCLK is divided by 16 before being + used for MFPCLK */ +/* SYSCTL_GENCLKCFG[MFPCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_OFS (9) /* !< MFPCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_MASK ((uint32_t)0x00000200U) /* !< MFPCLKSRC selects the MFPCLK + (middle frequency precision clock) + source. */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< MFPCLK is sourced from SYSOSC */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK ((uint32_t)0x00000200U) /* !< MFPCLK is sourced from HFCLK */ +/* SYSCTL_GENCLKCFG[USBCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_OFS (10) /* !< USBCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_MASK ((uint32_t)0x00000400U) /* !< USBCLKSRC selects the USBCLK + source. */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_USBFLLCLK ((uint32_t)0x00000000U) /* !< USBCLK source is USBFLL */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_SYSPLLOUT1 ((uint32_t)0x00000400U) /* !< USBCLK source is SYSPLLCLK1 */ +/* SYSCTL_GENCLKCFG[FCCLFCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_OFS (29) /* !< FCCLFCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_MASK ((uint32_t)0x20000000U) /* !< FCCLFCLKSRC selects between SYSTEM + LFCLK and EXTERNAL SOURCED LFCLK. */ +/* SYSCTL_GENCLKCFG[FCCTRIGCNT] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS (24) /* !< FCCTRIGCNT Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK ((uint32_t)0x1F000000U) /* !< FCCTRIGCNT specifies the number of + trigger clock periods in the trigger + window. FCCTRIGCNT=0h (one trigger + clock period) up to 1Fh (32 trigger + clock periods) may be specified. */ +/* SYSCTL_GENCLKCFG[ANACPUMPCFG] Bits */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_OFS (22) /* !< ANACPUMPCFG Offset */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK ((uint32_t)0x00C00000U) /* !< ANACPUMPCFG selects the analog mux + charge pump (VBOOST) enable method. */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND ((uint32_t)0x00000000U) /* !< VBOOST is enabled on request from a + COMP, GPAMP, or OPA */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE ((uint32_t)0x00400000U) /* !< VBOOST is enabled when the device + is in RUN or SLEEP mode, or when a + COMP/GPAMP/OPA is enabled */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS ((uint32_t)0x00800000U) /* !< VBOOST is always enabled */ +/* SYSCTL_GENCLKCFG[FCCTRIGSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_OFS (20) /* !< FCCTRIGSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK ((uint32_t)0x00100000U) /* !< FCCTRIGSRC selects the frequency + clock counter (FCC) trigger source. */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN ((uint32_t)0x00000000U) /* !< FCC trigger is the external pin */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK ((uint32_t)0x00100000U) /* !< FCC trigger is the LFCLK */ +/* SYSCTL_GENCLKCFG[FCCSELCLK] Bits */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_OFS (16) /* !< FCCSELCLK Offset */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MASK ((uint32_t)0x000F0000U) /* !< FCCSELCLK selectes the frequency + clock counter (FCC) clock source. */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MCLK ((uint32_t)0x00000000U) /* !< FCC clock is MCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC ((uint32_t)0x00010000U) /* !< FCC clock is SYSOSC */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK ((uint32_t)0x00020000U) /* !< FCC clock is HFCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK ((uint32_t)0x00030000U) /* !< FCC clock is the CLK_OUT selection */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK0 ((uint32_t)0x00040000U) /* !< FCC clock is SYSPLLCLK0 */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK1 ((uint32_t)0x00050000U) /* !< FCC clock is SYSPLLCLK1 */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK2X ((uint32_t)0x00060000U) /* !< FCC clock is SYSPLLCLK2X */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN ((uint32_t)0x00070000U) /* !< FCC clock is the FCCIN external + input */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_USBFLL ((uint32_t)0x00080000U) /* !< FCC clock is USBFLL */ +/* SYSCTL_GENCLKCFG[FCCLVLTRIG] Bits */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_OFS (21) /* !< FCCLVLTRIG Offset */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK ((uint32_t)0x00200000U) /* !< FCCLVLTRIG selects the frequency + clock counter (FCC) trigger mode. */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE ((uint32_t)0x00000000U) /* !< Rising edge to rising edge + triggered */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL ((uint32_t)0x00200000U) /* !< Level triggered */ +/* SYSCTL_GENCLKCFG[EXCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_OFS (0) /* !< EXCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MASK ((uint32_t)0x00000007U) /* !< EXCLKSRC selects the source for the + CLK_OUT external clock output block. + ULPCLK and MFPCLK require the CLK_OUT + divider (EXCLKDIVEN) to be enabled */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< CLK_OUT is SYSOSC */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK ((uint32_t)0x00000001U) /* !< CLK_OUT is ULPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK ((uint32_t)0x00000002U) /* !< CLK_OUT is LFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK ((uint32_t)0x00000003U) /* !< CLK_OUT is MFPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK ((uint32_t)0x00000004U) /* !< CLK_OUT is HFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSPLLOUT1 ((uint32_t)0x00000005U) /* !< CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 + must be <=48MHz) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_USBFLL ((uint32_t)0x00000006U) /* !< CLK_OUT is USBFLL (At 60Mhz must + divide for external output) */ +/* SYSCTL_GENCLKCFG[EXCLKDIVVAL] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_OFS (4) /* !< EXCLKDIVVAL Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK ((uint32_t)0x00000070U) /* !< EXCLKDIVVAL selects the divider + value for the divider in the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2 ((uint32_t)0x00000000U) /* !< CLK_OUT source is divided by 2 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4 ((uint32_t)0x00000010U) /* !< CLK_OUT source is divided by 4 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6 ((uint32_t)0x00000020U) /* !< CLK_OUT source is divided by 6 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8 ((uint32_t)0x00000030U) /* !< CLK_OUT source is divided by 8 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10 ((uint32_t)0x00000040U) /* !< CLK_OUT source is divided by 10 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12 ((uint32_t)0x00000050U) /* !< CLK_OUT source is divided by 12 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14 ((uint32_t)0x00000060U) /* !< CLK_OUT source is divided by 14 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16 ((uint32_t)0x00000070U) /* !< CLK_OUT source is divided by 16 */ +/* SYSCTL_GENCLKCFG[EXCLKDIVEN] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_OFS (7) /* !< EXCLKDIVEN Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK ((uint32_t)0x00000080U) /* !< EXCLKDIVEN enables or disables the + divider function of the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU ((uint32_t)0x00000000U) /* !< CLock divider is disabled + (passthrough, EXCLKDIVVAL is not + applied) */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE ((uint32_t)0x00000080U) /* !< Clock divider is enabled + (EXCLKDIVVAL is applied) */ + +/* SYSCTL_GENCLKEN Bits */ +/* SYSCTL_GENCLKEN[EXCLKEN] Bits */ +#define SYSCTL_GENCLKEN_EXCLKEN_OFS (0) /* !< EXCLKEN Offset */ +#define SYSCTL_GENCLKEN_EXCLKEN_MASK ((uint32_t)0x00000001U) /* !< EXCLKEN enables the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKEN_EXCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< CLK_OUT block is disabled */ +#define SYSCTL_GENCLKEN_EXCLKEN_ENABLE ((uint32_t)0x00000001U) /* !< CLK_OUT block is enabled */ +/* SYSCTL_GENCLKEN[MFPCLKEN] Bits */ +#define SYSCTL_GENCLKEN_MFPCLKEN_OFS (4) /* !< MFPCLKEN Offset */ +#define SYSCTL_GENCLKEN_MFPCLKEN_MASK ((uint32_t)0x00000010U) /* !< MFPCLKEN enables the middle + frequency precision clock (MFPCLK). */ +#define SYSCTL_GENCLKEN_MFPCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< MFPCLK is disabled */ +#define SYSCTL_GENCLKEN_MFPCLKEN_ENABLE ((uint32_t)0x00000010U) /* !< MFPCLK is enabled */ + +/* SYSCTL_PMODECFG Bits */ +/* SYSCTL_PMODECFG[DSLEEP] Bits */ +#define SYSCTL_PMODECFG_DSLEEP_OFS (0) /* !< DSLEEP Offset */ +#define SYSCTL_PMODECFG_DSLEEP_MASK ((uint32_t)0x00000003U) /* !< DSLEEP selects the operating mode + to enter upon a DEEPSLEEP request + from the CPU. */ +#define SYSCTL_PMODECFG_DSLEEP_STOP ((uint32_t)0x00000000U) /* !< STOP mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_STANDBY ((uint32_t)0x00000001U) /* !< STANDBY mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_SHUTDOWN ((uint32_t)0x00000002U) /* !< SHUTDOWN mode is entered */ + +/* SYSCTL_FCC Bits */ +/* SYSCTL_FCC[DATA] Bits */ +#define SYSCTL_FCC_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FCC_DATA_MASK ((uint32_t)0x003FFFFFU) /* !< Frequency clock counter (FCC) count + value. */ + +/* SYSCTL_SYSOSCTRIMUSER Bits */ +/* SYSCTL_SYSOSCTRIMUSER[RESCOARSE] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RESCOARSE_OFS (8) /* !< RESCOARSE Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RESCOARSE_MASK ((uint32_t)0x00003F00U) /* !< RESCOARSE specifies the resister + coarse trim. This value changes with + the target frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[RESFINE] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RESFINE_OFS (16) /* !< RESFINE Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RESFINE_MASK ((uint32_t)0x000F0000U) /* !< RESFINE specifies the resister fine + trim. This value changes with the + target frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[RDIV] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RDIV_OFS (20) /* !< RDIV Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RDIV_MASK ((uint32_t)0x1FF00000U) /* !< RDIV specifies the frequency + correction loop (FCL) resistor trim. + This value changes with the target + frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[FREQ] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_MASK ((uint32_t)0x00000003U) /* !< FREQ specifies the target + user-trimmed frequency for SYSOSC. */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC16M ((uint32_t)0x00000001U) /* !< 16MHz user frequency */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC24M ((uint32_t)0x00000002U) /* !< 24MHz user frequency */ +/* SYSCTL_SYSOSCTRIMUSER[CAP] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_CAP_OFS (4) /* !< CAP Offset */ +#define SYSCTL_SYSOSCTRIMUSER_CAP_MASK ((uint32_t)0x00000070U) /* !< CAP specifies the SYSOSC capacitor + trim. This value changes with the + target frequency. */ + +/* SYSCTL_SRAMBOUNDARY Bits */ +/* SYSCTL_SRAMBOUNDARY[ADDR] Bits */ +#define SYSCTL_SRAMBOUNDARY_ADDR_OFS (5) /* !< ADDR Offset */ +#define SYSCTL_SRAMBOUNDARY_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary configuration. The + value configured into this acts such + that: SRAM accesses to addresses less + than or equal value will be RW only. + SRAM accesses to addresses greater + than value will be RX only. Value of + 0 is not valid (system will have no + stack). If set to 0, the system acts + as if the entire SRAM is RWX. Any + non-zero value can be configured, + including a value = SRAM size. */ + +/* SYSCTL_SYSTEMCFG Bits */ +/* SYSCTL_SYSTEMCFG[KEY] Bits */ +#define SYSCTL_SYSTEMCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSTEMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 1Bh (27) must be + written to KEY together with contents + to be updated. Reads as 0 */ +#define SYSCTL_SYSTEMCFG_KEY_VALUE ((uint32_t)0x1B000000U) /* !< Issue write */ +/* SYSCTL_SYSTEMCFG[FLASHECCRSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS (2) /* !< FLASHECCRSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK ((uint32_t)0x00000004U) /* !< FLASHECCRSTDIS specifies whether a + flash ECC double error detect (DED) + will trigger a SYSRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_FALSE ((uint32_t)0x00000000U) /* !< Flash ECC DED will trigger a SYSRST */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_TRUE ((uint32_t)0x00000004U) /* !< Flash ECC DED will trigger a NMI */ +/* SYSCTL_SYSTEMCFG[WWDTLP0RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS (0) /* !< WWDTLP0RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK ((uint32_t)0x00000001U) /* !< WWDTLP0RSTDIS specifies whether a + WWDT Error Event will trigger a + BOOTRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP0 Error Event will trigger a + BOOTRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_TRUE ((uint32_t)0x00000001U) /* !< WWDTLP0 Error Event will trigger an + NMI */ +/* SYSCTL_SYSTEMCFG[WWDTLP1RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS (1) /* !< WWDTLP1RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK ((uint32_t)0x00000002U) /* !< WWDTLP1RSTDIS specifies whether a + WWDT Error Event will trigger a + SYSRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP1 Error Event will trigger a + SYSRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_TRUE ((uint32_t)0x00000002U) /* !< WWDTLP1 Error Event will trigger an + NMI */ + +/* SYSCTL_WRITELOCK Bits */ +/* SYSCTL_WRITELOCK[ACTIVE] Bits */ +#define SYSCTL_WRITELOCK_ACTIVE_OFS (0) /* !< ACTIVE Offset */ +#define SYSCTL_WRITELOCK_ACTIVE_MASK ((uint32_t)0x00000001U) /* !< ACTIVE controls whether critical + SYSCTL registers are write protected + or not. */ +#define SYSCTL_WRITELOCK_ACTIVE_DISABLE ((uint32_t)0x00000000U) /* !< Allow writes to lockable registers */ +#define SYSCTL_WRITELOCK_ACTIVE_ENABLE ((uint32_t)0x00000001U) /* !< Disallow writes to lockable + registers */ + +/* SYSCTL_CLKSTATUS Bits */ +/* SYSCTL_CLKSTATUS[LFOSCGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_OFS (11) /* !< LFOSCGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_MASK ((uint32_t)0x00000800U) /* !< LFOSCGOOD indicates when the LFOSC + startup has completed and the LFOSC + is ready for use. */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFOSC is not ready */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE ((uint32_t)0x00000800U) /* !< LFOSC is ready */ +/* SYSCTL_CLKSTATUS[HFCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_OFS (8) /* !< HFCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_MASK ((uint32_t)0x00000100U) /* !< HFCLKGOOD indicates that the HFCLK + started correctly. When the HFXT is + started or HFCLK_IN is selected as + the HFCLK source, this bit will be + set by hardware if a valid HFCLK is + detected, and cleared if HFCLK is not + operating within the expected range. */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< HFCLK did not start correctly */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE ((uint32_t)0x00000100U) /* !< HFCLK started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKDEAD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_OFS (20) /* !< HSCLKDEAD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_MASK ((uint32_t)0x00100000U) /* !< HSCLKDEAD is set by hardware if the + selected source for HSCLK was started + but did not start successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source was not started or + started correctly */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE ((uint32_t)0x00100000U) /* !< The HSCLK source did not start + correctly */ +/* SYSCTL_CLKSTATUS[SYSPLLBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_OFS (29) /* !< SYSPLLBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_MASK ((uint32_t)0x20000000U) /* !< SYSPLLBLKUPD indicates when writes + to SYSPLLCFG0/1 and SYSPLLPARAM0/1 + are blocked. */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< writes to SYSPLLCFG0/1 and + SYSPLLPARAM0/1 are allowed */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_TRUE ((uint32_t)0x20000000U) /* !< writes to SYSPLLCFG0/1 and + SYSPLLPARAM0/1 are blocked */ +/* SYSCTL_CLKSTATUS[HFCLKOFF] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_OFS (13) /* !< HFCLKOFF Offset */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_MASK ((uint32_t)0x00002000U) /* !< HFCLKOFF indicates if the HFCLK is + disabled or was dead at startup. + When the HFCLK is started, HFCLKOFF + is cleared by hardware. Following + startup of the HFCLK, if the HFCLK + startup monitor determines that the + HFCLK was not started correctly, + HFCLKOFF is set. */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_FALSE ((uint32_t)0x00000000U) /* !< HFCLK started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_TRUE ((uint32_t)0x00002000U) /* !< HFCLK is disabled or was dead at + startup */ +/* SYSCTL_CLKSTATUS[HFCLKBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_OFS (28) /* !< HFCLKBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_MASK ((uint32_t)0x10000000U) /* !< HFCLKBLKUPD indicates when writes + to the HFCLKCLKCFG register are + blocked. */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< Writes to HFCLKCLKCFG are allowed */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE ((uint32_t)0x10000000U) /* !< Writes to HFCLKCLKCFG are blocked */ +/* SYSCTL_CLKSTATUS[HSCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_OFS (21) /* !< HSCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_MASK ((uint32_t)0x00200000U) /* !< HSCLKGOOD is set by hardware if the + selected clock source for HSCLK + started successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source did not start + correctly */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE ((uint32_t)0x00200000U) /* !< The HSCLK source started correctly */ +/* SYSCTL_CLKSTATUS[SYSPLLGOOD] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_OFS (9) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK ((uint32_t)0x00000200U) /* !< SYSPLLGOOD indicates if the SYSPLL + started correctly. When the SYSPLL + is started, SYSPLLGOOD is cleared by + hardware. After the startup settling + time has expired, the SYSPLL status + is tested. If the SYSPLL started + successfully the SYSPLLGOOD bit is + set, else it is left cleared. */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL did not start correctly */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_TRUE ((uint32_t)0x00000200U) /* !< SYSPLL started correctly */ +/* SYSCTL_CLKSTATUS[ANACLKERR] Bits */ +#define SYSCTL_CLKSTATUS_ANACLKERR_OFS (31) /* !< ANACLKERR Offset */ +#define SYSCTL_CLKSTATUS_ANACLKERR_MASK ((uint32_t)0x80000000U) /* !< ANACLKERR is set when the device + clock configuration does not support + an enabled analog peripheral mode and + the analog peripheral may not be + functioning as expected. */ +#define SYSCTL_CLKSTATUS_ANACLKERR_FALSE ((uint32_t)0x00000000U) /* !< No analog clock errors detected */ +#define SYSCTL_CLKSTATUS_ANACLKERR_TRUE ((uint32_t)0x80000000U) /* !< Analog clock error detected */ +/* SYSCTL_CLKSTATUS[HSCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_OFS (4) /* !< HSCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_MASK ((uint32_t)0x00000010U) /* !< HSCLKMUX indicates if MCLK is + currently sourced from the high-speed + clock (HSCLK). */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_SYSOSC ((uint32_t)0x00000000U) /* !< MCLK is not sourced from HSCLK */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK ((uint32_t)0x00000010U) /* !< MCLK is sourced from HSCLK */ +/* SYSCTL_CLKSTATUS[LFCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_OFS (6) /* !< LFCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_MASK ((uint32_t)0x000000C0U) /* !< LFCLKMUX indicates if LFCLK is + sourced from the internal LFOSC, the + low frequency crystal (LFXT), or the + LFCLK_IN digital clock input. */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFOSC ((uint32_t)0x00000000U) /* !< LFCLK is sourced from the internal + LFOSC */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFXT ((uint32_t)0x00000040U) /* !< LFCLK is sourced from the LFXT + (crystal) */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_EXLF ((uint32_t)0x00000080U) /* !< LFCLK is sourced from LFCLK_IN + (external digital clock input) */ +/* SYSCTL_CLKSTATUS[SYSOSCFREQ] Bits */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_OFS (0) /* !< SYSOSCFREQ Offset */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK ((uint32_t)0x00000003U) /* !< SYSOSCFREQ indicates the current + SYSOSC operating frequency. */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC32M ((uint32_t)0x00000000U) /* !< SYSOSC is at base frequency (32MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< SYSOSC is at low frequency (4MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< SYSOSC is at the user-trimmed + frequency (16 or 24MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCTURBO ((uint32_t)0x00000003U) /* !< Reserved */ +/* SYSCTL_CLKSTATUS[LFXTGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_OFS (10) /* !< LFXTGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_MASK ((uint32_t)0x00000400U) /* !< LFXTGOOD indicates if the LFXT + started correctly. When the LFXT is + started, LFXTGOOD is cleared by + hardware. After the startup settling + time has expired, the LFXT status is + tested. If the LFXT started + successfully the LFXTGOOD bit is set, + else it is left cleared. */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFXT did not start correctly */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_TRUE ((uint32_t)0x00000400U) /* !< LFXT started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKSOFF] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_OFS (12) /* !< HSCLKSOFF Offset */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_MASK ((uint32_t)0x00001000U) /* !< HSCLKSOFF is set when the high + speed clock sources (SYSPLL, HFCLK) + are disabled or dead. It is the + logical AND of HFCLKOFF and + SYSPLLOFF. */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL, HFCLK, or both were started + correctly and remain enabled */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE ((uint32_t)0x00001000U) /* !< SYSPLL and HFCLK are both either + off or dead */ +/* SYSCTL_CLKSTATUS[FCLMODE] Bits */ +#define SYSCTL_CLKSTATUS_FCLMODE_OFS (24) /* !< FCLMODE Offset */ +#define SYSCTL_CLKSTATUS_FCLMODE_MASK ((uint32_t)0x01000000U) /* !< FCLMODE indicates if the SYSOSC + frequency correction loop (FCL) is + enabled. */ +#define SYSCTL_CLKSTATUS_FCLMODE_DISABLED ((uint32_t)0x00000000U) /* !< SYSOSC FCL is disabled */ +#define SYSCTL_CLKSTATUS_FCLMODE_ENABLED ((uint32_t)0x01000000U) /* !< SYSOSC FCL is enabled */ +/* SYSCTL_CLKSTATUS[CURHSCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_OFS (16) /* !< CURHSCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_MASK ((uint32_t)0x00010000U) /* !< CURHSCLKSEL indicates the current + clock source for HSCLK. */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is currently sourced from the + SYSPLL */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK ((uint32_t)0x00010000U) /* !< HSCLK is currently sourced from the + HFCLK */ +/* SYSCTL_CLKSTATUS[CURMCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_OFS (17) /* !< CURMCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_MASK ((uint32_t)0x00020000U) /* !< CURMCLKSEL indicates if MCLK is + currently sourced from LFCLK. */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_NOTLFCLK ((uint32_t)0x00000000U) /* !< MCLK is not sourced from LFCLK */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK ((uint32_t)0x00020000U) /* !< MCLK is sourced from LFCLK */ +/* SYSCTL_CLKSTATUS[FCCDONE] Bits */ +#define SYSCTL_CLKSTATUS_FCCDONE_OFS (25) /* !< FCCDONE Offset */ +#define SYSCTL_CLKSTATUS_FCCDONE_MASK ((uint32_t)0x02000000U) /* !< FCCDONE indicates when a frequency + clock counter capture is complete. */ +#define SYSCTL_CLKSTATUS_FCCDONE_NOTDONE ((uint32_t)0x00000000U) /* !< FCC capture is not done */ +#define SYSCTL_CLKSTATUS_FCCDONE_DONE ((uint32_t)0x02000000U) /* !< FCC capture is done */ +/* SYSCTL_CLKSTATUS[SYSPLLOFF] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_OFS (14) /* !< SYSPLLOFF Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_MASK ((uint32_t)0x00004000U) /* !< SYSPLLOFF indicates if the SYSPLL + is disabled or was dead at startup. + When the SYSPLL is started, SYSPLLOFF + is cleared by hardware. Following + startup of the SYSPLL, if the SYSPLL + startup monitor determines that the + SYSPLL was not started correctly, + SYSPLLOFF is set. */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_TRUE ((uint32_t)0x00004000U) /* !< SYSPLL is disabled or was dead + startup */ +/* SYSCTL_CLKSTATUS[LFCLKFAIL] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_OFS (23) /* !< LFCLKFAIL Offset */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_MASK ((uint32_t)0x00800000U) /* !< LFCLKFAIL indicates when the + continous LFCLK monitor detects a + LFXT or LFCLK_IN clock stuck failure. */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) /* !< No LFCLK fault detected */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE ((uint32_t)0x00800000U) /* !< LFCLK stuck fault detected */ + +/* SYSCTL_SYSSTATUS Bits */ +/* SYSCTL_SYSSTATUS[USBFS0READY] Bits */ +#define SYSCTL_SYSSTATUS_USBFS0READY_OFS (25) /* !< USBFS0READY Offset */ +#define SYSCTL_SYSSTATUS_USBFS0READY_MASK ((uint32_t)0x02000000U) /* !< USBFS0READY indicates when the + USBFS0 peripheral is ready. */ +#define SYSCTL_SYSSTATUS_USBFS0READY_FALSE ((uint32_t)0x00000000U) /* !< USBFS0 is not ready */ +#define SYSCTL_SYSSTATUS_USBFS0READY_TRUE ((uint32_t)0x02000000U) /* !< USBFS0 is ready */ +/* SYSCTL_SYSSTATUS[SHDNIOLOCK] Bits */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_OFS (14) /* !< SHDNIOLOCK Offset */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_MASK ((uint32_t)0x00004000U) /* !< SHDNIOLOCK indicates when IO is + locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_FALSE ((uint32_t)0x00000000U) /* !< IO IS NOT Locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE ((uint32_t)0x00004000U) /* !< IO IS Locked due to SHUTDOWN */ +/* SYSCTL_SYSSTATUS[EXTRSTPINDIS] Bits */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_OFS (12) /* !< EXTRSTPINDIS Offset */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_MASK ((uint32_t)0x00001000U) /* !< EXTRSTPINDIS indicates when user + has disabled the use of external + reset pin */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_FALSE ((uint32_t)0x00000000U) /* !< External Reset Pin Enabled */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE ((uint32_t)0x00001000U) /* !< External Reset Pin Disabled */ +/* SYSCTL_SYSSTATUS[SWDCFGDIS] Bits */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_OFS (13) /* !< SWDCFGDIS Offset */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_MASK ((uint32_t)0x00002000U) /* !< SWDCFGDIS indicates when user has + disabled the use of SWD Port */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_FALSE ((uint32_t)0x00000000U) /* !< SWD Port Enabled */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE ((uint32_t)0x00002000U) /* !< SWD Port Disabled */ +/* SYSCTL_SYSSTATUS[ANACPUMPGOOD] Bits */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_OFS (5) /* !< ANACPUMPGOOD Offset */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_MASK ((uint32_t)0x00000020U) /* !< ANACPUMPGOOD is set by hardware + when the VBOOST analog mux charge + pump is ready. */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_FALSE ((uint32_t)0x00000000U) /* !< VBOOST is not ready */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE ((uint32_t)0x00000020U) /* !< VBOOST is ready */ +/* SYSCTL_SYSSTATUS[BORLVL] Bits */ +#define SYSCTL_SYSSTATUS_BORLVL_OFS (4) /* !< BORLVL Offset */ +#define SYSCTL_SYSSTATUS_BORLVL_MASK ((uint32_t)0x00000010U) /* !< BORLVL indicates if a BOR event + occured and the BOR threshold was + switched to BOR0 by hardware. */ +#define SYSCTL_SYSSTATUS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No BOR violation occured */ +#define SYSCTL_SYSSTATUS_BORLVL_TRUE ((uint32_t)0x00000010U) /* !< A BOR violation occured and the BOR + threshold was switched to BOR0 */ +/* SYSCTL_SYSSTATUS[NPUREADY] Bits */ +#define SYSCTL_SYSSTATUS_NPUREADY_OFS (24) /* !< NPUREADY Offset */ +#define SYSCTL_SYSSTATUS_NPUREADY_MASK ((uint32_t)0x01000000U) /* !< NPUREADY indicates when the NPU + peripheral is ready. */ +#define SYSCTL_SYSSTATUS_NPUREADY_FALSE ((uint32_t)0x00000000U) /* !< NPU is not ready */ +#define SYSCTL_SYSSTATUS_NPUREADY_TRUE ((uint32_t)0x01000000U) /* !< NPU is ready */ +/* SYSCTL_SYSSTATUS[FLASHDED] Bits */ +#define SYSCTL_SYSSTATUS_FLASHDED_OFS (0) /* !< FLASHDED Offset */ +#define SYSCTL_SYSSTATUS_FLASHDED_MASK ((uint32_t)0x00000001U) /* !< FLASHDED indicates if a flash ECC + double bit error was detected (DED). */ +#define SYSCTL_SYSSTATUS_FLASHDED_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC double bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHDED_TRUE ((uint32_t)0x00000001U) /* !< Flash ECC double bit error detected */ +/* SYSCTL_SYSSTATUS[FLASHSEC] Bits */ +#define SYSCTL_SYSSTATUS_FLASHSEC_OFS (1) /* !< FLASHSEC Offset */ +#define SYSCTL_SYSSTATUS_FLASHSEC_MASK ((uint32_t)0x00000002U) /* !< FLASHSEC indicates if a flash ECC + single bit error was detected and + corrected (SEC). */ +#define SYSCTL_SYSSTATUS_FLASHSEC_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC single bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHSEC_TRUE ((uint32_t)0x00000002U) /* !< Flash ECC single bit error was + detected and corrected */ +/* SYSCTL_SYSSTATUS[PMUIREFGOOD] Bits */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_OFS (6) /* !< PMUIREFGOOD Offset */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_MASK ((uint32_t)0x00000040U) /* !< PMUIREFGOOD is set by hardware when + the PMU current reference is ready. */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_FALSE ((uint32_t)0x00000000U) /* !< IREF is not ready */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE ((uint32_t)0x00000040U) /* !< IREF is ready */ +/* SYSCTL_SYSSTATUS[REBOOTATTEMPTS] Bits */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_OFS (30) /* !< REBOOTATTEMPTS Offset */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_MASK ((uint32_t)0xC0000000U) /* !< REBOOTATTEMPTS indicates the number + of boot attempts taken before the + user application starts. */ +/* SYSCTL_SYSSTATUS[BORCURTHRESHOLD] Bits */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_OFS (2) /* !< BORCURTHRESHOLD Offset */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_MASK ((uint32_t)0x0000000CU) /* !< BORCURTHRESHOLD indicates the + active brown-out reset supply monitor + configuration. */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1 ((uint32_t)0x00000004U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2 ((uint32_t)0x00000008U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3 ((uint32_t)0x0000000CU) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_DEDERRADDR Bits */ +/* SYSCTL_DEDERRADDR[ADDR] Bits */ +#define SYSCTL_DEDERRADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define SYSCTL_DEDERRADDR_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< Address of MEMORY DED Error. */ + +/* SYSCTL_RSTCAUSE Bits */ +/* SYSCTL_RSTCAUSE[ID] Bits */ +#define SYSCTL_RSTCAUSE_ID_OFS (0) /* !< ID Offset */ +#define SYSCTL_RSTCAUSE_ID_MASK ((uint32_t)0x0000001FU) /* !< ID is a read-to-clear field which + indicates the lowest level reset + cause since the last read. */ +#define SYSCTL_RSTCAUSE_ID_NORST ((uint32_t)0x00000000U) /* !< No reset since last read */ +#define SYSCTL_RSTCAUSE_ID_PORHWFAIL ((uint32_t)0x00000001U) /* !< POR- violation, SHUTDNSTOREx or PMU + trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_POREXNRST ((uint32_t)0x00000002U) /* !< NRST triggered POR (>1s hold) */ +#define SYSCTL_RSTCAUSE_ID_PORSW ((uint32_t)0x00000003U) /* !< Software triggered POR */ +#define SYSCTL_RSTCAUSE_ID_BORSUPPLY ((uint32_t)0x00000004U) /* !< BOR0- violation */ +#define SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN ((uint32_t)0x00000005U) /* !< SHUTDOWN mode exit */ +#define SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY ((uint32_t)0x00000008U) /* !< Non-PMU trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL ((uint32_t)0x00000009U) /* !< Fatal clock failure */ +#define SYSCTL_RSTCAUSE_ID_BOOTEXNRST ((uint32_t)0x0000000CU) /* !< NRST triggered BOOTRST (<1s hold) */ +#define SYSCTL_RSTCAUSE_ID_BOOTSW ((uint32_t)0x0000000DU) /* !< Software triggered BOOTRST */ +#define SYSCTL_RSTCAUSE_ID_BOOTWWDT0 ((uint32_t)0x0000000EU) /* !< WWDT0 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLEXIT ((uint32_t)0x00000010U) /* !< BSL exit */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLENTRY ((uint32_t)0x00000011U) /* !< BSL entry */ +#define SYSCTL_RSTCAUSE_ID_SYSWWDT1 ((uint32_t)0x00000013U) /* !< WWDT1 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSFLASHECC ((uint32_t)0x00000014U) /* !< Flash uncorrectable ECC error */ +#define SYSCTL_RSTCAUSE_ID_SYSCPULOCK ((uint32_t)0x00000015U) /* !< CPULOCK violation */ +#define SYSCTL_RSTCAUSE_ID_SYSDBG ((uint32_t)0x0000001AU) /* !< Debug triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_SYSSW ((uint32_t)0x0000001BU) /* !< Software triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_CPUDBG ((uint32_t)0x0000001CU) /* !< Debug triggered CPURST */ +#define SYSCTL_RSTCAUSE_ID_CPUSW ((uint32_t)0x0000001DU) /* !< Software triggered CPURST */ + +/* SYSCTL_RESETLEVEL Bits */ +/* SYSCTL_RESETLEVEL[LEVEL] Bits */ +#define SYSCTL_RESETLEVEL_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_RESETLEVEL_LEVEL_MASK ((uint32_t)0x00000007U) /* !< LEVEL is used to specify the type + of reset to be issued when RESETCMD + is set to generate a software + triggered reset. */ +#define SYSCTL_RESETLEVEL_LEVEL_CPU ((uint32_t)0x00000000U) /* !< Issue a SYSRST (CPU plus + peripherals only) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOT ((uint32_t)0x00000001U) /* !< Issue a BOOTRST (CPU, peripherals, + and boot configuration routine) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY ((uint32_t)0x00000002U) /* !< Issue a SYSRST and enter the boot + strap loader (BSL) */ +#define SYSCTL_RESETLEVEL_LEVEL_POR ((uint32_t)0x00000003U) /* !< Issue a power-on reset (POR) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT ((uint32_t)0x00000004U) /* !< Issue a SYSRST and exit the boot + strap loader (BSL) */ + +/* SYSCTL_RESETCMD Bits */ +/* SYSCTL_RESETCMD[KEY] Bits */ +#define SYSCTL_RESETCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_RESETCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of E4h (228) must be + written to KEY together with GO to + trigger the reset. */ +#define SYSCTL_RESETCMD_KEY_VALUE ((uint32_t)0xE4000000U) /* !< Issue reset */ +/* SYSCTL_RESETCMD[GO] Bits */ +#define SYSCTL_RESETCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_RESETCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Execute the reset specified in + RESETLEVEL.LEVEL. Must be written + together with the KEY. */ +#define SYSCTL_RESETCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue reset */ + +/* SYSCTL_BORTHRESHOLD Bits */ +/* SYSCTL_BORTHRESHOLD[LEVEL] Bits */ +#define SYSCTL_BORTHRESHOLD_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_BORTHRESHOLD_LEVEL_MASK ((uint32_t)0x00000003U) /* !< LEVEL specifies the desired BOR + threshold and BOR mode. */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1 ((uint32_t)0x00000001U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2 ((uint32_t)0x00000002U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3 ((uint32_t)0x00000003U) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_BORCLRCMD Bits */ +/* SYSCTL_BORCLRCMD[KEY] Bits */ +#define SYSCTL_BORCLRCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_BORCLRCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of C7h (199) must be + written to KEY together with GO to + trigger the clear and BOR threshold + change. */ +#define SYSCTL_BORCLRCMD_KEY_VALUE ((uint32_t)0xC7000000U) /* !< Issue clear */ +/* SYSCTL_BORCLRCMD[GO] Bits */ +#define SYSCTL_BORCLRCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_BORCLRCMD_GO_MASK ((uint32_t)0x00000001U) /* !< GO clears any prior BOR violation + status indications and attempts to + change the active BOR mode to that + specified in the LEVEL field of the + BORTHRESHOLD register. */ +#define SYSCTL_BORCLRCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue clear */ + +/* SYSCTL_SYSOSCFCLCTL Bits */ +/* SYSCTL_SYSOSCFCLCTL[KEY] Bits */ +#define SYSCTL_SYSOSCFCLCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSOSCFCLCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 2Ah (42) must be + written to KEY together with + SETUSEFCL to enable the FCL. */ +#define SYSCTL_SYSOSCFCLCTL_KEY_VALUE ((uint32_t)0x2A000000U) /* !< Issue Command */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEFCL] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_OFS (0) /* !< SETUSEFCL Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEFCL to enable the + frequency correction loop in SYSOSC. + Once enabled, this state is locked + until the next BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEEXRES] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_OFS (1) /* !< SETUSEEXRES Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_MASK ((uint32_t)0x00000002U) /* !< Set SETUSEEXRES to specify that an + external resistor will be used for + the FCL. An appropriate resistor + must be populated on the ROSC pin. + This state is locked until the next + BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE ((uint32_t)0x00000002U) /* !< Enable the SYSOSC external Resistor */ + +/* SYSCTL_LFXTCTL Bits */ +/* SYSCTL_LFXTCTL[KEY] Bits */ +#define SYSCTL_LFXTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_LFXTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 91h (145) must be + written to KEY together with either + STARTLFXT or SETUSELFXT to set the + corresponding bit. */ +#define SYSCTL_LFXTCTL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_LFXTCTL[SETUSELFXT] Bits */ +#define SYSCTL_LFXTCTL_SETUSELFXT_OFS (1) /* !< SETUSELFXT Offset */ +#define SYSCTL_LFXTCTL_SETUSELFXT_MASK ((uint32_t)0x00000002U) /* !< Set SETUSELFXT to switch LFCLK to + LFXT. Once set, SETUSELFXT remains + set until the next BOOTRST. */ +#define SYSCTL_LFXTCTL_SETUSELFXT_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_LFXTCTL_SETUSELFXT_TRUE ((uint32_t)0x00000002U) /* !< Use LFXT as the LFCLK source */ +/* SYSCTL_LFXTCTL[STARTLFXT] Bits */ +#define SYSCTL_LFXTCTL_STARTLFXT_OFS (0) /* !< STARTLFXT Offset */ +#define SYSCTL_LFXTCTL_STARTLFXT_MASK ((uint32_t)0x00000001U) /* !< Set STARTLFXT to start the low + frequency crystal oscillator (LFXT). + Once set, STARTLFXT remains set until + the next BOOTRST. */ +#define SYSCTL_LFXTCTL_STARTLFXT_FALSE ((uint32_t)0x00000000U) /* !< LFXT not started */ +#define SYSCTL_LFXTCTL_STARTLFXT_TRUE ((uint32_t)0x00000001U) /* !< Start LFXT */ + +/* SYSCTL_EXLFCTL Bits */ +/* SYSCTL_EXLFCTL[KEY] Bits */ +#define SYSCTL_EXLFCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXLFCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 36h (54) must be + written to KEY together with + SETUSEEXLF to set SETUSEEXLF. */ +#define SYSCTL_EXLFCTL_KEY_VALUE ((uint32_t)0x36000000U) /* !< Issue command */ +/* SYSCTL_EXLFCTL[SETUSEEXLF] Bits */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_OFS (0) /* !< SETUSEEXLF Offset */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEEXLF to switch LFCLK to + the LFCLK_IN digital clock input. + Once set, SETUSEEXLF remains set + until the next BOOTRST. */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_TRUE ((uint32_t)0x00000001U) /* !< Use LFCLK_IN as the LFCLK source */ + +/* SYSCTL_SHDNIOREL Bits */ +/* SYSCTL_SHDNIOREL[KEY] Bits */ +#define SYSCTL_SHDNIOREL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SHDNIOREL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 91h must be written + to KEY together with RELEASE to set + RELEASE. */ +#define SYSCTL_SHDNIOREL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_SHDNIOREL[RELEASE] Bits */ +#define SYSCTL_SHDNIOREL_RELEASE_OFS (0) /* !< RELEASE Offset */ +#define SYSCTL_SHDNIOREL_RELEASE_MASK ((uint32_t)0x00000001U) /* !< Set RELEASE to release the IO after + a SHUTDOWN mode exit. */ +#define SYSCTL_SHDNIOREL_RELEASE_TRUE ((uint32_t)0x00000001U) /* !< Release IO */ + +/* SYSCTL_EXRSTPIN Bits */ +/* SYSCTL_EXRSTPIN[KEY] Bits */ +#define SYSCTL_EXRSTPIN_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXRSTPIN_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 1Eh must be written + together with DISABLE to disable the + reset function. */ +#define SYSCTL_EXRSTPIN_KEY_VALUE ((uint32_t)0x1E000000U) /* !< Issue command */ +/* SYSCTL_EXRSTPIN[DISABLE] Bits */ +#define SYSCTL_EXRSTPIN_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_EXRSTPIN_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the reset + function of the NRST pin. Once set, + this configuration is locked until + the next POR. */ +#define SYSCTL_EXRSTPIN_DISABLE_FALSE ((uint32_t)0x00000000U) /* !< Reset function of NRST pin is + enabled */ +#define SYSCTL_EXRSTPIN_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Reset function of NRST pin is + disabled */ + +/* SYSCTL_SYSSTATUSCLR Bits */ +/* SYSCTL_SYSSTATUSCLR[KEY] Bits */ +#define SYSCTL_SYSSTATUSCLR_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSSTATUSCLR_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value CEh (206) must be + written to KEY together with ALLECC + to clear the ECC state. */ +#define SYSCTL_SYSSTATUSCLR_KEY_VALUE ((uint32_t)0xCE000000U) /* !< Issue command */ +/* SYSCTL_SYSSTATUSCLR[ALLECC] Bits */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_OFS (0) /* !< ALLECC Offset */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_MASK ((uint32_t)0x00000001U) /* !< Set ALLECC to clear all ECC related + SYSSTATUS indicators. */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR ((uint32_t)0x00000001U) /* !< Clear ECC error state */ + +/* SYSCTL_SWDCFG Bits */ +/* SYSCTL_SWDCFG[KEY] Bits */ +#define SYSCTL_SWDCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SWDCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 62h (98) must be + written to KEY together with DISBALE + to disable the SWD functions. */ +#define SYSCTL_SWDCFG_KEY_VALUE ((uint32_t)0x62000000U) /* !< Issue command */ +/* SYSCTL_SWDCFG[DISABLE] Bits */ +#define SYSCTL_SWDCFG_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_SWDCFG_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the SWD + function on SWD pins, allowing the + SWD pins to be used as GPIO. */ +#define SYSCTL_SWDCFG_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disable SWD function on SWD pins */ + +/* SYSCTL_FCCCMD Bits */ +/* SYSCTL_FCCCMD[KEY] Bits */ +#define SYSCTL_FCCCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FCCCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 0Eh (14) must be + written with GO to start a capture. */ +#define SYSCTL_FCCCMD_KEY_VALUE ((uint32_t)0x0E000000U) /* !< Issue command */ +/* SYSCTL_FCCCMD[GO] Bits */ +#define SYSCTL_FCCCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_FCCCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Set GO to start a capture with the + frequency clock counter (FCC). */ +#define SYSCTL_FCCCMD_GO_TRUE ((uint32_t)0x00000001U) + +/* SYSCTL_USBFLLCTL Bits */ +/* SYSCTL_USBFLLCTL[FLLEN] Bits */ +#define SYSCTL_USBFLLCTL_FLLEN_OFS (1) /* !< FLLEN Offset */ +#define SYSCTL_USBFLLCTL_FLLEN_MASK ((uint32_t)0x00000002U) /* !< USB Oscillator Frequeny Lock Loop + Enable */ +#define SYSCTL_USBFLLCTL_FLLEN_FALSE ((uint32_t)0x00000000U) /* !< USB CLK Frequeny Lock Loop is + disabled */ +#define SYSCTL_USBFLLCTL_FLLEN_TRUE ((uint32_t)0x00000002U) /* !< USB CLK Frequeny Lock Loop is + enabled */ +/* SYSCTL_USBFLLCTL[REFSEL] Bits */ +#define SYSCTL_USBFLLCTL_REFSEL_OFS (8) /* !< REFSEL Offset */ +#define SYSCTL_USBFLLCTL_REFSEL_MASK ((uint32_t)0x00000100U) /* !< Reference Clock Selection for + Frequency Lock Loop */ +#define SYSCTL_USBFLLCTL_REFSEL_LFCLK ((uint32_t)0x00000100U) /* !< Use LFCLK as Reference Clock */ +/* SYSCTL_USBFLLCTL[CLKEN] Bits */ +#define SYSCTL_USBFLLCTL_CLKEN_OFS (0) /* !< CLKEN Offset */ +#define SYSCTL_USBFLLCTL_CLKEN_MASK ((uint32_t)0x00000001U) /* !< USB Oscillator Enable */ +#define SYSCTL_USBFLLCTL_CLKEN_FALSE ((uint32_t)0x00000000U) /* !< USB CLK is disabled */ +#define SYSCTL_USBFLLCTL_CLKEN_TRUE ((uint32_t)0x00000001U) /* !< USB CLK is enabled */ + +/* SYSCTL_USBFLLADJ Bits */ +/* SYSCTL_USBFLLADJ[FRQMOD] Bits */ +#define SYSCTL_USBFLLADJ_FRQMOD_OFS (8) /* !< FRQMOD Offset */ +#define SYSCTL_USBFLLADJ_FRQMOD_MASK ((uint32_t)0x00000700U) /* !< Frequency Lock Loop Modulator Value */ +/* SYSCTL_USBFLLADJ[FRQADJ] Bits */ +#define SYSCTL_USBFLLADJ_FRQADJ_OFS (0) /* !< FRQADJ Offset */ +#define SYSCTL_USBFLLADJ_FRQADJ_MASK ((uint32_t)0x0000003FU) /* !< Frequency Lock Loop Adjust */ + +/* SYSCTL_USBFLLSTAT Bits */ +/* SYSCTL_USBFLLSTAT[FRQMOD] Bits */ +#define SYSCTL_USBFLLSTAT_FRQMOD_OFS (24) /* !< FRQMOD Offset */ +#define SYSCTL_USBFLLSTAT_FRQMOD_MASK ((uint32_t)0x07000000U) /* !< Current Frequency Lock Loop + Modulator Value */ +/* SYSCTL_USBFLLSTAT[REFRDY] Bits */ +#define SYSCTL_USBFLLSTAT_REFRDY_OFS (8) /* !< REFRDY Offset */ +#define SYSCTL_USBFLLSTAT_REFRDY_MASK ((uint32_t)0x00000100U) /* !< Reference Clock for Frequency Lock + Loop ready indication */ +#define SYSCTL_USBFLLSTAT_REFRDY_FALSE ((uint32_t)0x00000000U) /* !< USB FLL Reference clock is not + ready */ +#define SYSCTL_USBFLLSTAT_REFRDY_TRUE ((uint32_t)0x00000100U) /* !< USB FLL Reference clock is ready */ +/* SYSCTL_USBFLLSTAT[FLLLOCK] Bits */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_OFS (1) /* !< FLLLOCK Offset */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_MASK ((uint32_t)0x00000002U) /* !< USB Oscillator Frequeny Lock Loop + Lock Indication */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_FALSE ((uint32_t)0x00000000U) /* !< USB CLK Frequeny Lock Loop is not + locked */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_TRUE ((uint32_t)0x00000002U) /* !< USB CLK Frequeny Lock Loop is + locked */ +/* SYSCTL_USBFLLSTAT[CLKRDY] Bits */ +#define SYSCTL_USBFLLSTAT_CLKRDY_OFS (0) /* !< CLKRDY Offset */ +#define SYSCTL_USBFLLSTAT_CLKRDY_MASK ((uint32_t)0x00000001U) /* !< USB Oscillator Ready Indication */ +#define SYSCTL_USBFLLSTAT_CLKRDY_FALSE ((uint32_t)0x00000000U) /* !< USB CLK is not ready */ +#define SYSCTL_USBFLLSTAT_CLKRDY_TRUE ((uint32_t)0x00000001U) /* !< USB CLK is ready */ +/* SYSCTL_USBFLLSTAT[FRQADJ] Bits */ +#define SYSCTL_USBFLLSTAT_FRQADJ_OFS (16) /* !< FRQADJ Offset */ +#define SYSCTL_USBFLLSTAT_FRQADJ_MASK ((uint32_t)0x003F0000U) /* !< Current Frequency Lock Loop Adjust */ + +/* SYSCTL_SHUTDNSTORE0 Bits */ +/* SYSCTL_SHUTDNSTORE0[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE0_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE0_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 0 */ + +/* SYSCTL_SHUTDNSTORE1 Bits */ +/* SYSCTL_SHUTDNSTORE1[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE1_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE1_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 1 */ + +/* SYSCTL_SHUTDNSTORE2 Bits */ +/* SYSCTL_SHUTDNSTORE2[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE2_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE2_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 2 */ + +/* SYSCTL_SHUTDNSTORE3 Bits */ +/* SYSCTL_SHUTDNSTORE3[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE3_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE3_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 3 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g511x__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g518x.h b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g518x.h new file mode 100644 index 0000000..6de1c99 --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g518x.h @@ -0,0 +1,1966 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g518x__include +#define ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g518x__include + +/* Filename: hw_sysctl_mspm0g518x.h */ +/* Revised: 2024-12-23 19:16:39 */ +/* Revision: 7689f773d1f3e94bdd42e4fda8b3557bbed5f247 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* SYSCTL Registers +******************************************************************************/ +#define SYSCTL_SECCFG_OFS ((uint32_t)0x00003000U) +#define SYSCTL_SOCLOCK_OFS ((uint32_t)0x00001000U) + + +/** @addtogroup SYSCTL_SECCFG + @{ +*/ + +typedef struct { + __IO uint32_t FWEPROTMAIN; /* !< (@ 0x00003000) 1 Sector Write-Erase per bit starting at address + 0x0 of flash */ + uint32_t RESERVED0[4]; + __IO uint32_t FWPROTMAINDATA; /* !< (@ 0x00003014) Read-Write Protection for first 4 Sectors of Data + Bank */ + __IO uint32_t FRXPROTMAINSTART; /* !< (@ 0x00003018) Flash RX Protection Start Address */ + __IO uint32_t FRXPROTMAINEND; /* !< (@ 0x0000301C) Flash RX Protection End Address */ + __IO uint32_t FIPPROTMAINSTART; /* !< (@ 0x00003020) Flash IP Protection Start Address */ + __IO uint32_t FIPPROTMAINEND; /* !< (@ 0x00003024) Flash IP Protection End Address */ + uint32_t RESERVED1[4]; + __O uint32_t FLBANKSWPPOLICY; /* !< (@ 0x00003038) Flash Bank Swap Policy */ + __O uint32_t FLBANKSWP; /* !< (@ 0x0000303C) Flash MAIN bank address swap */ + uint32_t RESERVED2; + __O uint32_t FWENABLE; /* !< (@ 0x00003044) Security Firewall Enable Register */ + __I uint32_t SECSTATUS; /* !< (@ 0x00003048) Security Configuration status */ + uint32_t RESERVED3[5]; + __O uint32_t INITDONE; /* !< (@ 0x00003060) INITCODE PASS */ +} SYSCTL_SECCFG_Regs; + +/*@}*/ /* end of group SYSCTL_SECCFG */ + +/** @addtogroup SYSCTL_SOCLOCK + @{ +*/ + +typedef struct { + uint32_t RESERVED0[8]; + __I uint32_t IIDX; /* !< (@ 0x00001020) SYSCTL interrupt index */ + uint32_t RESERVED1; + __IO uint32_t IMASK; /* !< (@ 0x00001028) SYSCTL interrupt mask */ + uint32_t RESERVED2; + __I uint32_t RIS; /* !< (@ 0x00001030) SYSCTL raw interrupt status */ + uint32_t RESERVED3; + __I uint32_t MIS; /* !< (@ 0x00001038) SYSCTL masked interrupt status */ + uint32_t RESERVED4; + __O uint32_t ISET; /* !< (@ 0x00001040) SYSCTL interrupt set */ + uint32_t RESERVED5; + __O uint32_t ICLR; /* !< (@ 0x00001048) SYSCTL interrupt clear */ + uint32_t RESERVED6; + __I uint32_t NMIIIDX; /* !< (@ 0x00001050) NMI interrupt index */ + uint32_t RESERVED7[3]; + __I uint32_t NMIRIS; /* !< (@ 0x00001060) NMI raw interrupt status */ + uint32_t RESERVED8[3]; + __O uint32_t NMIISET; /* !< (@ 0x00001070) NMI interrupt set */ + uint32_t RESERVED9; + __O uint32_t NMIICLR; /* !< (@ 0x00001078) NMI interrupt clear */ + uint32_t RESERVED10[33]; + __IO uint32_t SYSOSCCFG; /* !< (@ 0x00001100) SYSOSC configuration */ + __IO uint32_t MCLKCFG; /* !< (@ 0x00001104) Main clock (MCLK) configuration */ + __IO uint32_t HSCLKEN; /* !< (@ 0x00001108) High-speed clock (HSCLK) source enable/disable */ + __IO uint32_t HSCLKCFG; /* !< (@ 0x0000110C) High-speed clock (HSCLK) source selection */ + __IO uint32_t HFCLKCLKCFG; /* !< (@ 0x00001110) High-frequency clock (HFCLK) configuration */ + __IO uint32_t LFCLKCFG; /* !< (@ 0x00001114) Low frequency crystal oscillator (LFXT) + configuration */ + uint32_t RESERVED11[2]; + __IO uint32_t SYSPLLCFG0; /* !< (@ 0x00001120) SYSPLL reference and output configuration */ + __IO uint32_t SYSPLLCFG1; /* !< (@ 0x00001124) SYSPLL reference and feedback divider */ + __IO uint32_t SYSPLLPARAM0; /* !< (@ 0x00001128) SYSPLL PARAM0 (load from FACTORY region) */ + __IO uint32_t SYSPLLPARAM1; /* !< (@ 0x0000112C) SYSPLL PARAM1 (load from FACTORY region) */ + uint32_t RESERVED12[2]; + __IO uint32_t GENCLKCFG; /* !< (@ 0x00001138) General clock configuration */ + __IO uint32_t GENCLKEN; /* !< (@ 0x0000113C) General clock enable control */ + __IO uint32_t PMODECFG; /* !< (@ 0x00001140) Power mode configuration */ + uint32_t RESERVED13[3]; + __I uint32_t FCC; /* !< (@ 0x00001150) Frequency clock counter (FCC) count */ + uint32_t RESERVED14[7]; + __IO uint32_t SYSOSCTRIMUSER; /* !< (@ 0x00001170) SYSOSC user-specified trim */ + uint32_t RESERVED15; + __IO uint32_t SRAMBOUNDARY; /* !< (@ 0x00001178) SRAM Write Boundary */ + uint32_t RESERVED16; + __IO uint32_t SYSTEMCFG; /* !< (@ 0x00001180) System configuration */ + uint32_t RESERVED17[31]; + __IO uint32_t WRITELOCK; /* !< (@ 0x00001200) SYSCTL register write lockout */ + __I uint32_t CLKSTATUS; /* !< (@ 0x00001204) Clock module (CKM) status */ + __I uint32_t SYSSTATUS; /* !< (@ 0x00001208) System status information */ + __I uint32_t DEDERRADDR; /* !< (@ 0x0000120C) Memory DED Address */ + uint32_t RESERVED18[4]; + __I uint32_t RSTCAUSE; /* !< (@ 0x00001220) Reset cause */ + uint32_t RESERVED19[55]; + __IO uint32_t RESETLEVEL; /* !< (@ 0x00001300) Reset level for application-triggered reset + command */ + __O uint32_t RESETCMD; /* !< (@ 0x00001304) Execute an application-triggered reset command */ + __IO uint32_t BORTHRESHOLD; /* !< (@ 0x00001308) BOR threshold selection */ + __O uint32_t BORCLRCMD; /* !< (@ 0x0000130C) Set the BOR threshold */ + __O uint32_t SYSOSCFCLCTL; /* !< (@ 0x00001310) SYSOSC frequency correction loop (FCL) ROSC enable */ + __O uint32_t LFXTCTL; /* !< (@ 0x00001314) LFXT and LFCLK control */ + __O uint32_t EXLFCTL; /* !< (@ 0x00001318) LFCLK_IN and LFCLK control */ + __O uint32_t SHDNIOREL; /* !< (@ 0x0000131C) SHUTDOWN IO release control */ + __O uint32_t EXRSTPIN; /* !< (@ 0x00001320) Disable the reset function of the NRST pin */ + __O uint32_t SYSSTATUSCLR; /* !< (@ 0x00001324) Clear sticky bits of SYSSTATUS */ + __O uint32_t SWDCFG; /* !< (@ 0x00001328) Disable the SWD function on the SWD pins */ + __O uint32_t FCCCMD; /* !< (@ 0x0000132C) Frequency clock counter start capture */ + uint32_t RESERVED20[4]; + __IO uint32_t USBFLLCTL; /* !< (@ 0x00001340) USB FLL Control Register */ + __IO uint32_t USBFLLADJ; /* !< (@ 0x00001344) USB FLL Manual Adjustment Register */ + __I uint32_t USBFLLSTAT; /* !< (@ 0x00001348) USB FLL Status Register */ + uint32_t RESERVED21[45]; + __IO uint32_t SHUTDNSTORE0; /* !< (@ 0x00001400) Shutdown storage memory (byte 0) */ + __IO uint32_t SHUTDNSTORE1; /* !< (@ 0x00001404) Shutdown storage memory (byte 1) */ + __IO uint32_t SHUTDNSTORE2; /* !< (@ 0x00001408) Shutdown storage memory (byte 2) */ + __IO uint32_t SHUTDNSTORE3; /* !< (@ 0x0000140C) Shutdown storage memory (byte 3) */ +} SYSCTL_SOCLOCK_Regs; + +/*@}*/ /* end of group SYSCTL_SOCLOCK */ + +/** @addtogroup SYSCTL + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + SYSCTL_SOCLOCK_Regs SOCLOCK; /* !< (@ 0x00001000) SYSCTL SOCLOCK Region */ + uint32_t RESERVED1[1788]; + SYSCTL_SECCFG_Regs SECCFG; /* !< (@ 0x00003000) SYSCTL SECCFG Region */ +} SYSCTL_Regs; + +/*@}*/ /* end of group SYSCTL */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* SYSCTL Register Control Bits +******************************************************************************/ + +/* SYSCTL_FWEPROTMAIN Bits */ +/* SYSCTL_FWEPROTMAIN[DATA] Bits */ +#define SYSCTL_FWEPROTMAIN_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWEPROTMAIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< 1 Sector Write Erase protection 1: + prohibits write-erase, 0: allows */ + +/* SYSCTL_FWPROTMAINDATA Bits */ +/* SYSCTL_FWPROTMAINDATA[DATA] Bits */ +#define SYSCTL_FWPROTMAINDATA_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWPROTMAINDATA_DATA_MASK ((uint32_t)0x000000FFU) /* !< 00: Both RW allowed 01: Read Only + 10: No Read No Write 11: No Read No + Write - Not Used */ + +/* SYSCTL_FRXPROTMAINSTART Bits */ +/* SYSCTL_FRXPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection Start Address + 64B granularity */ + +/* SYSCTL_FRXPROTMAINEND Bits */ +/* SYSCTL_FRXPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection End Address 64B + granularity */ + +/* SYSCTL_FIPPROTMAINSTART Bits */ +/* SYSCTL_FIPPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection Start Address + 64B granularity */ + +/* SYSCTL_FIPPROTMAINEND Bits */ +/* SYSCTL_FIPPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection End Address 64B + granularity */ + +/* SYSCTL_FLBANKSWPPOLICY Bits */ +/* SYSCTL_FLBANKSWPPOLICY[KEY] Bits */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0xCA(202) for write */ +#define SYSCTL_FLBANKSWPPOLICY_KEY_VALUE ((uint32_t)0xCA000000U) /* !< Write Key */ +/* SYSCTL_FLBANKSWPPOLICY[DISABLE] Bits */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_MASK ((uint32_t)0x00000001U) /* !< 1: Disables Policy To Allow Flash + Bank Swapping */ +#define SYSCTL_FLBANKSWPPOLICY_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disallow Bank Swap */ + +/* SYSCTL_FLBANKSWP Bits */ +/* SYSCTL_FLBANKSWP[KEY] Bits */ +#define SYSCTL_FLBANKSWP_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FLBANKSWP_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 58h (88) must be + written with USEUPPER to change the + bank swap configuration. */ +#define SYSCTL_FLBANKSWP_KEY_VALUE ((uint32_t)0x58000000U) /* !< Issue write */ +/* SYSCTL_FLBANKSWP[USEUPPER] Bits */ +#define SYSCTL_FLBANKSWP_USEUPPER_OFS (0) /* !< USEUPPER Offset */ +#define SYSCTL_FLBANKSWP_USEUPPER_MASK ((uint32_t)0x00000001U) /* !< 1: Use Upper Bank as Logical 0 */ +#define SYSCTL_FLBANKSWP_USEUPPER_DISABLE ((uint32_t)0x00000000U) /* !< Normal (default) memory map + addressing scheme */ +#define SYSCTL_FLBANKSWP_USEUPPER_ENABLE ((uint32_t)0x00000001U) /* !< Flash upper region address space + swapped with lower region */ + +/* SYSCTL_FWENABLE Bits */ +/* SYSCTL_FWENABLE[KEY] Bits */ +#define SYSCTL_FWENABLE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FWENABLE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x76(118) for write */ +#define SYSCTL_FWENABLE_KEY_VALUE ((uint32_t)0x76000000U) /* !< Write Key */ +/* SYSCTL_FWENABLE[FLIPPROT] Bits */ +#define SYSCTL_FWENABLE_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_FWENABLE_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash Read IP ProtectionActive */ +#define SYSCTL_FWENABLE_FLIPPROT_ENABLE ((uint32_t)0x00000040U) /* !< Turn On Flash IP Protection */ +/* SYSCTL_FWENABLE[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: Blocks Writes from Changing + SRAMBOUNDARY MMR */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE ((uint32_t)0x00000100U) /* !< SRAMBOUNDARY MMR Locked */ +/* SYSCTL_FWENABLE[FLRXPROT] Bits */ +#define SYSCTL_FWENABLE_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_FWENABLE_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_FWENABLE_FLRXPROT_ENABLE ((uint32_t)0x00000010U) /* !< Turn On Flash Read-eXecute + Protection */ + +/* SYSCTL_SECSTATUS Bits */ +/* SYSCTL_SECSTATUS[FLBANKSWPPOLICY] Bits */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_OFS (10) /* !< FLBANKSWPPOLICY Offset */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_MASK ((uint32_t)0x00000400U) /* !< 1: Upper and Lower Banks allowed to + be swapped */ +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED ((uint32_t)0x00000400U) +/* SYSCTL_SECSTATUS[FLIPPROT] Bits */ +#define SYSCTL_SECSTATUS_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_SECSTATUS_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash IP Protection Active */ +#define SYSCTL_SECSTATUS_FLIPPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLIPPROT_ENABLED ((uint32_t)0x00000040U) +/* SYSCTL_SECSTATUS[FLBANKSWP] Bits */ +#define SYSCTL_SECSTATUS_FLBANKSWP_OFS (12) /* !< FLBANKSWP Offset */ +#define SYSCTL_SECSTATUS_FLBANKSWP_MASK ((uint32_t)0x00001000U) /* !< 1: Upper and Lower Banks have been + swapped */ +/* SYSCTL_SECSTATUS[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: SRAM Boundary MMR Locked */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED ((uint32_t)0x00000100U) +/* SYSCTL_SECSTATUS[FLRXPROT] Bits */ +#define SYSCTL_SECSTATUS_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_SECSTATUS_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_SECSTATUS_FLRXPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLRXPROT_ENABLED ((uint32_t)0x00000010U) +/* SYSCTL_SECSTATUS[INITDONE] Bits */ +#define SYSCTL_SECSTATUS_INITDONE_OFS (0) /* !< INITDONE Offset */ +#define SYSCTL_SECSTATUS_INITDONE_MASK ((uint32_t)0x00000001U) /* !< 1: CSC has been completed */ +#define SYSCTL_SECSTATUS_INITDONE_NO ((uint32_t)0x00000000U) /* !< INIT is not yet done */ +#define SYSCTL_SECSTATUS_INITDONE_YES ((uint32_t)0x00000001U) /* !< INIT is done */ +/* SYSCTL_SECSTATUS[CSCEXISTS] Bits */ +#define SYSCTL_SECSTATUS_CSCEXISTS_OFS (2) /* !< CSCEXISTS Offset */ +#define SYSCTL_SECSTATUS_CSCEXISTS_MASK ((uint32_t)0x00000004U) /* !< 1: CSC Exists in the system */ +#define SYSCTL_SECSTATUS_CSCEXISTS_NO ((uint32_t)0x00000000U) /* !< System does not have a CSC */ +#define SYSCTL_SECSTATUS_CSCEXISTS_YES ((uint32_t)0x00000004U) /* !< System does have a CSC */ + +/* SYSCTL_INITDONE Bits */ +/* SYSCTL_INITDONE[KEY] Bits */ +#define SYSCTL_INITDONE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_INITDONE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x9D(157) for write */ +#define SYSCTL_INITDONE_KEY_VALUE ((uint32_t)0x9D000000U) /* !< Issue Reset */ +/* SYSCTL_INITDONE[PASS] Bits */ +#define SYSCTL_INITDONE_PASS_OFS (0) /* !< PASS Offset */ +#define SYSCTL_INITDONE_PASS_MASK ((uint32_t)0x00000001U) /* !< INITCODE writes 1 for PASS, left + unwritten a timeout will occur if not + blocked */ +#define SYSCTL_INITDONE_PASS_TRUE ((uint32_t)0x00000001U) /* !< INITCODE PASS */ + +/* SYSCTL_IIDX Bits */ +/* SYSCTL_IIDX[STAT] Bits */ +#define SYSCTL_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_IIDX_STAT_MASK ((uint32_t)0x0000000FU) /* !< The SYSCTL interrupt index (IIDX) + register generates a value + corresponding to the highest priority + pending interrupt source. This value + may be used as an address offset for + fast, deterministic handling in the + interrupt service routine. A read of + the IIDX register will clear the + corresponding interrupt status in the + RIS and MIS registers. */ +#define SYSCTL_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_IIDX_STAT_LFOSCGOOD ((uint32_t)0x00000001U) /* !< LFOSCGOOD interrupt pending */ +#define SYSCTL_IIDX_STAT_ANACLKERR ((uint32_t)0x00000002U) +#define SYSCTL_IIDX_STAT_FLASHSEC ((uint32_t)0x00000003U) +#define SYSCTL_IIDX_STAT_SRAMSEC ((uint32_t)0x00000004U) +#define SYSCTL_IIDX_STAT_LFXTGOOD ((uint32_t)0x00000005U) +#define SYSCTL_IIDX_STAT_HFCLKGOOD ((uint32_t)0x00000006U) +#define SYSCTL_IIDX_STAT_SYSPLLGOOD ((uint32_t)0x00000007U) +#define SYSCTL_IIDX_STAT_HSCLKGOOD ((uint32_t)0x00000008U) +#define SYSCTL_IIDX_STAT_USBFLLERR ((uint32_t)0x00000009U) + +/* SYSCTL_IMASK Bits */ +/* SYSCTL_IMASK[LFOSCGOOD] Bits */ +#define SYSCTL_IMASK_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_IMASK_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Enable or disable the LFOSCGOOD + interrupt. LFOSCGOOD indicates that + the LFOSC has started successfully. */ +#define SYSCTL_IMASK_LFOSCGOOD_DISABLE ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define SYSCTL_IMASK_LFOSCGOOD_ENABLE ((uint32_t)0x00000001U) /* !< Interrupt enabled */ +/* SYSCTL_IMASK[HFCLKGOOD] Bits */ +#define SYSCTL_IMASK_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_IMASK_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_IMASK_HFCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HFCLKGOOD_ENABLE ((uint32_t)0x00000020U) +/* SYSCTL_IMASK[SRAMSEC] Bits */ +#define SYSCTL_IMASK_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_IMASK_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_IMASK_SRAMSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_SRAMSEC_ENABLE ((uint32_t)0x00000008U) +/* SYSCTL_IMASK[LFXTGOOD] Bits */ +#define SYSCTL_IMASK_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_IMASK_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_IMASK_LFXTGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_LFXTGOOD_ENABLE ((uint32_t)0x00000010U) +/* SYSCTL_IMASK[HSCLKGOOD] Bits */ +#define SYSCTL_IMASK_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_IMASK_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_IMASK_HSCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HSCLKGOOD_ENABLE ((uint32_t)0x00000080U) +/* SYSCTL_IMASK[SYSPLLGOOD] Bits */ +#define SYSCTL_IMASK_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_IMASK_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_IMASK_SYSPLLGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_SYSPLLGOOD_ENABLE ((uint32_t)0x00000040U) +/* SYSCTL_IMASK[ANACLKERR] Bits */ +#define SYSCTL_IMASK_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_IMASK_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_IMASK_ANACLKERR_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_ANACLKERR_ENABLE ((uint32_t)0x00000002U) +/* SYSCTL_IMASK[FLASHSEC] Bits */ +#define SYSCTL_IMASK_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_IMASK_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_IMASK_FLASHSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_FLASHSEC_ENABLE ((uint32_t)0x00000004U) +/* SYSCTL_IMASK[USBFLLERR] Bits */ +#define SYSCTL_IMASK_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_IMASK_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_IMASK_USBFLLERR_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_USBFLLERR_ENABLE ((uint32_t)0x00000100U) + +/* SYSCTL_RIS Bits */ +/* SYSCTL_RIS[LFOSCGOOD] Bits */ +#define SYSCTL_RIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_RIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Raw status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_RIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_RIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_RIS[HFCLKGOOD] Bits */ +#define SYSCTL_RIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_RIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_RIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_RIS[SRAMSEC] Bits */ +#define SYSCTL_RIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_RIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_RIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_RIS[LFXTGOOD] Bits */ +#define SYSCTL_RIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_RIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_RIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_RIS[HSCLKGOOD] Bits */ +#define SYSCTL_RIS_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_RIS_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_RIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HSCLKGOOD_TRUE ((uint32_t)0x00000080U) +/* SYSCTL_RIS[SYSPLLGOOD] Bits */ +#define SYSCTL_RIS_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_RIS_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_RIS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_SYSPLLGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_RIS[ANACLKERR] Bits */ +#define SYSCTL_RIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_RIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_RIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_RIS[FLASHSEC] Bits */ +#define SYSCTL_RIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_RIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_RIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_RIS[USBFLLERR] Bits */ +#define SYSCTL_RIS_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_RIS_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_RIS_USBFLLERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_USBFLLERR_TRUE ((uint32_t)0x00000100U) + +/* SYSCTL_MIS Bits */ +/* SYSCTL_MIS[LFOSCGOOD] Bits */ +#define SYSCTL_MIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_MIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Masked status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_MIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_MIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_MIS[HFCLKGOOD] Bits */ +#define SYSCTL_MIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_MIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_MIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_MIS[SRAMSEC] Bits */ +#define SYSCTL_MIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_MIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_MIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_MIS[LFXTGOOD] Bits */ +#define SYSCTL_MIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_MIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_MIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_MIS[HSCLKGOOD] Bits */ +#define SYSCTL_MIS_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_MIS_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_MIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HSCLKGOOD_TRUE ((uint32_t)0x00000080U) +/* SYSCTL_MIS[SYSPLLGOOD] Bits */ +#define SYSCTL_MIS_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_MIS_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_MIS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_SYSPLLGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_MIS[ANACLKERR] Bits */ +#define SYSCTL_MIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_MIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_MIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_MIS[FLASHSEC] Bits */ +#define SYSCTL_MIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_MIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_MIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_MIS[USBFLLERR] Bits */ +#define SYSCTL_MIS_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_MIS_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_MIS_USBFLLERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_USBFLLERR_TRUE ((uint32_t)0x00000100U) + +/* SYSCTL_ISET Bits */ +/* SYSCTL_ISET[LFOSCGOOD] Bits */ +#define SYSCTL_ISET_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ISET_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Set the LFOSCGOOD interrupt. */ +#define SYSCTL_ISET_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_ISET_LFOSCGOOD_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_ISET[HFCLKGOOD] Bits */ +#define SYSCTL_ISET_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ISET_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ISET_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HFCLKGOOD_SET ((uint32_t)0x00000020U) +/* SYSCTL_ISET[SRAMSEC] Bits */ +#define SYSCTL_ISET_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ISET_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ISET_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_SRAMSEC_SET ((uint32_t)0x00000008U) +/* SYSCTL_ISET[LFXTGOOD] Bits */ +#define SYSCTL_ISET_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ISET_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ISET_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_LFXTGOOD_SET ((uint32_t)0x00000010U) +/* SYSCTL_ISET[HSCLKGOOD] Bits */ +#define SYSCTL_ISET_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ISET_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_ISET_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HSCLKGOOD_SET ((uint32_t)0x00000080U) +/* SYSCTL_ISET[SYSPLLGOOD] Bits */ +#define SYSCTL_ISET_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_ISET_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_ISET_SYSPLLGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_SYSPLLGOOD_SET ((uint32_t)0x00000040U) +/* SYSCTL_ISET[ANACLKERR] Bits */ +#define SYSCTL_ISET_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ISET_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ISET_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_ANACLKERR_SET ((uint32_t)0x00000002U) +/* SYSCTL_ISET[FLASHSEC] Bits */ +#define SYSCTL_ISET_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ISET_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ISET_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_FLASHSEC_SET ((uint32_t)0x00000004U) +/* SYSCTL_ISET[USBFLLERR] Bits */ +#define SYSCTL_ISET_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_ISET_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_ISET_USBFLLERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_USBFLLERR_SET ((uint32_t)0x00000100U) + +/* SYSCTL_ICLR Bits */ +/* SYSCTL_ICLR[LFOSCGOOD] Bits */ +#define SYSCTL_ICLR_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ICLR_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Clear the LFOSCGOOD interrupt. */ +#define SYSCTL_ICLR_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h has no effect */ +#define SYSCTL_ICLR_LFOSCGOOD_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_ICLR[HFCLKGOOD] Bits */ +#define SYSCTL_ICLR_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ICLR_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ICLR_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HFCLKGOOD_CLR ((uint32_t)0x00000020U) +/* SYSCTL_ICLR[SRAMSEC] Bits */ +#define SYSCTL_ICLR_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ICLR_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ICLR_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_SRAMSEC_CLR ((uint32_t)0x00000008U) +/* SYSCTL_ICLR[LFXTGOOD] Bits */ +#define SYSCTL_ICLR_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ICLR_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ICLR_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_LFXTGOOD_CLR ((uint32_t)0x00000010U) +/* SYSCTL_ICLR[HSCLKGOOD] Bits */ +#define SYSCTL_ICLR_HSCLKGOOD_OFS (7) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ICLR_HSCLKGOOD_MASK ((uint32_t)0x00000080U) /* !< HSCLK GOOD */ +#define SYSCTL_ICLR_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HSCLKGOOD_CLR ((uint32_t)0x00000080U) +/* SYSCTL_ICLR[SYSPLLGOOD] Bits */ +#define SYSCTL_ICLR_SYSPLLGOOD_OFS (6) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_ICLR_SYSPLLGOOD_MASK ((uint32_t)0x00000040U) /* !< SYSPLL GOOD */ +#define SYSCTL_ICLR_SYSPLLGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_SYSPLLGOOD_CLR ((uint32_t)0x00000040U) +/* SYSCTL_ICLR[ANACLKERR] Bits */ +#define SYSCTL_ICLR_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ICLR_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ICLR_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_ANACLKERR_CLR ((uint32_t)0x00000002U) +/* SYSCTL_ICLR[FLASHSEC] Bits */ +#define SYSCTL_ICLR_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ICLR_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ICLR_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_FLASHSEC_CLR ((uint32_t)0x00000004U) +/* SYSCTL_ICLR[USBFLLERR] Bits */ +#define SYSCTL_ICLR_USBFLLERR_OFS (8) /* !< USBFLLERR Offset */ +#define SYSCTL_ICLR_USBFLLERR_MASK ((uint32_t)0x00000100U) /* !< USB FLL Reference Clock Error */ +#define SYSCTL_ICLR_USBFLLERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_USBFLLERR_CLR ((uint32_t)0x00000100U) + +/* SYSCTL_NMIIIDX Bits */ +/* SYSCTL_NMIIIDX[STAT] Bits */ +#define SYSCTL_NMIIIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_NMIIIDX_STAT_MASK ((uint32_t)0x0000000FU) /* !< The NMI interrupt index (NMIIIDX) + register generates a value + corresponding to the highest priority + pending NMI source. This value may + be used as an address offset for + fast, deterministic handling in the + NMI service routine. A read of the + NMIIIDX register will clear the + corresponding interrupt status in the + NMIRIS register. */ +#define SYSCTL_NMIIIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No NMI pending */ +#define SYSCTL_NMIIIDX_STAT_BORLVL ((uint32_t)0x00000001U) /* !< BOR Threshold NMI pending */ +#define SYSCTL_NMIIIDX_STAT_WWDT0 ((uint32_t)0x00000002U) +#define SYSCTL_NMIIIDX_STAT_WWDT1 ((uint32_t)0x00000003U) +#define SYSCTL_NMIIIDX_STAT_LFCLKFAIL ((uint32_t)0x00000004U) +#define SYSCTL_NMIIIDX_STAT_FLASHDED ((uint32_t)0x00000005U) +#define SYSCTL_NMIIIDX_STAT_SRAMDED ((uint32_t)0x00000006U) + +/* SYSCTL_NMIRIS Bits */ +/* SYSCTL_NMIRIS[WWDT1] Bits */ +#define SYSCTL_NMIRIS_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIRIS_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT1_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT1_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_NMIRIS[SRAMDED] Bits */ +#define SYSCTL_NMIRIS_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIRIS_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIRIS_SRAMDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_SRAMDED_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_NMIRIS[BORLVL] Bits */ +#define SYSCTL_NMIRIS_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIRIS_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Raw status of the BORLVL NMI */ +#define SYSCTL_NMIRIS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_NMIRIS_BORLVL_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_NMIRIS[FLASHDED] Bits */ +#define SYSCTL_NMIRIS_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIRIS_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIRIS_FLASHDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_FLASHDED_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_NMIRIS[WWDT0] Bits */ +#define SYSCTL_NMIRIS_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIRIS_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT0_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT0_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_NMIRIS[LFCLKFAIL] Bits */ +#define SYSCTL_NMIRIS_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIRIS_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIRIS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_LFCLKFAIL_TRUE ((uint32_t)0x00000008U) + +/* SYSCTL_NMIISET Bits */ +/* SYSCTL_NMIISET[WWDT1] Bits */ +#define SYSCTL_NMIISET_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIISET_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT1_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT1_SET ((uint32_t)0x00000004U) +/* SYSCTL_NMIISET[SRAMDED] Bits */ +#define SYSCTL_NMIISET_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIISET_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIISET_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_SRAMDED_SET ((uint32_t)0x00000020U) +/* SYSCTL_NMIISET[BORLVL] Bits */ +#define SYSCTL_NMIISET_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIISET_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Set the BORLVL NMI */ +#define SYSCTL_NMIISET_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIISET_BORLVL_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_NMIISET[FLASHDED] Bits */ +#define SYSCTL_NMIISET_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIISET_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIISET_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_FLASHDED_SET ((uint32_t)0x00000010U) +/* SYSCTL_NMIISET[WWDT0] Bits */ +#define SYSCTL_NMIISET_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIISET_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT0_SET ((uint32_t)0x00000002U) +/* SYSCTL_NMIISET[LFCLKFAIL] Bits */ +#define SYSCTL_NMIISET_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIISET_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIISET_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_LFCLKFAIL_SET ((uint32_t)0x00000008U) + +/* SYSCTL_NMIICLR Bits */ +/* SYSCTL_NMIICLR[WWDT1] Bits */ +#define SYSCTL_NMIICLR_WWDT1_OFS (2) /* !< WWDT1 Offset */ +#define SYSCTL_NMIICLR_WWDT1_MASK ((uint32_t)0x00000004U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT1_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT1_CLR ((uint32_t)0x00000004U) +/* SYSCTL_NMIICLR[SRAMDED] Bits */ +#define SYSCTL_NMIICLR_SRAMDED_OFS (5) /* !< SRAMDED Offset */ +#define SYSCTL_NMIICLR_SRAMDED_MASK ((uint32_t)0x00000020U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIICLR_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_SRAMDED_CLR ((uint32_t)0x00000020U) +/* SYSCTL_NMIICLR[BORLVL] Bits */ +#define SYSCTL_NMIICLR_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIICLR_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Clr the BORLVL NMI */ +#define SYSCTL_NMIICLR_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIICLR_BORLVL_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_NMIICLR[FLASHDED] Bits */ +#define SYSCTL_NMIICLR_FLASHDED_OFS (4) /* !< FLASHDED Offset */ +#define SYSCTL_NMIICLR_FLASHDED_MASK ((uint32_t)0x00000010U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIICLR_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_FLASHDED_CLR ((uint32_t)0x00000010U) +/* SYSCTL_NMIICLR[WWDT0] Bits */ +#define SYSCTL_NMIICLR_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIICLR_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT0_CLR ((uint32_t)0x00000002U) +/* SYSCTL_NMIICLR[LFCLKFAIL] Bits */ +#define SYSCTL_NMIICLR_LFCLKFAIL_OFS (3) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIICLR_LFCLKFAIL_MASK ((uint32_t)0x00000008U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIICLR_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_LFCLKFAIL_CLR ((uint32_t)0x00000008U) + +/* SYSCTL_SYSOSCCFG Bits */ +/* SYSCTL_SYSOSCCFG[USE4MHZSTOP] Bits */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_OFS (8) /* !< USE4MHZSTOP Offset */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK ((uint32_t)0x00000100U) /* !< USE4MHZSTOP sets the SYSOSC stop + mode frequency policy. When entering + STOP mode, the SYSOSC frequency may + be automatically switched to 4MHz to + reduce SYSOSC power consumption. */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not gear shift the SYSOSC to + 4MHz in STOP mode */ +#define SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE ((uint32_t)0x00000100U) /* !< Gear shift SYSOSC to 4MHz in STOP + mode */ +/* SYSCTL_SYSOSCCFG[DISABLESTOP] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_OFS (9) /* !< DISABLESTOP Offset */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_MASK ((uint32_t)0x00000200U) /* !< DISABLESTOP sets the SYSOSC stop + mode enable/disable policy. When + operating in STOP mode, the SYSOSC + may be automatically disabled. When + set, ULPCLK will run from LFCLK in + STOP mode and SYSOSC will be disabled + to reduce power consumption. */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC in STOP mode */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE ((uint32_t)0x00000200U) /* !< Disable SYSOSC in STOP mode and + source ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[BLOCKASYNCALL] Bits */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_OFS (16) /* !< BLOCKASYNCALL Offset */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_MASK ((uint32_t)0x00010000U) /* !< BLOCKASYNCALL may be used to mask + block all asynchronous fast clock + requests, preventing hardware from + dynamically changing the active clock + configuration when operating in a + given mode. */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_DISABLE ((uint32_t)0x00000000U) /* !< Asynchronous fast clock requests + are controlled by the requesting + peripheral */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE ((uint32_t)0x00010000U) /* !< All asynchronous fast clock + requests are blocked */ +/* SYSCTL_SYSOSCCFG[DISABLE] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLE_OFS (10) /* !< DISABLE Offset */ +#define SYSCTL_SYSOSCCFG_DISABLE_MASK ((uint32_t)0x00000400U) /* !< DISABLE sets the SYSOSC + enable/disable policy. SYSOSC may be + powered off in RUN, SLEEP, and STOP + modes to reduce power consumption. + When SYSOSC is disabled, MCLK and + ULPCLK are sourced from LFCLK. */ +#define SYSCTL_SYSOSCCFG_DISABLE_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC */ +#define SYSCTL_SYSOSCCFG_DISABLE_ENABLE ((uint32_t)0x00000400U) /* !< Disable SYSOSC immediately and + source MCLK and ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[FASTCPUEVENT] Bits */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_OFS (17) /* !< FASTCPUEVENT Offset */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_MASK ((uint32_t)0x00020000U) /* !< FASTCPUEVENT may be used to assert + a fast clock request when an + interrupt is asserted to the CPU, + reducing interrupt latency. */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_DISABLE ((uint32_t)0x00000000U) /* !< An interrupt to the CPU will not + assert a fast clock request */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE ((uint32_t)0x00020000U) /* !< An interrupt to the CPU will assert + a fast clock request */ +/* SYSCTL_SYSOSCCFG[FREQ] Bits */ +#define SYSCTL_SYSOSCCFG_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCCFG_FREQ_MASK ((uint32_t)0x00000003U) /* !< Target operating frequency for the + system oscillator (SYSOSC) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE ((uint32_t)0x00000000U) /* !< Base frequency (32MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< Low frequency (4MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< User-trimmed frequency (16 or 24 + MHz) */ + +/* SYSCTL_MCLKCFG Bits */ +/* SYSCTL_MCLKCFG[USEMFTICK] Bits */ +#define SYSCTL_MCLKCFG_USEMFTICK_OFS (12) /* !< USEMFTICK Offset */ +#define SYSCTL_MCLKCFG_USEMFTICK_MASK ((uint32_t)0x00001000U) /* !< USEMFTICK specifies whether the + 4MHz constant-rate clock (MFCLK) to + peripherals is enabled or disabled. + When enabled, MDIV must be disabled + (set to 0h=/1). */ +#define SYSCTL_MCLKCFG_USEMFTICK_DISABLE ((uint32_t)0x00000000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled */ +#define SYSCTL_MCLKCFG_USEMFTICK_ENABLE ((uint32_t)0x00001000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled. */ +/* SYSCTL_MCLKCFG[MDIV] Bits */ +#define SYSCTL_MCLKCFG_MDIV_OFS (0) /* !< MDIV Offset */ +#define SYSCTL_MCLKCFG_MDIV_MASK ((uint32_t)0x0000000FU) /* !< MDIV may be used to divide the MCLK + frequency when MCLK is sourced from + SYSOSC. MDIV=0h corresponds to /1 + (no divider). MDIV=1h corresponds to + /2 (divide-by-2). MDIV=Fh + corresponds to /16 (divide-by-16). + MDIV may be set between /1 and /16 on + an integer basis. */ +/* SYSCTL_MCLKCFG[USEHSCLK] Bits */ +#define SYSCTL_MCLKCFG_USEHSCLK_OFS (16) /* !< USEHSCLK Offset */ +#define SYSCTL_MCLKCFG_USEHSCLK_MASK ((uint32_t)0x00010000U) /* !< USEHSCLK, together with USELFCLK, + sets the MCLK source policy. Set + USEHSCLK to use HSCLK (HFCLK or + SYSPLL) as the MCLK source in RUN and + SLEEP modes. */ +#define SYSCTL_MCLKCFG_USEHSCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the high speed + clock (HSCLK) */ +#define SYSCTL_MCLKCFG_USEHSCLK_ENABLE ((uint32_t)0x00010000U) /* !< MCLK will use the high speed clock + (HSCLK) in RUN and SLEEP mode */ +/* SYSCTL_MCLKCFG[USELFCLK] Bits */ +#define SYSCTL_MCLKCFG_USELFCLK_OFS (20) /* !< USELFCLK Offset */ +#define SYSCTL_MCLKCFG_USELFCLK_MASK ((uint32_t)0x00100000U) /* !< USELFCLK sets the MCLK source + policy. Set USELFCLK to use LFCLK as + the MCLK source. Note that setting + USELFCLK does not disable SYSOSC, and + SYSOSC remains available for direct + use by analog modules. */ +#define SYSCTL_MCLKCFG_USELFCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the low frequency + clock (LFCLK) */ +#define SYSCTL_MCLKCFG_USELFCLK_ENABLE ((uint32_t)0x00100000U) /* !< MCLK will use the low frequency + clock (LFCLK) */ +/* SYSCTL_MCLKCFG[STOPCLKSTBY] Bits */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_OFS (21) /* !< STOPCLKSTBY Offset */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_MASK ((uint32_t)0x00200000U) /* !< STOPCLKSTBY sets the STANDBY mode + policy (STANDBY0 or STANDBY1). When + set, ULPCLK and LFCLK are disabled to + all peripherals in STANDBY mode, with + the exception of TIMG0 and TIMG1 + which continue to run. Wake-up is + only possible via an asynchronous + fast clock request. */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_DISABLE ((uint32_t)0x00000000U) /* !< ULPCLK/LFCLK runs to all PD0 + peripherals in STANDBY mode */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE ((uint32_t)0x00200000U) /* !< ULPCLK/LFCLK is disabled to all + peripherals in STANDBY mode except + TIMG0 and TIMG1 */ +/* SYSCTL_MCLKCFG[FLASHWAIT] Bits */ +#define SYSCTL_MCLKCFG_FLASHWAIT_OFS (8) /* !< FLASHWAIT Offset */ +#define SYSCTL_MCLKCFG_FLASHWAIT_MASK ((uint32_t)0x00000F00U) /* !< FLASHWAIT specifies the number of + flash wait states when MCLK is + sourced from HSCLK. FLASHWAIT has no + effect when MCLK is sourced from + SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT0 ((uint32_t)0x00000000U) /* !< No flash wait states are applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT1 ((uint32_t)0x00000100U) /* !< One flash wait state is applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT2 ((uint32_t)0x00000200U) /* !< 2 flash wait states are applied */ +/* SYSCTL_MCLKCFG[MCLKDEADCHK] Bits */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_OFS (22) /* !< MCLKDEADCHK Offset */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_MASK ((uint32_t)0x00400000U) /* !< MCLKDEADCHK enables or disables the + continuous MCLK dead check monitor. + LFCLK must be running before + MCLKDEADCHK is enabled. */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_DISABLE ((uint32_t)0x00000000U) /* !< The MCLK dead check monitor is + disabled */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_ENABLE ((uint32_t)0x00400000U) /* !< The MCLK dead check monitor is + enabled */ +/* SYSCTL_MCLKCFG[UDIV] Bits */ +#define SYSCTL_MCLKCFG_UDIV_OFS (4) /* !< UDIV Offset */ +#define SYSCTL_MCLKCFG_UDIV_MASK ((uint32_t)0x00000030U) /* !< UDIV specifies the ULPCLK divider + when MCLK is sourced from HSCLK. + UDIV has no effect when MCLK is + sourced from SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_UDIV_NODIVIDE ((uint32_t)0x00000000U) /* !< ULPCLK is not divided and is equal + to MCLK */ +#define SYSCTL_MCLKCFG_UDIV_DIVIDE2 ((uint32_t)0x00000010U) /* !< ULPCLK is MCLK/2 (divided-by-2) */ + +/* SYSCTL_HSCLKEN Bits */ +/* SYSCTL_HSCLKEN[HFXTEN] Bits */ +#define SYSCTL_HSCLKEN_HFXTEN_OFS (0) /* !< HFXTEN Offset */ +#define SYSCTL_HSCLKEN_HFXTEN_MASK ((uint32_t)0x00000001U) /* !< HFXTEN enables or disables the high + frequency crystal oscillator (HFXT). */ +#define SYSCTL_HSCLKEN_HFXTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the HFXT */ +#define SYSCTL_HSCLKEN_HFXTEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable the HFXT */ +/* SYSCTL_HSCLKEN[USEEXTHFCLK] Bits */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_OFS (16) /* !< USEEXTHFCLK Offset */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_MASK ((uint32_t)0x00010000U) /* !< USEEXTHFCLK selects the HFCLK_IN + digital clock input to be the source + for HFCLK. When disabled, HFXT is + the HFCLK source and HFXTEN may be + set. Do not set HFXTEN and + USEEXTHFCLK simultaneously. */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_DISABLE ((uint32_t)0x00000000U) /* !< Use HFXT as the HFCLK source */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE ((uint32_t)0x00010000U) /* !< Use the HFCLK_IN digital clock + input as the HFCLK source */ +/* SYSCTL_HSCLKEN[SYSPLLEN] Bits */ +#define SYSCTL_HSCLKEN_SYSPLLEN_OFS (8) /* !< SYSPLLEN Offset */ +#define SYSCTL_HSCLKEN_SYSPLLEN_MASK ((uint32_t)0x00000100U) /* !< SYSPLLEN enables or disables the + system phase-lock loop (SYSPLL). */ +#define SYSCTL_HSCLKEN_SYSPLLEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the SYSPLL */ +#define SYSCTL_HSCLKEN_SYSPLLEN_ENABLE ((uint32_t)0x00000100U) /* !< Enable the SYSPLL */ + +/* SYSCTL_HSCLKCFG Bits */ +/* SYSCTL_HSCLKCFG[USBFLL4HSCLK] Bits */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_OFS (1) /* !< USBFLL4HSCLK Offset */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_MASK ((uint32_t)0x00000002U) /* !< USBFLL4HSCLK selects the USBFLL as + High Speed clock source */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_SYSPLL_HFCLK ((uint32_t)0x00000000U) /* !< HSCLK is sourced from the + HSCLKCFG.HSCLKSEL */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_USBFLL ((uint32_t)0x00000002U) /* !< HSCLK is sourced from the USBFLL */ +/* SYSCTL_HSCLKCFG[HSCLKSEL] Bits */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_OFS (0) /* !< HSCLKSEL Offset */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_MASK ((uint32_t)0x00000001U) /* !< HSCLKSEL selects the HSCLK source + (SYSPLL or HFCLK). */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is sourced from the SYSPLL */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK ((uint32_t)0x00000001U) /* !< HSCLK is sourced from the HFCLK */ + +/* SYSCTL_HFCLKCLKCFG Bits */ +/* SYSCTL_HFCLKCLKCFG[HFXTTIME] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_OFS (0) /* !< HFXTTIME Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK ((uint32_t)0x000000FFU) /* !< HFXTTIME specifies the HFXT startup + time in 64us resolution. If the + HFCLK startup monitor is enabled + (HFCLKFLTCHK), HFXT will be checked + after this time expires. */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MINSTARTTIME ((uint32_t)0x00000000U) /* !< Minimum startup time (approximatly + zero) */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MAXSTARTTIME ((uint32_t)0x000000FFU) /* !< Maximum startup time (approximatly + 16.32ms) */ +/* SYSCTL_HFCLKCLKCFG[HFCLKFLTCHK] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_OFS (28) /* !< HFCLKFLTCHK Offset */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK ((uint32_t)0x10000000U) /* !< HFCLKFLTCHK enables or disables the + HFCLK startup monitor. */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_DISABLE ((uint32_t)0x00000000U) /* !< HFCLK startup is not checked */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE ((uint32_t)0x10000000U) /* !< HFCLK startup is checked */ +/* SYSCTL_HFCLKCLKCFG[HFXTRSEL] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS (12) /* !< HFXTRSEL Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK ((uint32_t)0x00003000U) /* !< HFXT Range Select */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8 ((uint32_t)0x00000000U) /* !< 4MHz <= HFXT frequency <= 8MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16 ((uint32_t)0x00001000U) /* !< 8MHz < HFXT frequency <= 16MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32 ((uint32_t)0x00002000U) /* !< 16MHz < HFXT frequency <= 32MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48 ((uint32_t)0x00003000U) /* !< 32MHz < HFXT frequency <= 48MHz */ + +/* SYSCTL_LFCLKCFG Bits */ +/* SYSCTL_LFCLKCFG[XT1DRIVE] Bits */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_OFS (0) /* !< XT1DRIVE Offset */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_MASK ((uint32_t)0x00000003U) /* !< XT1DRIVE selects the low frequency + crystal oscillator (LFXT) drive + strength. */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV ((uint32_t)0x00000000U) /* !< Lowest drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV ((uint32_t)0x00000001U) /* !< Lower drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV ((uint32_t)0x00000002U) /* !< Higher drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV ((uint32_t)0x00000003U) /* !< Highest drive and current */ +/* SYSCTL_LFCLKCFG[MONITOR] Bits */ +#define SYSCTL_LFCLKCFG_MONITOR_OFS (4) /* !< MONITOR Offset */ +#define SYSCTL_LFCLKCFG_MONITOR_MASK ((uint32_t)0x00000010U) /* !< MONITOR enables or disables the + LFCLK monitor, which continuously + checks LFXT or LFCLK_IN for a clock + stuck fault. */ +#define SYSCTL_LFCLKCFG_MONITOR_DISABLE ((uint32_t)0x00000000U) /* !< Clock monitor is disabled */ +#define SYSCTL_LFCLKCFG_MONITOR_ENABLE ((uint32_t)0x00000010U) /* !< Clock monitor is enabled */ +/* SYSCTL_LFCLKCFG[LOWCAP] Bits */ +#define SYSCTL_LFCLKCFG_LOWCAP_OFS (8) /* !< LOWCAP Offset */ +#define SYSCTL_LFCLKCFG_LOWCAP_MASK ((uint32_t)0x00000100U) /* !< LOWCAP controls the low-power LFXT + mode. When the LFXT load capacitance + is less than 3pf, LOWCAP may be set + for reduced power consumption. */ +#define SYSCTL_LFCLKCFG_LOWCAP_DISABLE ((uint32_t)0x00000000U) /* !< LFXT low capacitance mode is + disabled */ +#define SYSCTL_LFCLKCFG_LOWCAP_ENABLE ((uint32_t)0x00000100U) /* !< LFXT low capacitance mode is + enabled */ + +/* SYSCTL_SYSPLLCFG0 Bits */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK0] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_OFS (4) /* !< ENABLECLK0 Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK ((uint32_t)0x00000010U) /* !< ENABLECLK0 enables or disables the + SYSPLLCLK0 output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK0 is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK0_ENABLE ((uint32_t)0x00000010U) /* !< SYSPLLCLK0 is enabled */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK1] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_OFS (5) /* !< ENABLECLK1 Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK ((uint32_t)0x00000020U) /* !< ENABLECLK1 enables or disables the + SYSPLLCLK1 output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK1_ENABLE ((uint32_t)0x00000020U) /* !< SYSPLLCLK1 is enabled */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK1] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS (12) /* !< RDIVCLK1 Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK ((uint32_t)0x0000F000U) /* !< RDIVCLK1 sets the final divider for + the SYSPLLCLK1 output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV2 ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV4 ((uint32_t)0x00001000U) /* !< SYSPLLCLK1 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV6 ((uint32_t)0x00002000U) /* !< SYSPLLCLK1 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV8 ((uint32_t)0x00003000U) /* !< SYSPLLCLK1 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV10 ((uint32_t)0x00004000U) /* !< SYSPLLCLK1 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV12 ((uint32_t)0x00005000U) /* !< SYSPLLCLK1 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV14 ((uint32_t)0x00006000U) /* !< SYSPLLCLK1 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV16 ((uint32_t)0x00007000U) /* !< SYSPLLCLK1 is divided by 16 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV18 ((uint32_t)0x00008000U) /* !< SYSPLLCLK1 is divided by 18 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV20 ((uint32_t)0x00009000U) /* !< SYSPLLCLK1 is divided by 20 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV22 ((uint32_t)0x0000A000U) /* !< SYSPLLCLK1 is divided by 22 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV24 ((uint32_t)0x0000B000U) /* !< SYSPLLCLK1 is divided by 24 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV26 ((uint32_t)0x0000C000U) /* !< SYSPLLCLK1 is divided by 26 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV28 ((uint32_t)0x0000D000U) /* !< SYSPLLCLK1 is divided by 28 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV30 ((uint32_t)0x0000E000U) /* !< SYSPLLCLK1 is divided by 30 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK1_CLK1DIV32 ((uint32_t)0x0000F000U) /* !< SYSPLLCLK1 is divided by 32 */ +/* SYSCTL_SYSPLLCFG0[MCLK2XVCO] Bits */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_OFS (1) /* !< MCLK2XVCO Offset */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK ((uint32_t)0x00000002U) /* !< MCLK2XVCO selects the SYSPLL output + which is sent to the HSCLK mux for + use by MCLK. */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_DISABLE ((uint32_t)0x00000000U) /* !< The SYSPLLCLK0 output is sent to + the HSCLK mux */ +#define SYSCTL_SYSPLLCFG0_MCLK2XVCO_ENABLE ((uint32_t)0x00000002U) /* !< The SYSPLLCLK2X output is sent to + the HSCLK mux */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK2X] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS (16) /* !< RDIVCLK2X Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK ((uint32_t)0x000F0000U) /* !< RDIVCLK2X sets the final divider + for the SYSPLLCLK2X output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV1 ((uint32_t)0x00000000U) /* !< SYSPLLCLK1 is divided by 1 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV2 ((uint32_t)0x00010000U) /* !< SYSPLLCLK1 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV3 ((uint32_t)0x00020000U) /* !< SYSPLLCLK1 is divided by 3 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV4 ((uint32_t)0x00030000U) /* !< SYSPLLCLK1 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV5 ((uint32_t)0x00040000U) /* !< SYSPLLCLK1 is divided by 5 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV6 ((uint32_t)0x00050000U) /* !< SYSPLLCLK1 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV7 ((uint32_t)0x00060000U) /* !< SYSPLLCLK1 is divided by 7 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV8 ((uint32_t)0x00070000U) /* !< SYSPLLCLK1 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV9 ((uint32_t)0x00080000U) /* !< SYSPLLCLK1 is divided by 9 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV10 ((uint32_t)0x00090000U) /* !< SYSPLLCLK1 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV11 ((uint32_t)0x000A0000U) /* !< SYSPLLCLK1 is divided by 11 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV12 ((uint32_t)0x000B0000U) /* !< SYSPLLCLK1 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV13 ((uint32_t)0x000C0000U) /* !< SYSPLLCLK1 is divided by 13 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV14 ((uint32_t)0x000D0000U) /* !< SYSPLLCLK1 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV15 ((uint32_t)0x000E0000U) /* !< SYSPLLCLK1 is divided by 15 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK2X_CLK2XDIV16 ((uint32_t)0x000F0000U) /* !< SYSPLLCLK1 is divided by 16 */ +/* SYSCTL_SYSPLLCFG0[RDIVCLK0] Bits */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS (8) /* !< RDIVCLK0 Offset */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK ((uint32_t)0x00000F00U) /* !< RDIVCLK0 sets the final divider for + the SYSPLLCLK0 output. */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV2 ((uint32_t)0x00000000U) /* !< SYSPLLCLK0 is divided by 2 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV4 ((uint32_t)0x00000100U) /* !< SYSPLLCLK0 is divided by 4 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV6 ((uint32_t)0x00000200U) /* !< SYSPLLCLK0 is divided by 6 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV8 ((uint32_t)0x00000300U) /* !< SYSPLLCLK0 is divided by 8 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV10 ((uint32_t)0x00000400U) /* !< SYSPLLCLK0 is divided by 10 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV12 ((uint32_t)0x00000500U) /* !< SYSPLLCLK0 is divided by 12 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV14 ((uint32_t)0x00000600U) /* !< SYSPLLCLK0 is divided by 14 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV16 ((uint32_t)0x00000700U) /* !< SYSPLLCLK0 is divided by 16 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV18 ((uint32_t)0x00000800U) /* !< SYSPLLCLK0 is divided by 18 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV20 ((uint32_t)0x00000900U) /* !< SYSPLLCLK0 is divided by 20 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV22 ((uint32_t)0x00000A00U) /* !< SYSPLLCLK0 is divided by 22 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV24 ((uint32_t)0x00000B00U) /* !< SYSPLLCLK0 is divided by 24 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV26 ((uint32_t)0x00000C00U) /* !< SYSPLLCLK0 is divided by 26 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV28 ((uint32_t)0x00000D00U) /* !< SYSPLLCLK0 is divided by 28 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV30 ((uint32_t)0x00000E00U) /* !< SYSPLLCLK0 is divided by 30 */ +#define SYSCTL_SYSPLLCFG0_RDIVCLK0_CLK0DIV32 ((uint32_t)0x00000F00U) /* !< SYSPLLCLK0 is divided by 32 */ +/* SYSCTL_SYSPLLCFG0[SYSPLLREF] Bits */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_OFS (0) /* !< SYSPLLREF Offset */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK ((uint32_t)0x00000001U) /* !< SYSPLLREF selects the system PLL + (SYSPLL) reference clock source. */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_SYSOSC ((uint32_t)0x00000000U) /* !< SYSPLL reference is SYSOSC */ +#define SYSCTL_SYSPLLCFG0_SYSPLLREF_HFCLK ((uint32_t)0x00000001U) /* !< SYSPLL reference is HFCLK */ +/* SYSCTL_SYSPLLCFG0[ENABLECLK2X] Bits */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_OFS (6) /* !< ENABLECLK2X Offset */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK ((uint32_t)0x00000040U) /* !< ENABLECLK2X enables or disables the + SYSPLLCLK2X output. */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_DISABLE ((uint32_t)0x00000000U) /* !< SYSPLLCLK2X is disabled */ +#define SYSCTL_SYSPLLCFG0_ENABLECLK2X_ENABLE ((uint32_t)0x00000040U) /* !< SYSPLLCLK2X is enabled */ + +/* SYSCTL_SYSPLLCFG1 Bits */ +/* SYSCTL_SYSPLLCFG1[PDIV] Bits */ +#define SYSCTL_SYSPLLCFG1_PDIV_OFS (0) /* !< PDIV Offset */ +#define SYSCTL_SYSPLLCFG1_PDIV_MASK ((uint32_t)0x00000003U) /* !< PDIV selects the SYSPLL reference + clock prescale divider. */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV1 ((uint32_t)0x00000000U) /* !< SYSPLLREF is not divided */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV2 ((uint32_t)0x00000001U) /* !< SYSPLLREF is divided by 2 */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV4 ((uint32_t)0x00000002U) /* !< SYSPLLREF is divided by 4 */ +#define SYSCTL_SYSPLLCFG1_PDIV_REFDIV8 ((uint32_t)0x00000003U) /* !< SYSPLLREF is divided by 8 */ +/* SYSCTL_SYSPLLCFG1[QDIV] Bits */ +#define SYSCTL_SYSPLLCFG1_QDIV_OFS (8) /* !< QDIV Offset */ +#define SYSCTL_SYSPLLCFG1_QDIV_MASK ((uint32_t)0x00007F00U) /* !< QDIV selects the SYSPLL feedback + path divider. */ +#define SYSCTL_SYSPLLCFG1_QDIV_INVALID ((uint32_t)0x00000000U) /* !< Divide-by-one is not a valid QDIV + option */ +#define SYSCTL_SYSPLLCFG1_QDIV_QDIVMIN ((uint32_t)0x00000100U) /* !< Feedback path is divided by 2 */ +#define SYSCTL_SYSPLLCFG1_QDIV_QDIVMAX ((uint32_t)0x00007E00U) /* !< Feedback path is divided by 127 + (0x7E) */ + +/* SYSCTL_SYSPLLPARAM0 Bits */ +/* SYSCTL_SYSPLLPARAM0[CPCURRENT] Bits */ +#define SYSCTL_SYSPLLPARAM0_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */ +#define SYSCTL_SYSPLLPARAM0_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge pump current */ +/* SYSCTL_SYSPLLPARAM0[CAPBOVERRIDE] Bits */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< CAPBOVERRIDE controls the override + for Cap B */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U) /* !< Cap B override disabled */ +#define SYSCTL_SYSPLLPARAM0_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U) /* !< Cap B override enabled */ +/* SYSCTL_SYSPLLPARAM0[STARTTIME] Bits */ +#define SYSCTL_SYSPLLPARAM0_STARTTIME_OFS (0) /* !< STARTTIME Offset */ +#define SYSCTL_SYSPLLPARAM0_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from enable to locked + clock, in 1us resolution */ +/* SYSCTL_SYSPLLPARAM0[CAPBVAL] Bits */ +#define SYSCTL_SYSPLLPARAM0_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */ +#define SYSCTL_SYSPLLPARAM0_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override value for Cap B */ +/* SYSCTL_SYSPLLPARAM0[STARTTIMELP] Bits */ +#define SYSCTL_SYSPLLPARAM0_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */ +#define SYSCTL_SYSPLLPARAM0_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from low power mode + exit to locked clock, in 1us + resolution */ + +/* SYSCTL_SYSPLLPARAM1 Bits */ +/* SYSCTL_SYSPLLPARAM1[LPFCAPA] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop filter Cap A */ +/* SYSCTL_SYSPLLPARAM1[LPFRESC] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFRESC_OFS (24) /* !< LPFRESC Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop filter Res C */ +/* SYSCTL_SYSPLLPARAM1[LPFRESA] Bits */ +#define SYSCTL_SYSPLLPARAM1_LPFRESA_OFS (8) /* !< LPFRESA Offset */ +#define SYSCTL_SYSPLLPARAM1_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop filter Res A */ + +/* SYSCTL_GENCLKCFG Bits */ +/* SYSCTL_GENCLKCFG[HFCLK4MFPCLKDIV] Bits */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS (12) /* !< HFCLK4MFPCLKDIV Offset */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK ((uint32_t)0x0000F000U) /* !< HFCLK4MFPCLKDIV selects the divider + applied to HFCLK when HFCLK is used + as the MFPCLK source. Integer + dividers from /1 to /16 may be + selected. */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV1 ((uint32_t)0x00000000U) /* !< HFCLK is not divided before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV2 ((uint32_t)0x00001000U) /* !< HFCLK is divided by 2 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV3 ((uint32_t)0x00002000U) /* !< HFCLK is divided by 3 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV4 ((uint32_t)0x00003000U) /* !< HFCLK is divided by 4 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV5 ((uint32_t)0x00004000U) /* !< HFCLK is divided by 5 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV6 ((uint32_t)0x00005000U) /* !< HFCLK is divided by 6 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV7 ((uint32_t)0x00006000U) /* !< HFCLK is divided by 7 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV8 ((uint32_t)0x00007000U) /* !< HFCLK is divided by 8 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV9 ((uint32_t)0x00008000U) /* !< HFCLK is divided by 9 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV10 ((uint32_t)0x00009000U) /* !< HFCLK is divided by 10 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV11 ((uint32_t)0x0000A000U) /* !< HFCLK is divided by 11 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV12 ((uint32_t)0x0000B000U) /* !< HFCLK is divided by 12 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV13 ((uint32_t)0x0000C000U) /* !< HFCLK is divided by 13 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV14 ((uint32_t)0x0000D000U) /* !< HFCLK is divided by 14 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV15 ((uint32_t)0x0000E000U) /* !< HFCLK is divided by 15 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV16 ((uint32_t)0x0000F000U) /* !< HFCLK is divided by 16 before being + used for MFPCLK */ +/* SYSCTL_GENCLKCFG[MFPCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_OFS (9) /* !< MFPCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_MASK ((uint32_t)0x00000200U) /* !< MFPCLKSRC selects the MFPCLK + (middle frequency precision clock) + source. */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< MFPCLK is sourced from SYSOSC */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK ((uint32_t)0x00000200U) /* !< MFPCLK is sourced from HFCLK */ +/* SYSCTL_GENCLKCFG[USBCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_OFS (10) /* !< USBCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_MASK ((uint32_t)0x00000400U) /* !< USBCLKSRC selects the USBCLK + source. */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_USBFLLCLK ((uint32_t)0x00000000U) /* !< USBCLK source is USBFLL */ +#define SYSCTL_GENCLKCFG_USBCLKSRC_SYSPLLOUT1 ((uint32_t)0x00000400U) /* !< USBCLK source is SYSPLLCLK1 */ +/* SYSCTL_GENCLKCFG[FCCLFCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_OFS (29) /* !< FCCLFCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_MASK ((uint32_t)0x20000000U) /* !< FCCLFCLKSRC selects between SYSTEM + LFCLK and EXTERNAL SOURCED LFCLK. */ +/* SYSCTL_GENCLKCFG[FCCTRIGCNT] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS (24) /* !< FCCTRIGCNT Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK ((uint32_t)0x1F000000U) /* !< FCCTRIGCNT specifies the number of + trigger clock periods in the trigger + window. FCCTRIGCNT=0h (one trigger + clock period) up to 1Fh (32 trigger + clock periods) may be specified. */ +/* SYSCTL_GENCLKCFG[ANACPUMPCFG] Bits */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_OFS (22) /* !< ANACPUMPCFG Offset */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK ((uint32_t)0x00C00000U) /* !< ANACPUMPCFG selects the analog mux + charge pump (VBOOST) enable method. */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND ((uint32_t)0x00000000U) /* !< VBOOST is enabled on request from a + COMP, GPAMP, or OPA */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE ((uint32_t)0x00400000U) /* !< VBOOST is enabled when the device + is in RUN or SLEEP mode, or when a + COMP/GPAMP/OPA is enabled */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS ((uint32_t)0x00800000U) /* !< VBOOST is always enabled */ +/* SYSCTL_GENCLKCFG[FCCTRIGSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_OFS (20) /* !< FCCTRIGSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK ((uint32_t)0x00100000U) /* !< FCCTRIGSRC selects the frequency + clock counter (FCC) trigger source. */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN ((uint32_t)0x00000000U) /* !< FCC trigger is the external pin */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK ((uint32_t)0x00100000U) /* !< FCC trigger is the LFCLK */ +/* SYSCTL_GENCLKCFG[FCCSELCLK] Bits */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_OFS (16) /* !< FCCSELCLK Offset */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MASK ((uint32_t)0x000F0000U) /* !< FCCSELCLK selectes the frequency + clock counter (FCC) clock source. */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MCLK ((uint32_t)0x00000000U) /* !< FCC clock is MCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC ((uint32_t)0x00010000U) /* !< FCC clock is SYSOSC */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK ((uint32_t)0x00020000U) /* !< FCC clock is HFCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK ((uint32_t)0x00030000U) /* !< FCC clock is the CLK_OUT selection */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK0 ((uint32_t)0x00040000U) /* !< FCC clock is SYSPLLCLK0 */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK1 ((uint32_t)0x00050000U) /* !< FCC clock is SYSPLLCLK1 */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK2X ((uint32_t)0x00060000U) /* !< FCC clock is SYSPLLCLK2X */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN ((uint32_t)0x00070000U) /* !< FCC clock is the FCCIN external + input */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_USBFLL ((uint32_t)0x00080000U) /* !< FCC clock is USBFLL */ +/* SYSCTL_GENCLKCFG[FCCLVLTRIG] Bits */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_OFS (21) /* !< FCCLVLTRIG Offset */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK ((uint32_t)0x00200000U) /* !< FCCLVLTRIG selects the frequency + clock counter (FCC) trigger mode. */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE ((uint32_t)0x00000000U) /* !< Rising edge to rising edge + triggered */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL ((uint32_t)0x00200000U) /* !< Level triggered */ +/* SYSCTL_GENCLKCFG[EXCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_OFS (0) /* !< EXCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MASK ((uint32_t)0x00000007U) /* !< EXCLKSRC selects the source for the + CLK_OUT external clock output block. + ULPCLK and MFPCLK require the CLK_OUT + divider (EXCLKDIVEN) to be enabled */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< CLK_OUT is SYSOSC */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK ((uint32_t)0x00000001U) /* !< CLK_OUT is ULPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK ((uint32_t)0x00000002U) /* !< CLK_OUT is LFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK ((uint32_t)0x00000003U) /* !< CLK_OUT is MFPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK ((uint32_t)0x00000004U) /* !< CLK_OUT is HFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSPLLOUT1 ((uint32_t)0x00000005U) /* !< CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 + must be <=48MHz) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_USBFLL ((uint32_t)0x00000006U) /* !< CLK_OUT is USBFLL (At 60Mhz must + divide for external output) */ +/* SYSCTL_GENCLKCFG[EXCLKDIVVAL] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_OFS (4) /* !< EXCLKDIVVAL Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK ((uint32_t)0x00000070U) /* !< EXCLKDIVVAL selects the divider + value for the divider in the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2 ((uint32_t)0x00000000U) /* !< CLK_OUT source is divided by 2 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4 ((uint32_t)0x00000010U) /* !< CLK_OUT source is divided by 4 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6 ((uint32_t)0x00000020U) /* !< CLK_OUT source is divided by 6 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8 ((uint32_t)0x00000030U) /* !< CLK_OUT source is divided by 8 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10 ((uint32_t)0x00000040U) /* !< CLK_OUT source is divided by 10 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12 ((uint32_t)0x00000050U) /* !< CLK_OUT source is divided by 12 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14 ((uint32_t)0x00000060U) /* !< CLK_OUT source is divided by 14 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16 ((uint32_t)0x00000070U) /* !< CLK_OUT source is divided by 16 */ +/* SYSCTL_GENCLKCFG[EXCLKDIVEN] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_OFS (7) /* !< EXCLKDIVEN Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK ((uint32_t)0x00000080U) /* !< EXCLKDIVEN enables or disables the + divider function of the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU ((uint32_t)0x00000000U) /* !< CLock divider is disabled + (passthrough, EXCLKDIVVAL is not + applied) */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE ((uint32_t)0x00000080U) /* !< Clock divider is enabled + (EXCLKDIVVAL is applied) */ + +/* SYSCTL_GENCLKEN Bits */ +/* SYSCTL_GENCLKEN[EXCLKEN] Bits */ +#define SYSCTL_GENCLKEN_EXCLKEN_OFS (0) /* !< EXCLKEN Offset */ +#define SYSCTL_GENCLKEN_EXCLKEN_MASK ((uint32_t)0x00000001U) /* !< EXCLKEN enables the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKEN_EXCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< CLK_OUT block is disabled */ +#define SYSCTL_GENCLKEN_EXCLKEN_ENABLE ((uint32_t)0x00000001U) /* !< CLK_OUT block is enabled */ +/* SYSCTL_GENCLKEN[MFPCLKEN] Bits */ +#define SYSCTL_GENCLKEN_MFPCLKEN_OFS (4) /* !< MFPCLKEN Offset */ +#define SYSCTL_GENCLKEN_MFPCLKEN_MASK ((uint32_t)0x00000010U) /* !< MFPCLKEN enables the middle + frequency precision clock (MFPCLK). */ +#define SYSCTL_GENCLKEN_MFPCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< MFPCLK is disabled */ +#define SYSCTL_GENCLKEN_MFPCLKEN_ENABLE ((uint32_t)0x00000010U) /* !< MFPCLK is enabled */ + +/* SYSCTL_PMODECFG Bits */ +/* SYSCTL_PMODECFG[DSLEEP] Bits */ +#define SYSCTL_PMODECFG_DSLEEP_OFS (0) /* !< DSLEEP Offset */ +#define SYSCTL_PMODECFG_DSLEEP_MASK ((uint32_t)0x00000003U) /* !< DSLEEP selects the operating mode + to enter upon a DEEPSLEEP request + from the CPU. */ +#define SYSCTL_PMODECFG_DSLEEP_STOP ((uint32_t)0x00000000U) /* !< STOP mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_STANDBY ((uint32_t)0x00000001U) /* !< STANDBY mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_SHUTDOWN ((uint32_t)0x00000002U) /* !< SHUTDOWN mode is entered */ + +/* SYSCTL_FCC Bits */ +/* SYSCTL_FCC[DATA] Bits */ +#define SYSCTL_FCC_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FCC_DATA_MASK ((uint32_t)0x003FFFFFU) /* !< Frequency clock counter (FCC) count + value. */ + +/* SYSCTL_SYSOSCTRIMUSER Bits */ +/* SYSCTL_SYSOSCTRIMUSER[RESCOARSE] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RESCOARSE_OFS (8) /* !< RESCOARSE Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RESCOARSE_MASK ((uint32_t)0x00003F00U) /* !< RESCOARSE specifies the resister + coarse trim. This value changes with + the target frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[RESFINE] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RESFINE_OFS (16) /* !< RESFINE Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RESFINE_MASK ((uint32_t)0x000F0000U) /* !< RESFINE specifies the resister fine + trim. This value changes with the + target frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[RDIV] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_RDIV_OFS (20) /* !< RDIV Offset */ +#define SYSCTL_SYSOSCTRIMUSER_RDIV_MASK ((uint32_t)0x1FF00000U) /* !< RDIV specifies the frequency + correction loop (FCL) resistor trim. + This value changes with the target + frequency. */ +/* SYSCTL_SYSOSCTRIMUSER[FREQ] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_MASK ((uint32_t)0x00000003U) /* !< FREQ specifies the target + user-trimmed frequency for SYSOSC. */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC16M ((uint32_t)0x00000001U) /* !< 16MHz user frequency */ +#define SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC24M ((uint32_t)0x00000002U) /* !< 24MHz user frequency */ +/* SYSCTL_SYSOSCTRIMUSER[CAP] Bits */ +#define SYSCTL_SYSOSCTRIMUSER_CAP_OFS (4) /* !< CAP Offset */ +#define SYSCTL_SYSOSCTRIMUSER_CAP_MASK ((uint32_t)0x00000070U) /* !< CAP specifies the SYSOSC capacitor + trim. This value changes with the + target frequency. */ + +/* SYSCTL_SRAMBOUNDARY Bits */ +/* SYSCTL_SRAMBOUNDARY[ADDR] Bits */ +#define SYSCTL_SRAMBOUNDARY_ADDR_OFS (5) /* !< ADDR Offset */ +#define SYSCTL_SRAMBOUNDARY_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary configuration. The + value configured into this acts such + that: SRAM accesses to addresses less + than or equal value will be RW only. + SRAM accesses to addresses greater + than value will be RX only. Value of + 0 is not valid (system will have no + stack). If set to 0, the system acts + as if the entire SRAM is RWX. Any + non-zero value can be configured, + including a value = SRAM size. */ + +/* SYSCTL_SYSTEMCFG Bits */ +/* SYSCTL_SYSTEMCFG[KEY] Bits */ +#define SYSCTL_SYSTEMCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSTEMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 1Bh (27) must be + written to KEY together with contents + to be updated. Reads as 0 */ +#define SYSCTL_SYSTEMCFG_KEY_VALUE ((uint32_t)0x1B000000U) /* !< Issue write */ +/* SYSCTL_SYSTEMCFG[FLASHECCRSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS (2) /* !< FLASHECCRSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK ((uint32_t)0x00000004U) /* !< FLASHECCRSTDIS specifies whether a + flash ECC double error detect (DED) + will trigger a SYSRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_FALSE ((uint32_t)0x00000000U) /* !< Flash ECC DED will trigger a SYSRST */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_TRUE ((uint32_t)0x00000004U) /* !< Flash ECC DED will trigger a NMI */ +/* SYSCTL_SYSTEMCFG[WWDTLP0RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS (0) /* !< WWDTLP0RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK ((uint32_t)0x00000001U) /* !< WWDTLP0RSTDIS specifies whether a + WWDT Error Event will trigger a + BOOTRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP0 Error Event will trigger a + BOOTRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_TRUE ((uint32_t)0x00000001U) /* !< WWDTLP0 Error Event will trigger an + NMI */ +/* SYSCTL_SYSTEMCFG[WWDTLP1RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS (1) /* !< WWDTLP1RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK ((uint32_t)0x00000002U) /* !< WWDTLP1RSTDIS specifies whether a + WWDT Error Event will trigger a + SYSRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP1 Error Event will trigger a + SYSRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_TRUE ((uint32_t)0x00000002U) /* !< WWDTLP1 Error Event will trigger an + NMI */ + +/* SYSCTL_WRITELOCK Bits */ +/* SYSCTL_WRITELOCK[ACTIVE] Bits */ +#define SYSCTL_WRITELOCK_ACTIVE_OFS (0) /* !< ACTIVE Offset */ +#define SYSCTL_WRITELOCK_ACTIVE_MASK ((uint32_t)0x00000001U) /* !< ACTIVE controls whether critical + SYSCTL registers are write protected + or not. */ +#define SYSCTL_WRITELOCK_ACTIVE_DISABLE ((uint32_t)0x00000000U) /* !< Allow writes to lockable registers */ +#define SYSCTL_WRITELOCK_ACTIVE_ENABLE ((uint32_t)0x00000001U) /* !< Disallow writes to lockable + registers */ + +/* SYSCTL_CLKSTATUS Bits */ +/* SYSCTL_CLKSTATUS[LFOSCGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_OFS (11) /* !< LFOSCGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_MASK ((uint32_t)0x00000800U) /* !< LFOSCGOOD indicates when the LFOSC + startup has completed and the LFOSC + is ready for use. */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFOSC is not ready */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE ((uint32_t)0x00000800U) /* !< LFOSC is ready */ +/* SYSCTL_CLKSTATUS[HFCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_OFS (8) /* !< HFCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_MASK ((uint32_t)0x00000100U) /* !< HFCLKGOOD indicates that the HFCLK + started correctly. When the HFXT is + started or HFCLK_IN is selected as + the HFCLK source, this bit will be + set by hardware if a valid HFCLK is + detected, and cleared if HFCLK is not + operating within the expected range. */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< HFCLK did not start correctly */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE ((uint32_t)0x00000100U) /* !< HFCLK started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKDEAD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_OFS (20) /* !< HSCLKDEAD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_MASK ((uint32_t)0x00100000U) /* !< HSCLKDEAD is set by hardware if the + selected source for HSCLK was started + but did not start successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source was not started or + started correctly */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE ((uint32_t)0x00100000U) /* !< The HSCLK source did not start + correctly */ +/* SYSCTL_CLKSTATUS[SYSPLLBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_OFS (29) /* !< SYSPLLBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_MASK ((uint32_t)0x20000000U) /* !< SYSPLLBLKUPD indicates when writes + to SYSPLLCFG0/1 and SYSPLLPARAM0/1 + are blocked. */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< writes to SYSPLLCFG0/1 and + SYSPLLPARAM0/1 are allowed */ +#define SYSCTL_CLKSTATUS_SYSPLLBLKUPD_TRUE ((uint32_t)0x20000000U) /* !< writes to SYSPLLCFG0/1 and + SYSPLLPARAM0/1 are blocked */ +/* SYSCTL_CLKSTATUS[HFCLKOFF] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_OFS (13) /* !< HFCLKOFF Offset */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_MASK ((uint32_t)0x00002000U) /* !< HFCLKOFF indicates if the HFCLK is + disabled or was dead at startup. + When the HFCLK is started, HFCLKOFF + is cleared by hardware. Following + startup of the HFCLK, if the HFCLK + startup monitor determines that the + HFCLK was not started correctly, + HFCLKOFF is set. */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_FALSE ((uint32_t)0x00000000U) /* !< HFCLK started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_TRUE ((uint32_t)0x00002000U) /* !< HFCLK is disabled or was dead at + startup */ +/* SYSCTL_CLKSTATUS[HFCLKBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_OFS (28) /* !< HFCLKBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_MASK ((uint32_t)0x10000000U) /* !< HFCLKBLKUPD indicates when writes + to the HFCLKCLKCFG register are + blocked. */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< Writes to HFCLKCLKCFG are allowed */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE ((uint32_t)0x10000000U) /* !< Writes to HFCLKCLKCFG are blocked */ +/* SYSCTL_CLKSTATUS[HSCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_OFS (21) /* !< HSCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_MASK ((uint32_t)0x00200000U) /* !< HSCLKGOOD is set by hardware if the + selected clock source for HSCLK + started successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source did not start + correctly */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE ((uint32_t)0x00200000U) /* !< The HSCLK source started correctly */ +/* SYSCTL_CLKSTATUS[SYSPLLGOOD] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_OFS (9) /* !< SYSPLLGOOD Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK ((uint32_t)0x00000200U) /* !< SYSPLLGOOD indicates if the SYSPLL + started correctly. When the SYSPLL + is started, SYSPLLGOOD is cleared by + hardware. After the startup settling + time has expired, the SYSPLL status + is tested. If the SYSPLL started + successfully the SYSPLLGOOD bit is + set, else it is left cleared. */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL did not start correctly */ +#define SYSCTL_CLKSTATUS_SYSPLLGOOD_TRUE ((uint32_t)0x00000200U) /* !< SYSPLL started correctly */ +/* SYSCTL_CLKSTATUS[ANACLKERR] Bits */ +#define SYSCTL_CLKSTATUS_ANACLKERR_OFS (31) /* !< ANACLKERR Offset */ +#define SYSCTL_CLKSTATUS_ANACLKERR_MASK ((uint32_t)0x80000000U) /* !< ANACLKERR is set when the device + clock configuration does not support + an enabled analog peripheral mode and + the analog peripheral may not be + functioning as expected. */ +#define SYSCTL_CLKSTATUS_ANACLKERR_FALSE ((uint32_t)0x00000000U) /* !< No analog clock errors detected */ +#define SYSCTL_CLKSTATUS_ANACLKERR_TRUE ((uint32_t)0x80000000U) /* !< Analog clock error detected */ +/* SYSCTL_CLKSTATUS[HSCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_OFS (4) /* !< HSCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_MASK ((uint32_t)0x00000010U) /* !< HSCLKMUX indicates if MCLK is + currently sourced from the high-speed + clock (HSCLK). */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_SYSOSC ((uint32_t)0x00000000U) /* !< MCLK is not sourced from HSCLK */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK ((uint32_t)0x00000010U) /* !< MCLK is sourced from HSCLK */ +/* SYSCTL_CLKSTATUS[LFCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_OFS (6) /* !< LFCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_MASK ((uint32_t)0x000000C0U) /* !< LFCLKMUX indicates if LFCLK is + sourced from the internal LFOSC, the + low frequency crystal (LFXT), or the + LFCLK_IN digital clock input. */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFOSC ((uint32_t)0x00000000U) /* !< LFCLK is sourced from the internal + LFOSC */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFXT ((uint32_t)0x00000040U) /* !< LFCLK is sourced from the LFXT + (crystal) */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_EXLF ((uint32_t)0x00000080U) /* !< LFCLK is sourced from LFCLK_IN + (external digital clock input) */ +/* SYSCTL_CLKSTATUS[SYSOSCFREQ] Bits */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_OFS (0) /* !< SYSOSCFREQ Offset */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK ((uint32_t)0x00000003U) /* !< SYSOSCFREQ indicates the current + SYSOSC operating frequency. */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC32M ((uint32_t)0x00000000U) /* !< SYSOSC is at base frequency (32MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< SYSOSC is at low frequency (4MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< SYSOSC is at the user-trimmed + frequency (16 or 24MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCTURBO ((uint32_t)0x00000003U) /* !< Reserved */ +/* SYSCTL_CLKSTATUS[LFXTGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_OFS (10) /* !< LFXTGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_MASK ((uint32_t)0x00000400U) /* !< LFXTGOOD indicates if the LFXT + started correctly. When the LFXT is + started, LFXTGOOD is cleared by + hardware. After the startup settling + time has expired, the LFXT status is + tested. If the LFXT started + successfully the LFXTGOOD bit is set, + else it is left cleared. */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFXT did not start correctly */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_TRUE ((uint32_t)0x00000400U) /* !< LFXT started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKSOFF] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_OFS (12) /* !< HSCLKSOFF Offset */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_MASK ((uint32_t)0x00001000U) /* !< HSCLKSOFF is set when the high + speed clock sources (SYSPLL, HFCLK) + are disabled or dead. It is the + logical AND of HFCLKOFF and + SYSPLLOFF. */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL, HFCLK, or both were started + correctly and remain enabled */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE ((uint32_t)0x00001000U) /* !< SYSPLL and HFCLK are both either + off or dead */ +/* SYSCTL_CLKSTATUS[FCLMODE] Bits */ +#define SYSCTL_CLKSTATUS_FCLMODE_OFS (24) /* !< FCLMODE Offset */ +#define SYSCTL_CLKSTATUS_FCLMODE_MASK ((uint32_t)0x01000000U) /* !< FCLMODE indicates if the SYSOSC + frequency correction loop (FCL) is + enabled. */ +#define SYSCTL_CLKSTATUS_FCLMODE_DISABLED ((uint32_t)0x00000000U) /* !< SYSOSC FCL is disabled */ +#define SYSCTL_CLKSTATUS_FCLMODE_ENABLED ((uint32_t)0x01000000U) /* !< SYSOSC FCL is enabled */ +/* SYSCTL_CLKSTATUS[CURHSCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_OFS (16) /* !< CURHSCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_MASK ((uint32_t)0x00010000U) /* !< CURHSCLKSEL indicates the current + clock source for HSCLK. */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is currently sourced from the + SYSPLL */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK ((uint32_t)0x00010000U) /* !< HSCLK is currently sourced from the + HFCLK */ +/* SYSCTL_CLKSTATUS[CURMCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_OFS (17) /* !< CURMCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_MASK ((uint32_t)0x00020000U) /* !< CURMCLKSEL indicates if MCLK is + currently sourced from LFCLK. */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_NOTLFCLK ((uint32_t)0x00000000U) /* !< MCLK is not sourced from LFCLK */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK ((uint32_t)0x00020000U) /* !< MCLK is sourced from LFCLK */ +/* SYSCTL_CLKSTATUS[FCCDONE] Bits */ +#define SYSCTL_CLKSTATUS_FCCDONE_OFS (25) /* !< FCCDONE Offset */ +#define SYSCTL_CLKSTATUS_FCCDONE_MASK ((uint32_t)0x02000000U) /* !< FCCDONE indicates when a frequency + clock counter capture is complete. */ +#define SYSCTL_CLKSTATUS_FCCDONE_NOTDONE ((uint32_t)0x00000000U) /* !< FCC capture is not done */ +#define SYSCTL_CLKSTATUS_FCCDONE_DONE ((uint32_t)0x02000000U) /* !< FCC capture is done */ +/* SYSCTL_CLKSTATUS[SYSPLLOFF] Bits */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_OFS (14) /* !< SYSPLLOFF Offset */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_MASK ((uint32_t)0x00004000U) /* !< SYSPLLOFF indicates if the SYSPLL + is disabled or was dead at startup. + When the SYSPLL is started, SYSPLLOFF + is cleared by hardware. Following + startup of the SYSPLL, if the SYSPLL + startup monitor determines that the + SYSPLL was not started correctly, + SYSPLLOFF is set. */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_SYSPLLOFF_TRUE ((uint32_t)0x00004000U) /* !< SYSPLL is disabled or was dead + startup */ +/* SYSCTL_CLKSTATUS[LFCLKFAIL] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_OFS (23) /* !< LFCLKFAIL Offset */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_MASK ((uint32_t)0x00800000U) /* !< LFCLKFAIL indicates when the + continous LFCLK monitor detects a + LFXT or LFCLK_IN clock stuck failure. */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) /* !< No LFCLK fault detected */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE ((uint32_t)0x00800000U) /* !< LFCLK stuck fault detected */ + +/* SYSCTL_SYSSTATUS Bits */ +/* SYSCTL_SYSSTATUS[USBFS0READY] Bits */ +#define SYSCTL_SYSSTATUS_USBFS0READY_OFS (25) /* !< USBFS0READY Offset */ +#define SYSCTL_SYSSTATUS_USBFS0READY_MASK ((uint32_t)0x02000000U) /* !< USBFS0READY indicates when the + USBFS0 peripheral is ready. */ +#define SYSCTL_SYSSTATUS_USBFS0READY_FALSE ((uint32_t)0x00000000U) /* !< USBFS0 is not ready */ +#define SYSCTL_SYSSTATUS_USBFS0READY_TRUE ((uint32_t)0x02000000U) /* !< USBFS0 is ready */ +/* SYSCTL_SYSSTATUS[SHDNIOLOCK] Bits */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_OFS (14) /* !< SHDNIOLOCK Offset */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_MASK ((uint32_t)0x00004000U) /* !< SHDNIOLOCK indicates when IO is + locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_FALSE ((uint32_t)0x00000000U) /* !< IO IS NOT Locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE ((uint32_t)0x00004000U) /* !< IO IS Locked due to SHUTDOWN */ +/* SYSCTL_SYSSTATUS[EXTRSTPINDIS] Bits */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_OFS (12) /* !< EXTRSTPINDIS Offset */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_MASK ((uint32_t)0x00001000U) /* !< EXTRSTPINDIS indicates when user + has disabled the use of external + reset pin */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_FALSE ((uint32_t)0x00000000U) /* !< External Reset Pin Enabled */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE ((uint32_t)0x00001000U) /* !< External Reset Pin Disabled */ +/* SYSCTL_SYSSTATUS[SWDCFGDIS] Bits */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_OFS (13) /* !< SWDCFGDIS Offset */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_MASK ((uint32_t)0x00002000U) /* !< SWDCFGDIS indicates when user has + disabled the use of SWD Port */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_FALSE ((uint32_t)0x00000000U) /* !< SWD Port Enabled */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE ((uint32_t)0x00002000U) /* !< SWD Port Disabled */ +/* SYSCTL_SYSSTATUS[ANACPUMPGOOD] Bits */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_OFS (5) /* !< ANACPUMPGOOD Offset */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_MASK ((uint32_t)0x00000020U) /* !< ANACPUMPGOOD is set by hardware + when the VBOOST analog mux charge + pump is ready. */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_FALSE ((uint32_t)0x00000000U) /* !< VBOOST is not ready */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE ((uint32_t)0x00000020U) /* !< VBOOST is ready */ +/* SYSCTL_SYSSTATUS[BORLVL] Bits */ +#define SYSCTL_SYSSTATUS_BORLVL_OFS (4) /* !< BORLVL Offset */ +#define SYSCTL_SYSSTATUS_BORLVL_MASK ((uint32_t)0x00000010U) /* !< BORLVL indicates if a BOR event + occured and the BOR threshold was + switched to BOR0 by hardware. */ +#define SYSCTL_SYSSTATUS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No BOR violation occured */ +#define SYSCTL_SYSSTATUS_BORLVL_TRUE ((uint32_t)0x00000010U) /* !< A BOR violation occured and the BOR + threshold was switched to BOR0 */ +/* SYSCTL_SYSSTATUS[NPUREADY] Bits */ +#define SYSCTL_SYSSTATUS_NPUREADY_OFS (24) /* !< NPUREADY Offset */ +#define SYSCTL_SYSSTATUS_NPUREADY_MASK ((uint32_t)0x01000000U) /* !< NPUREADY indicates when the NPU + peripheral is ready. */ +#define SYSCTL_SYSSTATUS_NPUREADY_FALSE ((uint32_t)0x00000000U) /* !< NPU is not ready */ +#define SYSCTL_SYSSTATUS_NPUREADY_TRUE ((uint32_t)0x01000000U) /* !< NPU is ready */ +/* SYSCTL_SYSSTATUS[FLASHDED] Bits */ +#define SYSCTL_SYSSTATUS_FLASHDED_OFS (0) /* !< FLASHDED Offset */ +#define SYSCTL_SYSSTATUS_FLASHDED_MASK ((uint32_t)0x00000001U) /* !< FLASHDED indicates if a flash ECC + double bit error was detected (DED). */ +#define SYSCTL_SYSSTATUS_FLASHDED_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC double bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHDED_TRUE ((uint32_t)0x00000001U) /* !< Flash ECC double bit error detected */ +/* SYSCTL_SYSSTATUS[FLASHSEC] Bits */ +#define SYSCTL_SYSSTATUS_FLASHSEC_OFS (1) /* !< FLASHSEC Offset */ +#define SYSCTL_SYSSTATUS_FLASHSEC_MASK ((uint32_t)0x00000002U) /* !< FLASHSEC indicates if a flash ECC + single bit error was detected and + corrected (SEC). */ +#define SYSCTL_SYSSTATUS_FLASHSEC_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC single bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHSEC_TRUE ((uint32_t)0x00000002U) /* !< Flash ECC single bit error was + detected and corrected */ +/* SYSCTL_SYSSTATUS[PMUIREFGOOD] Bits */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_OFS (6) /* !< PMUIREFGOOD Offset */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_MASK ((uint32_t)0x00000040U) /* !< PMUIREFGOOD is set by hardware when + the PMU current reference is ready. */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_FALSE ((uint32_t)0x00000000U) /* !< IREF is not ready */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE ((uint32_t)0x00000040U) /* !< IREF is ready */ +/* SYSCTL_SYSSTATUS[REBOOTATTEMPTS] Bits */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_OFS (30) /* !< REBOOTATTEMPTS Offset */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_MASK ((uint32_t)0xC0000000U) /* !< REBOOTATTEMPTS indicates the number + of boot attempts taken before the + user application starts. */ +/* SYSCTL_SYSSTATUS[BORCURTHRESHOLD] Bits */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_OFS (2) /* !< BORCURTHRESHOLD Offset */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_MASK ((uint32_t)0x0000000CU) /* !< BORCURTHRESHOLD indicates the + active brown-out reset supply monitor + configuration. */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1 ((uint32_t)0x00000004U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2 ((uint32_t)0x00000008U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3 ((uint32_t)0x0000000CU) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_DEDERRADDR Bits */ +/* SYSCTL_DEDERRADDR[ADDR] Bits */ +#define SYSCTL_DEDERRADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define SYSCTL_DEDERRADDR_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< Address of MEMORY DED Error. */ + +/* SYSCTL_RSTCAUSE Bits */ +/* SYSCTL_RSTCAUSE[ID] Bits */ +#define SYSCTL_RSTCAUSE_ID_OFS (0) /* !< ID Offset */ +#define SYSCTL_RSTCAUSE_ID_MASK ((uint32_t)0x0000001FU) /* !< ID is a read-to-clear field which + indicates the lowest level reset + cause since the last read. */ +#define SYSCTL_RSTCAUSE_ID_NORST ((uint32_t)0x00000000U) /* !< No reset since last read */ +#define SYSCTL_RSTCAUSE_ID_PORHWFAIL ((uint32_t)0x00000001U) /* !< POR- violation, SHUTDNSTOREx or PMU + trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_POREXNRST ((uint32_t)0x00000002U) /* !< NRST triggered POR (>1s hold) */ +#define SYSCTL_RSTCAUSE_ID_PORSW ((uint32_t)0x00000003U) /* !< Software triggered POR */ +#define SYSCTL_RSTCAUSE_ID_BORSUPPLY ((uint32_t)0x00000004U) /* !< BOR0- violation */ +#define SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN ((uint32_t)0x00000005U) /* !< SHUTDOWN mode exit */ +#define SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY ((uint32_t)0x00000008U) /* !< Non-PMU trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL ((uint32_t)0x00000009U) /* !< Fatal clock failure */ +#define SYSCTL_RSTCAUSE_ID_BOOTEXNRST ((uint32_t)0x0000000CU) /* !< NRST triggered BOOTRST (<1s hold) */ +#define SYSCTL_RSTCAUSE_ID_BOOTSW ((uint32_t)0x0000000DU) /* !< Software triggered BOOTRST */ +#define SYSCTL_RSTCAUSE_ID_BOOTWWDT0 ((uint32_t)0x0000000EU) /* !< WWDT0 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLEXIT ((uint32_t)0x00000010U) /* !< BSL exit */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLENTRY ((uint32_t)0x00000011U) /* !< BSL entry */ +#define SYSCTL_RSTCAUSE_ID_SYSWWDT1 ((uint32_t)0x00000013U) /* !< WWDT1 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSFLASHECC ((uint32_t)0x00000014U) /* !< Flash uncorrectable ECC error */ +#define SYSCTL_RSTCAUSE_ID_SYSCPULOCK ((uint32_t)0x00000015U) /* !< CPULOCK violation */ +#define SYSCTL_RSTCAUSE_ID_SYSDBG ((uint32_t)0x0000001AU) /* !< Debug triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_SYSSW ((uint32_t)0x0000001BU) /* !< Software triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_CPUDBG ((uint32_t)0x0000001CU) /* !< Debug triggered CPURST */ +#define SYSCTL_RSTCAUSE_ID_CPUSW ((uint32_t)0x0000001DU) /* !< Software triggered CPURST */ + +/* SYSCTL_RESETLEVEL Bits */ +/* SYSCTL_RESETLEVEL[LEVEL] Bits */ +#define SYSCTL_RESETLEVEL_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_RESETLEVEL_LEVEL_MASK ((uint32_t)0x00000007U) /* !< LEVEL is used to specify the type + of reset to be issued when RESETCMD + is set to generate a software + triggered reset. */ +#define SYSCTL_RESETLEVEL_LEVEL_CPU ((uint32_t)0x00000000U) /* !< Issue a SYSRST (CPU plus + peripherals only) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOT ((uint32_t)0x00000001U) /* !< Issue a BOOTRST (CPU, peripherals, + and boot configuration routine) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY ((uint32_t)0x00000002U) /* !< Issue a SYSRST and enter the boot + strap loader (BSL) */ +#define SYSCTL_RESETLEVEL_LEVEL_POR ((uint32_t)0x00000003U) /* !< Issue a power-on reset (POR) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT ((uint32_t)0x00000004U) /* !< Issue a SYSRST and exit the boot + strap loader (BSL) */ + +/* SYSCTL_RESETCMD Bits */ +/* SYSCTL_RESETCMD[KEY] Bits */ +#define SYSCTL_RESETCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_RESETCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of E4h (228) must be + written to KEY together with GO to + trigger the reset. */ +#define SYSCTL_RESETCMD_KEY_VALUE ((uint32_t)0xE4000000U) /* !< Issue reset */ +/* SYSCTL_RESETCMD[GO] Bits */ +#define SYSCTL_RESETCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_RESETCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Execute the reset specified in + RESETLEVEL.LEVEL. Must be written + together with the KEY. */ +#define SYSCTL_RESETCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue reset */ + +/* SYSCTL_BORTHRESHOLD Bits */ +/* SYSCTL_BORTHRESHOLD[LEVEL] Bits */ +#define SYSCTL_BORTHRESHOLD_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_BORTHRESHOLD_LEVEL_MASK ((uint32_t)0x00000003U) /* !< LEVEL specifies the desired BOR + threshold and BOR mode. */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1 ((uint32_t)0x00000001U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2 ((uint32_t)0x00000002U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3 ((uint32_t)0x00000003U) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_BORCLRCMD Bits */ +/* SYSCTL_BORCLRCMD[KEY] Bits */ +#define SYSCTL_BORCLRCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_BORCLRCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of C7h (199) must be + written to KEY together with GO to + trigger the clear and BOR threshold + change. */ +#define SYSCTL_BORCLRCMD_KEY_VALUE ((uint32_t)0xC7000000U) /* !< Issue clear */ +/* SYSCTL_BORCLRCMD[GO] Bits */ +#define SYSCTL_BORCLRCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_BORCLRCMD_GO_MASK ((uint32_t)0x00000001U) /* !< GO clears any prior BOR violation + status indications and attempts to + change the active BOR mode to that + specified in the LEVEL field of the + BORTHRESHOLD register. */ +#define SYSCTL_BORCLRCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue clear */ + +/* SYSCTL_SYSOSCFCLCTL Bits */ +/* SYSCTL_SYSOSCFCLCTL[KEY] Bits */ +#define SYSCTL_SYSOSCFCLCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSOSCFCLCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 2Ah (42) must be + written to KEY together with + SETUSEFCL to enable the FCL. */ +#define SYSCTL_SYSOSCFCLCTL_KEY_VALUE ((uint32_t)0x2A000000U) /* !< Issue Command */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEFCL] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_OFS (0) /* !< SETUSEFCL Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEFCL to enable the + frequency correction loop in SYSOSC. + Once enabled, this state is locked + until the next BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEEXRES] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_OFS (1) /* !< SETUSEEXRES Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_MASK ((uint32_t)0x00000002U) /* !< Set SETUSEEXRES to specify that an + external resistor will be used for + the FCL. An appropriate resistor + must be populated on the ROSC pin. + This state is locked until the next + BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE ((uint32_t)0x00000002U) /* !< Enable the SYSOSC external Resistor */ + +/* SYSCTL_LFXTCTL Bits */ +/* SYSCTL_LFXTCTL[KEY] Bits */ +#define SYSCTL_LFXTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_LFXTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 91h (145) must be + written to KEY together with either + STARTLFXT or SETUSELFXT to set the + corresponding bit. */ +#define SYSCTL_LFXTCTL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_LFXTCTL[SETUSELFXT] Bits */ +#define SYSCTL_LFXTCTL_SETUSELFXT_OFS (1) /* !< SETUSELFXT Offset */ +#define SYSCTL_LFXTCTL_SETUSELFXT_MASK ((uint32_t)0x00000002U) /* !< Set SETUSELFXT to switch LFCLK to + LFXT. Once set, SETUSELFXT remains + set until the next BOOTRST. */ +#define SYSCTL_LFXTCTL_SETUSELFXT_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_LFXTCTL_SETUSELFXT_TRUE ((uint32_t)0x00000002U) /* !< Use LFXT as the LFCLK source */ +/* SYSCTL_LFXTCTL[STARTLFXT] Bits */ +#define SYSCTL_LFXTCTL_STARTLFXT_OFS (0) /* !< STARTLFXT Offset */ +#define SYSCTL_LFXTCTL_STARTLFXT_MASK ((uint32_t)0x00000001U) /* !< Set STARTLFXT to start the low + frequency crystal oscillator (LFXT). + Once set, STARTLFXT remains set until + the next BOOTRST. */ +#define SYSCTL_LFXTCTL_STARTLFXT_FALSE ((uint32_t)0x00000000U) /* !< LFXT not started */ +#define SYSCTL_LFXTCTL_STARTLFXT_TRUE ((uint32_t)0x00000001U) /* !< Start LFXT */ + +/* SYSCTL_EXLFCTL Bits */ +/* SYSCTL_EXLFCTL[KEY] Bits */ +#define SYSCTL_EXLFCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXLFCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 36h (54) must be + written to KEY together with + SETUSEEXLF to set SETUSEEXLF. */ +#define SYSCTL_EXLFCTL_KEY_VALUE ((uint32_t)0x36000000U) /* !< Issue command */ +/* SYSCTL_EXLFCTL[SETUSEEXLF] Bits */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_OFS (0) /* !< SETUSEEXLF Offset */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEEXLF to switch LFCLK to + the LFCLK_IN digital clock input. + Once set, SETUSEEXLF remains set + until the next BOOTRST. */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_TRUE ((uint32_t)0x00000001U) /* !< Use LFCLK_IN as the LFCLK source */ + +/* SYSCTL_SHDNIOREL Bits */ +/* SYSCTL_SHDNIOREL[KEY] Bits */ +#define SYSCTL_SHDNIOREL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SHDNIOREL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 91h must be written + to KEY together with RELEASE to set + RELEASE. */ +#define SYSCTL_SHDNIOREL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_SHDNIOREL[RELEASE] Bits */ +#define SYSCTL_SHDNIOREL_RELEASE_OFS (0) /* !< RELEASE Offset */ +#define SYSCTL_SHDNIOREL_RELEASE_MASK ((uint32_t)0x00000001U) /* !< Set RELEASE to release the IO after + a SHUTDOWN mode exit. */ +#define SYSCTL_SHDNIOREL_RELEASE_TRUE ((uint32_t)0x00000001U) /* !< Release IO */ + +/* SYSCTL_EXRSTPIN Bits */ +/* SYSCTL_EXRSTPIN[KEY] Bits */ +#define SYSCTL_EXRSTPIN_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXRSTPIN_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 1Eh must be written + together with DISABLE to disable the + reset function. */ +#define SYSCTL_EXRSTPIN_KEY_VALUE ((uint32_t)0x1E000000U) /* !< Issue command */ +/* SYSCTL_EXRSTPIN[DISABLE] Bits */ +#define SYSCTL_EXRSTPIN_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_EXRSTPIN_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the reset + function of the NRST pin. Once set, + this configuration is locked until + the next POR. */ +#define SYSCTL_EXRSTPIN_DISABLE_FALSE ((uint32_t)0x00000000U) /* !< Reset function of NRST pin is + enabled */ +#define SYSCTL_EXRSTPIN_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Reset function of NRST pin is + disabled */ + +/* SYSCTL_SYSSTATUSCLR Bits */ +/* SYSCTL_SYSSTATUSCLR[KEY] Bits */ +#define SYSCTL_SYSSTATUSCLR_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSSTATUSCLR_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value CEh (206) must be + written to KEY together with ALLECC + to clear the ECC state. */ +#define SYSCTL_SYSSTATUSCLR_KEY_VALUE ((uint32_t)0xCE000000U) /* !< Issue command */ +/* SYSCTL_SYSSTATUSCLR[ALLECC] Bits */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_OFS (0) /* !< ALLECC Offset */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_MASK ((uint32_t)0x00000001U) /* !< Set ALLECC to clear all ECC related + SYSSTATUS indicators. */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR ((uint32_t)0x00000001U) /* !< Clear ECC error state */ + +/* SYSCTL_SWDCFG Bits */ +/* SYSCTL_SWDCFG[KEY] Bits */ +#define SYSCTL_SWDCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SWDCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 62h (98) must be + written to KEY together with DISBALE + to disable the SWD functions. */ +#define SYSCTL_SWDCFG_KEY_VALUE ((uint32_t)0x62000000U) /* !< Issue command */ +/* SYSCTL_SWDCFG[DISABLE] Bits */ +#define SYSCTL_SWDCFG_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_SWDCFG_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the SWD + function on SWD pins, allowing the + SWD pins to be used as GPIO. */ +#define SYSCTL_SWDCFG_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disable SWD function on SWD pins */ + +/* SYSCTL_FCCCMD Bits */ +/* SYSCTL_FCCCMD[KEY] Bits */ +#define SYSCTL_FCCCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FCCCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 0Eh (14) must be + written with GO to start a capture. */ +#define SYSCTL_FCCCMD_KEY_VALUE ((uint32_t)0x0E000000U) /* !< Issue command */ +/* SYSCTL_FCCCMD[GO] Bits */ +#define SYSCTL_FCCCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_FCCCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Set GO to start a capture with the + frequency clock counter (FCC). */ +#define SYSCTL_FCCCMD_GO_TRUE ((uint32_t)0x00000001U) + +/* SYSCTL_USBFLLCTL Bits */ +/* SYSCTL_USBFLLCTL[FLLEN] Bits */ +#define SYSCTL_USBFLLCTL_FLLEN_OFS (1) /* !< FLLEN Offset */ +#define SYSCTL_USBFLLCTL_FLLEN_MASK ((uint32_t)0x00000002U) /* !< USB Oscillator Frequeny Lock Loop + Enable */ +#define SYSCTL_USBFLLCTL_FLLEN_FALSE ((uint32_t)0x00000000U) /* !< USB CLK Frequeny Lock Loop is + disabled */ +#define SYSCTL_USBFLLCTL_FLLEN_TRUE ((uint32_t)0x00000002U) /* !< USB CLK Frequeny Lock Loop is + enabled */ +/* SYSCTL_USBFLLCTL[REFSEL] Bits */ +#define SYSCTL_USBFLLCTL_REFSEL_OFS (8) /* !< REFSEL Offset */ +#define SYSCTL_USBFLLCTL_REFSEL_MASK ((uint32_t)0x00000100U) /* !< Reference Clock Selection for + Frequency Lock Loop */ +#define SYSCTL_USBFLLCTL_REFSEL_LFCLK ((uint32_t)0x00000100U) /* !< Use LFCLK as Reference Clock */ +/* SYSCTL_USBFLLCTL[CLKEN] Bits */ +#define SYSCTL_USBFLLCTL_CLKEN_OFS (0) /* !< CLKEN Offset */ +#define SYSCTL_USBFLLCTL_CLKEN_MASK ((uint32_t)0x00000001U) /* !< USB Oscillator Enable */ +#define SYSCTL_USBFLLCTL_CLKEN_FALSE ((uint32_t)0x00000000U) /* !< USB CLK is disabled */ +#define SYSCTL_USBFLLCTL_CLKEN_TRUE ((uint32_t)0x00000001U) /* !< USB CLK is enabled */ + +/* SYSCTL_USBFLLADJ Bits */ +/* SYSCTL_USBFLLADJ[FRQMOD] Bits */ +#define SYSCTL_USBFLLADJ_FRQMOD_OFS (8) /* !< FRQMOD Offset */ +#define SYSCTL_USBFLLADJ_FRQMOD_MASK ((uint32_t)0x00000700U) /* !< Frequency Lock Loop Modulator Value */ +/* SYSCTL_USBFLLADJ[FRQADJ] Bits */ +#define SYSCTL_USBFLLADJ_FRQADJ_OFS (0) /* !< FRQADJ Offset */ +#define SYSCTL_USBFLLADJ_FRQADJ_MASK ((uint32_t)0x0000003FU) /* !< Frequency Lock Loop Adjust */ + +/* SYSCTL_USBFLLSTAT Bits */ +/* SYSCTL_USBFLLSTAT[FRQMOD] Bits */ +#define SYSCTL_USBFLLSTAT_FRQMOD_OFS (24) /* !< FRQMOD Offset */ +#define SYSCTL_USBFLLSTAT_FRQMOD_MASK ((uint32_t)0x07000000U) /* !< Current Frequency Lock Loop + Modulator Value */ +/* SYSCTL_USBFLLSTAT[REFRDY] Bits */ +#define SYSCTL_USBFLLSTAT_REFRDY_OFS (8) /* !< REFRDY Offset */ +#define SYSCTL_USBFLLSTAT_REFRDY_MASK ((uint32_t)0x00000100U) /* !< Reference Clock for Frequency Lock + Loop ready indication */ +#define SYSCTL_USBFLLSTAT_REFRDY_FALSE ((uint32_t)0x00000000U) /* !< USB FLL Reference clock is not + ready */ +#define SYSCTL_USBFLLSTAT_REFRDY_TRUE ((uint32_t)0x00000100U) /* !< USB FLL Reference clock is ready */ +/* SYSCTL_USBFLLSTAT[FLLLOCK] Bits */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_OFS (1) /* !< FLLLOCK Offset */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_MASK ((uint32_t)0x00000002U) /* !< USB Oscillator Frequeny Lock Loop + Lock Indication */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_FALSE ((uint32_t)0x00000000U) /* !< USB CLK Frequeny Lock Loop is not + locked */ +#define SYSCTL_USBFLLSTAT_FLLLOCK_TRUE ((uint32_t)0x00000002U) /* !< USB CLK Frequeny Lock Loop is + locked */ +/* SYSCTL_USBFLLSTAT[CLKRDY] Bits */ +#define SYSCTL_USBFLLSTAT_CLKRDY_OFS (0) /* !< CLKRDY Offset */ +#define SYSCTL_USBFLLSTAT_CLKRDY_MASK ((uint32_t)0x00000001U) /* !< USB Oscillator Ready Indication */ +#define SYSCTL_USBFLLSTAT_CLKRDY_FALSE ((uint32_t)0x00000000U) /* !< USB CLK is not ready */ +#define SYSCTL_USBFLLSTAT_CLKRDY_TRUE ((uint32_t)0x00000001U) /* !< USB CLK is ready */ +/* SYSCTL_USBFLLSTAT[FRQADJ] Bits */ +#define SYSCTL_USBFLLSTAT_FRQADJ_OFS (16) /* !< FRQADJ Offset */ +#define SYSCTL_USBFLLSTAT_FRQADJ_MASK ((uint32_t)0x003F0000U) /* !< Current Frequency Lock Loop Adjust */ + +/* SYSCTL_SHUTDNSTORE0 Bits */ +/* SYSCTL_SHUTDNSTORE0[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE0_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE0_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 0 */ + +/* SYSCTL_SHUTDNSTORE1 Bits */ +/* SYSCTL_SHUTDNSTORE1[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE1_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE1_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 1 */ + +/* SYSCTL_SHUTDNSTORE2 Bits */ +/* SYSCTL_SHUTDNSTORE2[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE2_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE2_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 2 */ + +/* SYSCTL_SHUTDNSTORE3 Bits */ +/* SYSCTL_SHUTDNSTORE3[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE3_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE3_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 3 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0g518x__include */ diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0gx51x.h b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0gx51x.h index 594469d..73cfcea 100644 --- a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0gx51x.h +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0gx51x.h @@ -1759,6 +1759,15 @@ typedef struct { Once enabled, this state is locked until the next BOOTRST. */ #define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEEXRES] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_OFS (1) /* !< SETUSEEXRES Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_MASK ((uint32_t)0x00000002U) /* !< Set SETUSEEXRES to specify that an + external resistor will be used for + the FCL. An appropriate resistor + must be populated on the ROSC pin. + This state is locked until the next + BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE ((uint32_t)0x00000002U) /* !< Enable the SYSOSC external Resistor */ /* SYSCTL_LFXTCTL Bits */ /* SYSCTL_LFXTCTL[KEY] Bits */ diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l11xx_l13xx.h b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l11xx_l13xx.h index 206780c..297677b 100644 --- a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l11xx_l13xx.h +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l11xx_l13xx.h @@ -951,7 +951,6 @@ typedef struct { chopping mode. */ #define SYSCTL_PMUOPAMP_CHOPCLKMODE_CHOPDISABLED ((uint32_t)0x00000000U) /* !< Chopping disabled */ #define SYSCTL_PMUOPAMP_CHOPCLKMODE_REGCHOP ((uint32_t)0x00000400U) /* !< Normal chopping */ -#define SYSCTL_PMUOPAMP_CHOPCLKMODE_ADCASSIST ((uint32_t)0x00000800U) /* !< ADC Assisted chopping */ /* SYSCTL_PMUOPAMP[OUTENABLE] Bits */ #define SYSCTL_PMUOPAMP_OUTENABLE_OFS (6) /* !< OUTENABLE Offset */ #define SYSCTL_PMUOPAMP_OUTENABLE_MASK ((uint32_t)0x00000040U) /* !< Set OUTENABLE to connect the GPAMP diff --git a/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l211x_l112x.h b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l211x_l112x.h new file mode 100644 index 0000000..e22694c --- /dev/null +++ b/mspm0/source/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l211x_l112x.h @@ -0,0 +1,1514 @@ +/***************************************************************************** + + Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0l211x_l112x__include +#define ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0l211x_l112x__include + +/* Filename: hw_sysctl_mspm0l211x_l112x.h */ +/* Revised: 2024-11-13 14:08:09 */ +/* Revision: a2b958e769a1d3e13de7e536a3f497f4c3cc13e1 */ + +#ifndef __CORTEX_M + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* following defines should be used for structure members */ + #define __IM volatile const /*! Defines 'read only' structure member permissions */ + #define __OM volatile /*! Defines 'write only' structure member permissions */ + #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#endif + +/* Use standard integer types with explicit width */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** +* SYSCTL Registers +******************************************************************************/ +#define SYSCTL_SECCFG_OFS ((uint32_t)0x00003000U) +#define SYSCTL_SOCLOCK_OFS ((uint32_t)0x00001000U) + + +/** @addtogroup SYSCTL_SECCFG + @{ +*/ + +typedef struct { + __IO uint32_t FWEPROTMAIN; /* !< (@ 0x00003000) 1 Sector Write-Erase per bit starting at address + 0x0 of flash */ + uint32_t RESERVED0[5]; + __IO uint32_t FRXPROTMAINSTART; /* !< (@ 0x00003018) Flash RX Protection Start Address */ + __IO uint32_t FRXPROTMAINEND; /* !< (@ 0x0000301C) Flash RX Protection End Address */ + __IO uint32_t FIPPROTMAINSTART; /* !< (@ 0x00003020) Flash IP Protection Start Address */ + __IO uint32_t FIPPROTMAINEND; /* !< (@ 0x00003024) Flash IP Protection End Address */ + uint32_t RESERVED1[7]; + __O uint32_t FWENABLE; /* !< (@ 0x00003044) Security Firewall Enable Register */ + __I uint32_t SECSTATUS; /* !< (@ 0x00003048) Security Configuration status */ + uint32_t RESERVED2[5]; + __O uint32_t INITDONE; /* !< (@ 0x00003060) INITCODE PASS */ +} SYSCTL_SECCFG_Regs; + +/*@}*/ /* end of group SYSCTL_SECCFG */ + +/** @addtogroup SYSCTL_SOCLOCK + @{ +*/ + +typedef struct { + uint32_t RESERVED0[8]; + __I uint32_t IIDX; /* !< (@ 0x00001020) SYSCTL interrupt index */ + uint32_t RESERVED1; + __IO uint32_t IMASK; /* !< (@ 0x00001028) SYSCTL interrupt mask */ + uint32_t RESERVED2; + __I uint32_t RIS; /* !< (@ 0x00001030) SYSCTL raw interrupt status */ + uint32_t RESERVED3; + __I uint32_t MIS; /* !< (@ 0x00001038) SYSCTL masked interrupt status */ + uint32_t RESERVED4; + __O uint32_t ISET; /* !< (@ 0x00001040) SYSCTL interrupt set */ + uint32_t RESERVED5; + __O uint32_t ICLR; /* !< (@ 0x00001048) SYSCTL interrupt clear */ + uint32_t RESERVED6; + __I uint32_t NMIIIDX; /* !< (@ 0x00001050) NMI interrupt index */ + uint32_t RESERVED7[3]; + __I uint32_t NMIRIS; /* !< (@ 0x00001060) NMI raw interrupt status */ + uint32_t RESERVED8[3]; + __O uint32_t NMIISET; /* !< (@ 0x00001070) NMI interrupt set */ + uint32_t RESERVED9; + __O uint32_t NMIICLR; /* !< (@ 0x00001078) NMI interrupt clear */ + uint32_t RESERVED10[33]; + __IO uint32_t SYSOSCCFG; /* !< (@ 0x00001100) SYSOSC configuration */ + __IO uint32_t MCLKCFG; /* !< (@ 0x00001104) Main clock (MCLK) configuration */ + __IO uint32_t HSCLKEN; /* !< (@ 0x00001108) High-speed clock (HSCLK) source enable/disable */ + __IO uint32_t HSCLKCFG; /* !< (@ 0x0000110C) High-speed clock (HSCLK) source selection */ + __IO uint32_t HFCLKCLKCFG; /* !< (@ 0x00001110) High-frequency clock (HFCLK) configuration */ + __IO uint32_t LFCLKCFG; /* !< (@ 0x00001114) Low frequency crystal oscillator (LFXT) + configuration */ + uint32_t RESERVED11[8]; + __IO uint32_t GENCLKCFG; /* !< (@ 0x00001138) General clock configuration */ + __IO uint32_t GENCLKEN; /* !< (@ 0x0000113C) General clock enable control */ + __IO uint32_t PMODECFG; /* !< (@ 0x00001140) Power mode configuration */ + uint32_t RESERVED12[3]; + __I uint32_t FCC; /* !< (@ 0x00001150) Frequency clock counter (FCC) count */ + uint32_t RESERVED13[9]; + __IO uint32_t SRAMBOUNDARY; /* !< (@ 0x00001178) SRAM Write Boundary */ + uint32_t RESERVED14; + __IO uint32_t SYSTEMCFG; /* !< (@ 0x00001180) System configuration */ + uint32_t RESERVED15[3]; + __IO uint32_t BEEPCFG; /* !< (@ 0x00001190) BEEPER Configuration */ + uint32_t RESERVED16[27]; + __IO uint32_t WRITELOCK; /* !< (@ 0x00001200) SYSCTL register write lockout */ + __I uint32_t CLKSTATUS; /* !< (@ 0x00001204) Clock module (CKM) status */ + __I uint32_t SYSSTATUS; /* !< (@ 0x00001208) System status information */ + __I uint32_t DEDERRADDR; /* !< (@ 0x0000120C) Memory DED Address */ + uint32_t RESERVED17[4]; + __I uint32_t RSTCAUSE; /* !< (@ 0x00001220) Reset cause */ + uint32_t RESERVED18[55]; + __IO uint32_t RESETLEVEL; /* !< (@ 0x00001300) Reset level for application-triggered reset + command */ + __O uint32_t RESETCMD; /* !< (@ 0x00001304) Execute an application-triggered reset command */ + __IO uint32_t BORTHRESHOLD; /* !< (@ 0x00001308) BOR threshold selection */ + __O uint32_t BORCLRCMD; /* !< (@ 0x0000130C) Set the BOR threshold */ + __O uint32_t SYSOSCFCLCTL; /* !< (@ 0x00001310) SYSOSC frequency correction loop (FCL) ROSC enable */ + __O uint32_t LFXTCTL; /* !< (@ 0x00001314) LFXT and LFCLK control */ + __O uint32_t EXLFCTL; /* !< (@ 0x00001318) LFCLK_IN and LFCLK control */ + __O uint32_t SHDNIOREL; /* !< (@ 0x0000131C) SHUTDOWN IO release control */ + __O uint32_t EXRSTPIN; /* !< (@ 0x00001320) Disable the reset function of the NRST pin */ + __O uint32_t SYSSTATUSCLR; /* !< (@ 0x00001324) Clear sticky bits of SYSSTATUS */ + __O uint32_t SWDCFG; /* !< (@ 0x00001328) Disable the SWD function on the SWD pins */ + __O uint32_t FCCCMD; /* !< (@ 0x0000132C) Frequency clock counter start capture */ + uint32_t RESERVED19[52]; + __IO uint32_t SHUTDNSTORE0; /* !< (@ 0x00001400) Shutdown storage memory (byte 0) */ + __IO uint32_t SHUTDNSTORE1; /* !< (@ 0x00001404) Shutdown storage memory (byte 1) */ + __IO uint32_t SHUTDNSTORE2; /* !< (@ 0x00001408) Shutdown storage memory (byte 2) */ + __IO uint32_t SHUTDNSTORE3; /* !< (@ 0x0000140C) Shutdown storage memory (byte 3) */ +} SYSCTL_SOCLOCK_Regs; + +/*@}*/ /* end of group SYSCTL_SOCLOCK */ + +/** @addtogroup SYSCTL + @{ +*/ + +typedef struct { + uint32_t RESERVED0[1024]; + SYSCTL_SOCLOCK_Regs SOCLOCK; /* !< (@ 0x00001000) SYSCTL SOCLOCK Region */ + uint32_t RESERVED1[1788]; + SYSCTL_SECCFG_Regs SECCFG; /* !< (@ 0x00003000) SYSCTL SECCFG Region */ +} SYSCTL_Regs; + +/*@}*/ /* end of group SYSCTL */ + + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/****************************************************************************** +* SYSCTL Register Control Bits +******************************************************************************/ + +/* SYSCTL_FWEPROTMAIN Bits */ +/* SYSCTL_FWEPROTMAIN[DATA] Bits */ +#define SYSCTL_FWEPROTMAIN_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FWEPROTMAIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< 1 Sector Write Erase protection 1: + prohibits write-erase, 0: allows */ + +/* SYSCTL_FRXPROTMAINSTART Bits */ +/* SYSCTL_FRXPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection Start Address + 64B granularity */ + +/* SYSCTL_FRXPROTMAINEND Bits */ +/* SYSCTL_FRXPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FRXPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FRXPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash RX Protection End Address 64B + granularity */ + +/* SYSCTL_FIPPROTMAINSTART Bits */ +/* SYSCTL_FIPPROTMAINSTART[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINSTART_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection Start Address + 64B granularity */ + +/* SYSCTL_FIPPROTMAINEND Bits */ +/* SYSCTL_FIPPROTMAINEND[ADDR] Bits */ +#define SYSCTL_FIPPROTMAINEND_ADDR_OFS (6) /* !< ADDR Offset */ +#define SYSCTL_FIPPROTMAINEND_ADDR_MASK ((uint32_t)0x003FFFC0U) /* !< Flash IP Protection End Address 64B + granularity */ + +/* SYSCTL_FWENABLE Bits */ +/* SYSCTL_FWENABLE[KEY] Bits */ +#define SYSCTL_FWENABLE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FWENABLE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x76(118) for write */ +#define SYSCTL_FWENABLE_KEY_VALUE ((uint32_t)0x76000000U) /* !< Write Key */ +/* SYSCTL_FWENABLE[FLIPPROT] Bits */ +#define SYSCTL_FWENABLE_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_FWENABLE_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash Read IP ProtectionActive */ +#define SYSCTL_FWENABLE_FLIPPROT_ENABLE ((uint32_t)0x00000040U) /* !< Turn On Flash IP Protection */ +/* SYSCTL_FWENABLE[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: Blocks Writes from Changing + SRAMBOUNDARY MMR */ +#define SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE ((uint32_t)0x00000100U) /* !< SRAMBOUNDARY MMR Locked */ +/* SYSCTL_FWENABLE[FLRXPROT] Bits */ +#define SYSCTL_FWENABLE_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_FWENABLE_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_FWENABLE_FLRXPROT_ENABLE ((uint32_t)0x00000010U) /* !< Turn On Flash Read-eXecute + Protection */ + +/* SYSCTL_SECSTATUS Bits */ +/* SYSCTL_SECSTATUS[FLIPPROT] Bits */ +#define SYSCTL_SECSTATUS_FLIPPROT_OFS (6) /* !< FLIPPROT Offset */ +#define SYSCTL_SECSTATUS_FLIPPROT_MASK ((uint32_t)0x00000040U) /* !< 1: Flash IP Protection Active */ +#define SYSCTL_SECSTATUS_FLIPPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLIPPROT_ENABLED ((uint32_t)0x00000040U) +/* SYSCTL_SECSTATUS[SRAMBOUNDARYLOCK] Bits */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_OFS (8) /* !< SRAMBOUNDARYLOCK Offset */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_MASK ((uint32_t)0x00000100U) /* !< 1: SRAM Boundary MMR Locked */ +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED ((uint32_t)0x00000100U) +/* SYSCTL_SECSTATUS[FLRXPROT] Bits */ +#define SYSCTL_SECSTATUS_FLRXPROT_OFS (4) /* !< FLRXPROT Offset */ +#define SYSCTL_SECSTATUS_FLRXPROT_MASK ((uint32_t)0x00000010U) /* !< 1: Flash Read Execute Protection + Active */ +#define SYSCTL_SECSTATUS_FLRXPROT_DISABLED ((uint32_t)0x00000000U) +#define SYSCTL_SECSTATUS_FLRXPROT_ENABLED ((uint32_t)0x00000010U) +/* SYSCTL_SECSTATUS[INITDONE] Bits */ +#define SYSCTL_SECSTATUS_INITDONE_OFS (0) /* !< INITDONE Offset */ +#define SYSCTL_SECSTATUS_INITDONE_MASK ((uint32_t)0x00000001U) /* !< 1: CSC has been completed */ +#define SYSCTL_SECSTATUS_INITDONE_NO ((uint32_t)0x00000000U) /* !< INIT is not yet done */ +#define SYSCTL_SECSTATUS_INITDONE_YES ((uint32_t)0x00000001U) /* !< INIT is done */ +/* SYSCTL_SECSTATUS[CSCEXISTS] Bits */ +#define SYSCTL_SECSTATUS_CSCEXISTS_OFS (2) /* !< CSCEXISTS Offset */ +#define SYSCTL_SECSTATUS_CSCEXISTS_MASK ((uint32_t)0x00000004U) /* !< 1: CSC Exists in the system */ +#define SYSCTL_SECSTATUS_CSCEXISTS_NO ((uint32_t)0x00000000U) /* !< System does not have a CSC */ +#define SYSCTL_SECSTATUS_CSCEXISTS_YES ((uint32_t)0x00000004U) /* !< System does have a CSC */ + +/* SYSCTL_INITDONE Bits */ +/* SYSCTL_INITDONE[KEY] Bits */ +#define SYSCTL_INITDONE_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_INITDONE_KEY_MASK ((uint32_t)0xFF000000U) /* !< Must have KEY==0x9D(157) for write */ +#define SYSCTL_INITDONE_KEY_VALUE ((uint32_t)0x9D000000U) /* !< Issue Reset */ +/* SYSCTL_INITDONE[PASS] Bits */ +#define SYSCTL_INITDONE_PASS_OFS (0) /* !< PASS Offset */ +#define SYSCTL_INITDONE_PASS_MASK ((uint32_t)0x00000001U) /* !< INITCODE writes 1 for PASS, left + unwritten a timeout will occur if not + blocked */ +#define SYSCTL_INITDONE_PASS_TRUE ((uint32_t)0x00000001U) /* !< INITCODE PASS */ + +/* SYSCTL_IIDX Bits */ +/* SYSCTL_IIDX[STAT] Bits */ +#define SYSCTL_IIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_IIDX_STAT_MASK ((uint32_t)0x00000007U) /* !< The SYSCTL interrupt index (IIDX) + register generates a value + corresponding to the highest priority + pending interrupt source. This value + may be used as an address offset for + fast, deterministic handling in the + interrupt service routine. A read of + the IIDX register will clear the + corresponding interrupt status in the + RIS and MIS registers. */ +#define SYSCTL_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_IIDX_STAT_LFOSCGOOD ((uint32_t)0x00000001U) /* !< LFOSCGOOD interrupt pending */ +#define SYSCTL_IIDX_STAT_ANACLKERR ((uint32_t)0x00000002U) +#define SYSCTL_IIDX_STAT_FLASHSEC ((uint32_t)0x00000003U) +#define SYSCTL_IIDX_STAT_SRAMSEC ((uint32_t)0x00000004U) +#define SYSCTL_IIDX_STAT_LFXTGOOD ((uint32_t)0x00000005U) +#define SYSCTL_IIDX_STAT_HFCLKGOOD ((uint32_t)0x00000006U) +#define SYSCTL_IIDX_STAT_HSCLKGOOD ((uint32_t)0x00000007U) + +/* SYSCTL_IMASK Bits */ +/* SYSCTL_IMASK[LFOSCGOOD] Bits */ +#define SYSCTL_IMASK_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_IMASK_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Enable or disable the LFOSCGOOD + interrupt. LFOSCGOOD indicates that + the LFOSC has started successfully. */ +#define SYSCTL_IMASK_LFOSCGOOD_DISABLE ((uint32_t)0x00000000U) /* !< Interrupt disabled */ +#define SYSCTL_IMASK_LFOSCGOOD_ENABLE ((uint32_t)0x00000001U) /* !< Interrupt enabled */ +/* SYSCTL_IMASK[HFCLKGOOD] Bits */ +#define SYSCTL_IMASK_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_IMASK_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_IMASK_HFCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HFCLKGOOD_ENABLE ((uint32_t)0x00000020U) +/* SYSCTL_IMASK[SRAMSEC] Bits */ +#define SYSCTL_IMASK_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_IMASK_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_IMASK_SRAMSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_SRAMSEC_ENABLE ((uint32_t)0x00000008U) +/* SYSCTL_IMASK[HSCLKGOOD] Bits */ +#define SYSCTL_IMASK_HSCLKGOOD_OFS (6) /* !< HSCLKGOOD Offset */ +#define SYSCTL_IMASK_HSCLKGOOD_MASK ((uint32_t)0x00000040U) /* !< HSCLK GOOD */ +#define SYSCTL_IMASK_HSCLKGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_HSCLKGOOD_ENABLE ((uint32_t)0x00000040U) +/* SYSCTL_IMASK[ANACLKERR] Bits */ +#define SYSCTL_IMASK_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_IMASK_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_IMASK_ANACLKERR_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_ANACLKERR_ENABLE ((uint32_t)0x00000002U) +/* SYSCTL_IMASK[FLASHSEC] Bits */ +#define SYSCTL_IMASK_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_IMASK_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_IMASK_FLASHSEC_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_FLASHSEC_ENABLE ((uint32_t)0x00000004U) +/* SYSCTL_IMASK[LFXTGOOD] Bits */ +#define SYSCTL_IMASK_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_IMASK_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_IMASK_LFXTGOOD_DISABLE ((uint32_t)0x00000000U) +#define SYSCTL_IMASK_LFXTGOOD_ENABLE ((uint32_t)0x00000010U) + +/* SYSCTL_RIS Bits */ +/* SYSCTL_RIS[LFOSCGOOD] Bits */ +#define SYSCTL_RIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_RIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Raw status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_RIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_RIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_RIS[HFCLKGOOD] Bits */ +#define SYSCTL_RIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_RIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_RIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_RIS[SRAMSEC] Bits */ +#define SYSCTL_RIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_RIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_RIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_RIS[HSCLKGOOD] Bits */ +#define SYSCTL_RIS_HSCLKGOOD_OFS (6) /* !< HSCLKGOOD Offset */ +#define SYSCTL_RIS_HSCLKGOOD_MASK ((uint32_t)0x00000040U) /* !< HSCLK GOOD */ +#define SYSCTL_RIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_HSCLKGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_RIS[ANACLKERR] Bits */ +#define SYSCTL_RIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_RIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_RIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_RIS[FLASHSEC] Bits */ +#define SYSCTL_RIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_RIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_RIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_RIS[LFXTGOOD] Bits */ +#define SYSCTL_RIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_RIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_RIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_RIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) + +/* SYSCTL_MIS Bits */ +/* SYSCTL_MIS[LFOSCGOOD] Bits */ +#define SYSCTL_MIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_MIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Masked status of the LFOSCGOOD + interrupt. */ +#define SYSCTL_MIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_MIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_MIS[HFCLKGOOD] Bits */ +#define SYSCTL_MIS_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_MIS_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_MIS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HFCLKGOOD_TRUE ((uint32_t)0x00000020U) +/* SYSCTL_MIS[SRAMSEC] Bits */ +#define SYSCTL_MIS_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_MIS_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_MIS_SRAMSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_SRAMSEC_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_MIS[HSCLKGOOD] Bits */ +#define SYSCTL_MIS_HSCLKGOOD_OFS (6) /* !< HSCLKGOOD Offset */ +#define SYSCTL_MIS_HSCLKGOOD_MASK ((uint32_t)0x00000040U) /* !< HSCLK GOOD */ +#define SYSCTL_MIS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_HSCLKGOOD_TRUE ((uint32_t)0x00000040U) +/* SYSCTL_MIS[ANACLKERR] Bits */ +#define SYSCTL_MIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_MIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_MIS_ANACLKERR_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_ANACLKERR_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_MIS[FLASHSEC] Bits */ +#define SYSCTL_MIS_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_MIS_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_MIS_FLASHSEC_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_FLASHSEC_TRUE ((uint32_t)0x00000004U) +/* SYSCTL_MIS[LFXTGOOD] Bits */ +#define SYSCTL_MIS_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_MIS_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_MIS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_MIS_LFXTGOOD_TRUE ((uint32_t)0x00000010U) + +/* SYSCTL_ISET Bits */ +/* SYSCTL_ISET[LFOSCGOOD] Bits */ +#define SYSCTL_ISET_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ISET_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Set the LFOSCGOOD interrupt. */ +#define SYSCTL_ISET_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_ISET_LFOSCGOOD_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_ISET[HFCLKGOOD] Bits */ +#define SYSCTL_ISET_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ISET_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ISET_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HFCLKGOOD_SET ((uint32_t)0x00000020U) +/* SYSCTL_ISET[SRAMSEC] Bits */ +#define SYSCTL_ISET_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ISET_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ISET_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_SRAMSEC_SET ((uint32_t)0x00000008U) +/* SYSCTL_ISET[HSCLKGOOD] Bits */ +#define SYSCTL_ISET_HSCLKGOOD_OFS (6) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ISET_HSCLKGOOD_MASK ((uint32_t)0x00000040U) /* !< HSCLK GOOD */ +#define SYSCTL_ISET_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_HSCLKGOOD_SET ((uint32_t)0x00000040U) +/* SYSCTL_ISET[ANACLKERR] Bits */ +#define SYSCTL_ISET_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ISET_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ISET_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_ANACLKERR_SET ((uint32_t)0x00000002U) +/* SYSCTL_ISET[FLASHSEC] Bits */ +#define SYSCTL_ISET_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ISET_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ISET_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_FLASHSEC_SET ((uint32_t)0x00000004U) +/* SYSCTL_ISET[LFXTGOOD] Bits */ +#define SYSCTL_ISET_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ISET_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ISET_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ISET_LFXTGOOD_SET ((uint32_t)0x00000010U) + +/* SYSCTL_ICLR Bits */ +/* SYSCTL_ICLR[LFOSCGOOD] Bits */ +#define SYSCTL_ICLR_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */ +#define SYSCTL_ICLR_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Clear the LFOSCGOOD interrupt. */ +#define SYSCTL_ICLR_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h has no effect */ +#define SYSCTL_ICLR_LFOSCGOOD_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_ICLR[HFCLKGOOD] Bits */ +#define SYSCTL_ICLR_HFCLKGOOD_OFS (5) /* !< HFCLKGOOD Offset */ +#define SYSCTL_ICLR_HFCLKGOOD_MASK ((uint32_t)0x00000020U) /* !< HFCLK GOOD */ +#define SYSCTL_ICLR_HFCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HFCLKGOOD_CLR ((uint32_t)0x00000020U) +/* SYSCTL_ICLR[SRAMSEC] Bits */ +#define SYSCTL_ICLR_SRAMSEC_OFS (3) /* !< SRAMSEC Offset */ +#define SYSCTL_ICLR_SRAMSEC_MASK ((uint32_t)0x00000008U) /* !< SRAM Single Error Correct */ +#define SYSCTL_ICLR_SRAMSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_SRAMSEC_CLR ((uint32_t)0x00000008U) +/* SYSCTL_ICLR[HSCLKGOOD] Bits */ +#define SYSCTL_ICLR_HSCLKGOOD_OFS (6) /* !< HSCLKGOOD Offset */ +#define SYSCTL_ICLR_HSCLKGOOD_MASK ((uint32_t)0x00000040U) /* !< HSCLK GOOD */ +#define SYSCTL_ICLR_HSCLKGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_HSCLKGOOD_CLR ((uint32_t)0x00000040U) +/* SYSCTL_ICLR[ANACLKERR] Bits */ +#define SYSCTL_ICLR_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */ +#define SYSCTL_ICLR_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */ +#define SYSCTL_ICLR_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_ANACLKERR_CLR ((uint32_t)0x00000002U) +/* SYSCTL_ICLR[FLASHSEC] Bits */ +#define SYSCTL_ICLR_FLASHSEC_OFS (2) /* !< FLASHSEC Offset */ +#define SYSCTL_ICLR_FLASHSEC_MASK ((uint32_t)0x00000004U) /* !< Flash Single Error Correct */ +#define SYSCTL_ICLR_FLASHSEC_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_FLASHSEC_CLR ((uint32_t)0x00000004U) +/* SYSCTL_ICLR[LFXTGOOD] Bits */ +#define SYSCTL_ICLR_LFXTGOOD_OFS (4) /* !< LFXTGOOD Offset */ +#define SYSCTL_ICLR_LFXTGOOD_MASK ((uint32_t)0x00000010U) /* !< LFXT GOOD */ +#define SYSCTL_ICLR_LFXTGOOD_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_ICLR_LFXTGOOD_CLR ((uint32_t)0x00000010U) + +/* SYSCTL_NMIIIDX Bits */ +/* SYSCTL_NMIIIDX[STAT] Bits */ +#define SYSCTL_NMIIIDX_STAT_OFS (0) /* !< STAT Offset */ +#define SYSCTL_NMIIIDX_STAT_MASK ((uint32_t)0x00000007U) /* !< The NMI interrupt index (NMIIIDX) + register generates a value + corresponding to the highest priority + pending NMI source. This value may + be used as an address offset for + fast, deterministic handling in the + NMI service routine. A read of the + NMIIIDX register will clear the + corresponding interrupt status in the + NMIRIS register. */ +#define SYSCTL_NMIIIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No NMI pending */ +#define SYSCTL_NMIIIDX_STAT_BORLVL ((uint32_t)0x00000001U) /* !< BOR Threshold NMI pending */ +#define SYSCTL_NMIIIDX_STAT_WWDT0 ((uint32_t)0x00000002U) +#define SYSCTL_NMIIIDX_STAT_LFCLKFAIL ((uint32_t)0x00000003U) +#define SYSCTL_NMIIIDX_STAT_FLASHDED ((uint32_t)0x00000004U) +#define SYSCTL_NMIIIDX_STAT_SRAMDED ((uint32_t)0x00000005U) + +/* SYSCTL_NMIRIS Bits */ +/* SYSCTL_NMIRIS[SRAMDED] Bits */ +#define SYSCTL_NMIRIS_SRAMDED_OFS (4) /* !< SRAMDED Offset */ +#define SYSCTL_NMIRIS_SRAMDED_MASK ((uint32_t)0x00000010U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIRIS_SRAMDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_SRAMDED_TRUE ((uint32_t)0x00000010U) +/* SYSCTL_NMIRIS[BORLVL] Bits */ +#define SYSCTL_NMIRIS_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIRIS_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Raw status of the BORLVL NMI */ +#define SYSCTL_NMIRIS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */ +#define SYSCTL_NMIRIS_BORLVL_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */ +/* SYSCTL_NMIRIS[FLASHDED] Bits */ +#define SYSCTL_NMIRIS_FLASHDED_OFS (3) /* !< FLASHDED Offset */ +#define SYSCTL_NMIRIS_FLASHDED_MASK ((uint32_t)0x00000008U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIRIS_FLASHDED_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_FLASHDED_TRUE ((uint32_t)0x00000008U) +/* SYSCTL_NMIRIS[WWDT0] Bits */ +#define SYSCTL_NMIRIS_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIRIS_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIRIS_WWDT0_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_WWDT0_TRUE ((uint32_t)0x00000002U) +/* SYSCTL_NMIRIS[LFCLKFAIL] Bits */ +#define SYSCTL_NMIRIS_LFCLKFAIL_OFS (2) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIRIS_LFCLKFAIL_MASK ((uint32_t)0x00000004U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIRIS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_NMIRIS_LFCLKFAIL_TRUE ((uint32_t)0x00000004U) + +/* SYSCTL_NMIISET Bits */ +/* SYSCTL_NMIISET[SRAMDED] Bits */ +#define SYSCTL_NMIISET_SRAMDED_OFS (4) /* !< SRAMDED Offset */ +#define SYSCTL_NMIISET_SRAMDED_MASK ((uint32_t)0x00000010U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIISET_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_SRAMDED_SET ((uint32_t)0x00000010U) +/* SYSCTL_NMIISET[BORLVL] Bits */ +#define SYSCTL_NMIISET_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIISET_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Set the BORLVL NMI */ +#define SYSCTL_NMIISET_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIISET_BORLVL_SET ((uint32_t)0x00000001U) /* !< Set interrupt */ +/* SYSCTL_NMIISET[FLASHDED] Bits */ +#define SYSCTL_NMIISET_FLASHDED_OFS (3) /* !< FLASHDED Offset */ +#define SYSCTL_NMIISET_FLASHDED_MASK ((uint32_t)0x00000008U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIISET_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_FLASHDED_SET ((uint32_t)0x00000008U) +/* SYSCTL_NMIISET[WWDT0] Bits */ +#define SYSCTL_NMIISET_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIISET_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIISET_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_WWDT0_SET ((uint32_t)0x00000002U) +/* SYSCTL_NMIISET[LFCLKFAIL] Bits */ +#define SYSCTL_NMIISET_LFCLKFAIL_OFS (2) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIISET_LFCLKFAIL_MASK ((uint32_t)0x00000004U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIISET_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIISET_LFCLKFAIL_SET ((uint32_t)0x00000004U) + +/* SYSCTL_NMIICLR Bits */ +/* SYSCTL_NMIICLR[SRAMDED] Bits */ +#define SYSCTL_NMIICLR_SRAMDED_OFS (4) /* !< SRAMDED Offset */ +#define SYSCTL_NMIICLR_SRAMDED_MASK ((uint32_t)0x00000010U) /* !< SRAM Double Error Detect */ +#define SYSCTL_NMIICLR_SRAMDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_SRAMDED_CLR ((uint32_t)0x00000010U) +/* SYSCTL_NMIICLR[BORLVL] Bits */ +#define SYSCTL_NMIICLR_BORLVL_OFS (0) /* !< BORLVL Offset */ +#define SYSCTL_NMIICLR_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Clr the BORLVL NMI */ +#define SYSCTL_NMIICLR_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */ +#define SYSCTL_NMIICLR_BORLVL_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */ +/* SYSCTL_NMIICLR[FLASHDED] Bits */ +#define SYSCTL_NMIICLR_FLASHDED_OFS (3) /* !< FLASHDED Offset */ +#define SYSCTL_NMIICLR_FLASHDED_MASK ((uint32_t)0x00000008U) /* !< Flash Double Error Detect */ +#define SYSCTL_NMIICLR_FLASHDED_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_FLASHDED_CLR ((uint32_t)0x00000008U) +/* SYSCTL_NMIICLR[WWDT0] Bits */ +#define SYSCTL_NMIICLR_WWDT0_OFS (1) /* !< WWDT0 Offset */ +#define SYSCTL_NMIICLR_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */ +#define SYSCTL_NMIICLR_WWDT0_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_WWDT0_CLR ((uint32_t)0x00000002U) +/* SYSCTL_NMIICLR[LFCLKFAIL] Bits */ +#define SYSCTL_NMIICLR_LFCLKFAIL_OFS (2) /* !< LFCLKFAIL Offset */ +#define SYSCTL_NMIICLR_LFCLKFAIL_MASK ((uint32_t)0x00000004U) /* !< LFXT-EXLF Monitor Fail */ +#define SYSCTL_NMIICLR_LFCLKFAIL_NO_EFFECT ((uint32_t)0x00000000U) +#define SYSCTL_NMIICLR_LFCLKFAIL_CLR ((uint32_t)0x00000004U) + +/* SYSCTL_SYSOSCCFG Bits */ +/* SYSCTL_SYSOSCCFG[DISABLESTOP] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_OFS (9) /* !< DISABLESTOP Offset */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_MASK ((uint32_t)0x00000200U) /* !< DISABLESTOP sets the SYSOSC stop + mode enable/disable policy. When + operating in STOP mode, the SYSOSC + may be automatically disabled. When + set, ULPCLK will run from LFCLK in + STOP mode and SYSOSC will be disabled + to reduce power consumption. */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC in STOP mode */ +#define SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE ((uint32_t)0x00000200U) /* !< Disable SYSOSC in STOP mode and + source ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[BLOCKASYNCALL] Bits */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_OFS (16) /* !< BLOCKASYNCALL Offset */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_MASK ((uint32_t)0x00010000U) /* !< BLOCKASYNCALL may be used to mask + block all asynchronous fast clock + requests, preventing hardware from + dynamically changing the active clock + configuration when operating in a + given mode. */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_DISABLE ((uint32_t)0x00000000U) /* !< Asynchronous fast clock requests + are controlled by the requesting + peripheral */ +#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE ((uint32_t)0x00010000U) /* !< All asynchronous fast clock + requests are blocked */ +/* SYSCTL_SYSOSCCFG[DISABLE] Bits */ +#define SYSCTL_SYSOSCCFG_DISABLE_OFS (10) /* !< DISABLE Offset */ +#define SYSCTL_SYSOSCCFG_DISABLE_MASK ((uint32_t)0x00000400U) /* !< DISABLE sets the SYSOSC + enable/disable policy. SYSOSC may be + powered off in RUN, SLEEP, and STOP + modes to reduce power consumption. + When SYSOSC is disabled, MCLK and + ULPCLK are sourced from LFCLK. */ +#define SYSCTL_SYSOSCCFG_DISABLE_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC */ +#define SYSCTL_SYSOSCCFG_DISABLE_ENABLE ((uint32_t)0x00000400U) /* !< Disable SYSOSC immediately and + source MCLK and ULPCLK from LFCLK */ +/* SYSCTL_SYSOSCCFG[FASTCPUEVENT] Bits */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_OFS (17) /* !< FASTCPUEVENT Offset */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_MASK ((uint32_t)0x00020000U) /* !< FASTCPUEVENT may be used to assert + a fast clock request when an + interrupt is asserted to the CPU, + reducing interrupt latency. */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_DISABLE ((uint32_t)0x00000000U) /* !< An interrupt to the CPU will not + assert a fast clock request */ +#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE ((uint32_t)0x00020000U) /* !< An interrupt to the CPU will assert + a fast clock request */ +/* SYSCTL_SYSOSCCFG[FREQ] Bits */ +#define SYSCTL_SYSOSCCFG_FREQ_OFS (0) /* !< FREQ Offset */ +#define SYSCTL_SYSOSCCFG_FREQ_MASK ((uint32_t)0x00000003U) /* !< Target operating frequency for the + system oscillator (SYSOSC) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE ((uint32_t)0x00000000U) /* !< Base frequency (32MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< Low frequency (4MHz) */ +#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< User-trimmed frequency (16 or 24 + MHz) */ + +/* SYSCTL_MCLKCFG Bits */ +/* SYSCTL_MCLKCFG[USEMFTICK] Bits */ +#define SYSCTL_MCLKCFG_USEMFTICK_OFS (12) /* !< USEMFTICK Offset */ +#define SYSCTL_MCLKCFG_USEMFTICK_MASK ((uint32_t)0x00001000U) /* !< USEMFTICK specifies whether the + 4MHz constant-rate clock (MFCLK) to + peripherals is enabled or disabled. + When enabled, MDIV must be disabled + (set to 0h=/1). */ +#define SYSCTL_MCLKCFG_USEMFTICK_DISABLE ((uint32_t)0x00000000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled */ +#define SYSCTL_MCLKCFG_USEMFTICK_ENABLE ((uint32_t)0x00001000U) /* !< The 4MHz rate MFCLK to peripherals + is enabled. */ +/* SYSCTL_MCLKCFG[MDIV] Bits */ +#define SYSCTL_MCLKCFG_MDIV_OFS (0) /* !< MDIV Offset */ +#define SYSCTL_MCLKCFG_MDIV_MASK ((uint32_t)0x0000000FU) /* !< MDIV may be used to divide the MCLK + frequency when MCLK is sourced from + SYSOSC. MDIV=0h corresponds to /1 + (no divider). MDIV=1h corresponds to + /2 (divide-by-2). MDIV=Fh + corresponds to /16 (divide-by-16). + MDIV may be set between /1 and /16 on + an integer basis. */ +/* SYSCTL_MCLKCFG[USEHSCLK] Bits */ +#define SYSCTL_MCLKCFG_USEHSCLK_OFS (16) /* !< USEHSCLK Offset */ +#define SYSCTL_MCLKCFG_USEHSCLK_MASK ((uint32_t)0x00010000U) /* !< USEHSCLK, together with USELFCLK, + sets the MCLK source policy. Set + USEHSCLK to use HSCLK (HFCLK or + SYSPLL) as the MCLK source in RUN and + SLEEP modes. */ +#define SYSCTL_MCLKCFG_USEHSCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the high speed + clock (HSCLK) */ +#define SYSCTL_MCLKCFG_USEHSCLK_ENABLE ((uint32_t)0x00010000U) /* !< MCLK will use the high speed clock + (HSCLK) in RUN and SLEEP mode */ +/* SYSCTL_MCLKCFG[USELFCLK] Bits */ +#define SYSCTL_MCLKCFG_USELFCLK_OFS (20) /* !< USELFCLK Offset */ +#define SYSCTL_MCLKCFG_USELFCLK_MASK ((uint32_t)0x00100000U) /* !< USELFCLK sets the MCLK source + policy. Set USELFCLK to use LFCLK as + the MCLK source. Note that setting + USELFCLK does not disable SYSOSC, and + SYSOSC remains available for direct + use by analog modules. */ +#define SYSCTL_MCLKCFG_USELFCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the low frequency + clock (LFCLK) */ +#define SYSCTL_MCLKCFG_USELFCLK_ENABLE ((uint32_t)0x00100000U) /* !< MCLK will use the low frequency + clock (LFCLK) */ +/* SYSCTL_MCLKCFG[STOPCLKSTBY] Bits */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_OFS (21) /* !< STOPCLKSTBY Offset */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_MASK ((uint32_t)0x00200000U) /* !< STOPCLKSTBY sets the STANDBY mode + policy (STANDBY0 or STANDBY1). When + set, ULPCLK and LFCLK are disabled to + all peripherals in STANDBY mode, with + the exception of TIMG0 and TIMG1 + which continue to run. Wake-up is + only possible via an asynchronous + fast clock request. */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_DISABLE ((uint32_t)0x00000000U) /* !< ULPCLK/LFCLK runs to all PD0 + peripherals in STANDBY mode */ +#define SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE ((uint32_t)0x00200000U) /* !< ULPCLK/LFCLK is disabled to all + peripherals in STANDBY mode except + TIMG0 and TIMG1 */ +/* SYSCTL_MCLKCFG[FLASHWAIT] Bits */ +#define SYSCTL_MCLKCFG_FLASHWAIT_OFS (8) /* !< FLASHWAIT Offset */ +#define SYSCTL_MCLKCFG_FLASHWAIT_MASK ((uint32_t)0x00000F00U) /* !< FLASHWAIT specifies the number of + flash wait states when MCLK is + sourced from HSCLK. FLASHWAIT has no + effect when MCLK is sourced from + SYSOSC or LFCLK. */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT0 ((uint32_t)0x00000000U) /* !< No flash wait states are applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT1 ((uint32_t)0x00000100U) /* !< One flash wait state is applied */ +#define SYSCTL_MCLKCFG_FLASHWAIT_WAIT2 ((uint32_t)0x00000200U) /* !< 2 flash wait states are applied */ +/* SYSCTL_MCLKCFG[MCLKDEADCHK] Bits */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_OFS (22) /* !< MCLKDEADCHK Offset */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_MASK ((uint32_t)0x00400000U) /* !< MCLKDEADCHK enables or disables the + continuous MCLK dead check monitor. + LFCLK must be running before + MCLKDEADCHK is enabled. */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_DISABLE ((uint32_t)0x00000000U) /* !< The MCLK dead check monitor is + disabled */ +#define SYSCTL_MCLKCFG_MCLKDEADCHK_ENABLE ((uint32_t)0x00400000U) /* !< The MCLK dead check monitor is + enabled */ + +/* SYSCTL_HSCLKEN Bits */ +/* SYSCTL_HSCLKEN[HFXTEN] Bits */ +#define SYSCTL_HSCLKEN_HFXTEN_OFS (0) /* !< HFXTEN Offset */ +#define SYSCTL_HSCLKEN_HFXTEN_MASK ((uint32_t)0x00000001U) /* !< HFXTEN enables or disables the high + frequency crystal oscillator (HFXT). */ +#define SYSCTL_HSCLKEN_HFXTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable the HFXT */ +#define SYSCTL_HSCLKEN_HFXTEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable the HFXT */ +/* SYSCTL_HSCLKEN[USEEXTHFCLK] Bits */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_OFS (16) /* !< USEEXTHFCLK Offset */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_MASK ((uint32_t)0x00010000U) /* !< USEEXTHFCLK selects the HFCLK_IN + digital clock input to be the source + for HFCLK. When disabled, HFXT is + the HFCLK source and HFXTEN may be + set. Do not set HFXTEN and + USEEXTHFCLK simultaneously. */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_DISABLE ((uint32_t)0x00000000U) /* !< Use HFXT as the HFCLK source */ +#define SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE ((uint32_t)0x00010000U) /* !< Use the HFCLK_IN digital clock + input as the HFCLK source */ + +/* SYSCTL_HSCLKCFG Bits */ +/* SYSCTL_HSCLKCFG[USBFLL4HSCLK] Bits */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_OFS (1) /* !< USBFLL4HSCLK Offset */ +#define SYSCTL_HSCLKCFG_USBFLL4HSCLK_MASK ((uint32_t)0x00000002U) /* !< USBFLL4HSCLK selects the USBFLL as + High Speed clock source */ +/* SYSCTL_HSCLKCFG[HSCLKSEL] Bits */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_OFS (0) /* !< HSCLKSEL Offset */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_MASK ((uint32_t)0x00000001U) /* !< HSCLKSEL selects the HSCLK source + (SYSPLL or HFCLK). */ +#define SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK ((uint32_t)0x00000001U) /* !< HSCLK is sourced from the HFCLK */ + +/* SYSCTL_HFCLKCLKCFG Bits */ +/* SYSCTL_HFCLKCLKCFG[HFXTTIME] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_OFS (0) /* !< HFXTTIME Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK ((uint32_t)0x000000FFU) /* !< HFXTTIME specifies the HFXT startup + time in 64us resolution. If the + HFCLK startup monitor is enabled + (HFCLKFLTCHK), HFXT will be checked + after this time expires. */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MINSTARTTIME ((uint32_t)0x00000000U) /* !< Minimum startup time (approximatly + zero) */ +#define SYSCTL_HFCLKCLKCFG_HFXTTIME_MAXSTARTTIME ((uint32_t)0x000000FFU) /* !< Maximum startup time (approximatly + 16.32ms) */ +/* SYSCTL_HFCLKCLKCFG[HFCLKFLTCHK] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_OFS (28) /* !< HFCLKFLTCHK Offset */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK ((uint32_t)0x10000000U) /* !< HFCLKFLTCHK enables or disables the + HFCLK startup monitor. */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_DISABLE ((uint32_t)0x00000000U) /* !< HFCLK startup is not checked */ +#define SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE ((uint32_t)0x10000000U) /* !< HFCLK startup is checked */ +/* SYSCTL_HFCLKCLKCFG[HFXTRSEL] Bits */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS (12) /* !< HFXTRSEL Offset */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK ((uint32_t)0x00003000U) /* !< HFXT Range Select */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8 ((uint32_t)0x00000000U) /* !< 4MHz <= HFXT frequency <= 8MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16 ((uint32_t)0x00001000U) /* !< 8MHz < HFXT frequency <= 16MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32 ((uint32_t)0x00002000U) /* !< 16MHz < HFXT frequency <= 32MHz */ +#define SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48 ((uint32_t)0x00003000U) /* !< 32MHz < HFXT frequency <= 48MHz */ + +/* SYSCTL_LFCLKCFG Bits */ +/* SYSCTL_LFCLKCFG[XT1DRIVE] Bits */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_OFS (0) /* !< XT1DRIVE Offset */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_MASK ((uint32_t)0x00000003U) /* !< XT1DRIVE selects the low frequency + crystal oscillator (LFXT) drive + strength. */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV ((uint32_t)0x00000000U) /* !< Lowest drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV ((uint32_t)0x00000001U) /* !< Lower drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV ((uint32_t)0x00000002U) /* !< Higher drive and current */ +#define SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV ((uint32_t)0x00000003U) /* !< Highest drive and current */ +/* SYSCTL_LFCLKCFG[MONITOR] Bits */ +#define SYSCTL_LFCLKCFG_MONITOR_OFS (4) /* !< MONITOR Offset */ +#define SYSCTL_LFCLKCFG_MONITOR_MASK ((uint32_t)0x00000010U) /* !< MONITOR enables or disables the + LFCLK monitor, which continuously + checks LFXT or LFCLK_IN for a clock + stuck fault. */ +#define SYSCTL_LFCLKCFG_MONITOR_DISABLE ((uint32_t)0x00000000U) /* !< Clock monitor is disabled */ +#define SYSCTL_LFCLKCFG_MONITOR_ENABLE ((uint32_t)0x00000010U) /* !< Clock monitor is enabled */ +/* SYSCTL_LFCLKCFG[LOWCAP] Bits */ +#define SYSCTL_LFCLKCFG_LOWCAP_OFS (8) /* !< LOWCAP Offset */ +#define SYSCTL_LFCLKCFG_LOWCAP_MASK ((uint32_t)0x00000100U) /* !< LOWCAP controls the low-power LFXT + mode. When the LFXT load capacitance + is less than 3pf, LOWCAP may be set + for reduced power consumption. */ +#define SYSCTL_LFCLKCFG_LOWCAP_DISABLE ((uint32_t)0x00000000U) /* !< LFXT low capacitance mode is + disabled */ +#define SYSCTL_LFCLKCFG_LOWCAP_ENABLE ((uint32_t)0x00000100U) /* !< LFXT low capacitance mode is + enabled */ + +/* SYSCTL_GENCLKCFG Bits */ +/* SYSCTL_GENCLKCFG[HFCLK4MFPCLKDIV] Bits */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS (12) /* !< HFCLK4MFPCLKDIV Offset */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK ((uint32_t)0x0000F000U) /* !< HFCLK4MFPCLKDIV selects the divider + applied to HFCLK when HFCLK is used + as the MFPCLK source. Integer + dividers from /1 to /16 may be + selected. */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV1 ((uint32_t)0x00000000U) /* !< HFCLK is not divided before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV2 ((uint32_t)0x00001000U) /* !< HFCLK is divided by 2 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV3 ((uint32_t)0x00002000U) /* !< HFCLK is divided by 3 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV4 ((uint32_t)0x00003000U) /* !< HFCLK is divided by 4 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV5 ((uint32_t)0x00004000U) /* !< HFCLK is divided by 5 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV6 ((uint32_t)0x00005000U) /* !< HFCLK is divided by 6 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV7 ((uint32_t)0x00006000U) /* !< HFCLK is divided by 7 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV8 ((uint32_t)0x00007000U) /* !< HFCLK is divided by 8 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV9 ((uint32_t)0x00008000U) /* !< HFCLK is divided by 9 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV10 ((uint32_t)0x00009000U) /* !< HFCLK is divided by 10 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV11 ((uint32_t)0x0000A000U) /* !< HFCLK is divided by 11 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV12 ((uint32_t)0x0000B000U) /* !< HFCLK is divided by 12 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV13 ((uint32_t)0x0000C000U) /* !< HFCLK is divided by 13 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV14 ((uint32_t)0x0000D000U) /* !< HFCLK is divided by 14 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV15 ((uint32_t)0x0000E000U) /* !< HFCLK is divided by 15 before being + used for MFPCLK */ +#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV16 ((uint32_t)0x0000F000U) /* !< HFCLK is divided by 16 before being + used for MFPCLK */ +/* SYSCTL_GENCLKCFG[MFPCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_OFS (9) /* !< MFPCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_MASK ((uint32_t)0x00000200U) /* !< MFPCLKSRC selects the MFPCLK + (middle frequency precision clock) + source. */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< MFPCLK is sourced from SYSOSC */ +#define SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK ((uint32_t)0x00000200U) /* !< MFPCLK is sourced from HFCLK */ +/* SYSCTL_GENCLKCFG[FCCLFCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_OFS (29) /* !< FCCLFCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCLFCLKSRC_MASK ((uint32_t)0x20000000U) /* !< FCCLFCLKSRC selects between SYSTEM + LFCLK and EXTERNAL SOURCED LFCLK. */ +/* SYSCTL_GENCLKCFG[FCCTRIGCNT] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS (24) /* !< FCCTRIGCNT Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK ((uint32_t)0x1F000000U) /* !< FCCTRIGCNT specifies the number of + trigger clock periods in the trigger + window. FCCTRIGCNT=0h (one trigger + clock period) up to 1Fh (32 trigger + clock periods) may be specified. */ +/* SYSCTL_GENCLKCFG[ANACPUMPCFG] Bits */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_OFS (22) /* !< ANACPUMPCFG Offset */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK ((uint32_t)0x00C00000U) /* !< ANACPUMPCFG selects the analog mux + charge pump (VBOOST) enable method. */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND ((uint32_t)0x00000000U) /* !< VBOOST is enabled on request from a + COMP, GPAMP, or OPA */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE ((uint32_t)0x00400000U) /* !< VBOOST is enabled when the device + is in RUN or SLEEP mode, or when a + COMP/GPAMP/OPA is enabled */ +#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS ((uint32_t)0x00800000U) /* !< VBOOST is always enabled */ +/* SYSCTL_GENCLKCFG[FCCTRIGSRC] Bits */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_OFS (20) /* !< FCCTRIGSRC Offset */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK ((uint32_t)0x00100000U) /* !< FCCTRIGSRC selects the frequency + clock counter (FCC) trigger source. */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN ((uint32_t)0x00000000U) /* !< FCC trigger is the external pin */ +#define SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK ((uint32_t)0x00100000U) /* !< FCC trigger is the LFCLK */ +/* SYSCTL_GENCLKCFG[FCCSELCLK] Bits */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_OFS (16) /* !< FCCSELCLK Offset */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MASK ((uint32_t)0x000F0000U) /* !< FCCSELCLK selectes the frequency + clock counter (FCC) clock source. */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_MCLK ((uint32_t)0x00000000U) /* !< FCC clock is MCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC ((uint32_t)0x00010000U) /* !< FCC clock is SYSOSC */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK ((uint32_t)0x00020000U) /* !< FCC clock is HFCLK */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK ((uint32_t)0x00030000U) /* !< FCC clock is the CLK_OUT selection */ +#define SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN ((uint32_t)0x00070000U) /* !< FCC clock is the FCCIN external + input */ +/* SYSCTL_GENCLKCFG[FCCLVLTRIG] Bits */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_OFS (21) /* !< FCCLVLTRIG Offset */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK ((uint32_t)0x00200000U) /* !< FCCLVLTRIG selects the frequency + clock counter (FCC) trigger mode. */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE ((uint32_t)0x00000000U) /* !< Rising edge to rising edge + triggered */ +#define SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL ((uint32_t)0x00200000U) /* !< Level triggered */ +/* SYSCTL_GENCLKCFG[EXCLKSRC] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_OFS (0) /* !< EXCLKSRC Offset */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MASK ((uint32_t)0x00000007U) /* !< EXCLKSRC selects the source for the + CLK_OUT external clock output block. + ULPCLK and MFPCLK require the CLK_OUT + divider (EXCLKDIVEN) to be enabled */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< CLK_OUT is SYSOSC */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK ((uint32_t)0x00000001U) /* !< CLK_OUT is ULPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK ((uint32_t)0x00000002U) /* !< CLK_OUT is LFCLK */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK ((uint32_t)0x00000003U) /* !< CLK_OUT is MFPCLK (EXCLKDIVEN must + be enabled) */ +#define SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK ((uint32_t)0x00000004U) /* !< CLK_OUT is HFCLK */ +/* SYSCTL_GENCLKCFG[EXCLKDIVVAL] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_OFS (4) /* !< EXCLKDIVVAL Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK ((uint32_t)0x00000070U) /* !< EXCLKDIVVAL selects the divider + value for the divider in the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2 ((uint32_t)0x00000000U) /* !< CLK_OUT source is divided by 2 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4 ((uint32_t)0x00000010U) /* !< CLK_OUT source is divided by 4 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6 ((uint32_t)0x00000020U) /* !< CLK_OUT source is divided by 6 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8 ((uint32_t)0x00000030U) /* !< CLK_OUT source is divided by 8 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10 ((uint32_t)0x00000040U) /* !< CLK_OUT source is divided by 10 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12 ((uint32_t)0x00000050U) /* !< CLK_OUT source is divided by 12 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14 ((uint32_t)0x00000060U) /* !< CLK_OUT source is divided by 14 */ +#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16 ((uint32_t)0x00000070U) /* !< CLK_OUT source is divided by 16 */ +/* SYSCTL_GENCLKCFG[EXCLKDIVEN] Bits */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_OFS (7) /* !< EXCLKDIVEN Offset */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK ((uint32_t)0x00000080U) /* !< EXCLKDIVEN enables or disables the + divider function of the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU ((uint32_t)0x00000000U) /* !< CLock divider is disabled + (passthrough, EXCLKDIVVAL is not + applied) */ +#define SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE ((uint32_t)0x00000080U) /* !< Clock divider is enabled + (EXCLKDIVVAL is applied) */ + +/* SYSCTL_GENCLKEN Bits */ +/* SYSCTL_GENCLKEN[EXCLKEN] Bits */ +#define SYSCTL_GENCLKEN_EXCLKEN_OFS (0) /* !< EXCLKEN Offset */ +#define SYSCTL_GENCLKEN_EXCLKEN_MASK ((uint32_t)0x00000001U) /* !< EXCLKEN enables the CLK_OUT + external clock output block. */ +#define SYSCTL_GENCLKEN_EXCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< CLK_OUT block is disabled */ +#define SYSCTL_GENCLKEN_EXCLKEN_ENABLE ((uint32_t)0x00000001U) /* !< CLK_OUT block is enabled */ +/* SYSCTL_GENCLKEN[MFPCLKEN] Bits */ +#define SYSCTL_GENCLKEN_MFPCLKEN_OFS (4) /* !< MFPCLKEN Offset */ +#define SYSCTL_GENCLKEN_MFPCLKEN_MASK ((uint32_t)0x00000010U) /* !< MFPCLKEN enables the middle + frequency precision clock (MFPCLK). */ +#define SYSCTL_GENCLKEN_MFPCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< MFPCLK is disabled */ +#define SYSCTL_GENCLKEN_MFPCLKEN_ENABLE ((uint32_t)0x00000010U) /* !< MFPCLK is enabled */ + +/* SYSCTL_PMODECFG Bits */ +/* SYSCTL_PMODECFG[DSLEEP] Bits */ +#define SYSCTL_PMODECFG_DSLEEP_OFS (0) /* !< DSLEEP Offset */ +#define SYSCTL_PMODECFG_DSLEEP_MASK ((uint32_t)0x00000003U) /* !< DSLEEP selects the operating mode + to enter upon a DEEPSLEEP request + from the CPU. */ +#define SYSCTL_PMODECFG_DSLEEP_STOP ((uint32_t)0x00000000U) /* !< STOP mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_STANDBY ((uint32_t)0x00000001U) /* !< STANDBY mode is entered */ +#define SYSCTL_PMODECFG_DSLEEP_SHUTDOWN ((uint32_t)0x00000002U) /* !< SHUTDOWN mode is entered */ + +/* SYSCTL_FCC Bits */ +/* SYSCTL_FCC[DATA] Bits */ +#define SYSCTL_FCC_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_FCC_DATA_MASK ((uint32_t)0x003FFFFFU) /* !< Frequency clock counter (FCC) count + value. */ + +/* SYSCTL_SRAMBOUNDARY Bits */ +/* SYSCTL_SRAMBOUNDARY[ADDR] Bits */ +#define SYSCTL_SRAMBOUNDARY_ADDR_OFS (5) /* !< ADDR Offset */ +#define SYSCTL_SRAMBOUNDARY_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary configuration. The + value configured into this acts such + that: SRAM accesses to addresses less + than or equal value will be RW only. + SRAM accesses to addresses greater + than value will be RX only. Value of + 0 is not valid (system will have no + stack). If set to 0, the system acts + as if the entire SRAM is RWX. Any + non-zero value can be configured, + including a value = SRAM size. */ + +/* SYSCTL_SYSTEMCFG Bits */ +/* SYSCTL_SYSTEMCFG[KEY] Bits */ +#define SYSCTL_SYSTEMCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSTEMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 1Bh (27) must be + written to KEY together with contents + to be updated. Reads as 0 */ +#define SYSCTL_SYSTEMCFG_KEY_VALUE ((uint32_t)0x1B000000U) /* !< Issue write */ +/* SYSCTL_SYSTEMCFG[FLASHECCRSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS (2) /* !< FLASHECCRSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK ((uint32_t)0x00000004U) /* !< FLASHECCRSTDIS specifies whether a + flash ECC double error detect (DED) + will trigger a SYSRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_FALSE ((uint32_t)0x00000000U) /* !< Flash ECC DED will trigger a SYSRST */ +#define SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_TRUE ((uint32_t)0x00000004U) /* !< Flash ECC DED will trigger a NMI */ +/* SYSCTL_SYSTEMCFG[WWDTLP0RSTDIS] Bits */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS (0) /* !< WWDTLP0RSTDIS Offset */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK ((uint32_t)0x00000001U) /* !< WWDTLP0RSTDIS specifies whether a + WWDT Error Event will trigger a + BOOTRST or an NMI. */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP0 Error Event will trigger a + BOOTRST */ +#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_TRUE ((uint32_t)0x00000001U) /* !< WWDTLP0 Error Event will trigger an + NMI */ + +/* SYSCTL_BEEPCFG Bits */ +/* SYSCTL_BEEPCFG[FREQ] Bits */ +#define SYSCTL_BEEPCFG_FREQ_OFS (4) /* !< FREQ Offset */ +#define SYSCTL_BEEPCFG_FREQ_MASK ((uint32_t)0x00000030U) /* !< Beeper Output Frequency + Configuration */ +#define SYSCTL_BEEPCFG_FREQ_8KHZ ((uint32_t)0x00000000U) /* !< Beeper runs at 8KHz */ +#define SYSCTL_BEEPCFG_FREQ_4KHZ ((uint32_t)0x00000010U) /* !< Beeper runs at 4KHz */ +#define SYSCTL_BEEPCFG_FREQ_2KHZ ((uint32_t)0x00000020U) /* !< Beeper runs at 2KHz */ +#define SYSCTL_BEEPCFG_FREQ_1KHZ ((uint32_t)0x00000030U) /* !< Beeper runs at 1KHz */ +/* SYSCTL_BEEPCFG[EN] Bits */ +#define SYSCTL_BEEPCFG_EN_OFS (0) /* !< EN Offset */ +#define SYSCTL_BEEPCFG_EN_MASK ((uint32_t)0x00000001U) /* !< Beeper Output Enable */ +#define SYSCTL_BEEPCFG_EN_DISABLE ((uint32_t)0x00000000U) /* !< Beeper Output Disabled */ +#define SYSCTL_BEEPCFG_EN_ENABLE ((uint32_t)0x00000001U) /* !< Beeper Output Enabled */ + +/* SYSCTL_WRITELOCK Bits */ +/* SYSCTL_WRITELOCK[ACTIVE] Bits */ +#define SYSCTL_WRITELOCK_ACTIVE_OFS (0) /* !< ACTIVE Offset */ +#define SYSCTL_WRITELOCK_ACTIVE_MASK ((uint32_t)0x00000001U) /* !< ACTIVE controls whether critical + SYSCTL registers are write protected + or not. */ +#define SYSCTL_WRITELOCK_ACTIVE_DISABLE ((uint32_t)0x00000000U) /* !< Allow writes to lockable registers */ +#define SYSCTL_WRITELOCK_ACTIVE_ENABLE ((uint32_t)0x00000001U) /* !< Disallow writes to lockable + registers */ + +/* SYSCTL_CLKSTATUS Bits */ +/* SYSCTL_CLKSTATUS[LFOSCGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_OFS (11) /* !< LFOSCGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_MASK ((uint32_t)0x00000800U) /* !< LFOSCGOOD indicates when the LFOSC + startup has completed and the LFOSC + is ready for use. */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFOSC is not ready */ +#define SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE ((uint32_t)0x00000800U) /* !< LFOSC is ready */ +/* SYSCTL_CLKSTATUS[HFCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_OFS (8) /* !< HFCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_MASK ((uint32_t)0x00000100U) /* !< HFCLKGOOD indicates that the HFCLK + started correctly. When the HFXT is + started or HFCLK_IN is selected as + the HFCLK source, this bit will be + set by hardware if a valid HFCLK is + detected, and cleared if HFCLK is not + operating within the expected range. */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< HFCLK did not start correctly */ +#define SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE ((uint32_t)0x00000100U) /* !< HFCLK started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKDEAD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_OFS (20) /* !< HSCLKDEAD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_MASK ((uint32_t)0x00100000U) /* !< HSCLKDEAD is set by hardware if the + selected source for HSCLK was started + but did not start successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source was not started or + started correctly */ +#define SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE ((uint32_t)0x00100000U) /* !< The HSCLK source did not start + correctly */ +/* SYSCTL_CLKSTATUS[HFCLKOFF] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_OFS (13) /* !< HFCLKOFF Offset */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_MASK ((uint32_t)0x00002000U) /* !< HFCLKOFF indicates if the HFCLK is + disabled or was dead at startup. + When the HFCLK is started, HFCLKOFF + is cleared by hardware. Following + startup of the HFCLK, if the HFCLK + startup monitor determines that the + HFCLK was not started correctly, + HFCLKOFF is set. */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_FALSE ((uint32_t)0x00000000U) /* !< HFCLK started correctly and is + enabled */ +#define SYSCTL_CLKSTATUS_HFCLKOFF_TRUE ((uint32_t)0x00002000U) /* !< HFCLK is disabled or was dead at + startup */ +/* SYSCTL_CLKSTATUS[HFCLKBLKUPD] Bits */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_OFS (28) /* !< HFCLKBLKUPD Offset */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_MASK ((uint32_t)0x10000000U) /* !< HFCLKBLKUPD indicates when writes + to the HFCLKCLKCFG register are + blocked. */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_FALSE ((uint32_t)0x00000000U) /* !< Writes to HFCLKCLKCFG are allowed */ +#define SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE ((uint32_t)0x10000000U) /* !< Writes to HFCLKCLKCFG are blocked */ +/* SYSCTL_CLKSTATUS[HSCLKGOOD] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_OFS (21) /* !< HSCLKGOOD Offset */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_MASK ((uint32_t)0x00200000U) /* !< HSCLKGOOD is set by hardware if the + selected clock source for HSCLK + started successfully. */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_FALSE ((uint32_t)0x00000000U) /* !< The HSCLK source did not start + correctly */ +#define SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE ((uint32_t)0x00200000U) /* !< The HSCLK source started correctly */ +/* SYSCTL_CLKSTATUS[ANACLKERR] Bits */ +#define SYSCTL_CLKSTATUS_ANACLKERR_OFS (31) /* !< ANACLKERR Offset */ +#define SYSCTL_CLKSTATUS_ANACLKERR_MASK ((uint32_t)0x80000000U) /* !< ANACLKERR is set when the device + clock configuration does not support + an enabled analog peripheral mode and + the analog peripheral may not be + functioning as expected. */ +#define SYSCTL_CLKSTATUS_ANACLKERR_FALSE ((uint32_t)0x00000000U) /* !< No analog clock errors detected */ +#define SYSCTL_CLKSTATUS_ANACLKERR_TRUE ((uint32_t)0x80000000U) /* !< Analog clock error detected */ +/* SYSCTL_CLKSTATUS[HSCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_OFS (4) /* !< HSCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_MASK ((uint32_t)0x00000010U) /* !< HSCLKMUX indicates if MCLK is + currently sourced from the high-speed + clock (HSCLK). */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_SYSOSC ((uint32_t)0x00000000U) /* !< MCLK is not sourced from HSCLK */ +#define SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK ((uint32_t)0x00000010U) /* !< MCLK is sourced from HSCLK */ +/* SYSCTL_CLKSTATUS[LFCLKMUX] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_OFS (6) /* !< LFCLKMUX Offset */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_MASK ((uint32_t)0x000000C0U) /* !< LFCLKMUX indicates if LFCLK is + sourced from the internal LFOSC, the + low frequency crystal (LFXT), or the + LFCLK_IN digital clock input. */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFOSC ((uint32_t)0x00000000U) /* !< LFCLK is sourced from the internal + LFOSC */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_LFXT ((uint32_t)0x00000040U) /* !< LFCLK is sourced from the LFXT + (crystal) */ +#define SYSCTL_CLKSTATUS_LFCLKMUX_EXLF ((uint32_t)0x00000080U) /* !< LFCLK is sourced from LFCLK_IN + (external digital clock input) */ +/* SYSCTL_CLKSTATUS[SYSOSCFREQ] Bits */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_OFS (0) /* !< SYSOSCFREQ Offset */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK ((uint32_t)0x00000003U) /* !< SYSOSCFREQ indicates the current + SYSOSC operating frequency. */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC32M ((uint32_t)0x00000000U) /* !< SYSOSC is at base frequency (32MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< SYSOSC is at low frequency (4MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< SYSOSC is at the user-trimmed + frequency (16 or 24MHz) */ +#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCTURBO ((uint32_t)0x00000003U) /* !< Reserved */ +/* SYSCTL_CLKSTATUS[LFXTGOOD] Bits */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_OFS (10) /* !< LFXTGOOD Offset */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_MASK ((uint32_t)0x00000400U) /* !< LFXTGOOD indicates if the LFXT + started correctly. When the LFXT is + started, LFXTGOOD is cleared by + hardware. After the startup settling + time has expired, the LFXT status is + tested. If the LFXT started + successfully the LFXTGOOD bit is set, + else it is left cleared. */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFXT did not start correctly */ +#define SYSCTL_CLKSTATUS_LFXTGOOD_TRUE ((uint32_t)0x00000400U) /* !< LFXT started correctly */ +/* SYSCTL_CLKSTATUS[HSCLKSOFF] Bits */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_OFS (12) /* !< HSCLKSOFF Offset */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_MASK ((uint32_t)0x00001000U) /* !< HSCLKSOFF is set when the high + speed clock sources (SYSPLL, HFCLK) + are disabled or dead. It is the + logical AND of HFCLKOFF and + SYSPLLOFF. */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_FALSE ((uint32_t)0x00000000U) /* !< SYSPLL, HFCLK, or both were started + correctly and remain enabled */ +#define SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE ((uint32_t)0x00001000U) /* !< SYSPLL and HFCLK are both either + off or dead */ +/* SYSCTL_CLKSTATUS[FCLMODE] Bits */ +#define SYSCTL_CLKSTATUS_FCLMODE_OFS (24) /* !< FCLMODE Offset */ +#define SYSCTL_CLKSTATUS_FCLMODE_MASK ((uint32_t)0x01000000U) /* !< FCLMODE indicates if the SYSOSC + frequency correction loop (FCL) is + enabled. */ +#define SYSCTL_CLKSTATUS_FCLMODE_DISABLED ((uint32_t)0x00000000U) /* !< SYSOSC FCL is disabled */ +#define SYSCTL_CLKSTATUS_FCLMODE_ENABLED ((uint32_t)0x01000000U) /* !< SYSOSC FCL is enabled */ +/* SYSCTL_CLKSTATUS[CURHSCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_OFS (16) /* !< CURHSCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_MASK ((uint32_t)0x00010000U) /* !< CURHSCLKSEL indicates the current + clock source for HSCLK. */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_SYSPLL ((uint32_t)0x00000000U) /* !< HSCLK is currently sourced from the + SYSPLL */ +#define SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK ((uint32_t)0x00010000U) /* !< HSCLK is currently sourced from the + HFCLK */ +/* SYSCTL_CLKSTATUS[CURMCLKSEL] Bits */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_OFS (17) /* !< CURMCLKSEL Offset */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_MASK ((uint32_t)0x00020000U) /* !< CURMCLKSEL indicates if MCLK is + currently sourced from LFCLK. */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_NOTLFCLK ((uint32_t)0x00000000U) /* !< MCLK is not sourced from LFCLK */ +#define SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK ((uint32_t)0x00020000U) /* !< MCLK is sourced from LFCLK */ +/* SYSCTL_CLKSTATUS[FCCDONE] Bits */ +#define SYSCTL_CLKSTATUS_FCCDONE_OFS (25) /* !< FCCDONE Offset */ +#define SYSCTL_CLKSTATUS_FCCDONE_MASK ((uint32_t)0x02000000U) /* !< FCCDONE indicates when a frequency + clock counter capture is complete. */ +#define SYSCTL_CLKSTATUS_FCCDONE_NOTDONE ((uint32_t)0x00000000U) /* !< FCC capture is not done */ +#define SYSCTL_CLKSTATUS_FCCDONE_DONE ((uint32_t)0x02000000U) /* !< FCC capture is done */ +/* SYSCTL_CLKSTATUS[LFCLKFAIL] Bits */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_OFS (23) /* !< LFCLKFAIL Offset */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_MASK ((uint32_t)0x00800000U) /* !< LFCLKFAIL indicates when the + continous LFCLK monitor detects a + LFXT or LFCLK_IN clock stuck failure. */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_FALSE ((uint32_t)0x00000000U) /* !< No LFCLK fault detected */ +#define SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE ((uint32_t)0x00800000U) /* !< LFCLK stuck fault detected */ + +/* SYSCTL_SYSSTATUS Bits */ +/* SYSCTL_SYSSTATUS[SHDNIOLOCK] Bits */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_OFS (14) /* !< SHDNIOLOCK Offset */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_MASK ((uint32_t)0x00004000U) /* !< SHDNIOLOCK indicates when IO is + locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_FALSE ((uint32_t)0x00000000U) /* !< IO IS NOT Locked due to SHUTDOWN */ +#define SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE ((uint32_t)0x00004000U) /* !< IO IS Locked due to SHUTDOWN */ +/* SYSCTL_SYSSTATUS[EXTRSTPINDIS] Bits */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_OFS (12) /* !< EXTRSTPINDIS Offset */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_MASK ((uint32_t)0x00001000U) /* !< EXTRSTPINDIS indicates when user + has disabled the use of external + reset pin */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_FALSE ((uint32_t)0x00000000U) /* !< External Reset Pin Enabled */ +#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE ((uint32_t)0x00001000U) /* !< External Reset Pin Disabled */ +/* SYSCTL_SYSSTATUS[SWDCFGDIS] Bits */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_OFS (13) /* !< SWDCFGDIS Offset */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_MASK ((uint32_t)0x00002000U) /* !< SWDCFGDIS indicates when user has + disabled the use of SWD Port */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_FALSE ((uint32_t)0x00000000U) /* !< SWD Port Enabled */ +#define SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE ((uint32_t)0x00002000U) /* !< SWD Port Disabled */ +/* SYSCTL_SYSSTATUS[ANACPUMPGOOD] Bits */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_OFS (5) /* !< ANACPUMPGOOD Offset */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_MASK ((uint32_t)0x00000020U) /* !< ANACPUMPGOOD is set by hardware + when the VBOOST analog mux charge + pump is ready. */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_FALSE ((uint32_t)0x00000000U) /* !< VBOOST is not ready */ +#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE ((uint32_t)0x00000020U) /* !< VBOOST is ready */ +/* SYSCTL_SYSSTATUS[BORLVL] Bits */ +#define SYSCTL_SYSSTATUS_BORLVL_OFS (4) /* !< BORLVL Offset */ +#define SYSCTL_SYSSTATUS_BORLVL_MASK ((uint32_t)0x00000010U) /* !< BORLVL indicates if a BOR event + occured and the BOR threshold was + switched to BOR0 by hardware. */ +#define SYSCTL_SYSSTATUS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No BOR violation occured */ +#define SYSCTL_SYSSTATUS_BORLVL_TRUE ((uint32_t)0x00000010U) /* !< A BOR violation occured and the BOR + threshold was switched to BOR0 */ +/* SYSCTL_SYSSTATUS[FLASHDED] Bits */ +#define SYSCTL_SYSSTATUS_FLASHDED_OFS (0) /* !< FLASHDED Offset */ +#define SYSCTL_SYSSTATUS_FLASHDED_MASK ((uint32_t)0x00000001U) /* !< FLASHDED indicates if a flash ECC + double bit error was detected (DED). */ +#define SYSCTL_SYSSTATUS_FLASHDED_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC double bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHDED_TRUE ((uint32_t)0x00000001U) /* !< Flash ECC double bit error detected */ +/* SYSCTL_SYSSTATUS[FLASHSEC] Bits */ +#define SYSCTL_SYSSTATUS_FLASHSEC_OFS (1) /* !< FLASHSEC Offset */ +#define SYSCTL_SYSSTATUS_FLASHSEC_MASK ((uint32_t)0x00000002U) /* !< FLASHSEC indicates if a flash ECC + single bit error was detected and + corrected (SEC). */ +#define SYSCTL_SYSSTATUS_FLASHSEC_FALSE ((uint32_t)0x00000000U) /* !< No flash ECC single bit error + detected */ +#define SYSCTL_SYSSTATUS_FLASHSEC_TRUE ((uint32_t)0x00000002U) /* !< Flash ECC single bit error was + detected and corrected */ +/* SYSCTL_SYSSTATUS[PMUIREFGOOD] Bits */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_OFS (6) /* !< PMUIREFGOOD Offset */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_MASK ((uint32_t)0x00000040U) /* !< PMUIREFGOOD is set by hardware when + the PMU current reference is ready. */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_FALSE ((uint32_t)0x00000000U) /* !< IREF is not ready */ +#define SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE ((uint32_t)0x00000040U) /* !< IREF is ready */ +/* SYSCTL_SYSSTATUS[REBOOTATTEMPTS] Bits */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_OFS (30) /* !< REBOOTATTEMPTS Offset */ +#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_MASK ((uint32_t)0xC0000000U) /* !< REBOOTATTEMPTS indicates the number + of boot attempts taken before the + user application starts. */ +/* SYSCTL_SYSSTATUS[BORCURTHRESHOLD] Bits */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_OFS (2) /* !< BORCURTHRESHOLD Offset */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_MASK ((uint32_t)0x0000000CU) /* !< BORCURTHRESHOLD indicates the + active brown-out reset supply monitor + configuration. */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1 ((uint32_t)0x00000004U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2 ((uint32_t)0x00000008U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3 ((uint32_t)0x0000000CU) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_DEDERRADDR Bits */ +/* SYSCTL_DEDERRADDR[ADDR] Bits */ +#define SYSCTL_DEDERRADDR_ADDR_OFS (0) /* !< ADDR Offset */ +#define SYSCTL_DEDERRADDR_ADDR_MASK ((uint32_t)0xFFFFFFFFU) /* !< Address of MEMORY DED Error. */ + +/* SYSCTL_RSTCAUSE Bits */ +/* SYSCTL_RSTCAUSE[ID] Bits */ +#define SYSCTL_RSTCAUSE_ID_OFS (0) /* !< ID Offset */ +#define SYSCTL_RSTCAUSE_ID_MASK ((uint32_t)0x0000001FU) /* !< ID is a read-to-clear field which + indicates the lowest level reset + cause since the last read. */ +#define SYSCTL_RSTCAUSE_ID_NORST ((uint32_t)0x00000000U) /* !< No reset since last read */ +#define SYSCTL_RSTCAUSE_ID_PORHWFAIL ((uint32_t)0x00000001U) /* !< POR- violation, SHUTDNSTOREx or PMU + trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_POREXNRST ((uint32_t)0x00000002U) /* !< NRST triggered POR (>1s hold) */ +#define SYSCTL_RSTCAUSE_ID_PORSW ((uint32_t)0x00000003U) /* !< Software triggered POR */ +#define SYSCTL_RSTCAUSE_ID_BORSUPPLY ((uint32_t)0x00000004U) /* !< BOR0- violation */ +#define SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN ((uint32_t)0x00000005U) /* !< SHUTDOWN mode exit */ +#define SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY ((uint32_t)0x00000008U) /* !< Non-PMU trim parity fault */ +#define SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL ((uint32_t)0x00000009U) /* !< Fatal clock failure */ +#define SYSCTL_RSTCAUSE_ID_BOOTEXNRST ((uint32_t)0x0000000CU) /* !< NRST triggered BOOTRST (<1s hold) */ +#define SYSCTL_RSTCAUSE_ID_BOOTSW ((uint32_t)0x0000000DU) /* !< Software triggered BOOTRST */ +#define SYSCTL_RSTCAUSE_ID_BOOTWWDT0 ((uint32_t)0x0000000EU) /* !< WWDT0 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLEXIT ((uint32_t)0x00000010U) /* !< BSL exit */ +#define SYSCTL_RSTCAUSE_ID_SYSBSLENTRY ((uint32_t)0x00000011U) /* !< BSL entry */ +#define SYSCTL_RSTCAUSE_ID_SYSWWDT1 ((uint32_t)0x00000013U) /* !< WWDT1 violation */ +#define SYSCTL_RSTCAUSE_ID_SYSFLASHECC ((uint32_t)0x00000014U) /* !< Flash uncorrectable ECC error */ +#define SYSCTL_RSTCAUSE_ID_SYSCPULOCK ((uint32_t)0x00000015U) /* !< CPULOCK violation */ +#define SYSCTL_RSTCAUSE_ID_SYSDBG ((uint32_t)0x0000001AU) /* !< Debug triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_SYSSW ((uint32_t)0x0000001BU) /* !< Software triggered SYSRST */ +#define SYSCTL_RSTCAUSE_ID_CPUDBG ((uint32_t)0x0000001CU) /* !< Debug triggered CPURST */ +#define SYSCTL_RSTCAUSE_ID_CPUSW ((uint32_t)0x0000001DU) /* !< Software triggered CPURST */ + +/* SYSCTL_RESETLEVEL Bits */ +/* SYSCTL_RESETLEVEL[LEVEL] Bits */ +#define SYSCTL_RESETLEVEL_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_RESETLEVEL_LEVEL_MASK ((uint32_t)0x00000007U) /* !< LEVEL is used to specify the type + of reset to be issued when RESETCMD + is set to generate a software + triggered reset. */ +#define SYSCTL_RESETLEVEL_LEVEL_CPU ((uint32_t)0x00000000U) /* !< Issue a SYSRST (CPU plus + peripherals only) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOT ((uint32_t)0x00000001U) /* !< Issue a BOOTRST (CPU, peripherals, + and boot configuration routine) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY ((uint32_t)0x00000002U) /* !< Issue a SYSRST and enter the boot + strap loader (BSL) */ +#define SYSCTL_RESETLEVEL_LEVEL_POR ((uint32_t)0x00000003U) /* !< Issue a power-on reset (POR) */ +#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT ((uint32_t)0x00000004U) /* !< Issue a SYSRST and exit the boot + strap loader (BSL) */ + +/* SYSCTL_RESETCMD Bits */ +/* SYSCTL_RESETCMD[KEY] Bits */ +#define SYSCTL_RESETCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_RESETCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of E4h (228) must be + written to KEY together with GO to + trigger the reset. */ +#define SYSCTL_RESETCMD_KEY_VALUE ((uint32_t)0xE4000000U) /* !< Issue reset */ +/* SYSCTL_RESETCMD[GO] Bits */ +#define SYSCTL_RESETCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_RESETCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Execute the reset specified in + RESETLEVEL.LEVEL. Must be written + together with the KEY. */ +#define SYSCTL_RESETCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue reset */ + +/* SYSCTL_BORTHRESHOLD Bits */ +/* SYSCTL_BORTHRESHOLD[LEVEL] Bits */ +#define SYSCTL_BORTHRESHOLD_LEVEL_OFS (0) /* !< LEVEL Offset */ +#define SYSCTL_BORTHRESHOLD_LEVEL_MASK ((uint32_t)0x00000003U) /* !< LEVEL specifies the desired BOR + threshold and BOR mode. */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0- + violation triggers a BOR */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1 ((uint32_t)0x00000001U) /* !< A BOR1- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2 ((uint32_t)0x00000002U) /* !< A BOR2- violation generates a + BORLVL interrupt */ +#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3 ((uint32_t)0x00000003U) /* !< A BOR3- violation generates a + BORLVL interrupt */ + +/* SYSCTL_BORCLRCMD Bits */ +/* SYSCTL_BORCLRCMD[KEY] Bits */ +#define SYSCTL_BORCLRCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_BORCLRCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of C7h (199) must be + written to KEY together with GO to + trigger the clear and BOR threshold + change. */ +#define SYSCTL_BORCLRCMD_KEY_VALUE ((uint32_t)0xC7000000U) /* !< Issue clear */ +/* SYSCTL_BORCLRCMD[GO] Bits */ +#define SYSCTL_BORCLRCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_BORCLRCMD_GO_MASK ((uint32_t)0x00000001U) /* !< GO clears any prior BOR violation + status indications and attempts to + change the active BOR mode to that + specified in the LEVEL field of the + BORTHRESHOLD register. */ +#define SYSCTL_BORCLRCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue clear */ + +/* SYSCTL_SYSOSCFCLCTL Bits */ +/* SYSCTL_SYSOSCFCLCTL[KEY] Bits */ +#define SYSCTL_SYSOSCFCLCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSOSCFCLCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 2Ah (42) must be + written to KEY together with + SETUSEFCL to enable the FCL. */ +#define SYSCTL_SYSOSCFCLCTL_KEY_VALUE ((uint32_t)0x2A000000U) /* !< Issue Command */ +/* SYSCTL_SYSOSCFCLCTL[SETUSEFCL] Bits */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_OFS (0) /* !< SETUSEFCL Offset */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEFCL to enable the + frequency correction loop in SYSOSC. + Once enabled, this state is locked + until the next BOOTRST. */ +#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */ + +/* SYSCTL_LFXTCTL Bits */ +/* SYSCTL_LFXTCTL[KEY] Bits */ +#define SYSCTL_LFXTCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_LFXTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 91h (145) must be + written to KEY together with either + STARTLFXT or SETUSELFXT to set the + corresponding bit. */ +#define SYSCTL_LFXTCTL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_LFXTCTL[SETUSELFXT] Bits */ +#define SYSCTL_LFXTCTL_SETUSELFXT_OFS (1) /* !< SETUSELFXT Offset */ +#define SYSCTL_LFXTCTL_SETUSELFXT_MASK ((uint32_t)0x00000002U) /* !< Set SETUSELFXT to switch LFCLK to + LFXT. Once set, SETUSELFXT remains + set until the next BOOTRST. */ +#define SYSCTL_LFXTCTL_SETUSELFXT_FALSE ((uint32_t)0x00000000U) +#define SYSCTL_LFXTCTL_SETUSELFXT_TRUE ((uint32_t)0x00000002U) /* !< Use LFXT as the LFCLK source */ +/* SYSCTL_LFXTCTL[STARTLFXT] Bits */ +#define SYSCTL_LFXTCTL_STARTLFXT_OFS (0) /* !< STARTLFXT Offset */ +#define SYSCTL_LFXTCTL_STARTLFXT_MASK ((uint32_t)0x00000001U) /* !< Set STARTLFXT to start the low + frequency crystal oscillator (LFXT). + Once set, STARTLFXT remains set until + the next BOOTRST. */ +#define SYSCTL_LFXTCTL_STARTLFXT_FALSE ((uint32_t)0x00000000U) /* !< LFXT not started */ +#define SYSCTL_LFXTCTL_STARTLFXT_TRUE ((uint32_t)0x00000001U) /* !< Start LFXT */ + +/* SYSCTL_EXLFCTL Bits */ +/* SYSCTL_EXLFCTL[KEY] Bits */ +#define SYSCTL_EXLFCTL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXLFCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 36h (54) must be + written to KEY together with + SETUSEEXLF to set SETUSEEXLF. */ +#define SYSCTL_EXLFCTL_KEY_VALUE ((uint32_t)0x36000000U) /* !< Issue command */ +/* SYSCTL_EXLFCTL[SETUSEEXLF] Bits */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_OFS (0) /* !< SETUSEEXLF Offset */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEEXLF to switch LFCLK to + the LFCLK_IN digital clock input. + Once set, SETUSEEXLF remains set + until the next BOOTRST. */ +#define SYSCTL_EXLFCTL_SETUSEEXLF_TRUE ((uint32_t)0x00000001U) /* !< Use LFCLK_IN as the LFCLK source */ + +/* SYSCTL_SHDNIOREL Bits */ +/* SYSCTL_SHDNIOREL[KEY] Bits */ +#define SYSCTL_SHDNIOREL_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SHDNIOREL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 91h must be written + to KEY together with RELEASE to set + RELEASE. */ +#define SYSCTL_SHDNIOREL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */ +/* SYSCTL_SHDNIOREL[RELEASE] Bits */ +#define SYSCTL_SHDNIOREL_RELEASE_OFS (0) /* !< RELEASE Offset */ +#define SYSCTL_SHDNIOREL_RELEASE_MASK ((uint32_t)0x00000001U) /* !< Set RELEASE to release the IO after + a SHUTDOWN mode exit. */ +#define SYSCTL_SHDNIOREL_RELEASE_TRUE ((uint32_t)0x00000001U) /* !< Release IO */ + +/* SYSCTL_EXRSTPIN Bits */ +/* SYSCTL_EXRSTPIN[KEY] Bits */ +#define SYSCTL_EXRSTPIN_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_EXRSTPIN_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 1Eh must be written + together with DISABLE to disable the + reset function. */ +#define SYSCTL_EXRSTPIN_KEY_VALUE ((uint32_t)0x1E000000U) /* !< Issue command */ +/* SYSCTL_EXRSTPIN[DISABLE] Bits */ +#define SYSCTL_EXRSTPIN_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_EXRSTPIN_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the reset + function of the NRST pin. Once set, + this configuration is locked until + the next POR. */ +#define SYSCTL_EXRSTPIN_DISABLE_FALSE ((uint32_t)0x00000000U) /* !< Reset function of NRST pin is + enabled */ +#define SYSCTL_EXRSTPIN_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Reset function of NRST pin is + disabled */ + +/* SYSCTL_SYSSTATUSCLR Bits */ +/* SYSCTL_SYSSTATUSCLR[KEY] Bits */ +#define SYSCTL_SYSSTATUSCLR_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SYSSTATUSCLR_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value CEh (206) must be + written to KEY together with ALLECC + to clear the ECC state. */ +#define SYSCTL_SYSSTATUSCLR_KEY_VALUE ((uint32_t)0xCE000000U) /* !< Issue command */ +/* SYSCTL_SYSSTATUSCLR[ALLECC] Bits */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_OFS (0) /* !< ALLECC Offset */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_MASK ((uint32_t)0x00000001U) /* !< Set ALLECC to clear all ECC related + SYSSTATUS indicators. */ +#define SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR ((uint32_t)0x00000001U) /* !< Clear ECC error state */ + +/* SYSCTL_SWDCFG Bits */ +/* SYSCTL_SWDCFG[KEY] Bits */ +#define SYSCTL_SWDCFG_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_SWDCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 62h (98) must be + written to KEY together with DISBALE + to disable the SWD functions. */ +#define SYSCTL_SWDCFG_KEY_VALUE ((uint32_t)0x62000000U) /* !< Issue command */ +/* SYSCTL_SWDCFG[DISABLE] Bits */ +#define SYSCTL_SWDCFG_DISABLE_OFS (0) /* !< DISABLE Offset */ +#define SYSCTL_SWDCFG_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the SWD + function on SWD pins, allowing the + SWD pins to be used as GPIO. */ +#define SYSCTL_SWDCFG_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disable SWD function on SWD pins */ + +/* SYSCTL_FCCCMD Bits */ +/* SYSCTL_FCCCMD[KEY] Bits */ +#define SYSCTL_FCCCMD_KEY_OFS (24) /* !< KEY Offset */ +#define SYSCTL_FCCCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 0Eh (14) must be + written with GO to start a capture. */ +#define SYSCTL_FCCCMD_KEY_VALUE ((uint32_t)0x0E000000U) /* !< Issue command */ +/* SYSCTL_FCCCMD[GO] Bits */ +#define SYSCTL_FCCCMD_GO_OFS (0) /* !< GO Offset */ +#define SYSCTL_FCCCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Set GO to start a capture with the + frequency clock counter (FCC). */ +#define SYSCTL_FCCCMD_GO_TRUE ((uint32_t)0x00000001U) + +/* SYSCTL_SHUTDNSTORE0 Bits */ +/* SYSCTL_SHUTDNSTORE0[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE0_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE0_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 0 */ + +/* SYSCTL_SHUTDNSTORE1 Bits */ +/* SYSCTL_SHUTDNSTORE1[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE1_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE1_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 1 */ + +/* SYSCTL_SHUTDNSTORE2 Bits */ +/* SYSCTL_SHUTDNSTORE2[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE2_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE2_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 2 */ + +/* SYSCTL_SHUTDNSTORE3 Bits */ +/* SYSCTL_SHUTDNSTORE3[DATA] Bits */ +#define SYSCTL_SHUTDNSTORE3_DATA_OFS (0) /* !< DATA Offset */ +#define SYSCTL_SHUTDNSTORE3_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 3 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0l211x_l112x__include */ + diff --git a/mspm0/source/ti/driverlib/dl_adc12.h b/mspm0/source/ti/driverlib/dl_adc12.h index 4999d35..08595a2 100644 --- a/mspm0/source/ti/driverlib/dl_adc12.h +++ b/mspm0/source/ti/driverlib/dl_adc12.h @@ -242,43 +242,43 @@ extern "C" { #define DL_ADC12_HW_AVG_NUM_ACC_DISABLED (ADC12_CTL1_AVGN_DISABLE) /*! - * @brief Accumulates 2 conversions and then is get divided by the + * @brief Accumulates 2 conversions and then is divided by the * denominator selected. */ #define DL_ADC12_HW_AVG_NUM_ACC_2 (ADC12_CTL1_AVGN_AVG_2) /*! - * @brief Accumulates 4 conversions and then is get divided by the + * @brief Accumulates 4 conversions and then is divided by the * denominator selected. */ #define DL_ADC12_HW_AVG_NUM_ACC_4 (ADC12_CTL1_AVGN_AVG_4) /*! - * @brief Accumulates 8 conversions and then is get divided by the + * @brief Accumulates 8 conversions and then is divided by the * denominator selected. */ #define DL_ADC12_HW_AVG_NUM_ACC_8 (ADC12_CTL1_AVGN_AVG_8) /*! - * @brief Accumulates 16 conversions and then is get divided by the + * @brief Accumulates 16 conversions and then is divided by the * denominator selected. */ #define DL_ADC12_HW_AVG_NUM_ACC_16 (ADC12_CTL1_AVGN_AVG_16) /*! - * @brief Accumulates 32 conversions and then is get divided by the + * @brief Accumulates 32 conversions and then is divided by the * denominator selected. */ #define DL_ADC12_HW_AVG_NUM_ACC_32 (ADC12_CTL1_AVGN_AVG_32) /*! - * @brief Accumulates 64 conversions and then is get divided by the + * @brief Accumulates 64 conversions and then is divided by the * denominator selected. */ #define DL_ADC12_HW_AVG_NUM_ACC_64 (ADC12_CTL1_AVGN_AVG_64) /*! - * @brief Accumulates 128 conversions and then is get divided by the + * @brief Accumulates 128 conversions and then is divided by the * denominator selected. */ #define DL_ADC12_HW_AVG_NUM_ACC_128 (ADC12_CTL1_AVGN_AVG_128) @@ -605,7 +605,7 @@ extern "C" { #define DL_ADC12_BURN_OUT_SOURCE_ENABLED (ADC12_MEMCTL_BCSEN_ENABLE) /*! - * @brief ADC12 burn out current source enabled + * @brief ADC12 burn out current source disabled */ #define DL_ADC12_BURN_OUT_SOURCE_DISABLED (ADC12_MEMCTL_BCSEN_DISABLE) @@ -616,7 +616,7 @@ extern "C" { */ /*! - * @brief ADC12 trigger automaticaly step to next memory conversion register + * @brief ADC12 trigger automatically step to next memory conversion register */ #define DL_ADC12_TRIGGER_MODE_AUTO_NEXT (ADC12_MEMCTL_TRIG_AUTO_NEXT) @@ -1285,7 +1285,7 @@ __STATIC_INLINE void DL_ADC12_setStartAddress( * * @param[in] adc12 Pointer to the register overlay for the peripheral * - * @return One of @ref DL_ADC12_SEQ_END_ADDR + * @return One of @ref DL_ADC12_SEQ_START_ADDR * */ __STATIC_INLINE uint32_t DL_ADC12_getStartAddress(const ADC12_Regs *adc12) @@ -1671,8 +1671,21 @@ __STATIC_INLINE uint32_t DL_ADC12_getHwAverageConfig(const ADC12_Regs *adc12) * @brief Set sample time 0 * * @param[in] adc12 Pointer to the register overlay for the peripheral - * @param[in] adcclks Specifies the sample time in number of ADCCLK cycles. - * Actual sample time is (adcclks + 1) + * @param[in] adcclks The sample time in number of ADCCLK cycles. + * + * Actual sample time is calculated as follows: + * + * If adcclks (SCOMP register) = 0 or 1, then: + * number of sampling clocks = sample clock divide value + * (actual divide value of SCLKDIV register) + * Ex. If adcclks = 0, and SCLKDIV = 2 (implies divide value of 4), then: + * the total number of sampling clocks is 4. + * + * If adcclks (SCOMP register) >= 1, then: + * number of sampling clocks = adcclks * sample clock divide value + * (actual divide value of SCLKDIV) + * Ex. If adcclks = 5, and SCLKDIV = 6 (implies divide value of 16), then: + * 5 * 16 = 80 sampling clocks. * */ __STATIC_INLINE void DL_ADC12_setSampleTime0( @@ -1725,8 +1738,9 @@ __STATIC_INLINE uint16_t DL_ADC12_getSampleTime1(const ADC12_Regs *adc12) * @param[in] adc12 Pointer to the register overlay for the peripheral * @param[in] threshold Window comparator low threshold value. Threshold * value must take into account result data format and - * and resolution confugred via - * DL_ADC12_initSingleSample or DL_ADC12_initSeqSample + * resolution configured via + * @ref DL_ADC12_initSingleSample or + * @ref DL_ADC12_initSeqSample */ __STATIC_INLINE void DL_ADC12_configWinCompLowThld( ADC12_Regs *adc12, uint16_t threshold) @@ -1740,8 +1754,9 @@ __STATIC_INLINE void DL_ADC12_configWinCompLowThld( * @param[in] adc12 Pointer to the register overlay for the peripheral * @param[in] threshold Window comparator high threshold value. Threshold * value must take into account result data format and - * and resolution confugred via - * DL_ADC12_initSingleSample or DL_ADC12_initSeqSample + * resolution configured via + * @ref DL_ADC12_initSingleSample or + * @ref DL_ADC12_initSeqSample */ __STATIC_INLINE void DL_ADC12_configWinCompHighThld( ADC12_Regs *adc12, uint16_t threshold) @@ -2116,7 +2131,7 @@ __STATIC_INLINE void DL_ADC12_enableEvent( * * @param[in] adc12 Pointer to the register overlay for the * peripheral - * @param[in] eventMask Bit mask of events to enable. Bitwise OR of + * @param[in] eventMask Bit mask of events to disable. Bitwise OR of * @ref DL_ADC12_EVENT. */ __STATIC_INLINE void DL_ADC12_disableEvent( @@ -2126,7 +2141,7 @@ __STATIC_INLINE void DL_ADC12_disableEvent( } /** - * @brief Check which adc12 dma triggers are enabled + * @brief Check which ADC12 events are enabled * * @param[in] adc12 Pointer to the register overlay for the * peripheral @@ -2154,7 +2169,7 @@ __STATIC_INLINE uint32_t DL_ADC12_getEnabledEvents( * @param[in] eventMask Bit mask of events to check. Bitwise OR of * @ref DL_ADC12_EVENT. * - * @return Which of the requested adc12 eventes are pending + * @return Which of the requested adc12 events are pending * * @retval Bitwise OR of @ref DL_ADC12_EVENT values * @@ -2220,7 +2235,7 @@ __STATIC_INLINE void DL_ADC12_enableDMATrigger( * * @param[in] adc12 Pointer to the register overlay for the * peripheral - * @param[in] dmaMask Bit mask of DMA triggers to enable. Bitwise OR of + * @param[in] dmaMask Bit mask of DMA triggers to disable. Bitwise OR of * @ref DL_ADC12_DMA. */ __STATIC_INLINE void DL_ADC12_disableDMATrigger( @@ -2258,7 +2273,7 @@ __STATIC_INLINE uint32_t DL_ADC12_getEnabledDMATrigger( * @param[in] dmaMask Bit mask of DMA triggers to check. Bitwise OR of * @ref DL_ADC12_DMA. * - * @return Which of the requested adc12 eventes are pending + * @return Which of the requested adc12 events are pending * * @retval Bitwise OR of @ref DL_ADC12_DMA values * diff --git a/mspm0/source/ti/driverlib/dl_comp.h b/mspm0/source/ti/driverlib/dl_comp.h index 17fb59f..55af67f 100644 --- a/mspm0/source/ti/driverlib/dl_comp.h +++ b/mspm0/source/ti/driverlib/dl_comp.h @@ -61,6 +61,13 @@ extern "C" { #endif +#ifdef COMP_SYS_DACOUT_EN +/*! + * @brief Device has support for 8-bit DAC output to pin + */ +#define DEVICE_HAS_DAC_OUT_TO_PIN +#endif /* COMP_SYS_DACOUT_EN */ + /* clang-format off */ /** @addtogroup DL_COMP_INTERRUPT @@ -307,10 +314,10 @@ typedef enum { /*! @enum DL_COMP_OUTPUT */ typedef enum { - /*! Comparator output is high */ - DL_COMP_OUTPUT_HIGH = COMP_STAT_OUT_LOW, /*! Comparator output is low */ - DL_COMP_OUTPUT_LOW = COMP_STAT_OUT_HIGH, + DL_COMP_OUTPUT_LOW = COMP_STAT_OUT_LOW, + /*! Comparator output is high */ + DL_COMP_OUTPUT_HIGH = COMP_STAT_OUT_HIGH, } DL_COMP_OUTPUT; /*! @enum DL_COMP_SUBSCRIBER_INDEX */ @@ -828,6 +835,48 @@ __STATIC_INLINE void DL_COMP_disableWindowComparator(COMP_Regs *comp) comp->CTL1 &= ~(COMP_CTL1_WINCOMPEN_MASK); } +#ifdef DEVICE_HAS_DAC_OUT_TO_PIN +/** + * @brief Enable 8-bit DAC output to pin + * + * Please check your device datasheet for which pin the 8-bit DAC output is + * connected to. + * + * @param[in] comp Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_COMP_enableDACOutputToPin(COMP_Regs *comp) +{ + comp->CTL1 |= COMP_CTL1_DACOUTEN_ENABLE; +} + +/** + * @brief Checks if 8-bit DAC output to pin is enabled + * + * @param[in] comp Pointer to the register overlay for the peripheral + * + * @return Returns if the 8-bit DAC output is enabled + * + * @retval true The 8-bit DAC output is enabled + * @retval false The 8-bit DAC output is not enabled + */ +__STATIC_INLINE bool DL_COMP_isDACOutputToPinEnabled(COMP_Regs *comp) +{ + return ( + (comp->CTL1 & COMP_CTL1_DACOUTEN_MASK) == COMP_CTL1_DACOUTEN_ENABLE); +} + +/** + * @brief Disable 8-bit DAC output to pin + * + * @param[in] comp Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_COMP_disableDACOutputToPin(COMP_Regs *comp) +{ + comp->CTL1 &= ~(COMP_CTL1_DACOUTEN_MASK); +} + +#endif /* DEVICE_HAS_DAC_OUT_TO_PIN */ + /** * @brief Set the enabled channels for the comparator terminals * diff --git a/mspm0/source/ti/driverlib/dl_crcp.h b/mspm0/source/ti/driverlib/dl_crcp.h index 44e9ec7..f1d24cf 100644 --- a/mspm0/source/ti/driverlib/dl_crcp.h +++ b/mspm0/source/ti/driverlib/dl_crcp.h @@ -456,7 +456,7 @@ typedef enum { DL_CRCP_CRCPOLY_POLYNOMIAL_16_CDMA2000 = 0x0000C867, /*! CRCP commonly used polynomial CRC16_MODBUS. To match online output, * seed value must be set to 0xFFFF and bit order reversed */ - DL_CRCP_CRCPOLY_POLYNOMIAL_16_MODBUS = 0x00001DCF, + DL_CRCP_CRCPOLY_POLYNOMIAL_16_MODBUS = 0x00008005, } DL_CRCP_CRCPOLY_POLYNOMIAL; @@ -500,7 +500,7 @@ typedef enum { * polynomial must be set to 0x0000C867 */ DL_CRCP_CRCSEED_SEED_16_CDMA2000 = 0xFFFF, /*! CRCP commonly used polynomial CRC16_MODBUS. To match online output, - * polynomial must be set to 0x00001DCF and bit order reversed */ + * polynomial must be set to 0x00008005 and bit order reversed */ DL_CRCP_CRCSEED_SEED_16_MODBUS = 0xFFFF, } DL_CRCP_CRCSEED_SEED; diff --git a/mspm0/source/ti/driverlib/dl_flashctl.h b/mspm0/source/ti/driverlib/dl_flashctl.h index 3a1a6ff..1bc539c 100644 --- a/mspm0/source/ti/driverlib/dl_flashctl.h +++ b/mspm0/source/ti/driverlib/dl_flashctl.h @@ -1293,8 +1293,6 @@ void DL_FlashCTL_programMemory8( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1344,8 +1342,6 @@ void DL_FlashCTL_programMemory16( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1395,8 +1391,6 @@ void DL_FlashCTL_programMemory32( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1446,8 +1440,6 @@ void DL_FlashCTL_programMemory64( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1509,8 +1501,6 @@ void DL_FlashCTL_programMemory8WithECCGenerated( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1574,8 +1564,6 @@ void DL_FlashCTL_programMemory16WithECCGenerated( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1639,8 +1627,6 @@ void DL_FlashCTL_programMemory32WithECCGenerated( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1704,8 +1690,6 @@ void DL_FlashCTL_programMemory64WithECCGenerated( * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1781,8 +1765,6 @@ void DL_FlashCTL_programMemory8WithECCManual(FLASHCTL_Regs *flashctl, * @ref DL_FlashCTL_disableOverrideHardwareGeneratedECC is called * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1859,8 +1841,6 @@ void DL_FlashCTL_programMemory16WithECCManual(FLASHCTL_Regs *flashctl, * @ref DL_FlashCTL_disableOverrideHardwareGeneratedECC is called * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -1937,8 +1917,6 @@ void DL_FlashCTL_programMemory32WithECCManual(FLASHCTL_Regs *flashctl, * @ref DL_FlashCTL_disableOverrideHardwareGeneratedECC is called * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -2015,8 +1993,6 @@ void DL_FlashCTL_programMemory64WithECCManual(FLASHCTL_Regs *flashctl, * @ref DL_FlashCTL_disableOverrideHardwareGeneratedECC is called * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -2093,8 +2069,6 @@ bool DL_FlashCTL_programMemoryBlocking64WithECCGenerated( * @retval DL_FLASHCTL_COMMAND_STATUS_FAILED if command didn't succeed * @retval DL_FLASHCTL_COMMAND_STATUS_PASSED if command was successful * - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -2184,8 +2158,6 @@ bool DL_FlashCTL_programMemoryBlocking64WithECCManual(FLASHCTL_Regs *flashctl, * can be manually provided for programming. This override setting * will persist through multiple programs, until * @ref DL_FlashCTL_disableOverrideHardwareGeneratedECC is called - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -2260,8 +2232,6 @@ bool DL_FlashCTL_programMemoryBlocking(FLASHCTL_Regs *flashctl, * * @pre Before programming memory, the user must unprotect the region * of memory to program. Refer to @ref DL_FlashCTL_unprotectSector - * @post This API just starts the program process. Check the result of it - * using an interrupt or the @ref DL_FlashCTL_waitForCmdDone API * * NOTE: After completion of a program operation, the flash controller will * configure all memory to a protected state. @@ -2972,9 +2942,6 @@ void DL_FlashCTL_blankVerify(FLASHCTL_Regs *flashctl, uint32_t address); * * The command is executed from RAM, and blocks until the command is finished. * - * @post This API just starts the command process. Check if the command - * completed execution using an interrupt or the - * @ref DL_FlashCTL_waitForCmdDone API. * @post @ref DL_FlashCTL_getFailureStatus should be called to determine * the result of the BLANKVERIFY command. The * @ref DL_FlashCTL_getFailureStatus API will return diff --git a/mspm0/source/ti/driverlib/dl_gpamp.h b/mspm0/source/ti/driverlib/dl_gpamp.h index eee120a..d8281d3 100644 --- a/mspm0/source/ti/driverlib/dl_gpamp.h +++ b/mspm0/source/ti/driverlib/dl_gpamp.h @@ -113,9 +113,11 @@ typedef enum { DL_GPAMP_CHOPPING_MODE_DISABLED = SYSCTL_PMUOPAMP_CHOPCLKMODE_CHOPDISABLED, /*! Chopping mode is standard chop */ DL_GPAMP_CHOPPING_MODE_STANDARD = SYSCTL_PMUOPAMP_CHOPCLKMODE_REGCHOP, +#if defined(GPAMP_SYS_ADC_CHOPPING) && (GPAMP_SYS_ADC_CHOPPING == 1) /*! Chopping mode is ADC assisted chop */ DL_GPAMP_CHOPPING_MODE_ADC_ASSISTED = SYSCTL_PMUOPAMP_CHOPCLKMODE_ADCASSIST, +#endif } DL_GPAMP_CHOPPING_MODE; /*! diff --git a/mspm0/source/ti/driverlib/dl_gpio.h b/mspm0/source/ti/driverlib/dl_gpio.h index eb28707..0c6e339 100644 --- a/mspm0/source/ti/driverlib/dl_gpio.h +++ b/mspm0/source/ti/driverlib/dl_gpio.h @@ -1633,9 +1633,16 @@ typedef enum { DL_GPIO_WAKEUP_ON_0 = (IOMUX_PINCM_WUEN_ENABLE | IOMUX_PINCM_WCOMP_MATCH0), /*! Wakeup when pin changes to 1 */ DL_GPIO_WAKEUP_ON_1 = (IOMUX_PINCM_WUEN_ENABLE | IOMUX_PINCM_WCOMP_MATCH1), - } DL_GPIO_WAKEUP; +/*! @enum DL_GPIO_WAKEUP_COMPARE_VALUE */ +typedef enum { + /*! Wakeup compare value of 0 */ + DL_GPIO_WAKEUP_COMPARE_VALUE_0 = IOMUX_PINCM_WCOMP_MATCH0, + /*! Wakeup compare value of 1 */ + DL_GPIO_WAKEUP_COMPARE_VALUE_1 = IOMUX_PINCM_WCOMP_MATCH1, +} DL_GPIO_WAKEUP_COMPARE_VALUE; + /*! @enum DL_GPIO_HIZ */ typedef enum { /*! Enable Hi-Z on pin */ @@ -1943,13 +1950,12 @@ __STATIC_INLINE void DL_GPIO_initDigitalOutputFeatures(uint32_t pincmIndex, __STATIC_INLINE void DL_GPIO_setDigitalInternalResistor( uint32_t pincmIndex, DL_GPIO_RESISTOR internalResistor) { - /* GPIO functionality is always a pin function of 0x00000001 */ - IOMUX->SECCFG.PINCM[pincmIndex] = IOMUX_PINCM_PC_CONNECTED | - ((uint32_t) 0x00000001) | - (uint32_t) internalResistor; + IOMUX->SECCFG.PINCM[pincmIndex] &= + ~(DL_GPIO_RESISTOR_PULL_UP | DL_GPIO_RESISTOR_PULL_DOWN); + IOMUX->SECCFG.PINCM[pincmIndex] |= + IOMUX_PINCM_PC_CONNECTED | (uint32_t) internalResistor; } -// TODO: verify no need to add input/output variable for the Input/Output enebale functionality /** * @brief Configures internal resistor for analog pin * @@ -1964,8 +1970,7 @@ __STATIC_INLINE void DL_GPIO_setAnalogInternalResistor( /* GPIO functionality is always a pin function of 0x00000001 */ /* For analog use case, setting IOMUX input enable */ IOMUX->SECCFG.PINCM[pincmIndex] = - IOMUX_PINCM_INENA_ENABLE | IOMUX_PINCM_PC_UNCONNECTED | - ((uint32_t) 0x00000001) | (uint32_t) internalResistor; + IOMUX_PINCM_PC_UNCONNECTED | (uint32_t) internalResistor; } /** @@ -2008,7 +2013,9 @@ __STATIC_INLINE void DL_GPIO_initDigitalInputFeatures(uint32_t pincmIndex, IOMUX_PINCM_INENA_ENABLE | IOMUX_PINCM_PC_CONNECTED | ((uint32_t) 0x00000001) | (uint32_t) inversion | (uint32_t) internalResistor | (uint32_t) hysteresis | - (uint32_t) wakeup; + ((uint32_t) wakeup & IOMUX_PINCM_WCOMP_MASK); + IOMUX->SECCFG.PINCM[pincmIndex] |= + ((uint32_t) wakeup & IOMUX_PINCM_WUEN_MASK); } /** @@ -2106,7 +2113,9 @@ __STATIC_INLINE void DL_GPIO_initPeripheralInputFunctionFeatures( IOMUX->SECCFG.PINCM[pincmIndex] = function | IOMUX_PINCM_PC_CONNECTED | IOMUX_PINCM_INENA_ENABLE | (uint32_t) inversion | (uint32_t) internalResistor | - (uint32_t) hysteresis | (uint32_t) wakeup; + (uint32_t) hysteresis | ((uint32_t) wakeup & IOMUX_PINCM_WCOMP_MASK); + IOMUX->SECCFG.PINCM[pincmIndex] |= + ((uint32_t) wakeup & IOMUX_PINCM_WUEN_MASK); } /** @@ -2127,6 +2136,8 @@ __STATIC_INLINE void DL_GPIO_initPeripheralAnalogFunction(uint32_t pincmIndex) * @param[in] pincmIndex The PINCM register index that maps to the target * GPIO pin. * + * @note Before enabling wakeup, the wakeup compare value should be configured first + * in @ref DL_GPIO_setWakeupCompareValue. */ __STATIC_INLINE void DL_GPIO_enableWakeUp(uint32_t pincmIndex) { @@ -2159,6 +2170,39 @@ __STATIC_INLINE bool DL_GPIO_isWakeUpEnabled(uint32_t pincmIndex) IOMUX_PINCM_WUEN_ENABLE); } +/** + * @brief Set the compare value to use for wake for the specified pin + * + * @param[in] pincmIndex The PINCM register index that maps to the target + * GPIO pin. + * @param[in] value The wakeup compare value to set. + * One of @ref DL_GPIO_WAKEUP_COMPARE_VALUE + */ +__STATIC_INLINE void DL_GPIO_setWakeupCompareValue( + uint32_t pincmIndex, DL_GPIO_WAKEUP_COMPARE_VALUE value) +{ + DL_Common_updateReg(&IOMUX->SECCFG.PINCM[pincmIndex], (uint32_t) value, + IOMUX_PINCM_WCOMP_MASK); +} + +/** + * @brief Get the compare value to use for wake for the specified pin + * + * @param[in] pincmIndex The PINCM register index that maps to the target + * GPIO pin. + * + * @return The wakeup compare value for the specified pin + * + * @retval One of @ref DL_GPIO_WAKEUP_COMPARE_VALUE + */ +__STATIC_INLINE DL_GPIO_WAKEUP_COMPARE_VALUE DL_GPIO_getWakeupCompareValue( + uint32_t pincmIndex) +{ + uint32_t value = IOMUX->SECCFG.PINCM[pincmIndex] & IOMUX_PINCM_WCOMP_MASK; + + return (DL_GPIO_WAKEUP_COMPARE_VALUE)(value); +} + /** * @brief Checks if the GPIO pin's Wake State bit is active. * diff --git a/mspm0/source/ti/driverlib/dl_i2c.c b/mspm0/source/ti/driverlib/dl_i2c.c index c6ee878..81caf3a 100644 --- a/mspm0/source/ti/driverlib/dl_i2c.c +++ b/mspm0/source/ti/driverlib/dl_i2c.c @@ -132,6 +132,10 @@ void DL_I2C_transmitTargetDataBlocking(I2C_Regs *i2c, uint8_t data) ; } DL_I2C_transmitTargetData(i2c, data); + while ((DL_I2C_getTargetStatus(i2c) & DL_I2C_TARGET_STATUS_BUS_BUSY) == + DL_I2C_TARGET_STATUS_BUS_BUSY) { + ; + } } bool DL_I2C_transmitTargetDataCheck(I2C_Regs *i2c, uint8_t data) diff --git a/mspm0/source/ti/driverlib/dl_i2c.h b/mspm0/source/ti/driverlib/dl_i2c.h index 2d49dd8..92d874e 100644 --- a/mspm0/source/ti/driverlib/dl_i2c.h +++ b/mspm0/source/ti/driverlib/dl_i2c.h @@ -427,6 +427,11 @@ extern "C" { /** @}*/ +/*! + * @brief Backwards compatible redirect for @ref DL_I2C_getTargetOwnAddressAlternateMask +*/ +#define I2C_getTargetOwnAddressAlternateMask DL_I2C_getTargetOwnAddressAlternateMask + /* clang-format on */ /*! @enum DL_I2C_DMA_IIDX */ @@ -780,6 +785,7 @@ void DL_I2C_getClockConfig(const I2C_Regs *i2c, DL_I2C_ClockConfig *config); * @param[in] i2c Pointer to the register overlay for the peripheral * @param[in] buffer Pointer to buffer of bytes * @param[in] count Number of bytes to fill controller TX FIFO from buffer + * [0x00, 0xFFF] * * @return Number of bytes that were successfully written */ @@ -871,6 +877,7 @@ __STATIC_INLINE void DL_I2C_resetControllerTransfer(I2C_Regs *i2c) * @param[in] targetAddr Target address [0x00, 0x3FF] * @param[in] direction One of @ref DL_I2C_CONTROLLER_DIRECTION * @param[in] length Intended burst length in number of bytes + * [0x00, 0xFFF] */ __STATIC_INLINE void DL_I2C_startControllerTransfer(I2C_Regs *i2c, uint32_t targetAddr, DL_I2C_CONTROLLER_DIRECTION direction, @@ -995,7 +1002,10 @@ void DL_I2C_flushTargetTXFIFO(I2C_Regs *i2c); void DL_I2C_flushTargetRXFIFO(I2C_Regs *i2c); /** - * @brief Transmit target data, waiting until transmit request + * @brief Transmit target data, blocking until transmit request is received. + * Will wait indefintely until bus is not busy. Note that if data is + * already present in the TX FIFO when this API is called, it will + * block until all data is sent. * * @note Setting own target addresses and enabling target should be done * separately. @@ -2390,7 +2400,7 @@ __STATIC_INLINE void DL_I2C_setTargetOwnAddressAlternate( * @retval Bit mask with each bit corresponding to bits A6 through A0 of * the target address. Value between [0x00, 0x7F] */ -__STATIC_INLINE uint32_t I2C_getTargetOwnAddressAlternateMask( +__STATIC_INLINE uint32_t DL_I2C_getTargetOwnAddressAlternateMask( const I2C_Regs *i2c) { return ((i2c->SLAVE.SOAR2 & I2C_SOAR2_OAR2_MASK_MASK) >> @@ -3314,7 +3324,7 @@ __STATIC_INLINE void DL_I2C_enableTargetPEC(I2C_Regs *i2c) */ __STATIC_INLINE uint32_t DL_I2C_getTargetCurrentPECCount(const I2C_Regs *i2c) { - return (i2c->SLAVE.TARGET_PECCTL & I2C_TARGET_PECSR_PECBYTECNT_MASK); + return (i2c->SLAVE.TARGET_PECSR & I2C_TARGET_PECSR_PECBYTECNT_MASK); } /** diff --git a/mspm0/source/ti/driverlib/dl_i2s.c b/mspm0/source/ti/driverlib/dl_i2s.c new file mode 100644 index 0000000..2d1bfc2 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_i2s.c @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MSPM0_HAS_I2S__ + +/** + * @brief I2S APIs + */ + +void DL_I2S_setClockConfig(I2S_Regs *i2s, const DL_I2S_ClockConfig *config) +{ + i2s->GPRCM.CLKCFG = I2S_CLKCFG_KEY_UNLOCK | config->clockSel; + + DL_Common_updateReg(&i2s->WCLKSRC, (uint32_t) config->wordBaudClockSource, + I2S_WCLKSRC_WBCLKSRC_MASK); + + DL_Common_updateReg( + &i2s->CLKCTL, (uint32_t) config->wclkPhase, I2S_CLKCTL_WCLKPHASE_MASK); + + i2s->WCLKDIV = config->wclkDivider; + i2s->BCLKDIV = config->bclkDivider; +} + +void DL_I2S_getClockConfig(const I2S_Regs *i2s, DL_I2S_ClockConfig *config) +{ + uint32_t clockSel = i2s->GPRCM.CLKCFG & I2S_CLKCFG_DAICLK_MASK; + config->clockSel = (DL_I2S_CLOCK_SOURCE)(clockSel); + + uint32_t wordBaudClockSource = i2s->WCLKSRC & I2S_WCLKSRC_WBCLKSRC_MASK; + config->wordBaudClockSource = + (DL_I2S_WORD_BAUD_CLOCK_SOURCE)(wordBaudClockSource); + + uint32_t wclkPhase = i2s->CLKCTL & I2S_CLKCTL_WCLKPHASE_MASK; + config->wclkPhase = (DL_I2S_WCLK_PHASE)(wclkPhase); + + config->wclkDivider = i2s->WCLKDIV; + config->bclkDivider = i2s->BCLKDIV; +} + +void DL_I2S_init(I2S_Regs *i2s, const DL_I2S_Config *config) +{ + DL_Common_updateReg(&i2s->WCLKSRC, (uint32_t) config->wclkInvert, + I2S_WCLKSRC_WCLKINV_MASK); + + DL_Common_updateReg(&i2s->FMTCFG, + ((uint32_t) config->emptySlotOutput | (uint32_t) config->dataDelay | + (uint32_t) config->memoryAccessLength | + (uint32_t) config->samplingEdge | (uint32_t) config->phase), + (I2S_FMTCFG_EMPTYSLOTOUTPUT_MASK | I2S_FMTCFG_DATADLY_MASK | + I2S_FMTCFG_MEMLEN32_MASK | I2S_FMTCFG_SMPLEDGE_MASK | + I2S_FMTCFG_DUALPHASE_MASK)); + + DL_I2S_setSampleWordLength(i2s, config->sampleWordLength); + + DL_Common_updateReg(&i2s->DIRCFG, + ((uint32_t) config->dataPin0Direction) << I2S_DIRCFG_AD0_OFS, + I2S_DIRCFG_AD0_MASK); + i2s->WMASK0 = config->dataPin0ValidChannelMask; + +#ifdef DEVICE_HAS_MULTIPLE_DATA_PIN + DL_Common_updateReg(&i2s->DIRCFG, + ((uint32_t) config->dataPin1Direction) << I2S_DIRCFG_AD1_OFS, + I2S_DIRCFG_AD1_MASK); + i2s->WMASK1 = config->dataPin1ValidChannelMask; +#endif + + if (config->mode == DL_I2S_MODE_CONTROLLER) { + if (config->enableMCLK) { + /* If optional MCLK generation is required, configure MCLK */ + DL_Common_updateReg(&i2s->CLKCTL, + (I2S_CLKCTL_WBEN_EN | I2S_CLKCTL_MEN_EN), + (I2S_CLKCTL_WBEN_MASK | I2S_CLKCTL_MEN_MASK)); + } else { + /* Otherwise generate WCLK and BCLK only */ + DL_Common_updateReg(&i2s->CLKCTL, + (I2S_CLKCTL_WBEN_EN | I2S_CLKCTL_MEN_DIS), + (I2S_CLKCTL_WBEN_MASK | I2S_CLKCTL_MEN_MASK)); + } + } else { + /* In target mode, WCLK and BCLK are input signals */ + DL_Common_updateReg(&i2s->CLKCTL, + I2S_CLKCTL_WBEN_DIS | I2S_CLKCTL_MEN_DIS, + I2S_CLKCTL_WBEN_MASK | I2S_CLKCTL_MEN_MASK); + } + + /* Divider can be set outside of controller mode */ + i2s->MCLKDIV = config->mclkDivider; +} + +DL_I2S_MODE DL_I2S_getMode(const I2S_Regs *i2s) +{ + DL_I2S_MODE mode = DL_I2S_MODE_CONTROLLER; + + if (DL_I2S_isWBCLKGenerationEnabled(i2s)) { + mode = DL_I2S_MODE_CONTROLLER; + } else { + mode = DL_I2S_MODE_TARGET; + } + + return mode; +} + +void DL_I2S_setMode(I2S_Regs *i2s, DL_I2S_MODE mode) +{ + if (mode == DL_I2S_MODE_CONTROLLER) { + /* Controller mode means that I2S generates WCLK and BCLK */ + DL_I2S_enableWBCLKGeneration(i2s); + } else { + /* Target mode means that I2S consumes WCLK and BCLK */ + DL_I2S_disableWBCLKGeneration(i2s); + } +} + +void DL_I2S_transmitDataBlocking8(I2S_Regs *i2s, uint8_t data) +{ + while (DL_I2S_isTXFIFOFull(i2s)) { + ; + } + + DL_I2S_transmitData8(i2s, data); +} + +void DL_I2S_transmitDataBlocking16(I2S_Regs *i2s, uint16_t data) +{ + while (DL_I2S_isTXFIFOFull(i2s)) { + ; + } + + DL_I2S_transmitData16(i2s, data); +} + +void DL_I2S_transmitDataBlocking32(I2S_Regs *i2s, uint32_t data) +{ + while (DL_I2S_isTXFIFOFull(i2s)) { + ; + } + + DL_I2S_transmitData32(i2s, data); +} + +uint8_t DL_I2S_receiveDataBlocking8(const I2S_Regs *i2s) +{ + while (DL_I2S_isRXFIFOEmpty(i2s)) { + ; + } + + return DL_I2S_receiveData8(i2s); +} + +uint16_t DL_I2S_receiveDataBlocking16(const I2S_Regs *i2s) +{ + while (DL_I2S_isRXFIFOEmpty(i2s)) { + ; + } + + return DL_I2S_receiveData16(i2s); +} + +uint32_t DL_I2S_receiveDataBlocking32(const I2S_Regs *i2s) +{ + while (DL_I2S_isRXFIFOEmpty(i2s)) { + ; + } + + return DL_I2S_receiveData32(i2s); +} + +bool DL_I2S_transmitDataCheck8(I2S_Regs *i2s, uint8_t data) +{ + bool status; + if (DL_I2S_isTXFIFOFull(i2s)) { + status = false; + } else { + DL_I2S_transmitData8(i2s, data); + status = true; + } + return status; +} + +bool DL_I2S_transmitDataCheck16(I2S_Regs *i2s, uint16_t data) +{ + bool status; + if (DL_I2S_isTXFIFOFull(i2s)) { + status = false; + } else { + DL_I2S_transmitData16(i2s, data); + status = true; + } + return status; +} + +bool DL_I2S_transmitDataCheck32(I2S_Regs *i2s, uint32_t data) +{ + bool status; + if (DL_I2S_isTXFIFOFull(i2s)) { + status = false; + } else { + DL_I2S_transmitData32(i2s, data); + status = true; + } + return status; +} + +bool DL_I2S_receiveDataCheck8(const I2S_Regs *i2s, uint8_t *buffer) +{ + bool status; + if (DL_I2S_isRXFIFOEmpty(i2s)) { + status = false; + } else { + *buffer = DL_I2S_receiveData8(i2s); + status = true; + } + return status; +} + +bool DL_I2S_receiveDataCheck16(const I2S_Regs *i2s, uint16_t *buffer) +{ + bool status; + if (DL_I2S_isRXFIFOEmpty(i2s)) { + status = false; + } else { + *buffer = DL_I2S_receiveData16(i2s); + status = true; + } + return status; +} + +bool DL_I2S_receiveDataCheck32(const I2S_Regs *i2s, uint32_t *buffer) +{ + bool status; + if (DL_I2S_isRXFIFOEmpty(i2s)) { + status = false; + } else { + *buffer = DL_I2S_receiveData32(i2s); + status = true; + } + return status; +} + +uint32_t DL_I2S_drainRXFIFO8( + const I2S_Regs *i2s, uint8_t *buffer, uint32_t maxCount) +{ + uint32_t i; + for (i = 0; i < maxCount; i++) { + if (!DL_I2S_isRXFIFOEmpty(i2s)) { + buffer[i] = DL_I2S_receiveData8(i2s); + } else { + break; + } + } + + return i; +} + +uint32_t DL_I2S_drainRXFIFO16( + const I2S_Regs *i2s, uint16_t *buffer, uint32_t maxCount) +{ + uint32_t i; + for (i = 0; i < maxCount; i++) { + if (!DL_I2S_isRXFIFOEmpty(i2s)) { + buffer[i] = DL_I2S_receiveData16(i2s); + } else { + break; + } + } + + return i; +} + +uint32_t DL_I2S_drainRXFIFO32( + const I2S_Regs *i2s, uint32_t *buffer, uint32_t maxCount) +{ + uint32_t i; + for (i = 0; i < maxCount; i++) { + if (!DL_I2S_isRXFIFOEmpty(i2s)) { + buffer[i] = DL_I2S_receiveData32(i2s); + } else { + break; + } + } + + return i; +} + +uint32_t DL_I2S_fillTXFIFO8( + I2S_Regs *i2s, const uint8_t *buffer, uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) { + if (!DL_I2S_isTXFIFOFull(i2s)) { + DL_I2S_transmitData8(i2s, buffer[i]); + } else { + break; + } + } + + return i; +} + +uint32_t DL_I2S_fillTXFIFO16( + I2S_Regs *i2s, const uint16_t *buffer, uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) { + if (!DL_I2S_isTXFIFOFull(i2s)) { + DL_I2S_transmitData16(i2s, buffer[i]); + } else { + break; + } + } + + return i; +} + +uint32_t DL_I2S_fillTXFIFO32( + I2S_Regs *i2s, const uint32_t *buffer, uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) { + if (!DL_I2S_isTXFIFOFull(i2s)) { + DL_I2S_transmitData32(i2s, buffer[i]); + } else { + break; + } + } + + return i; +} + +void DL_I2S_clearTXFIFO(I2S_Regs *i2s) +{ + DL_Common_updateReg( + &i2s->IFLS, I2S_IFLS_TXCLR_ENABLE, I2S_IFLS_TXCLR_MASK); + + while (!DL_I2S_isTXFIFOClearComplete(i2s)) { + ; + } + + DL_Common_updateReg( + &i2s->IFLS, I2S_IFLS_TXCLR_DISABLE, I2S_IFLS_TXCLR_MASK); +} + +void DL_I2S_clearRXFIFO(I2S_Regs *i2s) +{ + DL_Common_updateReg( + &i2s->IFLS, I2S_IFLS_RXCLR_ENABLE, I2S_IFLS_RXCLR_MASK); + + while (!DL_I2S_isRXFIFOClearComplete(i2s)) { + ; + } + + DL_Common_updateReg( + &i2s->IFLS, I2S_IFLS_RXCLR_DISABLE, I2S_IFLS_RXCLR_MASK); +} + +#endif /* __MSPM0_HAS_I2S__ */ diff --git a/mspm0/source/ti/driverlib/dl_i2s.h b/mspm0/source/ti/driverlib/dl_i2s.h new file mode 100644 index 0000000..4f1242a --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_i2s.h @@ -0,0 +1,2264 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_i2s.h + * @brief Inter-Integrated Circuit Sound (I2S) Driver Library + * @defgroup I2S Inter-Integrated Circuit Sound (I2S) + * + * @anchor ti_dl_dl_i2s_Overview + * # Overview + * + * The I2S Library allows full configuration of the MSPM0 I2S module. + * The I2S module provides a standardized serial interface to transfer audio + * data between MSP devices and other external devices (such as an audio + * amplifier). + * + *
+ ****************************************************************************** + */ +/** @addtogroup I2S + * @{ + */ +#ifndef ti_dl_dl_i2s__include +#define ti_dl_dl_i2s__include + +#include +#include + +#include +#include + +#ifdef __MSPM0_HAS_I2S__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +#if (I2S0_SYS_SINGLE_PIN == 0) +/** + * @brief Device supports multiple data pins + */ +#define DEVICE_HAS_MULTIPLE_DATA_PIN +#endif + +/** + * @brief I2S Minimum factor of the division ratio used to generate the + * controller clock (MCLK). The minimum is 2, since 0 is evaluated as + * 1024, which is the maximum factor, and 1 is invalid. + */ +#define DL_I2S_MDIV_MINIMUM ((uint32_t)2U) + +/** + * @brief I2S Maximum factor of the division ratio used to generate the + * controller clock (MCLK). The maximum is 0, which is interpreted as 1024. + */ +#define DL_I2S_MDIV_MAXIMUM ((uint32_t)0U) + +/** + * @brief I2S Invalid factor of the division ratio used to generate the + * controller clock (MCLK). This is 1. + */ +#define DL_I2S_MDIV_INVALID ((uint32_t)1U) + +/** + * @brief I2S Minimum factor of the division ratio used to generate BCLK. The + * minimum is 2, since the 0 is interpreted as 1024, which is the maximum + * factor, and 1 is invalid. + */ +#define DL_I2S_BDIV_MINIMUM ((uint32_t)2U) + +/** + * @brief I2S Maximum factor of the division ratio used to generate BCLK. + * The maximum is 0, which is interpreted as 1024. + */ +#define DL_I2S_BDIV_MAXIMUM ((uint32_t)0U) + +/** + * @brief I2S Invalid factor of the division ratio used to generate BCLK. This + * is 1. + */ +#define DL_I2S_BDIV_INVALID ((uint32_t)1U) + +/** @addtogroup DL_I2S_INTERRUPT + * @{ + */ +/*! + * @brief WCLK Error Interrupt + */ +#define DL_I2S_INTERRUPT_WCLK_ERROR (I2S_CPU_INT_IMASK_WCLKERR_EN) + +/*! + * @brief RXFIFO Trigger when >= trigger level Interrupt + */ +#define DL_I2S_INTERRUPT_RXFIFO_TRIGGER (I2S_CPU_INT_IMASK_RXINT_SET) + +/*! + * @brief TXFIFO when <= trigger level Interrupt + */ +#define DL_I2S_INTERRUPT_TXFIFO_TRIGGER (I2S_CPU_INT_IMASK_TXINT_SET) + +/*! + * @brief DMA Done on RX Event Channel Interrupt + */ +#define DL_I2S_INTERRUPT_DMA_DONE_RX (I2S_CPU_INT_IMASK_DMA_DONE_RX_SET) + +/*! + * @brief DMA Done on TX Event Channel Interrupt + */ +#define DL_I2S_INTERRUPT_DMA_DONE_TX (I2S_CPU_INT_IMASK_DMA_DONE_TX_SET) + +/*! + * @brief RXFIFO Overflow Event Interrupt + */ +#define DL_I2S_INTERRUPT_RXFIFO_OVERFLOW (I2S_CPU_INT_IMASK_RXFIFO_OVF_SET) + +/*! + * @brief TXFIFO Underflow Event Interrupt + */ +#define DL_I2S_INTERRUPT_TXFIFO_UNDERFLOW (I2S_CPU_INT_IMASK_TXFIFO_UNF_SET) + +/** @}*/ + +/** @addtogroup DL_I2S_DMA_INTERRUPT + * @{ + */ +/*! + * @brief Transmit interrupt for DMA trigger + */ +#define DL_I2S_DMA_INTERRUPT_TX_TRIGGER (I2S_DMA_TRIG_TX_IMASK_TXINT_SET) + +/*! + * @brief Receive interrupt for DMA trigger + */ +#define DL_I2S_DMA_INTERRUPT_RX_TRIGGER (I2S_DMA_TRIG_RX_IMASK_RXINT_SET) + +/** @}*/ + +/* clang-format on */ + +/** @enum DL_I2S_WORD_BAUD_CLOCK_SOURCE */ +typedef enum { + /*! No source for audio clocks WCLK and BCLK */ + DL_I2S_WORD_BAUD_CLOCK_SOURCE_NONE = I2S_WCLKSRC_WBCLKSRC_NONE, + /*! External source for audio clocks WCLK and BCLK from pin */ + DL_I2S_WORD_BAUD_CLOCK_SOURCE_EXTERNAL = I2S_WCLKSRC_WBCLKSRC_EXT, + /*! Internal source for audio clocks WCLK and BCLK from module PRCM */ + DL_I2S_WORD_BAUD_CLOCK_SOURCE_INTERNAL = I2S_WCLKSRC_WBCLKSRC_INT, +} DL_I2S_WORD_BAUD_CLOCK_SOURCE; + +/** @enum DL_I2S_CLOCK_SOURCE */ +typedef enum { + /*! Select SYSOSC as the clock source for I2S */ + DL_I2S_CLOCK_SOURCE_SYSOSC = I2S_CLKCFG_DAICLK_SYSOSC, + /*! Select HFXT as the clock source for I2S */ + DL_I2S_CLOCK_SOURCE_HFXT = I2S_CLKCFG_DAICLK_HFXT, + /*! Select PLL as the clock source for I2S */ + DL_I2S_CLOCK_SOURCE_PLL = I2S_CLKCFG_DAICLK_PLL, +} DL_I2S_CLOCK_SOURCE; + +/** @enum DL_I2S_WCLK_INVERSION */ +typedef enum { + /*! WCLK is not inverted */ + DL_I2S_WCLK_INVERSION_DISABLED = I2S_WCLKSRC_WCLKINV_NOT_INVERTED, + /*! WCLK is inverted */ + DL_I2S_WCLK_INVERSION_ENABLED = I2S_WCLKSRC_WCLKINV_INVERTED, +} DL_I2S_WCLK_INVERSION; + +/** @enum DL_I2S_PHASE */ +typedef enum { + /*! I2S Single-Phase (DSP format) */ + DL_I2S_PHASE_SINGLE = I2S_FMTCFG_DUALPHASE_SINGLEPHASE, + /*! I2S Dual-Phase (I2S, LJF and RJF) */ + DL_I2S_PHASE_DUAL = I2S_FMTCFG_DUALPHASE_DUALPHASE, +} DL_I2S_PHASE; + +/** @enum DL_I2S_SAMPLE_EDGE */ +typedef enum { + /*! Data sampled on negative edge, clocked out on positive edge */ + DL_I2S_SAMPLE_EDGE_NEG = I2S_FMTCFG_SMPLEDGE_NEGEDGE, + /*! Data sampled on positive edge, clocked out on negative edge */ + DL_I2S_SAMPLE_EDGE_POS = I2S_FMTCFG_SMPLEDGE_POSEDGE, +} DL_I2S_SAMPLE_EDGE; + +/** @enum DL_I2S_MEMORY_LENGTH */ +typedef enum { + /*! 16-bit memory access per sample */ + DL_I2S_MEMORY_LENGTH_16_BIT = I2S_FMTCFG_MEMLEN32_16BIT, + /*! 32-bit memory access per sample */ + DL_I2S_MEMORY_LENGTH_32_BIT = I2S_FMTCFG_MEMLEN32_32BIT, +} DL_I2S_MEMORY_LENGTH; + +/** @enum DL_I2S_DATA_DELAY */ +typedef enum { + /*! Zero BCLK period delay between WCLK edge and MSB of first word */ + DL_I2S_DATA_DELAY_ZERO = I2S_FMTCFG_DATADLY_ZERO, + /*! One BCLK period delay between WCLK edge and MSB of first word */ + DL_I2S_DATA_DELAY_ONE = I2S_FMTCFG_DATADLY_ONE, + /*! Two BCLK periods delay between WCLK edge and MSB of first word */ + DL_I2S_DATA_DELAY_TWO = I2S_FMTCFG_DATADLY_TWO, + /*! Max BCLK periods delay between WCLK edge and MSB of first word */ + DL_I2S_DATA_DELAY_MAX = I2S_FMTCFG_DATADLY_MAX, +} DL_I2S_DATA_DELAY; + +/** @enum DL_I2S_EMPTY_SLOT_OUTPUT */ +typedef enum { + /*! Send out zeroes in empty slots */ + DL_I2S_EMPTY_SLOT_OUTPUT_ZERO = I2S_FMTCFG_EMPTYSLOTOUTPUT_ZERO, + /*! Send out ones in empty slots */ + DL_I2S_EMPTY_SLOT_OUTPUT_ONE = I2S_FMTCFG_EMPTYSLOTOUTPUT_ONE, + /*! Tristate data pin line during empty slot */ + DL_I2S_EMPTY_SLOT_OUTPUT_TRISTATE = I2S_FMTCFG_EMPTYSLOTOUTPUT_TRISTATE, +} DL_I2S_EMPTY_SLOT_OUTPUT; + +/** @enum DL_I2S_WCLK_PHASE */ +typedef enum { + /*! Calculate WCLK division ratio for single phase operation */ + DL_I2S_WCLK_PHASE_SINGLE = (0U << I2S_CLKCTL_WCLKPHASE_OFS), + /*! Calculate WCLK division ratio for dual phase operation */ + DL_I2S_WCLK_PHASE_DUAL = (1U << I2S_CLKCTL_WCLKPHASE_OFS), + /*! Calculate user-defined custom WCLK division ratio */ + DL_I2S_WCLK_PHASE_CUSTOM = (2U << I2S_CLKCTL_WCLKPHASE_OFS), +} DL_I2S_WCLK_PHASE; + +/** @enum DL_I2S_MODE */ +typedef enum { + /*! I2S controller mode. Module outputs audio clock signals (WCLK, BCLK) */ + DL_I2S_MODE_CONTROLLER = 0U, + /*! I2S target mode. Audio clock signals are inputs (WCLK, BCLK) */ + DL_I2S_MODE_TARGET = 1U, +} DL_I2S_MODE; + +/** @enum DL_I2S_DATA_PIN_DIRECTION */ +typedef enum { + /*! Data pin not in use (disabled) */ + DL_I2S_DATA_PIN_DIRECTION_UNUSED = 0U, + /*! Data pin acts as input */ + DL_I2S_DATA_PIN_DIRECTION_INPUT = 1U, + /*! Data pin acts as output */ + DL_I2S_DATA_PIN_DIRECTION_OUTPUT = 2U, +} DL_I2S_DATA_PIN_DIRECTION; + +/** @enum DL_I2S_TX_FIFO_LEVEL */ +typedef enum { + /*! Trigger when the TX FIFO <= 3/4 empty */ + DL_I2S_TX_FIFO_LEVEL_3_4_EMPTY = I2S_IFLS_TXIFLSEL_LVL_3_4, + /*! Trigger when TX FIFO <= 1/2 empty (default) */ + DL_I2S_TX_FIFO_LEVEL_1_2_EMPTY = I2S_IFLS_TXIFLSEL_LVL_1_2, + /*! Trigger when TX FIFO <= 1/4 empty */ + DL_I2S_TX_FIFO_LEVEL_1_4_EMPTY = I2S_IFLS_TXIFLSEL_LVL_1_4, + /*! Trigger when TX FIFO is empty */ + DL_I2S_TX_FIFO_LEVEL_EMPTY = I2S_IFLS_TXIFLSEL_LVL_EMPTY, + /*! Trigger when TX FIFO <= 1 */ + DL_I2S_TX_FIFO_LEVEL_ONE_ENTRY = I2S_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY, + /*! Trigger when TX FIFO >= (MAX_FIFO_LEN - 1) */ + DL_I2S_TX_FIFO_LEVEL_ALMOST_FULL = I2S_IFLS_TXIFLSEL_LVL_ALMOST_FULL, +} DL_I2S_TX_FIFO_LEVEL; + +/** @enum DL_I2S_RX_FIFO_LEVEL */ +typedef enum { + /*! Trigger when RX FIFO >= 1/4 full */ + DL_I2S_RX_FIFO_LEVEL_1_4_FULL = I2S_IFLS_RXIFLSEL_LVL_1_4, + /*! Trigger when RX FIFO >= 1/2 full (default) */ + DL_I2S_RX_FIFO_LEVEL_1_2_FULL = I2S_IFLS_RXIFLSEL_LVL_1_2, + /*! Trigger when RX FIFO >= 3/4 full */ + DL_I2S_RX_FIFO_LEVEL_3_4_FULL = I2S_IFLS_RXIFLSEL_LVL_3_4, + /*! Trigger when RX FIFO is full */ + DL_I2S_RX_FIFO_LEVEL_FULL = I2S_IFLS_RXIFLSEL_LVL_FULL, + /*! Trigger when RX FIFO >= (MAX_FIFO_LEN - 1) */ + DL_I2S_RX_FIFO_LEVEL_ALMOST_FULL = I2S_IFLS_RXIFLSEL_LVL_ALMOST_FULL, + /*! Trigger when RX FIFO <= 1 */ + DL_I2S_RX_FIFO_LEVEL_ONE_ENTRY = I2S_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY, +} DL_I2S_RX_FIFO_LEVEL; + +/*! @enum DL_I2S_IIDX */ +typedef enum { + /*! Interrupt index for I2S if no interrupt is pending */ + DL_I2S_IIDX_NO_INT = I2S_IIDX_STAT_NO_INTR, + /*! Interrupt index for I2S WCLK Error */ + DL_I2S_IIDX_WCLK_ERR = I2S_IIDX_STAT_WCLKERR, + /*! Interrupt index for I2S Receive Interrupt */ + DL_I2S_IIDX_RX_DONE = I2S_IIDX_STAT_RXIFG, + /*! Interrupt index for I2S Transmit Interrupt */ + DL_I2S_IIDX_TX_DONE = I2S_IIDX_STAT_TXIFG, + /*! Interrupt index for I2S RXFIFO Overflow Event */ + DL_I2S_IIDX_RXFIFO_OVERFLOW = I2S_IIDX_STAT_RXFIFO_OVF_EVT, + /*! Interrupt index for I2S TXFIFO Underflow Event */ + DL_I2S_IIDX_TXFIFO_UNDERFLOW = I2S_IIDX_STAT_TXFIFO_UNF_EVT, + /*! Interrupt index for DMA Done on RX */ + DL_I2S_IIDX_DMA_DONE_RX = I2S_IIDX_STAT_DMA_DONE_RX, + /*! Interrupt index for DMA Done on TX */ + DL_I2S_IIDX_DMA_DONE_TX = I2S_IIDX_STAT_DMA_DONE_TX, +} DL_I2S_IIDX; + +/** + * @brief Configuration struct for @ref DL_I2S_setClockConfig. + */ +typedef struct { + /*! I2S clock source. One of @ref DL_I2S_CLOCK_SOURCE */ + DL_I2S_CLOCK_SOURCE clockSel; + /*! Audio clocks (WCLK, BCLK) source. One of @ref DL_I2S_WORD_BAUD_CLOCK_SOURCE */ + DL_I2S_WORD_BAUD_CLOCK_SOURCE wordBaudClockSource; + /*! WCLK phase. One of @ref DL_I2S_WCLK_PHASE */ + DL_I2S_WCLK_PHASE wclkPhase; + /*! WCLK divide ratio. [0x1, 0xFFFF] */ + uint32_t wclkDivider; + /*! BCLK divide ratio. [ @ref DL_I2S_BDIV_MINIMUM, @ref DL_I2S_BDIV_MAXIMUM] */ + uint32_t bclkDivider; +} DL_I2S_ClockConfig; + +/** + * @brief Configuration struct for @ref DL_I2S_init. + */ +typedef struct { + /*! Controller or target mode. One of @ref DL_I2S_MODE */ + DL_I2S_MODE mode; + /*! WCLK inversion. One of @ref DL_I2S_WCLK_INVERSION */ + DL_I2S_WCLK_INVERSION wclkInvert; + /*! Single or dual-phase. One of @ref DL_I2S_PHASE */ + DL_I2S_PHASE phase; + /*! Positive or negative sampling edge. One of @ref DL_I2S_SAMPLE_EDGE */ + DL_I2S_SAMPLE_EDGE samplingEdge; + /*! Number of bits per sample word. [7, 31]. See @ref DL_I2S_setSampleWordLength */ + uint32_t sampleWordLength; + /*! Data delay. One of @ref DL_I2S_DATA_DELAY */ + DL_I2S_DATA_DELAY dataDelay; + /*! Empty slot output. One of @ref DL_I2S_EMPTY_SLOT_OUTPUT */ + DL_I2S_EMPTY_SLOT_OUTPUT emptySlotOutput; + /*! Memory access length. One of @ref DL_I2S_MEMORY_LENGTH */ + DL_I2S_MEMORY_LENGTH memoryAccessLength; + /*! Data pin 0 (AD0) direction. One of @ref DL_I2S_DATA_PIN_DIRECTION */ + DL_I2S_DATA_PIN_DIRECTION dataPin0Direction; + /*! Valid channel mask for a frame on a data pin. [0, 0xFF] */ + uint32_t dataPin0ValidChannelMask; +#ifdef DEVICE_HAS_MULTIPLE_DATA_PIN + /*! Data pin 1 (AD1) direction. One of @ref DL_I2S_DATA_PIN_DIRECTION */ + DL_I2S_DATA_PIN_DIRECTION dataPin1Direction; + /*! Valid channel mask for a frame on a data pin. [0, 0xFF] */ + uint32_t dataPin1ValidChannelMask; +#endif + /*! MCLK divide ratio. [ @ref DL_I2S_MDIV_MINIMUM, @ref DL_I2S_MDIV_MAXIMUM] */ + uint32_t mclkDivider; + /*! Enable the optional MCLK signal. Controller mode only */ + bool enableMCLK; +} DL_I2S_Config; + +/** + * @brief Configure I2S audio clocks (WCLK and BCLK) + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_I2S_ClockConfig. + */ +void DL_I2S_setClockConfig(I2S_Regs *i2s, const DL_I2S_ClockConfig *config); + +/** + * @brief Get I2S audio clocks configuration (WCLK and BCLK) + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[out] config Pointer to the clock configuration struct + * @ref DL_I2S_ClockConfig. + */ +void DL_I2S_getClockConfig(const I2S_Regs *i2s, DL_I2S_ClockConfig *config); + +/** + * @brief Initialize the I2S peripheral + * + * Initializes all the common configurable options for the I2S peripheral. Any + * other custom configuration can be done after calling this API. The I2S is + * not enabled in this API. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] config Configuration for I2S peripheral + */ +void DL_I2S_init(I2S_Regs *i2s, const DL_I2S_Config *config); + +/** + * @brief Writes 8-bit data into the TX FIFO for transmit + * + * Puts the data into the TX FIFO without checking its status. Use if already + * sure the TX FIFO has space for the write. See related APIs for additional + * transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_I2S_transmitDataBlocking8 + * @sa DL_I2S_transmitDataCheck8 + */ +__STATIC_INLINE void DL_I2S_transmitData8(I2S_Regs *i2s, uint8_t data) +{ + i2s->TXDATA = data; +} + +/** + * @brief Writes 16-bit data into the TX FIFO for transmit + * + * Puts the data into the TX FIFO without checking its status. Use if already + * sure the TX FIFO has space for the write. See related APIs for additional + * transmit options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_I2S_transmitDataBlocking16 + * @sa DL_I2S_transmitDataCheck16 + */ +__STATIC_INLINE void DL_I2S_transmitData16(I2S_Regs *i2s, uint16_t data) +{ + i2s->TXDATA = data; +} + +/** + * @brief Writes 32-bit data into the TX FIFO for transmit + * + * Puts the data into the TX FIFO without checking its status. Use if already + * sure the TX FIFO has space for the write. See related APIs for additional + * transmit options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * NOTE: A 32-bit write will be written as one FIFO entry. The application can + * choose to pack two 16-bit frames into one word. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_I2S_transmitDataBlocking32 + * @sa DL_I2S_transmitDataCheck32 + */ +__STATIC_INLINE void DL_I2S_transmitData32(I2S_Regs *i2s, uint32_t data) +{ + i2s->TXDATA = data; +} + +/** + * @brief Reads 8-bit data from the RX FIFO + * + * Reads the data from the RX FIFO without checking its status. Use if + * already sure the RX FIFO has data available. See related APIs for + * additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_I2S_receiveDataBlocking8 + * @sa DL_I2S_receiveDataCheck8 + */ +__STATIC_INLINE uint8_t DL_I2S_receiveData8(const I2S_Regs *i2s) +{ + return ((uint8_t)(i2s->RXDATA)); +} + +/** + * @brief Reads 16-bit data from the RX FIFO + * + * Reads the data from the RX FIFO without checking its status. Use if + * already sure the RX FIFO has data available. See related APIs for + * additional receive options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_I2S_receiveDataBlocking16 + * @sa DL_I2S_receiveDataCheck16 + */ +__STATIC_INLINE uint16_t DL_I2S_receiveData16(const I2S_Regs *i2s) +{ + return ((uint16_t)(i2s->RXDATA)); +} + +/** + * @brief Reads 32-bit data from the RX FIFO + * + * Reads the data from the RX FIFO without checking its status. Use if + * already sure the RX FIFO has data available. See related APIs for + * additional receive options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_I2S_receiveDataBlocking32 + * @sa DL_I2S_receiveDataCheck32 + */ +__STATIC_INLINE uint32_t DL_I2S_receiveData32(const I2S_Regs *i2s) +{ + return (i2s->RXDATA); +} + +/** + * @brief Blocks to ensure transmit is ready before sending data + * + * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not + * full. Will wait indefinitely until there is space in the TX FIFO. See + * related APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_I2S_transmitData8 + * @sa DL_I2S_transmitDataCheck8 + */ +void DL_I2S_transmitDataBlocking8(I2S_Regs *i2s, uint8_t data); + +/** + * @brief Blocks to ensure transmit is ready before sending data + * + * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not + * full. Will wait indefinitely until there is space in the TX FIFO. See + * related APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_I2S_transmitData16 + * @sa DL_I2S_transmitDataCheck16 + */ +void DL_I2S_transmitDataBlocking16(I2S_Regs *i2s, uint16_t data); + +/** + * @brief Blocks to ensure transmit is ready before sending data + * + * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not + * full. Will wait indefinitely until there is space in the TX FIFO. See + * related APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * NOTE: A 32-bit write will be written as one FIFO entry. The application can + * choose to pack two 16-bit frames into one word. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_I2S_transmitData32 + * @sa DL_I2S_transmitDataCheck32 + */ +void DL_I2S_transmitDataBlocking32(I2S_Regs *i2s, uint32_t data); + +/** + * @brief Blocks to ensure receive is ready before reading data + * + * Reads the data from the RX FIFO after blocking to ensure the RX FIFO is not + * empty. Will wait indefinitely until there is data in the RX FIFO. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_I2S_receiveData16 + * @sa DL_I2S_receiveDataCheck16 + */ +uint8_t DL_I2S_receiveDataBlocking8(const I2S_Regs *i2s); + +/** + * @brief Blocks to ensure receive is ready before reading data + * + * Reads the data from the RX FIFO after blocking to ensure the RX FIFO is not + * empty. Will wait indefinitely until there is data in the RX FIFO. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_I2S_receiveData16 + * @sa DL_I2S_receiveDataCheck16 + */ +uint16_t DL_I2S_receiveDataBlocking16(const I2S_Regs *i2s); + +/** + * @brief Blocks to ensure receive is ready before reading data + * + * Reads the data from the RX FIFO after blocking to ensure the RX FIFO is not + * empty. Will wait indefinitely until there is data in the RX FIFO. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_I2S_receiveData32 + * @sa DL_I2S_receiveDataCheck32 + */ +uint32_t DL_I2S_receiveDataBlocking32(const I2S_Regs *i2s); + +/** + * @brief Checks the TX FIFO before trying to transmit data + * + * Checks if the TX FIFO is already full before trying to add new data to the + * FIFO. Exits immediately if full rather than trying to block. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @return If the transmit occurred + * + * @retval true if data was added to the TX FIFO + * @retval false if the TX FIFO was full and data was not added + * + * @sa DL_I2S_transmitData8 + * @sa DL_I2S_transmitDataBlocking8 + */ +bool DL_I2S_transmitDataCheck8(I2S_Regs *i2s, uint8_t data); + +/** + * @brief Checks the TX FIFO before trying to transmit data + * + * Checks if the TX FIFO is already full before trying to add new data to the + * FIFO. Exits immediately if full rather than trying to block. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @return If the transmit occurred + * + * @retval true if data was added to the TX FIFO + * @retval false if the TX FIFO was full and data was not added + * + * @sa DL_I2S_transmitData16 + * @sa DL_I2S_transmitDataBlocking16 + */ +bool DL_I2S_transmitDataCheck16(I2S_Regs *i2s, uint16_t data); + +/** + * @brief Checks the TX FIFO before trying to transmit data + * + * Checks if the TX FIFO is already full before trying to add new data to the + * FIFO. Exits immediately if full rather than trying to block. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * NOTE: A 32-bit write will be written as one FIFO entry. The application can + * choose to pack two 16-bit frames into one word. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @return If the transmit occurred + * + * @retval true if data was added to the TX FIFO + * @retval false if the TX FIFO was full and data was not added + * + * @sa DL_I2S_transmitData32 + * @sa DL_I2S_transmitDataBlocking32 + */ +bool DL_I2S_transmitDataCheck32(I2S_Regs *i2s, uint32_t data); + +/** + * @brief Checks the RX FIFO before trying to receive data + * + * Checks if the RX FIFO is already empty before trying to read new data from + * the FIFO. Exits immediately if empty rather than trying to block. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[out] buffer a buffer to write the received data into + * + * @return If the receive occurred + * + * @retval true if data was read from the RX FIFO + * @retval false if the RX FIFO was empty and data was not read + * + * @sa DL_I2S_receiveData8 + * @sa DL_I2S_receiveDataBlocking8 + */ +bool DL_I2S_receiveDataCheck8(const I2S_Regs *i2s, uint8_t *buffer); + +/** + * @brief Checks the RX FIFO before trying to receive data + * + * Checks if the RX FIFO is already empty before trying to read new data from + * the FIFO. Exits immediately if empty rather than trying to block. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[out] buffer a buffer to write the received data into + * + * @return If the receive occurred + * + * @retval true if data was read from the RX FIFO + * @retval false if the RX FIFO was empty and data was not read + * + * @sa DL_I2S_receiveData16 + * @sa DL_I2S_receiveDataBlocking16 + */ +bool DL_I2S_receiveDataCheck16(const I2S_Regs *i2s, uint16_t *buffer); + +/** + * @brief Checks the RX FIFO before trying to receive data + * + * Checks if the RX FIFO is already empty before trying to read new data from + * the FIFO. Exits immediately if empty rather than trying to block. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * @param[in] i2s pointer to the register overlay for the peripheral + * @param[out] buffer a buffer to write the received data into + * + * @return If the receive occurred + * + * @retval true if data was read from the RX FIFO + * @retval false if the RX FIFO was empty and data was not read + * + * @sa DL_I2S_receiveData32 + * @sa DL_I2S_receiveDataBlocking32 + */ +bool DL_I2S_receiveDataCheck32(const I2S_Regs *i2s, uint32_t *buffer); + +/** + * @brief Read all available data out of the RX FIFO using 8 bit access + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[out] buffer Buffer to write received data into + * @param[in] maxCount Max number of halfwords to read from the RX FIFO + * + * @return Number of bytes read from the RX FIFO + */ +uint32_t DL_I2S_drainRXFIFO8( + const I2S_Regs *i2s, uint8_t *buffer, uint32_t maxCount); + +/** + * @brief Read all available data out of the RX FIFO using 16 bit access + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[out] buffer Buffer to write received data into + * @param[in] maxCount Max number of halfwords to read from the RX FIFO + * + * @return Number of halfwords read from the RX FIFO + */ +uint32_t DL_I2S_drainRXFIFO16( + const I2S_Regs *i2s, uint16_t *buffer, uint32_t maxCount); + +/** + * @brief Read all available data out of the RX FIFO using 32 bit access + * + * NOTE: A 32-bit write will be written as one FIFO entry. The application can + * choose to pack two 16-bit frames into one word. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[out] buffer Buffer to write received data into + * @param[in] maxCount Max number of words to read from the RX FIFO + * + * @return Number of words read from the RX FIFO + */ +uint32_t DL_I2S_drainRXFIFO32( + const I2S_Regs *i2s, uint32_t *buffer, uint32_t maxCount); + +/** + * @brief Fill the TX FIFO using 8 bit access + * + * Continuously write data into the TX FIFO until it is filled up or count has + * been reached. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] buffer Buffer of data to write to the TX FIFO + * @param[in] count Max number of halfwords to write to the TX FIFO + * + * @return Number of bytes written to the TX FIFO + */ +uint32_t DL_I2S_fillTXFIFO8( + I2S_Regs *i2s, const uint8_t *buffer, uint32_t count); + +/** + * @brief Fill the TX FIFO using 16 bit access + * + * Continuously write data into the TX FIFO until it is filled up or count has + * been reached. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] buffer Buffer of data to write to the TX FIFO + * @param[in] count Max number of halfwords to write to the TX FIFO + * + * @return Number of halfwords written to the TX FIFO + */ +uint32_t DL_I2S_fillTXFIFO16( + I2S_Regs *i2s, const uint16_t *buffer, uint32_t count); + +/** + * @brief Fill the TX FIFO using 32 bit access + * + * Continuously write data into the TX FIFO until it is filled up or count has + * been reached. + * + * NOTE: A 32-bit write will be written as one FIFO entry. The application can + * choose to pack two 16-bit frames into one word. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] buffer Buffer of data to write to the TX FIFO + * @param[in] count Max number of words to write to the TX FIFO + * + * @return Number of words written to the TX FIFO + */ +uint32_t DL_I2S_fillTXFIFO32( + I2S_Regs *i2s, const uint32_t *buffer, uint32_t count); + +/** + * @brief Clears contents of TX FIFO + * + * @note When a FIFO clear has been initiated, do not try to re-clear again. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +void DL_I2S_clearTXFIFO(I2S_Regs *i2s); + +/** + * @brief Clears contents of RX FIFO + * + * @note When a FIFO clear has been initiated, do not try to re-clear again. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +void DL_I2S_clearRXFIFO(I2S_Regs *i2s); + +/** + * @brief Checks if TX FIFO is full + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return If TX FIFO is full + * + * @retval true if TX FIFO is full + * @retval false if TX FIFO is not full + */ +__STATIC_INLINE bool DL_I2S_isTXFIFOFull(const I2S_Regs *i2s) +{ + return ((i2s->STAT & I2S_STAT_TXFF_MASK) == I2S_STAT_TXFF_SET); +} + +/** + * @brief Checks if TX FIFO is empty + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return If TX FIFO is empty + * + * @retval true if TX FIFO is empty + * @retval false if TX FIFO is not empty + */ +__STATIC_INLINE bool DL_I2S_isTXFIFOEmpty(const I2S_Regs *i2s) +{ + return ((i2s->STAT & I2S_STAT_TXFE_MASK) == I2S_STAT_TXFE_SET); +} + +/** + * @brief Checks if RX FIFO is full + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return If RX FIFO is full + * + * @retval true if RX FIFO is full + * @retval false if RX FIFO is not full + */ +__STATIC_INLINE bool DL_I2S_isRXFIFOFull(const I2S_Regs *i2s) +{ + return ((i2s->STAT & I2S_STAT_RXFF_MASK) == I2S_STAT_RXFF_SET); +} + +/** + * @brief Checks if RX FIFO is empty + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return If RX FIFO is empty + * + * @retval true if RX FIFO is empty + * @retval false if RX FIFO is not empty + */ +__STATIC_INLINE bool DL_I2S_isRXFIFOEmpty(const I2S_Regs *i2s) +{ + return ((i2s->STAT & I2S_STAT_RXFE_MASK) == I2S_STAT_RXFE_SET); +} + +/** + * @brief Enables the Peripheral Write Enable (PWREN) register for the I2S + * + * Before any peripheral registers can be configured by software, the + * peripheral itself must be enabled by writing the ENABLE bit together with + * the appropriate KEY value to the peripheral's PWREN register. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_enablePower(I2S_Regs *i2s) +{ + i2s->GPRCM.PWREN = (I2S_PWREN_KEY_UNLOCK_W | I2S_PWREN_ENABLE_ENABLE); +} + +/** + * @brief Disables the Peripheral Write Enable (PWREN) register for the I2S + * + * When the PWREN.ENABLE bit is cleared, the peripheral's registers are not + * accessible for read/write operations. + * + * @note This API does not provide large power savings. For power savings, + * please refer to @ref DL_I2S_enable + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_disablePower(I2S_Regs *i2s) +{ + i2s->GPRCM.PWREN = (I2S_PWREN_KEY_UNLOCK_W | I2S_PWREN_ENABLE_DISABLE); +} + +/** + * @brief Returns if the Peripheral Write Enable (PWREN) register for the I2S + * is enabled + * + * Before any peripheral registers can be configured by software, the + * peripheral itself must be enabled by writing the ENABLE bit together with + * the appropriate KEY value to the peripheral's PWREN register. + * + * When the PWREN.ENABLE bit is cleared, the peripheral's registers are not + * accessible for read/write operations. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Whether power is enabled + * + * @retval true if peripheral register access is enabled + * @retval false if peripheral register access is disabled + */ +__STATIC_INLINE bool DL_I2S_isPowerEnabled(const I2S_Regs *i2s) +{ + return ( + (i2s->GPRCM.PWREN & I2S_PWREN_ENABLE_MASK) == I2S_PWREN_ENABLE_ENABLE); +} + +/** + * @brief Resets I2S peripheral + * + * @param i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_reset(I2S_Regs *i2s) +{ + i2s->GPRCM.RSTCTL = + (I2S_RSTCTL_KEY_UNLOCK_W | I2S_RSTCTL_RESETSTKYCLR_CLR | + I2S_RSTCTL_RESETASSERT_ASSERT); +} + +/** + * @brief Returns if I2S peripheral was reset + * + * @param i2s Pointer to the register overlay for the peripheral + * + * @return Whether module was reset + * + * @retval true if module was reset + * @retval false if module wasn't reset + */ +__STATIC_INLINE bool DL_I2S_isReset(const I2S_Regs *i2s) +{ + return ((i2s->GPRCM.STAT & I2S_GPRCM_STAT_RESETSTKY_MASK) == + I2S_GPRCM_STAT_RESETSTKY_RESET); +} + +/** + * @brief Enable the I2S peripheral + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_enable(I2S_Regs *i2s) +{ + i2s->FMTCFG |= I2S_FMTCFG_ENABLE_ENABLE; +} + +/** + * @brief Disable the I2S peripheral + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_disable(I2S_Regs *i2s) +{ + i2s->FMTCFG &= ~(I2S_FMTCFG_ENABLE_MASK); +} + +/** + * @brief Checks if the I2S peripheral is enabled + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Returns the enabled status of the I2S + * + * @retval true The I2S peripheral is enabled + * @retval false The I2S peripheral is disabled + */ +__STATIC_INLINE bool DL_I2S_isEnabled(const I2S_Regs *i2s) +{ + return ( + (i2s->FMTCFG & I2S_FMTCFG_ENABLE_MASK) == I2S_FMTCFG_ENABLE_ENABLE); +} + +/** + * @brief Enable free run control + * + * When enabled, the module will continue to free run and ignores the state + * of the CPU halted debug state + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_enableFreeRun(I2S_Regs *i2s) +{ + DL_Common_updateReg( + &i2s->PDBGCTL, I2S_PDBGCTL_FREE_RUN, I2S_PDBGCTL_FREE_MASK); +} + +/** + * @brief Disable free run control + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_disableFreeRun(I2S_Regs *i2s) +{ + DL_Common_updateReg( + &i2s->PDBGCTL, I2S_PDBGCTL_FREE_STOP, I2S_PDBGCTL_FREE_MASK); +} + +/** + * @brief Returns if free run control is enabled + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Whether free run is enabled + * + * @retval true if free run is enabled + * @retval false if free run is disabled + */ +__STATIC_INLINE bool DL_I2S_isFreeRunEnabled(const I2S_Regs *i2s) +{ + return ((i2s->PDBGCTL & I2S_PDBGCTL_FREE_MASK) == I2S_PDBGCTL_FREE_RUN); +} + +/** + * @brief Get the current mode for the I2S (controller/target) + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The currently configured mode for I2S (controller/target) + * + * @retval One of @ref DL_I2S_MODE + */ +DL_I2S_MODE DL_I2S_getMode(const I2S_Regs *i2s); + +/** + * @brief Set whether the device should be in controller/target mode + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] mode Mode to configure the I2S into. One of @ref DL_I2S_MODE + * + * @sa DL_I2S_init + */ +void DL_I2S_setMode(I2S_Regs *i2s, DL_I2S_MODE mode); + +/** + * @brief Enable WCLK and BCLK generation + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_enableWBCLKGeneration(I2S_Regs *i2s) +{ + i2s->CLKCTL |= I2S_CLKCTL_WBEN_EN; +} + +/** + * @brief Disable WCLK and BCLK generation + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_disableWBCLKGeneration(I2S_Regs *i2s) +{ + i2s->CLKCTL &= ~(I2S_CLKCTL_WBEN_MASK); +} + +/** + * @brief Returns if WCLK and BCLK generation is enabled + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Whether clock generation is enabled + * + * @retval true if clock generation is enabled + * @retval false if clock generation is disabled + * + */ +__STATIC_INLINE bool DL_I2S_isWBCLKGenerationEnabled(const I2S_Regs *i2s) +{ + return ((i2s->CLKCTL & I2S_CLKCTL_WBEN_MASK) == I2S_CLKCTL_WBEN_EN); +} + +/** + * @brief Enable MCLK generation + * + * MCLK only applies when I2S is operating in controller mode. MCLK is an + * optional clock output signal + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @sa DL_I2S_init + * @sa DL_I2S_setMode + */ +__STATIC_INLINE void DL_I2S_enableMCLKGeneration(I2S_Regs *i2s) +{ + i2s->CLKCTL |= I2S_CLKCTL_MEN_EN; +} + +/** + * @brief Disable MCLK generation + * + * @param[in] i2s Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2S_disableMCLKGeneration(I2S_Regs *i2s) +{ + i2s->CLKCTL &= ~(I2S_CLKCTL_MEN_MASK); +} + +/** + * @brief Returns if MCLK generation is enabled + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Whether clock generation is enabled + * + * @retval true if clock generation is enabled + * @retval false if clock generation is disabled + */ +__STATIC_INLINE bool DL_I2S_isMCLKGenerationEnabled(const I2S_Regs *i2s) +{ + return ((i2s->CLKCTL & I2S_CLKCTL_MEN_MASK) == I2S_CLKCTL_MEN_EN); +} + +/** + * @brief Get source of WCLK and BCLK + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Source of WCLK and BCLK + * + * @retval One of @ref DL_I2S_WORD_BAUD_CLOCK_SOURCE + */ +__STATIC_INLINE DL_I2S_WORD_BAUD_CLOCK_SOURCE DL_I2S_getWBCLKSource( + const I2S_Regs *i2s) +{ + uint32_t clockSource = i2s->WCLKSRC & I2S_WCLKSRC_WBCLKSRC_MASK; + + return (DL_I2S_WORD_BAUD_CLOCK_SOURCE)(clockSource); +} + +/** + * @brief Set source of WCLK and BCLK + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @param[in] clockSource Source of WCLK and BCLK. + * One of @ref DL_I2S_WORD_BAUD_CLOCK_SOURCE. + */ +__STATIC_INLINE void DL_I2S_setWBCLKSource( + I2S_Regs *i2s, DL_I2S_WORD_BAUD_CLOCK_SOURCE clockSource) +{ + DL_Common_updateReg( + &i2s->WCLKSRC, (uint32_t) clockSource, I2S_WCLKSRC_WBCLKSRC_MASK); +} + +/** + * @brief Get WCLK inversion status + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return WCLK inversion status + * + * @retval One of @ref DL_I2S_WCLK_INVERSION + */ +__STATIC_INLINE DL_I2S_WCLK_INVERSION DL_I2S_getWCLKInversion( + const I2S_Regs *i2s) +{ + uint32_t wclkInversion = i2s->WCLKSRC & I2S_WCLKSRC_WCLKINV_MASK; + + return (DL_I2S_WCLK_INVERSION)(wclkInversion); +} + +/** + * @brief Invert WCLK + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @param[in] wclkInversion WCLK inversion status. + * One of @ref DL_I2S_WCLK_INVERSION. + */ +__STATIC_INLINE void DL_I2S_setWCLKInversion( + I2S_Regs *i2s, DL_I2S_WCLK_INVERSION wclkInversion) +{ + DL_Common_updateReg( + &i2s->WCLKSRC, (uint32_t) wclkInversion, I2S_WCLKSRC_WCLKINV_MASK); +} + +/** + * @brief Get WCLK phase + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return WCLK phase + * + * @retval One of @ref DL_I2S_WCLK_PHASE + */ +__STATIC_INLINE DL_I2S_WCLK_PHASE DL_I2S_getWCLKPhase(const I2S_Regs *i2s) +{ + uint32_t wclkPhase = i2s->CLKCTL & I2S_CLKCTL_WCLKPHASE_MASK; + + return (DL_I2S_WCLK_PHASE)(wclkPhase); +} + +/** + * @brief Set WCLK phase + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @param[in] wclkPhase WCLK phase. One of @ref DL_I2S_WCLK_PHASE. + */ +__STATIC_INLINE void DL_I2S_setWCLKPhase( + I2S_Regs *i2s, DL_I2S_WCLK_PHASE wclkPhase) +{ + DL_Common_updateReg( + &i2s->CLKCTL, (uint32_t) wclkPhase, I2S_CLKCTL_WCLKPHASE_MASK); +} + +/** + * @brief Set MCLK divider + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] mclkDivider MCLK divider. + * [ @ref DL_I2S_MDIV_MINIMUM, @ref DL_I2S_MDIV_MAXIMUM ] + * + * @sa @ref DL_I2S_MDIV_INVALID + */ +__STATIC_INLINE void DL_I2S_setMCLKDivider(I2S_Regs *i2s, uint32_t mclkDivider) +{ + DL_Common_updateReg(&i2s->MCLKDIV, mclkDivider, I2S_MCLKDIV_MDIV_MASK); +} + +/** + * @brief Get MCLK divider + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return MCLK divider + * + * @retval [ @ref DL_I2S_MDIV_MINIMUM, @ref DL_I2S_MDIV_MAXIMUM ] + * + * @sa @ref DL_I2S_MDIV_INVALID + */ +__STATIC_INLINE uint32_t DL_I2S_getMCLKDivider(const I2S_Regs *i2s) +{ + uint32_t mclkDivider = i2s->MCLKDIV & I2S_MCLKDIV_MDIV_MASK; + + return (mclkDivider); +} + +/** + * @brief Set WCLK divider. + * + * @note For single-phase and dual-phase frame formats, WDIV[9:0] are used for + * the clock calcuation, making 1023 the maximum factor of the division ratio. + * @note For user-defined frame formats such as PCM (long) and TDM formats, + * WCLK is high for WDIV[7:0] and low for WDIV[15:8], making both high and low + * portions have a maximum factor of 255. + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] wclkDivider WCLK divider to set. [0x1, 0xFFFF] + */ +__STATIC_INLINE void DL_I2S_setWCLKDivider(I2S_Regs *i2s, uint32_t wclkDivider) +{ + DL_Common_updateReg(&i2s->WCLKDIV, wclkDivider, I2S_WCLKDIV_WDIV_MASK); +} + +/** + * @brief Get WCLK divider + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return WCLK divider + * + * @retval [0x1, 0xFFFF] + */ +__STATIC_INLINE uint32_t DL_I2S_getWCLKDivider(const I2S_Regs *i2s) +{ + uint32_t wclkDivider = i2s->WCLKDIV & I2S_WCLKDIV_WDIV_MASK; + + return (wclkDivider); +} + +/** + * @brief Set BCLK divider + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] bclkDivider BCLK divider. [ @ref DL_I2S_BDIV_MINIMUM, @ref DL_I2S_BDIV_MAXIMUM ] + * + * @sa @ref DL_I2S_BDIV_INVALID + */ +__STATIC_INLINE void DL_I2S_setBCLKDivider(I2S_Regs *i2s, uint32_t bclkDivider) +{ + DL_Common_updateReg(&i2s->BCLKDIV, bclkDivider, I2S_BCLKDIV_BDIV_MASK); +} + +/** + * @brief Get BCLK divider + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return BCLK divider + * + * @retval [ @ref DL_I2S_BDIV_MINIMUM, @ref DL_I2S_BDIV_MAXIMUM ] + * + * @sa @ref DL_I2S_BDIV_INVALID + */ +__STATIC_INLINE uint32_t DL_I2S_getBCLKDivider(const I2S_Regs *i2s) +{ + uint32_t bclkDivider = i2s->BCLKDIV & I2S_BCLKDIV_BDIV_MASK; + + return (bclkDivider); +} + +/** + * @brief Sets the sample word length in bits. In single-phase format, this is + * the exact number of bits per word. In dual-phase format, this is the + * maximum number of bits per word. + * + * @note Values written to the hardware should be 1 less than the desired + * sample word length e.g. a desired sample word length of 8 bits requires + * the value of 7 to be written. Sample word lengths less than 8 and above 32 + * bits will result in undefined behavior. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] sampleWordLength Sample word length (in bits) to set. [7, 31] + */ +__STATIC_INLINE void DL_I2S_setSampleWordLength( + I2S_Regs *i2s, uint32_t sampleWordLength) +{ + DL_Common_updateReg( + &i2s->FMTCFG, sampleWordLength, I2S_FMTCFG_WORDLEN_MASK); +} + +/** + * @brief Get the sample word length in bits + * + * @note Values read from the hardware will be 1 less than the true + * sample word length e.g. a value of 7 read from the hardware means that the + * sample word length is 8 bits. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Sample word length in bits + * + * @retval Value in range [7, 31] + */ +__STATIC_INLINE uint32_t DL_I2S_getSampleWordLength(const I2S_Regs *i2s) +{ + uint32_t sampleWordLength = i2s->FMTCFG & I2S_FMTCFG_WORDLEN_MASK; + + return (sampleWordLength); +} + +/** + * @brief Set between single or dual-phase format + * + * @note Single-phase: DSP format + * @note Dual-phase: I2S, LJF and RJF formats + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] phase The sampling phase to use. One of @ref DL_I2S_PHASE + */ +__STATIC_INLINE void DL_I2S_setFormatPhase(I2S_Regs *i2s, DL_I2S_PHASE phase) +{ + DL_Common_updateReg( + &i2s->FMTCFG, (uint32_t) phase, I2S_FMTCFG_DUALPHASE_MASK); +} + +/** + * @brief Get the sampling phase being used + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The sampling phase being used + * + * @retval One of @ref DL_I2S_PHASE + */ +__STATIC_INLINE DL_I2S_PHASE DL_I2S_getFormatPhase(const I2S_Regs *i2s) +{ + uint32_t phase = i2s->FMTCFG & I2S_FMTCFG_DUALPHASE_MASK; + + return ((DL_I2S_PHASE)(phase)); +} + +/** + * @brief Set the sample edge of data on BCLK. + * + * @note On negative sample edge, data is sampled on the negative edge of + * BCLK and clocked out on the positive edge. + * @note On positive sample edge, data is sampled on the positive edge of + * BCLK and clocked out on the negative edge. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] edge The sample edge to use. One of @ref DL_I2S_SAMPLE_EDGE + */ +__STATIC_INLINE void DL_I2S_setSampleEdge( + I2S_Regs *i2s, DL_I2S_SAMPLE_EDGE edge) +{ + DL_Common_updateReg( + &i2s->FMTCFG, (uint32_t) edge, I2S_FMTCFG_SMPLEDGE_MASK); +} + +/** + * @brief Gets the sample edge being used + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The sample edge being used + * + * @retval One of @ref DL_I2S_SAMPLE_EDGE + */ +__STATIC_INLINE DL_I2S_SAMPLE_EDGE DL_I2S_getSampleEdge(const I2S_Regs *i2s) +{ + uint32_t edge = i2s->FMTCFG & I2S_FMTCFG_SMPLEDGE_MASK; + + return ((DL_I2S_SAMPLE_EDGE)(edge)); +} + +/** + * @brief Set the size of each sample word stored to or loaded from memory + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] length The memory access length to use. + * One of @ref DL_I2S_MEMORY_LENGTH + */ +__STATIC_INLINE void DL_I2S_setMemoryLength( + I2S_Regs *i2s, DL_I2S_MEMORY_LENGTH length) +{ + DL_Common_updateReg( + &i2s->FMTCFG, (uint32_t) length, I2S_FMTCFG_MEMLEN32_MASK); +} + +/** + * @brief Get the size of sample words stored to or loaded from memory + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The memory access length being used + * + * @retval One of @ref DL_I2S_MEMORY_LENGTH + */ +__STATIC_INLINE DL_I2S_MEMORY_LENGTH DL_I2S_getMemoryLength( + const I2S_Regs *i2s) +{ + uint32_t length = i2s->FMTCFG & I2S_FMTCFG_MEMLEN32_MASK; + + return ((DL_I2S_MEMORY_LENGTH)(length)); +} + +/** + * @brief Set the number of BCLK periods to wait between a WCLK edge and the + * MSB of the first word in a phase + * + * @note Data delay of 0 - LJF and DSP formats + * @note Data delay of 1 - I2S and DSP formats + * @note Data delay of 2 (minimum) - RJF format + * @note Data delay of 255 (maximum) - RJF format + + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] dataDelay The data delay to use. One of @ref DL_I2S_DATA_DELAY + */ +__STATIC_INLINE void DL_I2S_setDataDelay( + I2S_Regs *i2s, DL_I2S_DATA_DELAY dataDelay) +{ + DL_Common_updateReg( + &i2s->FMTCFG, (uint32_t) dataDelay, I2S_FMTCFG_DATADLY_MASK); +} + +/** + * @brief Gets the data delay being used + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The data delay being used + * + * @retval One of @ref DL_I2S_DATA_DELAY + */ +__STATIC_INLINE DL_I2S_DATA_DELAY DL_I2S_getDataDelay(const I2S_Regs *i2s) +{ + uint32_t dataDelay = i2s->FMTCFG & I2S_FMTCFG_DATADLY_MASK; + + return ((DL_I2S_DATA_DELAY)(dataDelay)); +} + +/** + * @brief Set the data pin behavior during empty slots + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] output The empty slot output behavior. + * One of @ref DL_I2S_EMPTY_SLOT_OUTPUT + */ +__STATIC_INLINE void DL_I2S_setEmptySlotOutput( + I2S_Regs *i2s, DL_I2S_EMPTY_SLOT_OUTPUT output) +{ + DL_Common_updateReg( + &i2s->FMTCFG, (uint32_t) output, I2S_FMTCFG_EMPTYSLOTOUTPUT_MASK); +} + +/** + * @brief Get the data pin behavior during empty slots + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The empty slot output behavior being used + * + * @retval One of @ref DL_I2S_EMPTY_SLOT_OUTPUT + */ +__STATIC_INLINE DL_I2S_EMPTY_SLOT_OUTPUT DL_I2S_getEmptySlotOutput( + const I2S_Regs *i2s) +{ + uint32_t output = i2s->FMTCFG & I2S_FMTCFG_EMPTYSLOTOUTPUT_MASK; + + return ((DL_I2S_EMPTY_SLOT_OUTPUT)(output)); +} + +#ifdef DEVICE_HAS_MULTIPLE_DATA_PIN +/** + * @brief Set the direction of the data pins + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] dataPin0Direction Data pin 0 (AD0) direction. + * One of @ref DL_I2S_DATA_PIN_DIRECTION + * @param[in] dataPin1Direction Data pin 1 (AD1) direction. + * One of @ref DL_I2S_DATA_PIN_DIRECTION + */ +__STATIC_INLINE void DL_I2S_setDataPinsDirection(I2S_Regs *i2s, + DL_I2S_DATA_PIN_DIRECTION dataPin0Direction, + DL_I2S_DATA_PIN_DIRECTION dataPin1Direction) +{ + DL_Common_updateReg(&i2s->DIRCFG, + ((((uint32_t) dataPin0Direction) << I2S_DIRCFG_AD0_OFS) | + (((uint32_t) dataPin1Direction) << I2S_DIRCFG_AD1_OFS)), + (I2S_DIRCFG_AD0_MASK | I2S_DIRCFG_AD1_MASK)); +} + +#endif +/** + * @brief Set the direction of data pin 0 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] direction Data pin direction. + * One of @ref DL_I2S_DATA_PIN_DIRECTION + */ +__STATIC_INLINE void DL_I2S_setDataPin0Direction( + I2S_Regs *i2s, DL_I2S_DATA_PIN_DIRECTION direction) +{ + DL_Common_updateReg(&i2s->DIRCFG, + ((uint32_t)(direction)) << I2S_DIRCFG_AD0_OFS, I2S_DIRCFG_AD0_MASK); +} + +#ifdef DEVICE_HAS_MULTIPLE_DATA_PIN +/** + * @brief Set the direction of data pin 1 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] direction Data pin direction. + * One of @ref DL_I2S_DATA_PIN_DIRECTION + */ +__STATIC_INLINE void DL_I2S_setDataPin1Direction( + I2S_Regs *i2s, DL_I2S_DATA_PIN_DIRECTION direction) +{ + DL_Common_updateReg(&i2s->DIRCFG, + ((uint32_t)(direction)) << I2S_DIRCFG_AD1_OFS, I2S_DIRCFG_AD1_MASK); +} + +#endif +/** + * @brief Get the direction of data pin 0 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Direction of the data pin + * + * @retval One of @ref DL_I2S_DATA_PIN_DIRECTION + */ +__STATIC_INLINE DL_I2S_DATA_PIN_DIRECTION DL_I2S_getDataPin0Direction( + const I2S_Regs *i2s) +{ + uint32_t direction = i2s->DIRCFG & I2S_DIRCFG_AD0_MASK; + + return ((DL_I2S_DATA_PIN_DIRECTION)(direction >> I2S_DIRCFG_AD0_OFS)); +} + +#ifdef DEVICE_HAS_MULTIPLE_DATA_PIN +/** + * @brief Get the direction of data pin 1 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Direction of the data pin + * + * @retval One of @ref DL_I2S_DATA_PIN_DIRECTION + */ +__STATIC_INLINE DL_I2S_DATA_PIN_DIRECTION DL_I2S_getDataPin1Direction( + const I2S_Regs *i2s) +{ + uint32_t direction = i2s->DIRCFG & I2S_DIRCFG_AD1_MASK; + + return ((DL_I2S_DATA_PIN_DIRECTION)(direction >> I2S_DIRCFG_AD1_OFS)); +} + +#endif +/** + * @brief Set the valid channel mask of data pin 0 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] channelMask Valid channel mask of the data pin + */ +__STATIC_INLINE void DL_I2S_setDataPin0ChannelMask( + I2S_Regs *i2s, uint32_t channelMask) +{ + i2s->WMASK0 = channelMask; +} + +#ifdef DEVICE_HAS_MULTIPLE_DATA_PIN +/** + * @brief Set the valid channel mask of data pin 1 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] channelMask Valid channel mask of the data pin + */ +__STATIC_INLINE void DL_I2S_setDataPin1ChannelMask( + I2S_Regs *i2s, uint32_t channelMask) +{ + i2s->WMASK1 = channelMask; +} + +#endif +/** + * @brief Get the valid channel mask of data pin 0 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Valid channel mask of the data pin + * + * @retval The valid channel mask of the data pin with the range [0, 0xFF]. + * For single-phase mode, each bit represents 1 channel. For + * dual-phase mode, only the first 2 LSBs are considered. + */ +__STATIC_INLINE uint32_t DL_I2S_getDataPin0ChannelMask(const I2S_Regs *i2s) +{ + uint32_t channelMask = i2s->WMASK0 & I2S_WMASK0_MASK_MASK; + + return (channelMask); +} + +#ifdef DEVICE_HAS_MULTIPLE_DATA_PIN +/** + * @brief Get the valid channel mask of data pin 1 + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Valid channel mask of the data pin + * + * @retval The valid channel mask of the data pin with the range [0, 0xFF]. + * For single-phase mode, each bit represents 1 channel. For + * dual-phase mode, only the first 2 LSBs are considered. + */ +__STATIC_INLINE uint32_t DL_I2S_getDataPin1ChannelMask(const I2S_Regs *i2s) +{ + uint32_t channelMask = i2s->WMASK1 & I2S_WMASK1_MASK_MASK; + + return (channelMask); +} + +#endif +/** + * @brief Get TX FIFO threshold level + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Indicates at what fill level in the TX FIFO a threshold will be + * generated + * + * @retval One of @ref DL_I2S_TX_FIFO_LEVEL + */ +__STATIC_INLINE DL_I2S_TX_FIFO_LEVEL DL_I2S_getTXFIFOThreshold( + const I2S_Regs *i2s) +{ + uint32_t level = i2s->IFLS & I2S_IFLS_TXIFLSEL_MASK; + + return (DL_I2S_TX_FIFO_LEVEL)(level); +} + +/** + * @brief Set TX FIFO threshold level + * + * @note Randomly changing FIFO levels when FIFO has contents might lead to + * unexpected behavior. It is recommended to clear the FIFO before changing + * FIFO threshold levels. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] level Indicates at what fill level in the TX FIFO a threshold + * will be generated. + * One of @ref DL_I2S_TX_FIFO_LEVEL. + * + * @sa DL_I2S_clearTXFIFO + */ +__STATIC_INLINE void DL_I2S_setTXFIFOThreshold( + I2S_Regs *i2s, DL_I2S_TX_FIFO_LEVEL level) +{ + DL_Common_updateReg(&i2s->IFLS, (uint32_t) level, I2S_IFLS_TXIFLSEL_MASK); +} + +/** + * @brief Get RX FIFO threshold level + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return Indicates at what fill level in the RX FIFO a threshold will be + * generated + * + * @retval One of @ref DL_I2S_RX_FIFO_LEVEL + */ +__STATIC_INLINE DL_I2S_RX_FIFO_LEVEL DL_I2S_getRXFIFOThreshold( + const I2S_Regs *i2s) +{ + uint32_t level = i2s->IFLS & I2S_IFLS_RXIFLSEL_MASK; + + return (DL_I2S_RX_FIFO_LEVEL)(level); +} + +/** + * @brief Set RX FIFO threshold level + * + * @note Randomly changing FIFO levels when FIFO has contents might lead to + * unexpected behavior. It is recommended to clear the FIFO before changing + * FIFO threshold levels. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] level Indicates at what fill level in the RX FIFO a threshold + * will be generated. + * One of @ref DL_I2S_RX_FIFO_LEVEL. + * + * @sa DL_I2S_clearRXFIFO + */ +__STATIC_INLINE void DL_I2S_setRXFIFOThreshold( + I2S_Regs *i2s, DL_I2S_RX_FIFO_LEVEL level) +{ + DL_Common_updateReg(&i2s->IFLS, (uint32_t) level, I2S_IFLS_RXIFLSEL_MASK); +} + +/** + * @brief Checks if RX FIFO clear is complete + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return If RX FIFO clear is complete + * + * @retval true if RX FIFO clear is complete + * @retval false if RX FIFO clear is complete + */ +__STATIC_INLINE bool DL_I2S_isRXFIFOClearComplete(const I2S_Regs *i2s) +{ + return ((i2s->STAT & I2S_STAT_RXCLR_MASK) == I2S_STAT_RXCLR_SET); +} + +/** + * @brief Checks if TX FIFO clear is complete + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return If TX FIFO clear is complete + * + * @retval true if TX FIFO clear is complete + * @retval false if TX FIFO clear is complete + */ +__STATIC_INLINE bool DL_I2S_isTXFIFOClearComplete(const I2S_Regs *i2s) +{ + return ((i2s->STAT & I2S_STAT_TXCLR_MASK) == I2S_STAT_TXCLR_SET); +} + +/** + * @brief Enable I2S interrupts + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_I2S_INTERRUPT. + */ +__STATIC_INLINE void DL_I2S_enableInterrupt( + I2S_Regs *i2s, uint32_t interruptMask) +{ + i2s->CPU_INT.IMASK |= interruptMask; +} + +/** + * @brief Disable I2S interrupts + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to disable. Bitwise OR of + * @ref DL_I2S_INTERRUPT. + */ +__STATIC_INLINE void DL_I2S_disableInterrupt( + I2S_Regs *i2s, uint32_t interruptMask) +{ + i2s->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which I2S interrupts are enabled + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_INTERRUPT. + * + * @return Which of the requested I2S interrupts are enabled + * + * @retval Bitwise OR of @ref DL_I2S_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2S_getEnabledInterrupts( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->CPU_INT.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled I2S interrupts + * + * Checks if any of the I2S interrupts that were previously enabled are + * pending. + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_INTERRUPT. + * + * @return Which of the requested I2S interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2S_INTERRUPT values + * + * @sa DL_I2S_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_I2S_getEnabledInterruptStatus( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->CPU_INT.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any I2S interrupt + * + * Checks if any of the I2S interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_INTERRUPT. + * + * @return Which of the requested I2S interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2S_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2S_getRawInterruptStatus( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->CPU_INT.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending I2S interrupt + * + * Checks if any of the I2S interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The highest priority pending I2S interrupt + * + * @retval One of @ref DL_I2S_IIDX + */ +__STATIC_INLINE DL_I2S_IIDX DL_I2S_getPendingInterrupt(const I2S_Regs *i2s) +{ + return ((DL_I2S_IIDX) i2s->CPU_INT.IIDX); +} + +/** + * @brief Clear pending I2S interrupts + * + * @param[in] i2s Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_I2S_INTERRUPT. + */ +__STATIC_INLINE void DL_I2S_clearInterruptStatus( + I2S_Regs *i2s, uint32_t interruptMask) +{ + i2s->CPU_INT.ICLR = interruptMask; +} + +/** + * @brief Enables I2S interrupt for triggering the DMA receive event + * + * Enables the I2S interrupt to be used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_RX + * register, which is the event publisher used for triggering the DMA to do a + * receive data transfer. + * + * @note Only one interrupt source should be enabled at a time. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interrupt Interrupt to enable as the trigger condition for + * the DMA. One of @ref DL_I2S_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2S_enableDMAReceiveEvent( + I2S_Regs *i2s, uint32_t interrupt) +{ + i2s->DMA_TRIG_RX.IMASK = interrupt; +} + +/** + * @brief Enables I2S interrupt for triggering the DMA transmit event + * + * Enables the I2S interrupt to be used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_TX + * register, which is the event publisher used for triggering the DMA to do a + * transmit data transfer. + * + * @note Only one interrupt source should be enabled at a time. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interrupt Interrupt to enable as the trigger condition for + * the DMA. One of @ref DL_I2S_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2S_enableDMATransmitEvent( + I2S_Regs *i2s, uint32_t interrupt) +{ + i2s->DMA_TRIG_TX.IMASK = interrupt; +} + +/** + * @brief Disables I2S interrupt from triggering the DMA receive event + * + * Disables the I2S interrupt from being used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_RX + * register, which is the event publisher used for triggering the DMA to do a + * receive data transfer. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interrupt Interrupt to disable as the trigger condition for + * the DMA. One of @ref DL_I2S_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2S_disableDMAReceiveEvent( + I2S_Regs *i2s, uint32_t interrupt) +{ + i2s->DMA_TRIG_RX.IMASK &= ~(interrupt); +} + +/** + * @brief Disables I2S interrupt from triggering the DMA transmit event + * + * Disables the I2S interrupt from being used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_TX + * register, which is the event publisher used for triggering the DMA to do a + * transmit data transfer. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interrupt Interrupt to disable as the trigger condition for + * the DMA. One of @ref DL_I2S_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2S_disableDMATransmitEvent( + I2S_Regs *i2s, uint32_t interrupt) +{ + i2s->DMA_TRIG_TX.IMASK &= ~(interrupt); +} + +/** + * @brief Check which I2S interrupt for DMA receive events is enabled + * + * This API checks the DMA_TRIG_RX register, which is used for triggering the + * DMA to do a receive data transfer. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2S interrupt status + * + * @retval One of @ref DL_I2S_DMA_INTERRUPT + */ +__STATIC_INLINE uint32_t DL_I2S_getEnabledDMAReceiveEvent( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->DMA_TRIG_RX.IMASK & interruptMask); +} + +/** + * @brief Check which I2S interrupt for DMA transmit events is enabled + * + * This API checks the DMA_TRIG_TX register, which is used for triggering the + * DMA to do a transmit data transfer. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2S interrupt status + * + * @retval One of @ref DL_I2S_DMA_INTERRUPT + */ +__STATIC_INLINE uint32_t DL_I2S_getEnabledDMATransmitEvent( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->DMA_TRIG_TX.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled I2S interrupt for DMA receive event + * + * Checks if any of the I2S interrupts for the DMA receive event that were + * previously enabled are pending. + * This API checks the DMA_TRIG_RX register, which is used for triggering the + * DMA to do a receive event. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2S interrupt status + * + * @retval One of @ref DL_I2S_DMA_INTERRUPT + * + * @sa DL_I2S_enableDMAReceiveEvent + */ +__STATIC_INLINE uint32_t DL_I2S_getEnabledDMAReceiveEventStatus( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->DMA_TRIG_RX.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled I2S interrupt for DMA transmit event + * + * Checks if any of the I2S interrupts for the DMA transmit event that were + * previously enabled are pending. + * This API checks the DMA_TRIG_TX register, which is used for triggering the + * DMA to do a transmit event. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2S interrupt status + * + * @retval One of @ref DL_I2S_DMA_INTERRUPT + * + * @sa DL_I2S_enableDMATransmitEvent + */ +__STATIC_INLINE uint32_t DL_I2S_getEnabledDMATransmitEventStatus( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->DMA_TRIG_TX.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any I2S interrupt for DMA receive event + * + * Checks if any of the I2S interrupts for DMA receive event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the DMA_TRIG_RX register, which is used for triggering the + * DMA to do a receive event. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_DMA_INTERRUPT. + * + * @return Which of the requested I2S interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2S_DMA_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2S_getRawDMAReceiveEventStatus( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->DMA_TRIG_RX.RIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any I2S interrupt for DMA transmit event + * + * Checks if any of the I2S interrupts for DMA transmit event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the DMA_TRIG_TX register, which is used for triggering the + * DMA to do a transmit event. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2S_DMA_INTERRUPT. + * + * @return Which of the requested I2S interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2S_DMA_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2S_getRawDMATransmitEventStatus( + const I2S_Regs *i2s, uint32_t interruptMask) +{ + return (i2s->DMA_TRIG_TX.RIS & interruptMask); +} + +/** + * @brief Suspend external communication + * + * Ongoing communication will complete, and further external communications + * are stopped. Tranmit line(s) will be driven to idle state, and further + * toggles on the receive line(s) will not be processed. Once suspend is + * requested, the CPU should poll to ensure that the device has reached idle. + * When the device is idle, the transmit FIFO should be flushed, and the + * receive FIFO should be drained prior to disabling the module. + * After suspending the module, the I2S register configurations are retained. + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @sa DL_I2S_disable + * @sa DL_I2S_resume + */ +__STATIC_INLINE void DL_I2S_suspend(I2S_Regs *i2s) +{ + DL_Common_updateReg( + &i2s->FMTCFG, I2S_FMTCFG_SUSPEND_ENABLE, I2S_FMTCFG_SUSPEND_MASK); +} + +/** + * @brief Resume functional mode + * + * Functional communication can be resumed by calling this API, and enabling + * the module + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @sa DL_I2S_enable + * @sa DL_I2S_suspend + */ +__STATIC_INLINE void DL_I2S_resume(I2S_Regs *i2s) +{ + DL_Common_updateReg( + &i2s->FMTCFG, I2S_FMTCFG_SUSPEND_DISABLE, I2S_FMTCFG_SUSPEND_MASK); +} + +/** + * @brief Set the clock source for the I2S peripheral + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @param[in] clockSource Source of the clock for I2S. + * One of @ref DL_I2S_CLOCK_SOURCE. + */ +__STATIC_INLINE void DL_I2S_setClockSource( + I2S_Regs *i2s, DL_I2S_CLOCK_SOURCE clockSource) +{ + i2s->GPRCM.CLKCFG = (I2S_CLKCFG_KEY_UNLOCK | (uint32_t) clockSource); +} + +/** + * @brief Get I2S audio clock configuration + * + * @param[in] i2s Pointer to the register overlay for the peripheral + * + * @return The currently configured clock for I2S + * + * @retval One of @ref DL_I2S_CLOCK_SOURCE + */ +__STATIC_INLINE DL_I2S_CLOCK_SOURCE DL_I2S_getClockSource(const I2S_Regs *i2s) +{ + uint32_t clockSource = i2s->GPRCM.CLKCFG & I2S_CLKCFG_DAICLK_MASK; + + return ((DL_I2S_CLOCK_SOURCE)(clockSource)); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MSPM0_HAS_I2S__ */ + +#endif /* ti_dl_dl_i2s__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_lfss.h b/mspm0/source/ti/driverlib/dl_lfss.h index 3b03f6b..fc14e21 100644 --- a/mspm0/source/ti/driverlib/dl_lfss.h +++ b/mspm0/source/ti/driverlib/dl_lfss.h @@ -1239,8 +1239,7 @@ __STATIC_INLINE void DL_LFSS_IWDT_setClockDivider( __STATIC_INLINE DL_LFSS_IWDT_CLOCK_DIVIDE DL_LFSS_IWDT_getClockDivider( const LFSS_Regs *lfss) { - uint32_t divider = - (lfss->IPSPECIFIC_WDT.WDTCTL & LFSS_WDTCTL_CLKDIV_MASK) + (uint32_t) 1; + uint32_t divider = (lfss->IPSPECIFIC_WDT.WDTCTL & LFSS_WDTCTL_CLKDIV_MASK); return (DL_LFSS_IWDT_CLOCK_DIVIDE)(divider); } diff --git a/mspm0/source/ti/driverlib/dl_mathacl.h b/mspm0/source/ti/driverlib/dl_mathacl.h index 5a3753f..915290c 100644 --- a/mspm0/source/ti/driverlib/dl_mathacl.h +++ b/mspm0/source/ti/driverlib/dl_mathacl.h @@ -264,6 +264,10 @@ typedef struct { * peripheral itself must be enabled by writing the ENABLE bit together with * the appropriate KEY value to the peripheral's PWREN register. * + * @note If using compiler TI Clang LTS 4.0.0+ with the --mathacl flag, do not reset + * the MATHACL then perform a math divide. The peripheral will need to be reenabled + * with @ref DL_MathACL_enablePower; before performing a division. + * * @param mathacl Pointer to the register overlay for the peripheral */ __STATIC_INLINE void DL_MathACL_enablePower(MATHACL_Regs *mathacl) diff --git a/mspm0/source/ti/driverlib/dl_mcan.h b/mspm0/source/ti/driverlib/dl_mcan.h index 145523d..42ec526 100644 --- a/mspm0/source/ti/driverlib/dl_mcan.h +++ b/mspm0/source/ti/driverlib/dl_mcan.h @@ -1399,7 +1399,7 @@ typedef struct { /*! Data bytes. * Only first dlc number of bytes are valid. */ - uint16_t data[DL_MCAN_MAX_PAYLOAD_BYTES]; + uint8_t data[DL_MCAN_MAX_PAYLOAD_BYTES]; } DL_MCAN_TxBufElement; /** @@ -1451,7 +1451,7 @@ typedef struct { /*! Data bytes. * Only first dlc number of bytes are valid. */ - uint16_t data[DL_MCAN_MAX_PAYLOAD_BYTES]; + uint8_t data[DL_MCAN_MAX_PAYLOAD_BYTES]; } DL_MCAN_RxBufElement; /** diff --git a/mspm0/source/ti/driverlib/dl_npu.c b/mspm0/source/ti/driverlib/dl_npu.c new file mode 100644 index 0000000..7a811b3 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_npu.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MSPM0_HAS_NPU__ + +#endif /* __MSPM0_HAS_NPU__ */ diff --git a/mspm0/source/ti/driverlib/dl_npu.h b/mspm0/source/ti/driverlib/dl_npu.h new file mode 100644 index 0000000..d9dbbaa --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_npu.h @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_npu.h + * @brief Neural Processing Unit (NPU) Driver Library + * @defgroup Neural Processing Unit (NPU) + * + * @anchor ti_dl_dl_npu_Overview + * # Overview + * + * The Neural Processing Unit (NPU) Driver Library provides low level + * NPU drivers for power control, interrupt management, and access + * to NPU control registers as well as NPU memory. + * The power control and interrupt management registers are expected to be + * called as a part of the user application, but the NPU control register + * and NPU memory address accessor functions are only intended to be used by + * the NPU library. + * + *
+ ****************************************************************************** + */ +/** @addtogroup NPU + * @{ + */ +#ifndef ti_dl_dl_npu__include +#define ti_dl_dl_npu__include + +#include +#include + +#include + +#ifdef __MSPM0_HAS_NPU__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_NPU_INTERRUPT + * @{ + */ + +/*! + * @brief NPU done interrupt + */ +#define DL_NPU_INTERRUPT_DONE (NPU_IMASK_DONE_SET) + +/** @}*/ + +/* clang-format on */ + +/*! @enum DL_NPU_IIDX */ +typedef enum { + /*! NPU interrupt index for no interrupt */ + DL_NPU_IIDX_NO_INTERRUPT = NPU_IIDX_STAT_NO_INTR, + /*! NPU interrupt index for NPU done interrupt */ + DL_NPU_IIDX_OUTPUT_READY = NPU_IIDX_STAT_DONE +} DL_NPU_IIDX; + +/** + * @brief Enables the Peripheral Write Enable (PWREN) register for the NPU + * + * Before any NPU registers can be configured by software, the + * NPU itself must be enabled by writing the ENABLE bit together with + * the appropriate KEY value to the NPU's PWREN register. + * + * @param npu Pointer to the register overlay for the NPU + */ +__STATIC_INLINE void DL_NPU_enablePower(NPU_Regs *npu) +{ + npu->GPRCM.PWREN = (NPU_PWREN_KEY_UNLOCK_W | NPU_PWREN_ENABLE_ENABLE); +} + +/** + * @brief Disables the Peripheral Write Enable (PWREN) register for the NPU + * + * When the PWREN.ENABLE bit is cleared, the NPU's registers and memory are + * not accessible for read/write operations. + * + * @note This API does not provide large power savings. + * + * @param npu Pointer to the register overlay for the NPU + */ +__STATIC_INLINE void DL_NPU_disablePower(NPU_Regs *npu) +{ + npu->GPRCM.PWREN = (NPU_PWREN_KEY_UNLOCK_W | NPU_PWREN_ENABLE_DISABLE); +} + +/** + * @brief Returns if the Peripheral Write Enable (PWREN) register for the NPU + * is enabled + * + * Before any NPU registers can be configured by software, the + * NPU itself must be enabled by writing the ENABLE bit together with + * the appropriate KEY value to the NPU's PWREN register. + * + * When the PWREN.ENABLE bit is cleared, the NPU's registers are not + * accessible for read/write operations. + * + * @param npu Pointer to the register overlay for the NPU + * + * @return true if NPU register access is enabled + * @return false if NPU register access is disabled + */ +__STATIC_INLINE bool DL_NPU_isPowerEnabled(const NPU_Regs *npu) +{ + return ( + (npu->GPRCM.PWREN & NPU_PWREN_ENABLE_MASK) == NPU_PWREN_ENABLE_ENABLE); +} + +/** + * @brief Resets NPU peripheral + * + * @param npu Pointer to the register overlay for the NPU + */ +__STATIC_INLINE void DL_NPU_reset(NPU_Regs *npu) +{ + npu->GPRCM.RSTCTL = + (NPU_RSTCTL_KEY_UNLOCK_W | NPU_RSTCTL_RESETSTKYCLR_CLR | + NPU_RSTCTL_RESETASSERT_ASSERT); +} + +/** + * @brief Returns if NPU was reset + * + * @param npu Pointer to the register overlay for the NPU + * + * @return true if NPU was reset + * @return false if NPU wasn't reset + * + */ +__STATIC_INLINE bool DL_NPU_isReset(const NPU_Regs *npu) +{ + return ((npu->GPRCM.STAT & NPU_STAT_RESETSTKY_MASK) == + NPU_STAT_RESETSTKY_RESET); +} + +/** + * @brief Enable NPU interrupts + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_NPU_INTERRUPT. + */ +__STATIC_INLINE void DL_NPU_enableInterrupt( + NPU_Regs *npu, uint32_t interruptMask) +{ + npu->CPU_INT.IMASK |= interruptMask; +} + +/** + * @brief Disable NPU interrupts + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @param[in] interruptMask Bit mask of interrupts to disable. Bitwise OR of + * @ref DL_NPU_INTERRUPT. + */ +__STATIC_INLINE void DL_NPU_disableInterrupt( + NPU_Regs *npu, uint32_t interruptMask) +{ + npu->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which NPU interrupts are enabled + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_NPU_INTERRUPT. + * + * @return Which of the requested NPU interrupts are enabled + * + * @retval Bitwise OR of @ref DL_NPU_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_NPU_getEnabledInterrupts( + NPU_Regs *npu, uint32_t interruptMask) +{ + return (npu->CPU_INT.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled NPU interrupts + * + * Checks if any of the NPU interrupts that were previously enabled are + * pending. + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_NPU_INTERRUPT. + * + * @return Which of the requested NPU interrupts are pending + * + * @retval Bitwise OR of @ref DL_NPU_INTERRUPT values + * + * @sa DL_NPU_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_NPU_getEnabledInterruptStatus( + NPU_Regs *npu, uint32_t interruptMask) +{ + return (npu->CPU_INT.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any NPU interrupt + * + * Checks if any of the NPU interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_NPU_INTERRUPT. + * + * @return Which of the requested NPU interrupts are pending + * + * @retval Bitwise OR of @ref DL_NPU_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_NPU_getRawInterruptStatus( + NPU_Regs *npu, uint32_t interruptMask) +{ + return (npu->CPU_INT.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending NPU interrupt + * + * Checks if any of the NPU interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @return The highest priority pending NPU interrupt. One of @ref + * DL_NPU_IIDX + */ +__STATIC_INLINE DL_NPU_IIDX DL_NPU_getPendingInterrupt(NPU_Regs *npu) +{ + return (DL_NPU_IIDX)(npu->CPU_INT.IIDX); +} + +/** + * @brief Clear pending NPU interrupts + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_NPU_INTERRUPT. + */ +__STATIC_INLINE void DL_NPU_clearInterruptStatus( + NPU_Regs *npu, uint32_t interruptMask) +{ + npu->CPU_INT.ICLR = interruptMask; +} + +/** + * @brief Get the physical starting address of the NPU instruction memory + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @return Address of the instruction memory + */ +__STATIC_INLINE uint32_t DL_NPU_getInstrMemAddress(const NPU_Regs *npu) +{ + return ((uint32_t)(&npu->DREG20)); +} + +/** + * @brief Get the physical starting address of the NPU parameter memory + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @return Address of the parameter memory + */ +__STATIC_INLINE uint32_t DL_NPU_getParamMemAddress(const NPU_Regs *npu) +{ + return ((uint32_t)(&npu->DREG21)); +} + +/** + * @brief Get the physical starting address of the NPU control registers + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @return Address of the NPU CTL register + */ +__STATIC_INLINE uint32_t DL_NPU_getCtlRegAddress(const NPU_Regs *npu) +{ + return ((uint32_t)(&npu->DREG0)); +} + +/** + * @brief Get the physical address of the NPU ACC register + * + * @param[in] npu Pointer to the register overlay for the NPU + * + * @return Address of the ACCVAL register + */ +__STATIC_INLINE uint32_t DL_NPU_getAccRegAddress(const NPU_Regs *npu) +{ + return ((uint32_t)(&npu->DREG19)); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MSPM0_HAS_NPU__ */ + +#endif /* ti_dl_dl_npu__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_opa.h b/mspm0/source/ti/driverlib/dl_opa.h index 5f26fab..5951ae7 100644 --- a/mspm0/source/ti/driverlib/dl_opa.h +++ b/mspm0/source/ti/driverlib/dl_opa.h @@ -337,7 +337,8 @@ __STATIC_INLINE void DL_OPA_init(OA_Regs *opa, const DL_OPA_Config *config) __STATIC_INLINE void DL_OPA_setGainBandwidth( OA_Regs *opa, DL_OPA_GBW bandwidth) { - opa->CFGBASE |= ((uint32_t) bandwidth); + DL_Common_updateReg( + &opa->CFGBASE, (uint32_t) bandwidth, OA_CFGBASE_GBW_MASK); } /** diff --git a/mspm0/source/ti/driverlib/dl_rtc_a.h b/mspm0/source/ti/driverlib/dl_rtc_a.h index a66863f..7f06744 100644 --- a/mspm0/source/ti/driverlib/dl_rtc_a.h +++ b/mspm0/source/ti/driverlib/dl_rtc_a.h @@ -86,11 +86,6 @@ extern "C" { */ #define DL_RTC_A_INTERRUPT_PRESCALER1 (DL_RTC_COMMON_INTERRUPT_PRESCALER1) -/** - * @brief Redirects to common @ref DL_RTC_COMMON_INTERRUPT_PRESCALER2 - */ -#define DL_RTC_A_INTERRUPT_PRESCALER2 (DL_RTC_COMMON_INTERRUPT_PRESCALER2) - /** * @brief Redirects to common @ref DL_RTC_COMMON_INTERRUPT_INTERVAL_ALARM */ @@ -133,11 +128,6 @@ extern "C" { */ #define DL_RTC_A_EVENT_PRESCALER1 (DL_RTC_COMMON_EVENT_PRESCALER1) -/** - * @brief Redirects to common @ref DL_RTC_COMMON_EVENT_PRESCALER2 - */ -#define DL_RTC_A_EVENT_PRESCALER2 (DL_RTC_COMMON_EVENT_PRESCALER2) - /** * @brief Redirects to common @ref DL_RTC_COMMON_EVENT_INTERVAL_ALARM */ @@ -507,21 +497,6 @@ extern "C" { */ #define DL_RTC_A_PRESCALER1_DIVIDE_256 DL_RTC_COMMON_PRESCALER1_DIVIDE_256 -/*! - * @brief Redirects to common @ref DL_RTC_COMMON_PRESCALER2_4_SEC - */ -#define DL_RTC_A_PRESCALER2_4_SEC DL_RTC_COMMON_PRESCALER2_4_SEC - -/*! - * @brief Redirects to common @ref DL_RTC_COMMON_PRESCALER2_8_SEC - */ -#define DL_RTC_A_PRESCALER2_8_SEC DL_RTC_COMMON_PRESCALER2_8_SEC - -/*! - * @brief Redirects to common @ref DL_RTC_COMMON_PRESCALER2_16_SEC - */ -#define DL_RTC_A_PRESCALER2_16_SEC DL_RTC_COMMON_PRESCALER2_16_SEC - /*! * @brief Redirects to common @ref DL_RTC_COMMON_IIDX_ALARM1 */ @@ -1250,11 +1225,6 @@ typedef DL_RTC_Common_CalendarAlarm DL_RTC_A_CalendarAlarm; */ #define DL_RTC_A_setPeriodicAlarm1 DL_RTC_Common_setPeriodicAlarm1 -/*! - * @brief Redirects to common @ref DL_RTC_Common_setPeriodicAlarm2 - */ -#define DL_RTC_A_setPeriodicAlarm2 DL_RTC_Common_setPeriodicAlarm2 - /*! * @brief Redirects to common @ref DL_RTC_Common_getPrescaler0 */ @@ -1265,11 +1235,6 @@ typedef DL_RTC_Common_CalendarAlarm DL_RTC_A_CalendarAlarm; */ #define DL_RTC_A_getPrescaler1 DL_RTC_Common_getPrescaler1 -/*! - * @brief Redirects to common @ref DL_RTC_Common_getPrescaler2 - */ -#define DL_RTC_A_getPrescaler2 DL_RTC_Common_getPrescaler2 - /*! * @brief Redirects to common @ref DL_RTC_Common_getTimeStampSecondsBCD */ @@ -1490,6 +1455,11 @@ typedef DL_RTC_Common_CalendarAlarm DL_RTC_A_CalendarAlarm; */ #define DL_RTC_A_getTimeStampEventCapture DL_RTC_Common_getTimeStampEventCapture +/*! + * @brief Redirects to common @ref DL_RTC_Common_getTimeStampCalendar + */ +#define DL_RTC_A_getTimeStampCalendar DL_RTC_Common_getTimeStampCalendar + /*! * @brief Redirects to common @ref DL_RTC_Common_clearTimeStamp */ diff --git a/mspm0/source/ti/driverlib/dl_rtc_b.h b/mspm0/source/ti/driverlib/dl_rtc_b.h index e75209f..31268cf 100644 --- a/mspm0/source/ti/driverlib/dl_rtc_b.h +++ b/mspm0/source/ti/driverlib/dl_rtc_b.h @@ -86,6 +86,11 @@ extern "C" { */ #define DL_RTC_B_INTERRUPT_PRESCALER1 (DL_RTC_COMMON_INTERRUPT_PRESCALER1) +/** + * @brief Redirects to common @ref DL_RTC_COMMON_INTERRUPT_PRESCALER2 + */ +#define DL_RTC_B_INTERRUPT_PRESCALER2 (DL_RTC_COMMON_INTERRUPT_PRESCALER2) + /** * @brief Redirects to common @ref DL_RTC_COMMON_INTERRUPT_INTERVAL_ALARM */ @@ -122,6 +127,11 @@ extern "C" { */ #define DL_RTC_B_EVENT_PRESCALER1 (DL_RTC_COMMON_EVENT_PRESCALER1) +/** + * @brief Redirects to common @ref DL_RTC_COMMON_EVENT_PRESCALER2 + */ +#define DL_RTC_B_EVENT_PRESCALER2 (DL_RTC_COMMON_EVENT_PRESCALER2) + /** * @brief Redirects to common @ref DL_RTC_COMMON_EVENT_INTERVAL_ALARM */ @@ -299,6 +309,21 @@ extern "C" { */ #define DL_RTC_B_PRESCALER1_DIVIDE_256 DL_RTC_COMMON_PRESCALER1_DIVIDE_256 +/*! + * @brief Redirects to common @ref DL_RTC_COMMON_PRESCALER2_4_SEC + */ +#define DL_RTC_B_PRESCALER2_4_SEC DL_RTC_COMMON_PRESCALER2_4_SEC + +/*! + * @brief Redirects to common @ref DL_RTC_COMMON_PRESCALER2_8_SEC + */ +#define DL_RTC_B_PRESCALER2_8_SEC DL_RTC_COMMON_PRESCALER2_8_SEC + +/*! + * @brief Redirects to common @ref DL_RTC_COMMON_PRESCALER2_16_SEC + */ +#define DL_RTC_B_PRESCALER2_16_SEC DL_RTC_COMMON_PRESCALER2_16_SEC + /*! * @brief Redirects to common @ref DL_RTC_COMMON_IIDX_ALARM1 */ @@ -319,6 +344,11 @@ extern "C" { */ #define DL_RTC_B_IIDX_PRESCALER1 DL_RTC_COMMON_IIDX_PRESCALER1 +/*! + * @brief Redirects to common @ref DL_RTC_COMMON_IIDX_PRESCALER2 + */ +#define DL_RTC_B_IIDX_PRESCALER2 DL_RTC_COMMON_IIDX_PRESCALER2 + /*! * @brief Redirects to common @ref DL_RTC_COMMON_IIDX_INTERVAL_TIMER */ @@ -357,16 +387,6 @@ typedef DL_RTC_Common_CalendarAlarm DL_RTC_B_CalendarAlarm; */ #define DL_RTC_B_disableClockControl DL_RTC_Common_disableClockControl -/*! - * @brief Redirects to common @ref DL_RTC_Common_reset - */ -#define DL_RTC_B_reset DL_RTC_Common_reset - -/*! - * @brief Redirects to common @ref DL_RTC_Common_isReset - */ -#define DL_RTC_B_isReset DL_RTC_Common_isReset - /*! * @brief Redirects to common @ref DL_RTC_Common_enableDebugInterrupts */ @@ -947,6 +967,11 @@ typedef DL_RTC_Common_CalendarAlarm DL_RTC_B_CalendarAlarm; */ #define DL_RTC_B_getPrescaler1 DL_RTC_Common_getPrescaler1 +/*! + * @brief Redirects to common @ref DL_RTC_Common_getPrescaler2 + */ +#define DL_RTC_B_getPrescaler2 DL_RTC_Common_getPrescaler2 + /*! * @brief Redirects to common @ref DL_RTC_Common_getTimeStampSecondsBCD */ diff --git a/mspm0/source/ti/driverlib/dl_rtc_common.c b/mspm0/source/ti/driverlib/dl_rtc_common.c index a5af9e8..810c96e 100644 --- a/mspm0/source/ti/driverlib/dl_rtc_common.c +++ b/mspm0/source/ti/driverlib/dl_rtc_common.c @@ -278,4 +278,41 @@ void DL_RTC_Common_disableCalendarAlarm2(RTC_Regs *rtc_common) } } +DL_RTC_Common_Calendar DL_RTC_Common_getTimeStampCalendar( + const RTC_Regs *rtc_common) +{ + DL_RTC_Common_Calendar calendarTime; + DL_RTC_COMMON_FORMAT format; + + format = DL_RTC_Common_getClockFormat(rtc_common); + + if (format == DL_RTC_COMMON_FORMAT_BINARY) { + calendarTime.seconds = + DL_RTC_Common_getTimeStampSecondsBinary(rtc_common); + calendarTime.minutes = + DL_RTC_Common_getTimeStampMinutesBinary(rtc_common); + calendarTime.hours = DL_RTC_Common_getTimeStampHoursBinary(rtc_common); + calendarTime.dayOfWeek = + DL_RTC_Common_getTimeStampDayOfWeekBinary(rtc_common); + calendarTime.dayOfMonth = + DL_RTC_Common_getTimeStampDayOfMonthBinary(rtc_common); + calendarTime.month = DL_RTC_Common_getTimeStampMonthBinary(rtc_common); + calendarTime.year = DL_RTC_Common_getTimeStampYearBinary(rtc_common); + } else { + calendarTime.seconds = + DL_RTC_Common_getTimeStampSecondsBCD(rtc_common); + calendarTime.minutes = + DL_RTC_Common_getTimeStampMinutesBCD(rtc_common); + calendarTime.hours = DL_RTC_Common_getTimeStampHoursBCD(rtc_common); + calendarTime.dayOfWeek = + DL_RTC_Common_getTimeStampDayOfWeekBCD(rtc_common); + calendarTime.dayOfMonth = + DL_RTC_Common_getTimeStampDayOfMonthBCD(rtc_common); + calendarTime.month = DL_RTC_Common_getTimeStampMonthBCD(rtc_common); + calendarTime.year = DL_RTC_Common_getTimeStampYearBCD(rtc_common); + } + + return calendarTime; +} + #endif /* __MSPM0_HAS_RTC_A__ || __MSPM0_HAS_RTC_B__ || defined __MSPM0_HAS_RTC__ */ diff --git a/mspm0/source/ti/driverlib/dl_rtc_common.h b/mspm0/source/ti/driverlib/dl_rtc_common.h index 0fd3cf5..adb4cc8 100644 --- a/mspm0/source/ti/driverlib/dl_rtc_common.h +++ b/mspm0/source/ti/driverlib/dl_rtc_common.h @@ -91,7 +91,7 @@ extern "C" { */ #define DL_RTC_COMMON_INTERRUPT_PRESCALER1 (RTC_CPU_INT_IMASK_RT1PS_SET) -#ifdef __MSPM0_HAS_RTC_A__ +#ifdef __MSPM0_HAS_RTC_B__ /** * @brief RTC Common prescaler 2 interrupt */ @@ -141,7 +141,7 @@ extern "C" { */ #define DL_RTC_COMMON_EVENT_PRESCALER1 (RTC_GEN_EVENT_IMASK_RT1PS_SET) -#ifdef __MSPM0_HAS_RTC_A__ +#ifdef __MSPM0_HAS_RTC_B__ /** * @brief RTC Common prescaler 2 event */ @@ -1358,7 +1358,7 @@ __STATIC_INLINE uint8_t DL_RTC_Common_getAlarm1MinutesBCD( */ __STATIC_INLINE void DL_RTC_Common_enableAlarm1HoursBCD(RTC_Regs *rtc_common) { - rtc_common->A1HOUR |= RTC_A1HOUR_AHOURAEBIN_ENABLE; + rtc_common->A1HOUR |= RTC_A1HOUR_AHOURAEBCD_ENABLE; } /** @@ -1369,7 +1369,7 @@ __STATIC_INLINE void DL_RTC_Common_enableAlarm1HoursBCD(RTC_Regs *rtc_common) */ __STATIC_INLINE void DL_RTC_Common_disableAlarm1HoursBCD(RTC_Regs *rtc_common) { - rtc_common->A1HOUR &= ~(RTC_A1HOUR_AHOURAEBIN_MASK); + rtc_common->A1HOUR &= ~(RTC_A1HOUR_AHOURAEBCD_MASK); } /** @@ -1581,7 +1581,7 @@ __STATIC_INLINE uint8_t DL_RTC_Common_getAlarm2MinutesBCD( */ __STATIC_INLINE void DL_RTC_Common_enableAlarm2HoursBCD(RTC_Regs *rtc_common) { - rtc_common->A2HOUR |= RTC_A2HOUR_AHOURAEBIN_ENABLE; + rtc_common->A2HOUR |= RTC_A2HOUR_AHOURAEBCD_ENABLE; } /** @@ -1592,7 +1592,7 @@ __STATIC_INLINE void DL_RTC_Common_enableAlarm2HoursBCD(RTC_Regs *rtc_common) */ __STATIC_INLINE void DL_RTC_Common_disableAlarm2HoursBCD(RTC_Regs *rtc_common) { - rtc_common->A2HOUR &= ~(RTC_A2HOUR_AHOURAEBIN_MASK); + rtc_common->A2HOUR &= ~(RTC_A2HOUR_AHOURAEBCD_MASK); } /** @@ -2405,7 +2405,7 @@ __STATIC_INLINE uint8_t DL_RTC_Common_getAlarm2DayOfMonthBinary( } /** - * @brief Set prescale interrupt interval for timer 0 and 1 + * @brief Set prescale interrupt interval for timer 0, 1, and 2. * * Set prescale timer interrupt interval to DL_RTC_COMMON_PRESCALE_NONE to keep the * timer disabled. @@ -3245,6 +3245,23 @@ __STATIC_INLINE uint32_t DL_RTC_Common_getTimeStampEventSource( return (rtc_common->TSCTL & sourceMask); } +/** + * @brief Returns the Calendar Time of the Time Stamp + * + * @param[in] rtc_common Pointer to the register overlay for the + * RTC Common peripheral + * + * This function returns the current Calendar Time of the Time Stamp + * in the form of a Calendar structure. + * The time returned will be in the previously selected format from + * @ref DL_RTC_Common_setClockFormat, one of @ref DL_RTC_COMMON_FORMAT. + * + * @return @ref DL_RTC_Common_Calendar containing the time stamp + * + */ +DL_RTC_Common_Calendar DL_RTC_Common_getTimeStampCalendar( + const RTC_Regs *rtc_common); + /** * @brief Set the capture method when a time stamp capture event occurs * diff --git a/mspm0/source/ti/driverlib/dl_spgss.c b/mspm0/source/ti/driverlib/dl_spgss.c new file mode 100644 index 0000000..1501678 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_spgss.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MCU_HAS_SPGSS__ +#endif /* __MCU_HAS_SPGSS__ */ diff --git a/mspm0/source/ti/driverlib/dl_spgss.h b/mspm0/source/ti/driverlib/dl_spgss.h new file mode 100644 index 0000000..03351f3 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_spgss.h @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_spgss.h + * @brief Serial Peripheral Group (SPGSS) Driver Library + * @defgroup SPGSS Serial Peripheral Group (SPGSS) + * + * @anchor ti_dl_dl_m0p_spgss_Overview + * # Overview + * + * The Serial Peripheral Group (SPGSS) Driver Library allows full configuration + * of the SPG module. + * The SPG module combines one or more UNICOMM modules for special functions + * like I2C loopback. + * + *
+ ****************************************************************************** + */ +/** @addtogroup SPGSS + * @{ + */ +#ifndef ti_dl_dl_spgss__include +#define ti_dl_dl_spgss__include + +#include +#include + +#include +#include + +#ifdef __MCU_HAS_SPGSS__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_SPGSS_INTERRUPTS + * @{ + */ + +/** @}*/ + +/*! @enum DL_SPGSS_PAIR_CONTROLLER_SEL */ +typedef enum { + /*! Select UC0 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC0_= SPGSS_PAIR0_CTL_SPG1, + /*! Select UC1 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC1_= SPGSS_PAIR0_CTL_SPG2, + /*! Select UC2 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC2_= SPGSS_PAIR0_CTL_SPG3, + /*! Select UC3 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC3_= SPGSS_PAIR0_CTL_SPG4, + /*! Select UC4 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC4_= SPGSS_PAIR0_CTL_SPG5, + /*! Select UC5 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC5_= SPGSS_PAIR0_CTL_SPG6, + /*! Select UC6 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC6_= SPGSS_PAIR0_CTL_SPG7, + /*! Select UC7 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC7_= SPGSS_PAIR0_CTL_SPG8, + /*! Select UC8 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC8_= SPGSS_PAIR0_CTL_SPG9, + /*! Select UC9 as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC9_= SPGSS_PAIR0_CTL_SPG10, + /*! Select UC10_as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC10_= SPGSS_PAIR0_CTL_SPG11, + /*! Select UC11_as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC11_= SPGSS_PAIR0_CTL_SPG12, + /*! Select UC12_as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC12_= SPGSS_PAIR0_CTL_SPG13, + /*! Select UC13_as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC13_= SPGSS_PAIR0_CTL_SPG14, + /*! Select UC14_as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC14_= SPGSS_PAIR0_CTL_SPG15, + /*! Select UC15_as controller for loopback */ + DL_SPGSS_PAIR_CONTROLLER_UC15_= SPGSS_PAIR0_CTL_SPG16, +} DL_SPGSS_PAIR_CONTROLLER_SEL; + +/*! @enum DL_SPGSS_PAIR_TARGET_SEL */ +typedef enum { + /*! Select UC0 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC0_= SPGSS_PAIR0_TARGET_SPG1, + /*! Select UC1 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC1_= SPGSS_PAIR0_TARGET_SPG2, + /*! Select UC2 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC2_= SPGSS_PAIR0_TARGET_SPG3, + /*! Select UC3 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC3_= SPGSS_PAIR0_TARGET_SPG4, + /*! Select UC4 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC4_= SPGSS_PAIR0_TARGET_SPG5, + /*! Select UC5 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC5_= SPGSS_PAIR0_TARGET_SPG6, + /*! Select UC6 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC6_= SPGSS_PAIR0_TARGET_SPG7, + /*! Select UC7 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC7_= SPGSS_PAIR0_TARGET_SPG8, + /*! Select UC8 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC8_= SPGSS_PAIR0_TARGET_SPG9, + /*! Select UC9 as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC9_= SPGSS_PAIR0_TARGET_SPG10, + /*! Select UC10_as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC10_= SPGSS_PAIR0_TARGET_SPG11, + /*! Select UC11_as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC11_= SPGSS_PAIR0_TARGET_SPG12, + /*! Select UC12_as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC12_= SPGSS_PAIR0_TARGET_SPG13, + /*! Select UC13_as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC13_= SPGSS_PAIR0_TARGET_SPG14, + /*! Select UC14_as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC14_= SPGSS_PAIR0_TARGET_SPG15, + /*! Select UC15_as target for loopback */ + DL_SPGSS_PAIR_TARGET_UC15_= SPGSS_PAIR0_TARGET_SPG16, +} DL_SPGSS_PAIR_TARGET_SEL; + +/*! @enum DL_SPGSS_PAIR_INDEX */ +typedef enum { + /*! Loopback pair index 0 */ + DL_SPGSS_PAIR_INDEX_0 = 0, + /*! Loopback pair index 1 */ + DL_SPGSS_PAIR_INDEX_1 = 1, + /*! Loopback pair index 2 */ + DL_SPGSS_PAIR_INDEX_2 = 2, + /*! Loopback pair index 3 */ + DL_SPGSS_PAIR_INDEX_3 = 3, + /*! Loopback pair index 4 */ + DL_SPGSS_PAIR_INDEX_4 = 4, + /*! Loopback pair index 5 */ + DL_SPGSS_PAIR_INDEX_5 = 5, + /*! Loopback pair index 6 */ + DL_SPGSS_PAIR_INDEX_6 = 6, + /*! Loopback pair index 7 */ + DL_SPGSS_PAIR_INDEX_7 = 7, +} DL_SPGSS_PAIR_INDEX; + +/** + * @brief Configuration struct for @ref DL_SPGSS_setLoopbackConfig. + */ +typedef struct { + /*! SPGSS pairing controller selection. One of @ref DL_SPGSS_PAIR_CONTROLLER_SEL */ + DL_SPGSS_PAIR_CONTROLLER_SEL controller; + /*! SPGSS pairing target selection. One of @ref DL_SPGSS_PAIR_TARGET_SEL */ + DL_SPGSS_PAIR_TARGET_SEL target; +} DL_SPGSS_LoopbackConfig; + +/** + * @brief Enable SPGSS pair loopback + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] index Specifies pair index to be configured. One of + * @ref DL_SPGSS_PAIR_INDEX. + */ +__STATIC_INLINE void DL_SPGSS_enableLoopback( + SPGSS_Regs *spgss, DL_SPGSS_PAIR_INDEX index) +{ + volatile uint32_t *pReg = &spgss->I2C_PAIR.PAIR0; + + *(pReg + (uint32_t) index) |= (SPGSS_PAIR0_EN_ENABLE); +} + +/** + * @brief Disable SPGSS pair loopback + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] index Specifies pair index to be configured. One of + * @ref DL_SPGSS_PAIR_INDEX. + */ +__STATIC_INLINE void DL_SPGSS_disableLoopback( + SPGSS_Regs *spgss, DL_SPGSS_PAIR_INDEX index) +{ + volatile uint32_t *pReg = &spgss->I2C_PAIR.PAIR0; + + *(pReg + (uint32_t) index) &= ~(SPGSS_PAIR0_EN_ENABLE); +} + +/** + * @brief Set SPG controller and target for loopback + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] index Specifies pair index to be configured. One of + * @ref DL_SPGSS_PAIR_INDEX. + * @param[in] config Pointer to the pair configuration struct + * @ref DL_SPGSS_LoopbackConfig. + */ +__STATIC_INLINE void DL_SPGSS_setLoopbackConfig(SPGSS_Regs *spgss, DL_SPGSS_PAIR_INDEX index, DL_SPGSS_LoopbackConfig *config) +{ + volatile uint32_t *pReg = &spgss->I2C_PAIR.PAIR0; + + DL_Common_updateReg((pReg + (uint32_t) index), + ((uint32_t) config->controller | (uint32_t) config->target), + (SPGSS_PAIR0_CTL_MASK | SPGSS_PAIR0_TARGET_MASK)); +} + +/** + * @brief Get SPG controller and target for loopback + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] index Specifies loopback index to be configured. One of + * @ref DL_SPGSS_PAIR_INDEX. + * @param[in] config Pointer to the pair configuration struct + * @ref DL_SPGSS_LoopbackConfig. + */ +__STATIC_INLINE void DL_SPGSS_getLoopbackConfig(SPGSS_Regs *spgss, DL_SPGSS_PAIR_INDEX index, DL_SPGSS_LoopbackConfig *config) +{ + volatile uint32_t *pReg = &spgss->I2C_PAIR.PAIR0; + + config->controller = (DL_SPGSS_PAIR_CONTROLLER_SEL)(*(pReg + (uint32_t) index) & SPGSS_PAIR0_CTL_MASK); + config->target = (DL_SPGSS_PAIR_TARGET_SEL)(*(pReg + (uint32_t) index) & SPGSS_PAIR0_TARGET_MASK); +} + +/** + * @brief Enable SPGSS interrupt + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPGSS_INTERRUPTS. + */ +__STATIC_INLINE void DL_SPGSS_enableInterrupt( + SPGSS_Regs *spgss, uint32_t interruptMask) +{ + spgss->CPU_INT.IMASK |= (interruptMask); +} + +/** + * @brief Disable SPGSS interrupt + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPGSS_INTERRUPTS. + * + */ +__STATIC_INLINE void DL_SPGSS_disableInterrupt( + SPGSS_Regs *spgss, uint32_t interruptMask) +{ + spgss->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which SPGSS interrupts are enabled + * + * @param[in] spgss Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPGSS_INTERRUPTS. + * + * @return Which of the requested SPGSS interrupts are enabled + * + * @retval Bitwise OR of @ref DL_SPGSS_INTERRUPTS values + */ +__STATIC_INLINE uint32_t DL_SPGSS_getEnabledInterrupts( + SPGSS_Regs *spgss, uint32_t interruptMask) +{ + return (spgss->CPU_INT.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SPGSS interrupt + * + * Checks if the SPGSS interrupt that was previously enabled is pending. + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPGSS_INTERRUPTS. + * + * @return If the enabled SPGSS interrupt is pending + * + * @sa DL_SPGSS_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_SPGSS_getEnabledInterruptStatus( + SPGSS_Regs *spgss, uint32_t interruptMask) +{ + return (spgss->CPU_INT.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SPGSS interrupt + * + * Checks if the SPGSS interrupt is pending. Interrupt does not have to + * be previously enabled. + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPGSS_INTERRUPTS. + * + * @return If the SPGSS interrupt is pending + * + */ +__STATIC_INLINE uint32_t DL_SPGSS_getRawInterruptStatus( + SPGSS_Regs *spgss, uint32_t interruptMask) +{ + return (spgss->CPU_INT.RIS & interruptMask); +} + +/** + * @brief Clear pending SPGSS interrupt + * + * @param[in] spgss Pointer to the register overlay for the peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPGSS_INTERRUPTS. + * + */ +__STATIC_INLINE void DL_SPGSS_clearInterruptStatus( + SPGSS_Regs *spgss, uint32_t interruptMask) +{ + spgss->CPU_INT.ICLR |= (interruptMask); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_HAS_SPGSS__ */ + +#endif /* ti_dl_dl_spgss__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_spi.c b/mspm0/source/ti/driverlib/dl_spi.c index b48a054..4c030c7 100644 --- a/mspm0/source/ti/driverlib/dl_spi.c +++ b/mspm0/source/ti/driverlib/dl_spi.c @@ -90,6 +90,8 @@ void DL_SPI_transmitDataBlocking8(SPI_Regs *spi, uint8_t data) while (DL_SPI_isTXFIFOFull(spi)) { }; DL_SPI_transmitData8(spi, data); + while (DL_SPI_isBusy(spi)) { + }; } void DL_SPI_transmitDataBlocking16(SPI_Regs *spi, uint16_t data) @@ -97,6 +99,8 @@ void DL_SPI_transmitDataBlocking16(SPI_Regs *spi, uint16_t data) while (DL_SPI_isTXFIFOFull(spi)) { }; DL_SPI_transmitData16(spi, data); + while (DL_SPI_isBusy(spi)) { + }; } void DL_SPI_transmitDataBlocking32(SPI_Regs *spi, uint32_t data) @@ -104,6 +108,8 @@ void DL_SPI_transmitDataBlocking32(SPI_Regs *spi, uint32_t data) while (DL_SPI_isTXFIFOFull(spi)) { }; DL_SPI_transmitData32(spi, data); + while (DL_SPI_isBusy(spi)) { + }; } bool DL_SPI_receiveDataCheck8(const SPI_Regs *spi, uint8_t *buffer) diff --git a/mspm0/source/ti/driverlib/dl_spi.h b/mspm0/source/ti/driverlib/dl_spi.h index 0be5162..266e6b4 100644 --- a/mspm0/source/ti/driverlib/dl_spi.h +++ b/mspm0/source/ti/driverlib/dl_spi.h @@ -1376,7 +1376,7 @@ __STATIC_INLINE void DL_SPI_setDelayedSampling(SPI_Regs *spi, uint32_t delay) */ __STATIC_INLINE uint32_t DL_SPI_getDelayedSampling(const SPI_Regs *spi) { - return (spi->CLKCTL & SPI_CLKCTL_DSAMPLE_MASK >> SPI_CLKCTL_DSAMPLE_OFS); + return ((spi->CLKCTL & SPI_CLKCTL_DSAMPLE_MASK) >> SPI_CLKCTL_DSAMPLE_OFS); } /** @@ -1735,9 +1735,11 @@ __STATIC_INLINE void DL_SPI_clearInterruptStatus( /** * @brief Blocks to ensure transmit is ready before sending data * - * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not - * full. Will wait indefinitely until there is space in the TX FIFO. See - * related APIs for additional transmit options. + * Puts data into the TX FIFO, waiting indefintely until there is space in the + * the TX FIFO. After placing data, waits indefintely until data is sent and + * the SPI busy is no longer busy. Note that if data is already present in the + * TX FIFO when this API is called, it will block until all data is sent. + * See related APIs for additional transmit options. * * Can be used for any data transfers that are less than or equal to 8 bits. * @@ -1752,9 +1754,11 @@ void DL_SPI_transmitDataBlocking8(SPI_Regs *spi, uint8_t data); /** * @brief Blocks to ensure transmit is ready before sending data * - * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not - * full. Will wait indefinitely until there is space in the TX FIFO. See related - * APIs for additional transmit options. + * Puts data into the TX FIFO, waiting indefintely until there is space in the + * the TX FIFO. After placing data, waits indefintely until data is sent and + * the SPI busy is no longer busy. Note that if data is already present in the + * TX FIFO when this API is called, it will block until all data is sent. + * See related APIs for additional transmit options. * * Can be used for any data transfers that are less than or equal to 16 bits. * @@ -1769,9 +1773,11 @@ void DL_SPI_transmitDataBlocking16(SPI_Regs *spi, uint16_t data); /** * @brief Blocks to ensure transmit is ready before sending data * - * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not - * full. Will wait indefinitely until there is space in the TX FIFO. See related - * APIs for additional transmit options. + * Puts data into the TX FIFO, waiting indefintely until there is space in the + * the TX FIFO. After placing data, waits indefintely until data is sent and + * the SPI busy is no longer busy. Note that if data is already present in the + * TX FIFO when this API is called, it will block until all data is sent. + * See related APIs for additional transmit options. * * Can be used for any data transfers that are less than or equal to 32 bits. * diff --git a/mspm0/source/ti/driverlib/dl_timer.c b/mspm0/source/ti/driverlib/dl_timer.c index d4b95ae..5166a4b 100644 --- a/mspm0/source/ti/driverlib/dl_timer.c +++ b/mspm0/source/ti/driverlib/dl_timer.c @@ -102,8 +102,14 @@ void DL_Timer_initTimerMode( DL_Timer_setCaptureCompareCtl(gptimer, (uint32_t) config->genIntermInt, DL_TIMER_CC_ACOND_TIMCLK, DL_TIMER_CC_0_INDEX); - gptimer->COUNTERREGS.CTRCTL = - ((uint32_t) config->timerMode | (uint32_t) config->startTimer); + /* CCCTL0 should be used by default for timer. */ + DL_Timer_setCounterControl(gptimer, DL_TIMER_CZC_CCCTL0_ZCOND, + DL_TIMER_CAC_CCCTL0_ACOND, DL_TIMER_CLC_CCCTL0_LCOND); + + DL_Common_updateReg(&gptimer->COUNTERREGS.CTRCTL, + ((uint32_t) config->timerMode | (uint32_t) config->startTimer), + (GPTIMER_CTRCTL_REPEAT_MASK | GPTIMER_CTRCTL_EN_MASK | + GPTIMER_CTRCTL_CM_MASK)); } void DL_Timer_initCaptureMode( diff --git a/mspm0/source/ti/driverlib/dl_timera.h b/mspm0/source/ti/driverlib/dl_timera.h index 14ae95d..34b2863 100644 --- a/mspm0/source/ti/driverlib/dl_timera.h +++ b/mspm0/source/ti/driverlib/dl_timera.h @@ -205,6 +205,26 @@ typedef struct { */ #define DL_TIMERA_CAPTURE_COMPARE_3_INDEX DL_TIMER_CC_3_INDEX +/** + * @brief Index associated to Capture Compare 4 + * @note This option is not supported by all device TimerA modules + * please refer to the "TIMx Configurations" table in the + * device specific datasheet to determine Timer instances which + * support "6 CC Channel" configuration with 4 external and 2 internal + * CC channels. + */ +#define DL_TIMERA_CAPTURE_COMPARE_4_INDEX DL_TIMER_CC_4_INDEX + +/** + * @brief Index associated to Capture Compare 5 + * @note This option is not supported by all device TimerA modules + * please refer to the "TIMx Configurations" table in the + * device specific datasheet to determine Timer instances which + * support "6 CC Channel" configuration with 4 external and 2 internal + * CC channels. + */ +#define DL_TIMERA_CAPTURE_COMPARE_5_INDEX DL_TIMER_CC_5_INDEX + /** @}*/ /** @addtogroup DL_TIMER_CCx diff --git a/mspm0/source/ti/driverlib/dl_timerb.c b/mspm0/source/ti/driverlib/dl_timerb.c new file mode 100644 index 0000000..351dde2 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_timerb.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2025, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MSPM0_HAS_TIMER_B__ + +void DL_TimerB_initTimer(BTIMER_Regs* const timerb, + DL_TimerB_TimerConfig* const config, DL_TIMERB_COUNTER_IDX idx) +{ + DL_TimerB_setLoadValue(timerb, idx, config->loadValue); + DL_TimerB_setTimerClockSource(timerb, idx, config->clockSource); + DL_TimerB_setTimerResetSource(timerb, idx, config->resetSource); + DL_TimerB_setTimerStopSource(timerb, idx, config->stopSource); + DL_TimerB_setTimerStartSource(timerb, idx, config->startSource); + if (config->startTimer) { + DL_TimerB_startCounter(timerb, idx); + } +} + +#endif /* __MSPM0_HAS_TIMER_B__ */ diff --git a/mspm0/source/ti/driverlib/dl_timerb.h b/mspm0/source/ti/driverlib/dl_timerb.h new file mode 100644 index 0000000..f1da68a --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_timerb.h @@ -0,0 +1,1432 @@ +/* + * Copyright (c) 2025, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_timerb.h + * @brief Basic Timer (BTIM) Driver Library + * @defgroup BTIM Basic Timer (BTIM) + * + * @anchor ti_dl_dl_timerb__Overview + * # Overview + * The Basic Timer (BTIM) Driver Library allows full configuration of the + * MSPM0 BTIM module. The BTIM module is an array of counters which can + * generate periodic interrupts, be concatenated to create longer time + * durations, and measure timing properties of external events. + * + *
+ ****************************************************************************** + */ +/** @addtogroup BTIM + * @{ + */ +#ifndef ti_dl_dl_timerb__include +#define ti_dl_dl_timerb__include + +#include +#include + +#include +#include + +#ifdef __MSPM0_HAS_TIMER_B__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_TIMERB_INTERRUPT + * @{ + */ + +/*! + * @brief Counter 0 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT0_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT0OVF_SET) + +/*! + * @brief Counter 0 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT0_START_EVENT (BTIMER_CPU_INT_IMASK_CNT0STRT_SET) + +/*! + * @brief Counter 0 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT0_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT0STOP_SET) + +/*! + * @brief Counter 1 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT1_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT1OVF_SET) + +/*! + * @brief Counter 1 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT1_START_EVENT (BTIMER_CPU_INT_IMASK_CNT1STRT_SET) + +/*! + * @brief Counter 1 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT1_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT1STOP_SET) + +/*! + * @brief Counter 2 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT2_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT2OVF_SET) + +/*! + * @brief Counter 2 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT2_START_EVENT (BTIMER_CPU_INT_IMASK_CNT2STRT_SET) + +/*! + * @brief Counter 2 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT2_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT2STOP_SET) + +/*! + * @brief Counter 3 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT3_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT3OVF_SET) + +/*! + * @brief Counter 3 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT3_START_EVENT (BTIMER_CPU_INT_IMASK_CNT3STRT_SET) + +/*! + * @brief Counter 3 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT3_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT3STOP_SET) + +/*! + * @brief Counter 4 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT4_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT4OVF_SET) + +/*! + * @brief Counter 4 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT4_START_EVENT (BTIMER_CPU_INT_IMASK_CNT4STRT_SET) + +/*! + * @brief Counter 4 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT4_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT4STOP_SET) + +/*! + * @brief Counter 5 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT5_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT5OVF_SET) + +/*! + * @brief Counter 5 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT5_START_EVENT (BTIMER_CPU_INT_IMASK_CNT5STRT_SET) + +/*! + * @brief Counter 5 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT5_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT5STOP_SET) + +/*! + * @brief Counter 6 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT6_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT6OVF_SET) + +/*! + * @brief Counter 6 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT6_START_EVENT (BTIMER_CPU_INT_IMASK_CNT6STRT_SET) + +/*! + * @brief Counter 6 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT6_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT6STOP_SET) + +/*! + * @brief Counter 7 Overflow interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT7_OVF_EVENT (BTIMER_CPU_INT_IMASK_CNT7OVF_SET) + +/*! + * @brief Counter 7 Start interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT7_START_EVENT (BTIMER_CPU_INT_IMASK_CNT7STRT_SET) + +/*! + * @brief Counter 7 Stop interrupt + */ +#define DL_TIMERB_INTERRUPT_CNT7_STOP_EVENT (BTIMER_CPU_INT_IMASK_CNT7STOP_SET) + +/** @}*/ + +/** @addtogroup DL_TIMERB_EVENT + * @{ + */ + +/*! + * @brief Counter 0 Overflow event + */ +#define DL_TIMERB_EVENT_CNT0_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT0OVF_SET) + +/*! + * @brief Counter 0 Start event + */ +#define DL_TIMERB_EVENT_CNT0_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT0STRT_SET) + +/*! + * @brief Counter 0 Stop event + */ +#define DL_TIMERB_EVENT_CNT0_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT0STOP_SET) + +/*! + * @brief Counter 1 Overflow event + */ +#define DL_TIMERB_EVENT_CNT1_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT1OVF_SET) + +/*! + * @brief Counter 1 Start event + */ +#define DL_TIMERB_EVENT_CNT1_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT1STRT_SET) + +/*! + * @brief Counter 1 Stop event + */ +#define DL_TIMERB_EVENT_CNT1_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT1STOP_SET) + +/*! + * @brief Counter 2 Overflow event + */ +#define DL_TIMERB_EVENT_CNT2_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT2OVF_SET) + +/*! + * @brief Counter 2 Start event + */ +#define DL_TIMERB_EVENT_CNT2_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT2STRT_SET) + +/*! + * @brief Counter 2 Stop event + */ +#define DL_TIMERB_EVENT_CNT2_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT2STOP_SET) + +/*! + * @brief Counter 3 Overflow event + */ +#define DL_TIMERB_EVENT_CNT3_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT3OVF_SET) + +/*! + * @brief Counter 3 Start event + */ +#define DL_TIMERB_EVENT_CNT3_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT3STRT_SET) + +/*! + * @brief Counter 3 Stop event + */ +#define DL_TIMERB_EVENT_CNT3_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT3STOP_SET) + +/*! + * @brief Counter 4 Overflow event + */ +#define DL_TIMERB_EVENT_CNT4_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT4OVF_SET) + +/*! + * @brief Counter 4 Start event + */ +#define DL_TIMERB_EVENT_CNT4_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT4STRT_SET) + +/*! + * @brief Counter 4 Stop event + */ +#define DL_TIMERB_EVENT_CNT4_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT4STOP_SET) + +/*! + * @brief Counter 5 Overflow event + */ +#define DL_TIMERB_EVENT_CNT5_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT5OVF_SET) + +/*! + * @brief Counter 5 Start event + */ +#define DL_TIMERB_EVENT_CNT5_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT5STRT_SET) + +/*! + * @brief Counter 5 Stop event + */ +#define DL_TIMERB_EVENT_CNT5_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT5STOP_SET) + +/*! + * @brief Counter 6 Overflow event + */ +#define DL_TIMERB_EVENT_CNT6_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT6OVF_SET) + +/*! + * @brief Counter 6 Start event + */ +#define DL_TIMERB_EVENT_CNT6_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT6STRT_SET) + +/*! + * @brief Counter 6 Stop event + */ +#define DL_TIMERB_EVENT_CNT6_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT6STOP_SET) + +/*! + * @brief Counter 7 Overflow event + */ +#define DL_TIMERB_EVENT_CNT7_OVF_EVENT (BTIMER_GEN_EVENT_IMASK_CNT7OVF_SET) + +/*! + * @brief Counter 7 Start event + */ +#define DL_TIMERB_EVENT_CNT7_START_EVENT (BTIMER_GEN_EVENT_IMASK_CNT7STRT_SET) + +/*! + * @brief Counter 7 Stop event + */ +#define DL_TIMERB_EVENT_CNT7_STOP_EVENT (BTIMER_GEN_EVENT_IMASK_CNT7STOP_SET) + +/** @}*/ + +/* clang-format on */ + +/*! @enum DL_TIMERB_COUNTER_IDX */ +typedef enum { + /*! BTimer counter index 0 */ + DL_TIMERB_COUNTER_IDX_0 = 0, + /*! BTimer counter index 1 */ + DL_TIMERB_COUNTER_IDX_1 = 1, + /*! BTimer counter index 2 */ + DL_TIMERB_COUNTER_IDX_2 = 2, + /*! BTimer counter index 3 */ + DL_TIMERB_COUNTER_IDX_3 = 3, + /*! BTimer counter index 4 */ + DL_TIMERB_COUNTER_IDX_4 = 4, + /*! BTimer counter index 5 */ + DL_TIMERB_COUNTER_IDX_5 = 5, + /*! BTimer counter index 6 */ + DL_TIMERB_COUNTER_IDX_6 = 6, + /*! BTimer counter index 7 */ + DL_TIMERB_COUNTER_IDX_7 = 7, +} DL_TIMERB_COUNTER_IDX; + +/*! @enum DL_TIMERB_CLOCK_SOURCE */ +typedef enum { + /*! Selects BUSCLK as clock source */ + DL_TIMERB_CLOCK_SOURCE_BUSCLK = (0U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects overflow from counter 0 as clock source */ + DL_TIMERB_CLOCK_SOURCE_CNT0_OVERFLOW = (1U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects overflow from counter 1 as clock source */ + DL_TIMERB_CLOCK_SOURCE_CNT1_OVERFLOW = (2U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects overflow from counter 2 as clock source */ + DL_TIMERB_CLOCK_SOURCE_CNT2_OVERFLOW = (3U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects overflow from counter 3 as clock source */ + DL_TIMERB_CLOCK_SOURCE_CNT3_OVERFLOW = (4U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects overflow from counter 4 as clock source */ + DL_TIMERB_CLOCK_SOURCE_CNT4_OVERFLOW = (5U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects overflow from counter 5 as clock source */ + DL_TIMERB_CLOCK_SOURCE_CNT5_OVERFLOW = (6U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects overflow from counter 6 as clock source */ + DL_TIMERB_CLOCK_SOURCE_CNT6_OVERFLOW = (7U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects external event 1 as clock source */ + DL_TIMERB_CLOCK_SOURCE_EVENT1 = (8U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects external event 2 as clock source */ + DL_TIMERB_CLOCK_SOURCE_EVENT2 = (9U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects external event 3 as clock source */ + DL_TIMERB_CLOCK_SOURCE_EVENT3 = (10U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects external event 4 as clock source */ + DL_TIMERB_CLOCK_SOURCE_EVENT4 = (11U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects external event 5 as clock source */ + DL_TIMERB_CLOCK_SOURCE_EVENT5 = (12U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects external event 6 as clock source */ + DL_TIMERB_CLOCK_SOURCE_EVENT6 = (13U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects external event 7 as clock source */ + DL_TIMERB_CLOCK_SOURCE_EVENT7 = (14U << BTIMER_CTL0_CLKSEL_OFS), + /*! Selects subscriber event as clock source */ + DL_TIMERB_CLOCK_SOURCE_SUBSCRIBER_EVENT = (15U << BTIMER_CTL0_CLKSEL_OFS), +} DL_TIMERB_CLOCK_SOURCE; + +/*! @enum DL_TIMERB_START_SOURCE */ +typedef enum { + /*! Start source is unused */ + DL_TIMERB_START_SOURCE_UNUSED = (0U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects overflow from counter 0 as start source */ + DL_TIMERB_START_SOURCE_CNT0_OVERFLOW = (1U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects overflow from counter 1 as start source */ + DL_TIMERB_START_SOURCE_CNT1_OVERFLOW = (2U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects overflow from counter 2 as start source */ + DL_TIMERB_START_SOURCE_CNT2_OVERFLOW = (3U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects overflow from counter 3 as start source */ + DL_TIMERB_START_SOURCE_CNT3_OVERFLOW = (4U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects overflow from counter 4 as start source */ + DL_TIMERB_START_SOURCE_CNT4_OVERFLOW = (5U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects overflow from counter 5 as start source */ + DL_TIMERB_START_SOURCE_CNT5_OVERFLOW = (6U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects overflow from counter 6 as start source */ + DL_TIMERB_START_SOURCE_CNT6_OVERFLOW = (7U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects external event 1 as start source */ + DL_TIMERB_START_SOURCE_EVENT1 = (8U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects external event 2 as start source */ + DL_TIMERB_START_SOURCE_EVENT2 = (9U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects external event 3 as start source */ + DL_TIMERB_START_SOURCE_EVENT3 = (10U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects external event 4 as start source */ + DL_TIMERB_START_SOURCE_EVENT4 = (11U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects external event 5 as start source */ + DL_TIMERB_START_SOURCE_EVENT5 = (12U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects external event 6 as start source */ + DL_TIMERB_START_SOURCE_EVENT6 = (13U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects external event 7 as start source */ + DL_TIMERB_START_SOURCE_EVENT7 = (14U << BTIMER_CTL0_STARTSEL_OFS), + /*! Selects subscriber event as start source */ + DL_TIMERB_START_SOURCE_SUBSCRIBER_EVENT = + (15U << BTIMER_CTL0_STARTSEL_OFS), +} DL_TIMERB_START_SOURCE; + +/*! @enum DL_TIMERB_STOP_SOURCE */ +typedef enum { + /*! Stop source is unused */ + DL_TIMERB_STOP_SOURCE_UNUSED = (0U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects overflow from counter 0 as stop source */ + DL_TIMERB_STOP_SOURCE_CNT0_OVERFLOW = (1U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects overflow from counter 1 as stop source */ + DL_TIMERB_STOP_SOURCE_CNT1_OVERFLOW = (2U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects overflow from counter 2 as stop source */ + DL_TIMERB_STOP_SOURCE_CNT2_OVERFLOW = (3U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects overflow from counter 3 as stop source */ + DL_TIMERB_STOP_SOURCE_CNT3_OVERFLOW = (4U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects overflow from counter 4 as stop source */ + DL_TIMERB_STOP_SOURCE_CNT4_OVERFLOW = (5U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects overflow from counter 5 as stop source */ + DL_TIMERB_STOP_SOURCE_CNT5_OVERFLOW = (6U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects overflow from counter 6 as stop source */ + DL_TIMERB_STOP_SOURCE_CNT6_OVERFLOW = (7U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects external event 1 as stop source */ + DL_TIMERB_STOP_SOURCE_EVENT1 = (8U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects external event 2 as stop source */ + DL_TIMERB_STOP_SOURCE_EVENT2 = (9U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects external event 3 as stop source */ + DL_TIMERB_STOP_SOURCE_EVENT3 = (10U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects external event 4 as stop source */ + DL_TIMERB_STOP_SOURCE_EVENT4 = (11U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects external event 5 as stop source */ + DL_TIMERB_STOP_SOURCE_EVENT5 = (12U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects external event 6 as stop source */ + DL_TIMERB_STOP_SOURCE_EVENT6 = (13U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects external event 7 as stop source */ + DL_TIMERB_STOP_SOURCE_EVENT7 = (14U << BTIMER_CTL0_STOPSEL_OFS), + /*! Selects subscriber event as stop source */ + DL_TIMERB_STOP_SOURCE_SUBSCRIBER_EVENT = (15U << BTIMER_CTL0_STOPSEL_OFS), +} DL_TIMERB_STOP_SOURCE; + +/*! @enum DL_TIMERB_RESET_SOURCE */ +typedef enum { + /*! Reset source is unused */ + DL_TIMERB_RESET_SOURCE_UNUSED = (0U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects overflow from counter 0 as reset source */ + DL_TIMERB_RESET_SOURCE_CNT0_OVERFLOW = (1U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects overflow from counter 1 as reset source */ + DL_TIMERB_RESET_SOURCE_CNT1_OVERFLOW = (2U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects overflow from counter 2 as reset source */ + DL_TIMERB_RESET_SOURCE_CNT2_OVERFLOW = (3U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects overflow from counter 3 as reset source */ + DL_TIMERB_RESET_SOURCE_CNT3_OVERFLOW = (4U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects overflow from counter 4 as reset source */ + DL_TIMERB_RESET_SOURCE_CNT4_OVERFLOW = (5U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects overflow from counter 5 as reset source */ + DL_TIMERB_RESET_SOURCE_CNT5_OVERFLOW = (6U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects overflow from counter 6 as reset source */ + DL_TIMERB_RESET_SOURCE_CNT6_OVERFLOW = (7U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects external event 1 as reset source */ + DL_TIMERB_RESET_SOURCE_EVENT1 = (8U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects external event 2 as reset source */ + DL_TIMERB_RESET_SOURCE_EVENT2 = (9U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects external event 3 as reset source */ + DL_TIMERB_RESET_SOURCE_EVENT3 = (10U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects external event 4 as reset source */ + DL_TIMERB_RESET_SOURCE_EVENT4 = (11U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects external event 5 as reset source */ + DL_TIMERB_RESET_SOURCE_EVENT5 = (12U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects external event 6 as reset source */ + DL_TIMERB_RESET_SOURCE_EVENT6 = (13U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects external event 7 as reset source */ + DL_TIMERB_RESET_SOURCE_EVENT7 = (14U << BTIMER_CTL0_RESETSEL_OFS), + /*! Selects subscriber event as reset source */ + DL_TIMERB_RESET_SOURCE_SUBSCRIBER_EVENT = + (15U << BTIMER_CTL0_RESETSEL_OFS), +} DL_TIMERB_RESET_SOURCE; + +/*! @enum DL_TIMERB_IIDX */ +typedef enum { + /*! Timer interrupt index for no pending interrupt */ + DL_TIMERB_IIDX_ZERO = BTIMER_CPU_INT_IIDX_STAT_NO_INTR, + /*! Timer interrupt index for counter 0 period match interrupt */ + DL_TIMERB_IIDX_CNT0_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT0OVF, + /*! Timer interrupt index for counter 0 start interrupt */ + DL_TIMERB_IIDX_CNT0_START = BTIMER_CPU_INT_IIDX_STAT_CNT0STRT, + /*! Timer interrupt index for counter 0 stop interrupt */ + DL_TIMERB_IIDX_CNT0_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT0STOP, + /*! Timer interrupt index for counter 1 period match interrupt */ + DL_TIMERB_IIDX_CNT1_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT1OVF, + /*! Timer interrupt index for counter 1 start interrupt */ + DL_TIMERB_IIDX_CNT1_START = BTIMER_CPU_INT_IIDX_STAT_CNT1STRT, + /*! Timer interrupt index for counter 1 stop interrupt */ + DL_TIMERB_IIDX_CNT1_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT1STOP, + /*! Timer interrupt index for counter 2 period match interrupt */ + DL_TIMERB_IIDX_CNT2_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT2OVF, + /*! Timer interrupt index for counter 2 start interrupt */ + DL_TIMERB_IIDX_CNT2_START = BTIMER_CPU_INT_IIDX_STAT_CNT2STRT, + /*! Timer interrupt index for counter 2 stop interrupt */ + DL_TIMERB_IIDX_CNT2_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT2STOP, + /*! Timer interrupt index for counter 3 period match interrupt */ + DL_TIMERB_IIDX_CNT3_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT3OVF, + /*! Timer interrupt index for counter 3 start interrupt */ + DL_TIMERB_IIDX_CNT3_START = BTIMER_CPU_INT_IIDX_STAT_CNT3STRT, + /*! Timer interrupt index for counter 3 stop interrupt */ + DL_TIMERB_IIDX_CNT3_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT3STOP, + /*! Timer interrupt index for counter 4 period match interrupt */ + DL_TIMERB_IIDX_CNT4_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT4OVF, + /*! Timer interrupt index for counter 4 start interrupt */ + DL_TIMERB_IIDX_CNT4_START = BTIMER_CPU_INT_IIDX_STAT_CNT4STRT, + /*! Timer interrupt index for counter 4 stop interrupt */ + DL_TIMERB_IIDX_CNT4_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT4STOP, + /*! Timer interrupt index for counter 5 period match interrupt */ + DL_TIMERB_IIDX_CNT5_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT5OVF, + /*! Timer interrupt index for counter 5 start interrupt */ + DL_TIMERB_IIDX_CNT5_START = BTIMER_CPU_INT_IIDX_STAT_CNT5STRT, + /*! Timer interrupt index for counter 5 stop interrupt */ + DL_TIMERB_IIDX_CNT5_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT5STOP, + /*! Timer interrupt index for counter 6 period match interrupt */ + DL_TIMERB_IIDX_CNT6_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT6OVF, + /*! Timer interrupt index for counter 6 start interrupt */ + DL_TIMERB_IIDX_CNT6_START = BTIMER_CPU_INT_IIDX_STAT_CNT6STRT, + /*! Timer interrupt index for counter 6 stop interrupt */ + DL_TIMERB_IIDX_CNT6_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT6STOP, + /*! Timer interrupt index for counter 7 period match interrupt */ + DL_TIMERB_IIDX_CNT7_OVERFLOW = BTIMER_CPU_INT_IIDX_STAT_CNT7OVF, + /*! Timer interrupt index for counter 7 start interrupt */ + DL_TIMERB_IIDX_CNT7_START = BTIMER_CPU_INT_IIDX_STAT_CNT7STRT, + /*! Timer interrupt index for counter 7 stop interrupt */ + DL_TIMERB_IIDX_CNT7_STOP = BTIMER_CPU_INT_IIDX_STAT_CNT7STOP, +} DL_TIMERB_IIDX; + +/*! @enum DL_TIMERB_CORE_HALT */ +typedef enum { + /*! Counter will halt immediately, even if the resultant state will result + in corruption if the system is restarted */ + DL_TIMERB_CORE_HALT_IMMEDIATE = + (BTIMER_PDBGCTL_FREE_STOP | BTIMER_PDBGCTL_SOFT_IMMEDIATE), + /*! Counter stops on reaching 0. When the debug halt condition is removed, + the counter starts from the current value */ + DL_TIMERB_CORE_HALT_DELAYED = + (BTIMER_PDBGCTL_FREE_STOP | BTIMER_PDBGCTL_SOFT_DELAYED), + /*! Counter ignores the state of the Core Halted input */ + DL_TIMERB_CORE_HALT_FREE_RUN = + (BTIMER_PDBGCTL_FREE_RUN | BTIMER_PDBGCTL_SOFT_DELAYED), +} DL_TIMERB_CORE_HALT; + +/*! + * @brief Configuration struct for @ref DL_TimerB_initTimer. + */ +typedef struct { + /*! Counter clock source. One of @ref DL_TIMERB_CLOCK_SOURCE */ + DL_TIMERB_CLOCK_SOURCE clockSource; + /*! Counter start source. One of @ref DL_TIMERB_START_SOURCE */ + DL_TIMERB_START_SOURCE startSource; + /*! Counter stop source. One of @ref DL_TIMERB_STOP_SOURCE */ + DL_TIMERB_STOP_SOURCE stopSource; + /*! Counter reset source. One of @ref DL_TIMERB_RESET_SOURCE */ + DL_TIMERB_RESET_SOURCE resetSource; + /*! Load value. Range of [0, 65535] */ + uint16_t loadValue; + /*! Start timer after configuration */ + bool startTimer; +} DL_TimerB_TimerConfig; + +/** + * @brief Enables the Peripheral Write Enable (PWREN) register for the timer + * + * Before any peripheral registers can be configured by software, the + * peripheral itself must be enabled by writing the ENABLE bit together with + * the appropriate KEY value to the peripheral's PWREN register. + * + * @param timerb Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_TimerB_enablePower(BTIMER_Regs* const timerb) +{ + timerb->GPRCM.PWREN = + (BTIMER_PWREN_KEY_UNLOCK_W | BTIMER_PWREN_ENABLE_ENABLE); +} + +/** + * @brief Disables the Peripheral Write Enable (PWREN) register for the timer + * + * When the PWREN.ENABLE bit is cleared, the peripheral's registers are not + * accessible for read/write operations. + * + * @note This API does not provide large power savings. + * + * @param timerb Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_TimerB_disablePower(BTIMER_Regs* const timerb) +{ + timerb->GPRCM.PWREN = + (BTIMER_PWREN_KEY_UNLOCK_W | BTIMER_PWREN_ENABLE_DISABLE); +} + +/** + * @brief Returns if the Peripheral Write Enable (PWREN) register for the timer + * is enabled + * + * Before any peripheral registers can be configured by software, the + * peripheral itself must be enabled by writing the ENABLE bit together with + * the appropriate KEY value to the peripheral's PWREN register. + * + * When the PWREN.ENABLE bit is cleared, the peripheral's registers are not + * accessible for read/write operations. + * + * @param timerb Pointer to the register overlay for the + * peripheral + * + * @return true if peripheral register access is enabled + * @return false if peripheral register access is disabled + */ +__STATIC_INLINE bool DL_TimerB_isPowerEnabled(BTIMER_Regs* const timerb) +{ + return ((bool) ((timerb->GPRCM.PWREN & BTIMER_PWREN_ENABLE_MASK) == + BTIMER_PWREN_ENABLE_ENABLE)); +} + +/** + * @brief Resets timer peripheral + * + * @param timerb Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_TimerB_reset(BTIMER_Regs* const timerb) +{ + timerb->GPRCM.RSTCTL = + (BTIMER_RSTCTL_KEY_UNLOCK_W | BTIMER_RSTCTL_RESETASSERT_ASSERT); +} + +/** + * @brief Clear timer peripheral reset assert flag + * + * Clear RESETSTKY bit in STAT register that indicates the + * peripheral was reset. + * + * @param timerb Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_TimerB_clearResetFlag(BTIMER_Regs* const timerb) +{ + timerb->GPRCM.RSTCTL = + (BTIMER_RSTCTL_KEY_UNLOCK_W | BTIMER_RSTCTL_RESETSTKYCLR_CLR); +} + +/** + * @brief Returns if timer peripheral has been reset + * + * @param timerb Pointer to the register overlay for the + * peripheral + * + * @return true if peripheral was reset + * @return false if peripheral wasn't reset + */ +__STATIC_INLINE bool DL_TimerB_isReset(BTIMER_Regs* const timerb) +{ + return ((bool) ((timerb->GPRCM.STAT & BTIMER_STAT_RESETSTKY_MASK) == + BTIMER_STAT_RESETSTKY_RESET)); +} + +/** + * @brief Sets timer load value + * + * @note Make sure the timer is not running with @ref DL_TimerB_isRunning() + * and @ref DL_TimerB_stopCounter() before calling this API, otherwise this + * API will have no effect + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * @param[in] value 16-bit load value. Range of [0, 65535] + * + * @sa DL_TimerB_stopCounter + * @sa DL_TimerB_isRunning + */ +__STATIC_INLINE void DL_TimerB_setLoadValue( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx, uint16_t value) +{ + timerb->CTRREGS[idx].LD = value; +} + +/** + * @brief Gets the timer load value + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * + * @return Returns the timer load value. Range of [0, 65535] + */ +__STATIC_INLINE uint16_t DL_TimerB_getLoadValue( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + return ((uint16_t)(timerb->CTRREGS[idx].LD & BTIMER_LD_VAL_MAXIMUM)); +} + +/** + * @brief Set timer counter value + * + * @note Make sure the timer is not running with @ref DL_TimerB_isRunning() + * and @ref DL_TimerB_stopCounter() before calling this API, otherwise this + * API will have no effect + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * @param[in] value 16-bit timer counter value. Range of [0, 65535] + * + * @sa DL_TimerB_stopCounter + * @sa DL_TimerB_isRunning + */ +__STATIC_INLINE void DL_TimerB_setTimerCount( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx, uint16_t value) +{ + timerb->CTRREGS[idx].CNT = value; +} + +/** + * @brief Gets the current counter value of the timer + * + * @note It is recommended to check that the counter is not running with + * @ref DL_TimerB_isRunning() and @ref DL_TimerB_stopCounter() before calling + * this API + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * + * @return Returns the timer counter 16-bit value. Range of [0, 65535] + * + * @sa DL_TimerB_stopCounter + * @sa DL_TimerB_isRunning + */ +__STATIC_INLINE uint16_t DL_TimerB_getTimerCount( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + return ((uint16_t)(timerb->CTRREGS[idx].CNT & BTIMER_CNT_VALUE_MASK)); +} + +/** + * @brief Initializes all the configurable options for the Basic Timer + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @warning Counter N cannot use the (N+1)th and beyond's counter overflow + * as the start, stop, reset, or clock source, to prevent combo loops + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the mode configuration struct + * @ref DL_TimerB_TimerConfig. + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + */ +void DL_TimerB_initTimer(BTIMER_Regs* const timerb, + DL_TimerB_TimerConfig* const config, DL_TIMERB_COUNTER_IDX idx); + +/** + * @brief Starts timer counter + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + */ +__STATIC_INLINE void DL_TimerB_startCounter( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + timerb->CTRREGS[idx].CTL0 |= (BTIMER_CTL0_EN_MASK); +} + +/** + * @brief Stops timer counter + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + */ +__STATIC_INLINE void DL_TimerB_stopCounter( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + timerb->CTRREGS[idx].CTL0 &= ~(BTIMER_CTL0_EN_MASK); +} + +/** + * @brief Check if timer is actively running + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * + * @return Returns the running status of the timer + * + * @retval true Timer is running + * @retval false Timer is not running + */ +__STATIC_INLINE bool DL_TimerB_isRunning( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + return ((bool) ((timerb->CTRREGS[idx].CTL0 & BTIMER_CTL0_EN_MASK) == + BTIMER_CTL0_EN_MASK)); +} + +/** + * @brief Set timer start source + * + * @note Make sure the timer is not running with @ref DL_TimerB_isRunning() + * and @ref DL_TimerB_stopCounter() before calling this API, otherwise this + * API will have no effect + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @warning Counter N cannot use the (N+1)th and beyond's counter overflow + * as the start source, to prevent combo loops + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * @param[in] startSource Timer start source. + * One of @ref DL_TIMERB_START_SOURCE + * + * @sa DL_TimerB_stopCounter + * @sa DL_TimerB_isRunning + */ +__STATIC_INLINE void DL_TimerB_setTimerStartSource(BTIMER_Regs* const timerb, + DL_TIMERB_COUNTER_IDX idx, DL_TIMERB_START_SOURCE startSource) +{ + DL_Common_updateReg(&timerb->CTRREGS[idx].CTL0, (uint32_t) startSource, + BTIMER_CTL0_STARTSEL_MASK); +} + +/** + * @brief Gets timer start source + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * + * @return Returns the timer start source. + * One of @ref DL_TIMERB_START_SOURCE + */ +__STATIC_INLINE DL_TIMERB_START_SOURCE DL_TimerB_getTimerStartSource( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + return ((DL_TIMERB_START_SOURCE)( + timerb->CTRREGS[idx].CTL0 & BTIMER_CTL0_STARTSEL_MASK)); +} + +/** + * @brief Set timer stop source + * + * @note Make sure the timer is not running with @ref DL_TimerB_isRunning() + * and @ref DL_TimerB_stopCounter() before calling this API, otherwise this + * API will have no effect + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @warning Counter N cannot use the (N+1)th and beyond's counter overflow + * as the stop source, to prevent combo loops + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * @param[in] stopSource Timer stop source. + * One of @ref DL_TIMERB_STOP_SOURCE + * + * @sa DL_TimerB_stopCounter + * @sa DL_TimerB_isRunning + */ +__STATIC_INLINE void DL_TimerB_setTimerStopSource(BTIMER_Regs* const timerb, + DL_TIMERB_COUNTER_IDX idx, DL_TIMERB_STOP_SOURCE stopSource) +{ + DL_Common_updateReg(&timerb->CTRREGS[idx].CTL0, (uint32_t) stopSource, + BTIMER_CTL0_STOPSEL_MASK); +} + +/** + * @brief Gets timer stop source + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * + * @return Returns the timer stop source. + * One of @ref DL_TIMERB_STOP_SOURCE + */ +__STATIC_INLINE DL_TIMERB_STOP_SOURCE DL_TimerB_getTimerStopSource( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + return ((DL_TIMERB_STOP_SOURCE)( + timerb->CTRREGS[idx].CTL0 & BTIMER_CTL0_STOPSEL_MASK)); +} + +/** + * @brief Set timer reset source + * + * @note Make sure the timer is not running with @ref DL_TimerB_isRunning() + * and @ref DL_TimerB_stopCounter() before calling this API, otherwise this + * API will have no effect + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @warning Counter N cannot use the (N+1)th and beyond's counter overflow + * as the reset source, to prevent combo loops + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * @param[in] resetSource Timer reset source. + * One of @ref DL_TIMERB_RESET_SOURCE + * + * @sa DL_TimerB_stopCounter + * @sa DL_TimerB_isRunning + */ +__STATIC_INLINE void DL_TimerB_setTimerResetSource(BTIMER_Regs* const timerb, + DL_TIMERB_COUNTER_IDX idx, DL_TIMERB_RESET_SOURCE resetSource) +{ + DL_Common_updateReg(&timerb->CTRREGS[idx].CTL0, (uint32_t) resetSource, + BTIMER_CTL0_RESETSEL_MASK); +} + +/** + * @brief Gets timer reset source + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * + * @return Returns the timer reset source. + * One of @ref DL_TIMERB_RESET_SOURCE + */ +__STATIC_INLINE DL_TIMERB_RESET_SOURCE DL_TimerB_getTimerResetSource( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + return ((DL_TIMERB_RESET_SOURCE)( + timerb->CTRREGS[idx].CTL0 & BTIMER_CTL0_RESETSEL_MASK)); +} + +/** + * @brief Set timer clock source + * + * @note Make sure the timer is not running with @ref DL_TimerB_isRunning() + * and @ref DL_TimerB_stopCounter() before calling this API, otherwise this + * API will have no effect + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @warning Counter N cannot use the (N+1)th and beyond's counter overflow + * as the clock source, to prevent combo loops + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * @param[in] clockSource Timer clock source. + * One of @ref DL_TIMERB_CLOCK_SOURCE + * + * @sa DL_TimerB_stopCounter + * @sa DL_TimerB_isRunning + */ +__STATIC_INLINE void DL_TimerB_setTimerClockSource(BTIMER_Regs* const timerb, + DL_TIMERB_COUNTER_IDX idx, DL_TIMERB_CLOCK_SOURCE clockSource) +{ + DL_Common_updateReg(&timerb->CTRREGS[idx].CTL0, (uint32_t) clockSource, + BTIMER_CTL0_CLKSEL_MASK); +} + +/** + * @brief Gets timer clock source + * + * @note The counter index should not exceed the number of counters on the + * BTimer instance. Passing an out-of-range index will result in reads + * returning 0, and writes having no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] idx Counter index. One of @ref DL_TIMERB_COUNTER_IDX. + * Refer to the device datasheet for the number of + * counters supported on a BTimer instance + * + * @return Returns the timer clock source. + * One of @ref DL_TIMERB_CLOCK_SOURCE + */ +__STATIC_INLINE DL_TIMERB_CLOCK_SOURCE DL_TimerB_getTimerClockSource( + BTIMER_Regs* const timerb, DL_TIMERB_COUNTER_IDX idx) +{ + return ((DL_TIMERB_CLOCK_SOURCE)( + timerb->CTRREGS[idx].CTL0 & BTIMER_CTL0_CLKSEL_MASK)); +} + +/** + * @brief Enable timer interrupts + * + * @note Configuring interrupts for counters not available on a BTimer + * instance will have no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_INTERRUPT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + */ +__STATIC_INLINE void DL_TimerB_enableInterrupt( + BTIMER_Regs* const timerb, uint32_t interruptMask) +{ + timerb->CPU_INT.IMASK |= interruptMask; +} + +/** + * @brief Disable timer interrupts + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_INTERRUPT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + */ +__STATIC_INLINE void DL_TimerB_disableInterrupt( + BTIMER_Regs* const timerb, uint32_t interruptMask) +{ + timerb->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which timer interrupts are enabled + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_INTERRUPT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + * + * @return Which of the requested timer interrupts are enabled + * + * @retval Bitwise OR of @ref DL_TIMERB_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_TimerB_getEnabledInterrupts( + BTIMER_Regs* const timerb, uint32_t interruptMask) +{ + return ((uint32_t)(timerb->CPU_INT.IMASK & interruptMask)); +} + +/** + * @brief Check interrupt flag of enabled timer interrupts + * + * Checks if any of the timer interrupts that were previously enabled are + * pending. + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_INTERRUPT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + * + * @return Which of the requested timer interrupts are pending + * + * @retval Bitwise OR of @ref DL_TIMERB_INTERRUPT values + * + * @sa DL_TimerB_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_TimerB_getEnabledInterruptStatus( + BTIMER_Regs* const timerb, uint32_t interruptMask) +{ + return ((uint32_t)(timerb->CPU_INT.MIS & interruptMask)); +} + +/** + * @brief Check interrupt flag of any timer interrupt + * + * Checks if any of the timer interrupts are pending. Interrupts do not have + * to be previously enabled. + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_INTERRUPT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + * + * @return Which of the requested timer interrupts are pending + * + * @retval Bitwise OR of @ref DL_TIMERB_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_TimerB_getRawInterruptStatus( + BTIMER_Regs* const timerb, uint32_t interruptMask) +{ + return ((uint32_t)(timerb->CPU_INT.RIS & interruptMask)); +} + +/** + * @brief Get highest priority pending timer interrupt + * + * Checks if any of the timer interrupts are pending. Interrupts do not have + * to be previously enabled. + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * + * @return The highest priority pending timer interrupt. One of + * @ref DL_TIMERB_IIDX + */ +__STATIC_INLINE DL_TIMERB_IIDX DL_TimerB_getPendingInterrupt( + BTIMER_Regs* const timerb) +{ + return ((DL_TIMERB_IIDX) timerb->CPU_INT.IIDX); +} + +/** + * @brief Clear pending timer interrupts + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_INTERRUPT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + */ +__STATIC_INLINE void DL_TimerB_clearInterruptStatus( + BTIMER_Regs* const timerb, uint32_t interruptMask) +{ + timerb->CPU_INT.ICLR = interruptMask; +} + +/** + * @brief Sets the event publisher channel ID + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] chanID Channel ID number. Valid range 0-15. If ChanID == 0 + * publisher is disconnected. + */ +__STATIC_INLINE void DL_TimerB_setPublisherChanID( + BTIMER_Regs* const timerb, uint8_t chanID) +{ + timerb->FPUB_0 = (chanID & BTIMER_FPUB_0_CHANID_MAXIMUM); +} + +/** + * @brief Gets the event publisher channel ID + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * + * @return Event publisher channel ID + * + */ +__STATIC_INLINE uint8_t DL_TimerB_getPublisherChanID(BTIMER_Regs* const timerb) +{ + return ((uint8_t)(timerb->FPUB_0 & BTIMER_FPUB_0_CHANID_MASK)); +} + +/** + * @brief Sets the event subscriber channel ID + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] chanID Channel ID number. Valid range 0-15. If ChanID == 0 + * subscriber is disconnected. + */ +__STATIC_INLINE void DL_TimerB_setSubscriberChanID( + BTIMER_Regs* const timerb, uint8_t chanID) +{ + timerb->FSUB_0 = (chanID & BTIMER_FSUB_0_CHANID_MAXIMUM); +} + +/** + * @brief Gets the event subscriber channel ID + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * + * @return Event subscriber channel ID + * + */ +__STATIC_INLINE uint8_t DL_TimerB_getSubscriberChanID( + BTIMER_Regs* const timerb) +{ + return ((uint8_t)(timerb->FSUB_0 & BTIMER_FSUB_0_CHANID_MASK)); +} + +/** + * @brief Enable timer event + * + * @note Configuring events for counters not available on a BTimer + * instance will have no effect + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] eventMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_EVENT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + */ +__STATIC_INLINE void DL_TimerB_enableEvent( + BTIMER_Regs* const timerb, uint32_t eventMask) +{ + timerb->GEN_EVENT.IMASK |= eventMask; +} + +/** + * @brief Disable timer event + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] eventMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_EVENT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + */ +__STATIC_INLINE void DL_TimerB_disableEvent( + BTIMER_Regs* const timerb, uint32_t eventMask) +{ + timerb->GEN_EVENT.IMASK &= ~(eventMask); +} + +/** + * @brief Check which timer events are enabled + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] eventMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_EVENT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + * + * @return Which of the requested timer interrupts are enabled + * + * @retval Bitwise OR of @ref DL_TIMERB_EVENT values + */ +__STATIC_INLINE uint32_t DL_TimerB_getEnabledEvents( + BTIMER_Regs* const timerb, uint32_t eventMask) +{ + return ((uint32_t)(timerb->GEN_EVENT.IMASK & eventMask)); +} + +/** + * @brief Check event flag of enabled timer event + * + * Checks if any of the timer events that were previously enabled are + * pending. + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] eventMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_EVENT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + * + * @return Which of the requested timer interrupts are pending + * + * @retval Bitwise OR of @ref DL_TIMERB_EVENT values + * + * @sa DL_TimerB_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_TimerB_getEnabledEventStatus( + BTIMER_Regs* const timerb, uint32_t eventMask) +{ + return ((uint32_t)(timerb->GEN_EVENT.MIS & eventMask)); +} + +/** + * @brief Check interrupt flag of any timer event + * + * Checks if any events are pending. Events do not have to + * be previously enabled. + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] eventMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_EVENT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + * + * @return Which of the requested timer interrupts are pending + * + * @retval Bitwise OR of @ref DL_TIMERB_EVENT values + */ +__STATIC_INLINE uint32_t DL_TimerB_getRawEventsStatus( + BTIMER_Regs* const timerb, uint32_t eventMask) +{ + return ((uint32_t)(timerb->GEN_EVENT.RIS & eventMask)); +} + +/** + * @brief Clear pending timer events + * + * @param[in] timerb Pointer to the register overlay for the + * peripheral + * @param[in] eventMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_TIMERB_EVENT. Refer to the device + * datasheet for the counters supported on a BTimer + * instance + */ +__STATIC_INLINE void DL_TimerB_clearEventsStatus( + BTIMER_Regs* const timerb, uint32_t eventMask) +{ + timerb->GEN_EVENT.ICLR |= eventMask; +} + +/** + * @brief Configures timer behavior when the core is halted. + * + * @param[in] timerb Pointer to the register overlay for the peripheral + * + * @param[in] haltMode Timer halt behavior. One of @ref DL_TIMERB_CORE_HALT. + * + */ +__STATIC_INLINE void DL_TimerB_setCoreHaltBehavior( + BTIMER_Regs* const timerb, DL_TIMERB_CORE_HALT haltMode) +{ + timerb->PDBGCTL = ((uint32_t) haltMode & + (BTIMER_PDBGCTL_FREE_MASK | BTIMER_PDBGCTL_SOFT_MASK)); +} + +/** + * @brief Get timer behavior when the core is halted. + * + * @param[in] timerb Pointer to the register overlay for the peripheral + * + * @return Timer behavior when core is halted. One of + * @ref DL_TIMERB_CORE_HALT + * + */ +__STATIC_INLINE DL_TIMERB_CORE_HALT DL_TimerB_getCoreHaltBehavior( + BTIMER_Regs* const timerb) +{ + uint32_t haltMode = (timerb->PDBGCTL & (BTIMER_PDBGCTL_FREE_MASK | + BTIMER_PDBGCTL_SOFT_MASK)); + + return ((DL_TIMERB_CORE_HALT)(haltMode)); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MSPM0_HAS_TIMER_B__ */ + +#endif /* ti_dl_dl_timerb__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_uart.c b/mspm0/source/ti/driverlib/dl_uart.c index 4b878fc..0040840 100644 --- a/mspm0/source/ti/driverlib/dl_uart.c +++ b/mspm0/source/ti/driverlib/dl_uart.c @@ -165,6 +165,8 @@ void DL_UART_transmitDataBlocking(UART_Regs *uart, uint8_t data) while (DL_UART_isTXFIFOFull(uart)) { }; DL_UART_transmitData(uart, data); + while (DL_UART_isBusy(uart)) { + }; } bool DL_UART_receiveDataCheck(const UART_Regs *uart, uint8_t *buffer) diff --git a/mspm0/source/ti/driverlib/dl_uart.h b/mspm0/source/ti/driverlib/dl_uart.h index 0572d4b..c8b4731 100644 --- a/mspm0/source/ti/driverlib/dl_uart.h +++ b/mspm0/source/ti/driverlib/dl_uart.h @@ -1645,7 +1645,7 @@ __STATIC_INLINE void DL_UART_setExternalDriverSetup( __STATIC_INLINE uint32_t DL_UART_getExternalDriverSetup(const UART_Regs *uart) { return ((uart->LCRH & - UART_LCRH_EXTDIR_SETUP_MASK >> UART_LCRH_EXTDIR_SETUP_OFS)); + UART_LCRH_EXTDIR_SETUP_MASK) >> UART_LCRH_EXTDIR_SETUP_OFS); } /** @@ -1681,7 +1681,7 @@ __STATIC_INLINE void DL_UART_setExternalDriverHold( __STATIC_INLINE uint32_t DL_UART_getExternalDriverHold(const UART_Regs *uart) { return (( - uart->LCRH & UART_LCRH_EXTDIR_HOLD_MASK >> UART_LCRH_EXTDIR_HOLD_OFS)); + uart->LCRH & UART_LCRH_EXTDIR_HOLD_MASK) >> UART_LCRH_EXTDIR_HOLD_OFS); } /** @@ -3023,9 +3023,11 @@ __STATIC_INLINE DL_UART_PULSE_WIDTH DL_UART_getAnalogPulseWidth( /** * @brief Blocks to ensure transmit is ready before sending data * - * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not - * full. Will wait indefintely until there is space in the TX FIFO. See - * related APIs for additional transmit options. + * Puts data into the TX FIFO, waiting indefintely until there is space in the + * the TX FIFO. After placing data, waits indefintely until data is sent and + * the entire TX FIFO is empty. Note that if data is already present in the TX + * FIFO when this API is called, it will block until all data is sent. + * See related APIs for additional transmit options. * * Can be used for any data transfers that are less than or equal to 8 bits. * diff --git a/mspm0/source/ti/driverlib/dl_unicomm.c b/mspm0/source/ti/driverlib/dl_unicomm.c new file mode 100644 index 0000000..1d977b1 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicomm.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MCU_HAS_UNICOMM__ +#endif /* __MCU_HAS_UNICOMM__ */ diff --git a/mspm0/source/ti/driverlib/dl_unicomm.h b/mspm0/source/ti/driverlib/dl_unicomm.h new file mode 100644 index 0000000..cada1ae --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicomm.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_unicomm.h + * @brief Unified Communication Module (UNICOMM) Driver Library + * @defgroup UNICOMM Unified Communication Module (UNICOMM) + * + * @anchor ti_dl_dl_m0p_unicomm_Overview + * # Overview + * + * The Unified Communication Module (UNICOMM) Driver Library allows full + * configuration of the UNICOMM module. + * UNICOMM is a highly flexible peripheral which can be configured as a UART, + * SPI, I2C Controller, or I2C Target function. + * + *
+ ****************************************************************************** + */ +/** @addtogroup UNICOMM + * @{ + */ +#ifndef ti_dl_dl_unicomm__include +#define ti_dl_dl_unicomm__include + +#include +#include + +#include +#include + +#ifdef __MCU_HAS_UNICOMM__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/*! @enum DL_UNICOMM_IP_MODE_SEL */ +typedef enum { + /*! Select UART functionality */ + DL_UNICOMM_UART = UNICOMM_IPMODE_SELECT_UART, + /*! Select SPI functionality*/ + DL_UNICOMM_SPI = UNICOMM_IPMODE_SELECT_SPI, + /*! Select I2C functionality in controller mode */ + DL_UNICOMM_I2C_CONTROLLER = UNICOMM_IPMODE_SELECT_I2C_CONTROLLER, + /*! Select I2C functionality in target mode */ + DL_UNICOMM_I2C_TARGET = UNICOMM_IPMODE_SELECT_I2C_PERIPHERAL, +} DL_UNICOMM_IP_MODE_SEL; + +/** + * @brief Enables power on unicomm module + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UNICOMM_enablePower(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->inst->GPRCM.PWREN = + (UNICOMM_PWREN_KEY_UNLOCK_W | UNICOMM_PWREN_ENABLE_ENABLE); +} + +/** + * @brief Disables power on unicomm module + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UNICOMM_disablePower(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->inst->GPRCM.PWREN = + (UNICOMM_PWREN_KEY_UNLOCK_W | UNICOMM_PWREN_ENABLE_DISABLE); +} + +/** + * @brief Returns if power on unicomm module + * + * @param unicomm Pointer to the register overlay for the peripheral + * + * @return true if power is enabled + * @return false if power is disabled + */ +__STATIC_INLINE bool DL_UNICOMM_isPowerEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->inst->GPRCM.PWREN & UNICOMM_PWREN_ENABLE_MASK) == + UNICOMM_PWREN_ENABLE_ENABLE); +} + +/** + * @brief Resets unicomm peripheral + * + * @param unicomm Pointer to the register overlay for the UNICOMM peripheral + */ +__STATIC_INLINE void DL_UNICOMM_reset(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->inst->GPRCM.RSTCTL = + (UNICOMM_RSTCTL_KEY_UNLOCK_W | UNICOMM_RSTCTL_RESETSTKYCLR_CLR | + UNICOMM_RSTCTL_RESETASSERT_ASSERT); +} + +/** + * @brief Returns if unicomm peripheral was reset + * + * @param unicomm Pointer to the register overlay for the UNICOMM peripheral + * + * @return true if peripheral was reset + * @return false if peripheral wasn't reset + * + */ +__STATIC_INLINE bool DL_UNICOMM_isReset(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->inst->GPRCM.STAT & UNICOMM_STAT_RESETSTKY_MASK) == + UNICOMM_STAT_RESETSTKY_RESET); +} + +/** + * @brief Configure the unicomm peripheral for specified ip mode + * + * @param unicomm Pointer to the register overlay for the UNICOMM peripheral + * @param ipMode Specifies IP mode functionality. One of @ref DL_UNICOMM_IP_MODE_SEL + */ +__STATIC_INLINE void DL_UNICOMM_setIPMode(UNICOMM_Inst_Regs *unicomm, DL_UNICOMM_IP_MODE_SEL ipMode) +{ + unicomm->inst->IPMODE = (ipMode & UNICOMM_IPMODE_SELECT_MASK); +} + +/** + * @brief Returns ip mode the unicomm peripheral is configured to + * + * @param unicomm Pointer to the register overlay for the UNICOMM peripheral + * + * @return Configured IP mode selection + * @retval One of @ref DL_UNICOMM_IP_MODE_SEL + */ +__STATIC_INLINE DL_UNICOMM_IP_MODE_SEL DL_UNICOMM_getIPMode(UNICOMM_Inst_Regs *unicomm) +{ + return (DL_UNICOMM_IP_MODE_SEL)(unicomm->inst->IPMODE & UNICOMM_IPMODE_SELECT_MASK); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_HAS_UNICOMM__ */ + +#endif /* ti_dl_dl_unicomm__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_unicommi2cc.c b/mspm0/source/ti/driverlib/dl_unicommi2cc.c new file mode 100644 index 0000000..f17354e --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommi2cc.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MCU_HAS_UNICOMMI2CC__ + +void DL_I2CC_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_ClockConfig *config) +{ + DL_Common_updateReg(&unicomm->i2cc->CLKSEL, (uint32_t) config->clockSel, + UNICOMMI2CC_CLKSEL_BUSCLK_SEL_MASK | + UNICOMMI2CC_CLKSEL_MFCLK_SEL_MASK); + + DL_Common_updateReg(&unicomm->i2cc->CLKDIV, (uint32_t) config->divideRatio, + UNICOMMI2CC_CLKDIV_RATIO_MASK); +} + +void DL_I2CC_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_ClockConfig *config) +{ + uint32_t clockSel = + unicomm->i2cc->CLKSEL & (UNICOMMI2CC_CLKSEL_BUSCLK_SEL_MASK | + UNICOMMI2CC_CLKSEL_MFCLK_SEL_MASK); + config->clockSel = (DL_I2CC_CLOCK)(clockSel); + + uint32_t divideRatio = + unicomm->i2cc->CLKDIV & UNICOMMI2CC_CLKDIV_RATIO_MASK; + config->divideRatio = (DL_I2CC_CLOCK_DIVIDE)(divideRatio); +} + +uint16_t DL_I2CC_fillTXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint16_t count) +{ + uint16_t i; + for (i = (uint16_t) 0; i < count; i++) { + if (DL_I2CC_isTXFIFOFull(unicomm) == false) { + DL_I2CC_transmitData(unicomm, buffer[i]); + } else { // TX FIFO is full + break; + } + } + return i; +} + +void DL_I2CC_flushTXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + DL_I2CC_startFlushTXFIFO(unicomm); + while (DL_I2CC_isTXFIFOEmpty(unicomm) == false) { + ; + } + DL_I2CC_stopFlushTXFIFO(unicomm); +} + +void DL_I2CC_flushRXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + DL_I2CC_startFlushRXFIFO(unicomm); + while (DL_I2CC_isRXFIFOEmpty(unicomm) == false) { + ; + } + DL_I2CC_stopFlushRXFIFO(unicomm); +} + +#endif /* __MCU_HAS_UNICOMMI2CC__ */ diff --git a/mspm0/source/ti/driverlib/dl_unicommi2cc.h b/mspm0/source/ti/driverlib/dl_unicommi2cc.h new file mode 100644 index 0000000..33eba81 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommi2cc.h @@ -0,0 +1,2191 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_unicommi2cc.h + * @brief Unified Communication Module (UNICOMM) - Inter-Integrated Circuit Controller (I2CC) Driver Library + * @defgroup UNICOMMI2CC Unified Communication Module (UNICOMM) - Inter-Integrated Circuit Controller (I2CC) + * + * @anchor ti_dl_dl_m0p_unicommi2cc_Overview + * # Overview + * + * Unified Communication Module Inter-Integrated Circuit Controller Driver Library allows + * full configuration of the UNICOMM I2CC module. + * + * This Inter-Integrated Circuit Controller (I2CC) module provides a standardized + * interface to transfer data, as a controller, between devices and other external + * devices with the I2C interface. + * + *
+ ****************************************************************************** + */ +/** @addtogroup UNICOMMI2CC + * @{ + */ +#ifndef ti_dl_dl_unicommi2cc__include +#define ti_dl_dl_unicommi2cc__include + +#include +#include + +#include +#include +#include + +#ifdef __MCU_HAS_UNICOMMI2CC__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/*! + * @brief I2CC number of bytes which could be put into the TX FIFO + * + * This variable is device specific and is calculated using the system parameter + * UNICOMMI2CC_SYS_FENTRIES defined in each devices header file. +*/ +#define DL_I2CC_TX_FIFO_COUNT_MAXIMUM ((uint32_t)UNICOMMI2CC_SYS_FENTRIES << 8) + +/*! + * @brief I2CC number of bytes which could be put into the RX FIFO + * + * This variable is device specific and is calculated using the system parameter + * UNICOMMI2CC_SYS_FENTRIES defined in each devices header file. +*/ +#define DL_I2CC_RX_FIFO_COUNT_MAXIMUM ((uint32_t)UNICOMMI2CC_SYS_FENTRIES) + +/** @addtogroup DL_I2CC_STATUS + * @{ + */ +/*! + * @brief I2CC is busy + * + * The BUSY bit is set during an ongoing transaction, so is set during the + * transmit/receive of the amount of data set in WBLEN including START, RESTART, + * Address and STOP signal generation when required for the current transaction + */ +#define DL_I2CC_STATUS_BUSY (UNICOMMI2CC_SR_BUSY_MASK) + +/*! + * @brief I2CC error detected + * + * The error can be from the target address not being acknowledged or the + * transmit data not being acknowledged + */ +#define DL_I2CC_STATUS_ERROR (UNICOMMI2CC_SR_ERR_MASK) + +/*! + * @brief I2CC address acknowledged + */ +#define DL_I2CC_STATUS_ADDR_ACK (UNICOMMI2CC_SR_ADRACK_MASK) + +/*! + * @brief I2CC data acknowledged + */ +#define DL_I2CC_STATUS_DATA_ACK (UNICOMMI2CC_SR_DATACK_MASK) + +/*! + * @brief I2CC arbitration lost + */ +#define DL_I2CC_STATUS_ARBITRATION_LOST (UNICOMMI2CC_SR_ARBLST_MASK) + +/*! + * @brief I2CC idle + */ +#define DL_I2CC_STATUS_IDLE (UNICOMMI2CC_SR_IDLE_MASK) + +/*! + * @brief I2CC bus busy + * + * The bit changes based on the START and STOP conditions + */ +#define DL_I2CC_STATUS_BUSY_BUS (UNICOMMI2CC_SR_BUSBSY_MASK) + +/** @}*/ + + +/** @addtogroup DL_I2CC_INTERRUPT + * @{ + */ +/*! + * @brief Receive Transaction completed Interrupt + */ +#define DL_I2CC_INTERRUPT_RX_DONE (UNICOMMI2CC_CPU_INT_IMASK_RXDONE_SET) + +/*! + * @brief Transmit Transaction completed Interrupt + */ +#define DL_I2CC_INTERRUPT_TX_DONE (UNICOMMI2CC_CPU_INT_IMASK_TXDONE_SET) + +/*! + * @brief Receive FIFO Trigger when >= defined bytes + */ +#define DL_I2CC_INTERRUPT_RXFIFO_TRIGGER \ + (UNICOMMI2CC_CPU_INT_IMASK_RXTRG_SET) + +/*! + * @brief Transmit FIFO Trigger when <= defined bytes + */ +#define DL_I2CC_INTERRUPT_TXFIFO_TRIGGER \ + (UNICOMMI2CC_CPU_INT_IMASK_TXTRG_SET) + +/*! + * @brief Receive FIFO is full + */ +#define DL_I2CC_INTERRUPT_RXFIFO_FULL \ + (UNICOMMI2CC_CPU_INT_IMASK_RXFULL_SET) + +/*! + * @brief Transmit FIFO is empty + */ +#define DL_I2CC_INTERRUPT_TXFIFO_EMPTY \ + (UNICOMMI2CC_CPU_INT_IMASK_TXEMPTY_SET) + +/*! + * @brief Address/Data NACK Interrupt + */ +#define DL_I2CC_INTERRUPT_NACK (UNICOMMI2CC_CPU_INT_IMASK_NACK_SET) + +/*! + * @brief START Detection Interrupt + */ +#define DL_I2CC_INTERRUPT_START (UNICOMMI2CC_CPU_INT_IMASK_START_SET) + +/*! + * @brief STOP Detection Interrupt + */ +#define DL_I2CC_INTERRUPT_STOP (UNICOMMI2CC_CPU_INT_IMASK_STOP_SET) + +/*! + * @brief Arbitration Lost Interrupt + */ +#define DL_I2CC_INTERRUPT_ARBITRATION_LOST \ + (UNICOMMI2CC_CPU_INT_IMASK_ARBLOST_SET) + +/*! + * @brief DMA Done on Event 1 publisher + */ +#define DL_I2CC_INTERRUPT_EVENT1_DMA_DONE \ + (UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_TX_SET) + +/*! + * @brief DMA Done on Event 2 publisher + */ +#define DL_I2CC_INTERRUPT_EVENT2_DMA_DONE \ + (UNICOMMI2CC_CPU_INT_IMASK_DMA_DONE_RX_SET) + + +/*! + * @brief SMBus/PMBus PEC Receive Error Interrupt + */ +#define DL_I2CC_INTERRUPT_PEC_RX_ERROR \ + (UNICOMMI2CC_CPU_INT_IMASK_PEC_RX_ERR_SET) + +/*! + * @brief Timeout A Interrupt + */ +#define DL_I2CC_INTERRUPT_TIMEOUT_A (UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTA_SET) + +/*! + * @brief Timeout B Interrupt + */ +#define DL_I2CC_INTERRUPT_TIMEOUT_B (UNICOMMI2CC_CPU_INT_IMASK_TIMEOUTB_SET) + + +/** @}*/ + +/** @addtogroup DL_I2CC_DMA_INTERRUPT + * @{ + */ +/*! + * @brief Controller Transmit FIFO Trigger interrupt for DMA trigger + */ +#define DL_I2CC_DMA_INTERRUPT_TXFIFO_TRIGGER \ + (UNICOMMI2CC_DMA_TRIG0_IMASK_TXTRG_SET) + +/*! + * @brief Controller Receive FIFO Trigger interrupt for DMA trigger + */ +#define DL_I2CC_DMA_INTERRUPT_RXFIFO_TRIGGER \ + (UNICOMMI2CC_DMA_TRIG1_IMASK_RXTRG_SET) + +/** @}*/ + +/* clang-format on */ + +/** @enum DL_I2CC_EVENT_ROUTE */ +typedef enum { + /*! I2CC event route 1 */ + DL_I2CC_EVENT_ROUTE_1 = 0, + /*! I2CC event route 2 */ + DL_I2CC_EVENT_ROUTE_2 = 12 +} DL_I2CC_EVENT_ROUTE; + +/** @enum DL_I2CC_CLOCK */ +typedef enum { + /*! BUSCLK enabled as I2CC clock source */ + DL_I2CC_CLOCK_BUSCLK = UNICOMMI2CC_CLKSEL_BUSCLK_SEL_ENABLE, + /*! MFCLK enabled as I2CC clock source */ + DL_I2CC_CLOCK_MFCLK = UNICOMMI2CC_CLKSEL_MFCLK_SEL_ENABLE, + /*! Asynchronous SYSCLK enabled as I2CC clock source */ + DL_I2CC_CLOCK_ASYNC_SYSCLK = UNICOMMI2CC_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE, + /*! Asynchronous HFCLK enabled as I2CC clock source */ + DL_I2CC_CLOCK_ASYNC_HFCLK = UNICOMMI2CC_CLKSEL_ASYNC_HFCLK_SEL_ENABLE, + /*! Asynchronous PLL enabled as I2CC clock source */ + DL_I2CC_CLOCK_ASYNC_PLL = UNICOMMI2CC_CLKSEL_ASYNC_PLL_SEL_ENABLE, +} DL_I2CC_CLOCK; + +/** @enum DL_I2CC_CLOCK_DIVIDE */ +typedef enum { + /*! I2CC Clock Divided by 1 */ + DL_I2CC_CLOCK_DIVIDE_1 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_1, + /*! I2CC Clock Divided by 2 */ + DL_I2CC_CLOCK_DIVIDE_2 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_2, + /*! I2CC Clock Divided by 3 */ + DL_I2CC_CLOCK_DIVIDE_3 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_3, + /*! I2CC Clock Divided by 4 */ + DL_I2CC_CLOCK_DIVIDE_4 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_4, + /*! I2CC Clock Divided by 5 */ + DL_I2CC_CLOCK_DIVIDE_5 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_5, + /*! I2CC Clock Divided by 6 */ + DL_I2CC_CLOCK_DIVIDE_6 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_6, + /*! I2CC Clock Divided by 7 */ + DL_I2CC_CLOCK_DIVIDE_7 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_7, + /*! I2CC Clock Divided by 8 */ + DL_I2CC_CLOCK_DIVIDE_8 = UNICOMMI2CC_CLKDIV_RATIO_DIV_BY_8, +} DL_I2CC_CLOCK_DIVIDE; + +/** @enum DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH */ +typedef enum { + /*! Pulses filtering disabled. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_DISABLED = + UNICOMMI2CC_GFCTL_DGFSEL_DISABLED, + /*! Pulses shorter than 1 functional clock tick in length are filtered. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_1 = + UNICOMMI2CC_GFCTL_DGFSEL_CLK_1, + /*! Pulses shorter than 2 functional clock ticks in length are filtered. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_2 = + UNICOMMI2CC_GFCTL_DGFSEL_CLK_2, + /*! Pulses shorter than 3 functional clock ticks in length are filtered. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_3 = + UNICOMMI2CC_GFCTL_DGFSEL_CLK_3, + /*! Pulses shorter than 4 functional clock ticks in length are filtered. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_4 = + UNICOMMI2CC_GFCTL_DGFSEL_CLK_4, + /*! Pulses shorter than 8 functional clock ticks in length are filtered. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_8 = + UNICOMMI2CC_GFCTL_DGFSEL_CLK_8, + /*! Pulses shorter than 16 functional clock ticks in length are filtered. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_16 = + UNICOMMI2CC_GFCTL_DGFSEL_CLK_16, + /*! Pulses shorter than 31 functional clock ticks in length are filtered. */ + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_31 = + UNICOMMI2CC_GFCTL_DGFSEL_CLK_31, +} DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH; + +/** @enum DL_I2CC_DIRECTION */ +typedef enum { + /*! Set direction to transmitting to target */ + DL_I2CC_DIRECTION_TX = UNICOMMI2CC_TA_DIR_TRANSMIT, + /*! Set direction to receiving from target */ + DL_I2CC_DIRECTION_RX = UNICOMMI2CC_TA_DIR_RECEIVE, +} DL_I2CC_DIRECTION; + +/** @enum DL_I2CC_ADDRESSING_MODE */ +typedef enum { + /*! Enable in 7-bit addressing mode */ + DL_I2CC_ADDRESSING_MODE_7_BIT = UNICOMMI2CC_TA_MODE_MODE7, + /*! Enable in 10-bit addressing mode */ + DL_I2CC_ADDRESSING_MODE_10_BIT = UNICOMMI2CC_TA_MODE_MODE10, +} DL_I2CC_ADDRESSING_MODE; + +/** @enum DL_I2CC_PEC_STATUS */ +typedef enum { + /*! I2CC SMBus/PMBus PEC was checked in the transaction that + * occurred before the last Stop */ + DL_I2CC_PEC_STATUS_CHECKED = UNICOMMI2CC_PECSR_PECSTS_CHECK_SET, + /*! I2CC SMBus/PMBus PEC was not checked in the transaction that + * occurred the last Stop */ + DL_I2CC_PEC_STATUS_NOT_CHECKED = UNICOMMI2CC_PECSR_PECSTS_CHECK_CLEARED, +} DL_I2CC_PEC_STATUS; + +/** @enum DL_I2CC_PEC_CHECK_ERROR */ +typedef enum { + /*! I2CC SMBus/PMBus PEC check error occurred in the transaction + * before the last stop */ + DL_I2CC_PEC_CHECK_ERROR_SET = UNICOMMI2CC_PECSR_PECSTS_ERROR_SET, + /*! I2CC SMBus/PMBus PEC check error did not occur in the + * transaction before the last stop */ + DL_I2CC_PEC_CHECK_ERROR_CLEARED = UNICOMMI2CC_PECSR_PECSTS_ERROR_CLEARED, +} DL_I2CC_PEC_CHECK_ERROR; + +/** @enum DL_I2CC_SCL */ +typedef enum { + /*! I2CC SCL signal high */ + DL_I2CC_SCL_HIGH = UNICOMMI2CC_BMON_SCL_SET, + /*! I2CC SCL signal low */ + DL_I2CC_SCL_LOW = UNICOMMI2CC_BMON_SCL_CLEARED, +} DL_I2CC_SCL; + +/** @enum DL_I2CC_SDA */ +typedef enum { + /*! I2CC SDA signal high */ + DL_I2CC_SDA_HIGH = UNICOMMI2CC_BMON_SDA_SET, + /*! I2CC SDA signal low */ + DL_I2CC_SDA_LOW = UNICOMMI2CC_BMON_SDA_CLEARED, +} DL_I2CC_SDA; + +/** @enum DL_I2CC_START */ +typedef enum { + /*! generates START condition */ + DL_I2CC_START_ENABLE = UNICOMMI2CC_CTR_START_ENABLE, + /*! doesn't generate START condition */ + DL_I2CC_START_DISABLE = UNICOMMI2CC_CTR_START_DISABLE, +} DL_I2CC_START; + +/** @enum DL_I2CC_STOP */ +typedef enum { + /*! generates STOP condition */ + DL_I2CC_STOP_ENABLE = UNICOMMI2CC_CTR_STOP_ENABLE, + /*! doesn't generate STOP condition */ + DL_I2CC_STOP_DISABLE = UNICOMMI2CC_CTR_STOP_DISABLE, +} DL_I2CC_STOP; + +/** @enum DL_I2CC_ACK */ +typedef enum { + /*! Last received data byte of a transaction is not ACKed automatically */ + DL_I2CC_ACK_ENABLE = UNICOMMI2CC_CTR_ACK_ENABLE, + /*! Last received data byte of a transaction is ACKed automatically */ + DL_I2CC_ACK_DISABLE = UNICOMMI2CC_CTR_ACK_DISABLE, +} DL_I2CC_ACK; + +/** @enum DL_I2CC_TX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when FIFO <= 3/4 empty */ + DL_I2CC_TX_FIFO_LEVEL_3_4_EMPTY = UNICOMMI2CC_IFLS_TXIFLSEL_LVL_3_4, + /*! Interrupt triggers when FIFO <= 1/2 empty */ + DL_I2CC_TX_FIFO_LEVEL_1_2_EMPTY = UNICOMMI2CC_IFLS_TXIFLSEL_LVL_1_2, + /*! Interrupt triggers when FIFO <= 1/4 empty */ + DL_I2CC_TX_FIFO_LEVEL_1_4_EMPTY = UNICOMMI2CC_IFLS_TXIFLSEL_LVL_1_4, + /*! Interrupt triggers when FIFO is not full */ + DL_I2CC_TX_FIFO_LEVEL_ONE_ENTRY = UNICOMMI2CC_IFLS_TXIFLSEL_LVL_NOT_FULL, + /*! Interrupt triggers when FIFO is empty */ + DL_I2CC_TX_FIFO_LEVEL_EMPTY = UNICOMMI2CC_IFLS_TXIFLSEL_LVL_EMPTY, + /*! Interrupt triggers when FIFO is almost empty (FIFO <= 1) */ + DL_I2CC_TX_FIFO_LEVEL_ALMOST_EMPTY = + UNICOMMI2CC_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY, + /*! Interrupt triggers when FIFO is almost full (FIFO >= (MAX_FIFO_LEN - 1)) */ + DL_I2CC_TX_FIFO_LEVEL_ALMOST_FULL = + UNICOMMI2CC_IFLS_TXIFLSEL_LVL_ALMOST_FULL +} DL_I2CC_TX_FIFO_LEVEL; + +/** @enum DL_I2CC_RX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when FIFO >= 3/4 full */ + DL_I2CC_RX_FIFO_LEVEL_3_4_FULL = UNICOMMI2CC_IFLS_RXIFLSEL_LVL_3_4, + /*! Interrupt triggers when FIFO >= 1/2 full */ + DL_I2CC_RX_FIFO_LEVEL_1_2_FULL = UNICOMMI2CC_IFLS_RXIFLSEL_LVL_1_2, + /*! Interrupt triggers when FIFO >= 1/4 full */ + DL_I2CC_RX_FIFO_LEVEL_1_4_FULL = UNICOMMI2CC_IFLS_RXIFLSEL_LVL_1_4, + /*! Interrupt triggers when FIFO is not empty */ + DL_I2CC_RX_FIFO_LEVEL_ONE_ENTRY = UNICOMMI2CC_IFLS_RXIFLSEL_LVL_NOT_EMPTY, + /*! Interrupt triggers when FIFO is full */ + DL_I2CC_RX_FIFO_LEVEL_FULL = UNICOMMI2CC_IFLS_RXIFLSEL_LVL_FULL, + /*! Interrupt triggers when FIFO is almost full (FIFO >= (MAX_FIFO_LEN - 1)) */ + DL_I2CC_RX_FIFO_LEVEL_ALMOST_FULL = + UNICOMMI2CC_IFLS_RXIFLSEL_LVL_ALMOST_FULL, + /*! Interrupt triggers when FIFO is almost empty (FIFO <= 1) */ + DL_I2CC_RX_FIFO_LEVEL_ALMOST_EMPTY = + UNICOMMI2CC_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY, +} DL_I2CC_RX_FIFO_LEVEL; + +/*! @enum DL_I2CC_IIDX */ +typedef enum { + /*! Interrupt index for I2CC if no interrupt is pending */ + DL_I2CC_IIDX_NO_INT = UNICOMMI2CC_IIDX_STAT_NO_INTR, + /*! Interrupt index for I2CC Receive Transaction completed */ + DL_I2CC_IIDX_RX_DONE = UNICOMMI2CC_IIDX_STAT_RXDONEFG, + /*! Interrupt index for Transmit Transaction completed */ + DL_I2CC_IIDX_TX_DONE = UNICOMMI2CC_IIDX_STAT_TXDONEFG, + /*! Interrupt index for I2CC Receive FIFO Trigger */ + DL_I2CC_IIDX_RXFIFO_TRIGGER = UNICOMMI2CC_IIDX_STAT_RXTRG, + /*! Interrupt index for I2CC Transmit FIFO Trigger */ + DL_I2CC_IIDX_TXFIFO_TRIGGER = UNICOMMI2CC_IIDX_STAT_TXTRG, + /*! Interrupt index for I2CC Receive when FIFO is full */ + DL_I2CC_IIDX_RXFIFO_FULL = UNICOMMI2CC_IIDX_STAT_RXFULL, + /*! Interrupt index for I2CC when Transmit FIFO is empty */ + DL_I2CC_IIDX_TXFIFO_EMPTY = UNICOMMI2CC_IIDX_STAT_TXEMPTY, + /*! Interrupt index for Address/Data NACK */ + DL_I2CC_IIDX_NACK = UNICOMMI2CC_IIDX_STAT_NACKFG, + /*! Interrupt index for I2CC START Detection */ + DL_I2CC_IIDX_START = UNICOMMI2CC_IIDX_STAT_STARTFG, + /*! Interrupt index for I2CC STOP Detection */ + DL_I2CC_IIDX_STOP = UNICOMMI2CC_IIDX_STAT_STOPFG, + /*! Interrupt index for I2CC Arbitration Lost */ + DL_I2CC_IIDX_ARBITRATION_LOST = UNICOMMI2CC_IIDX_STAT_ARBLOSTFG, + /*! Interrupt index for I2CC Event 1 DMA Done */ + DL_I2CC_IIDX_EVENT1_DMA_DONE = UNICOMMI2CC_IIDX_STAT_DMA_DONE_TX, + /*! Interrupt index for I2CC Event 2 DMA Done */ + DL_I2CC_IIDX_EVENT2_DMA_DONE = UNICOMMI2CC_IIDX_STAT_DMA_DONE_RX, + /*! Interrupt index for I2CC receive pre-emptive interrupt */ + DL_I2CC_IIDX_PREEMPT_INT_TX = UNICOMMI2CC_IIDX_STAT_DMA_PREIRQ_TX, + /*! Interrupt index for I2CC receive pre-emptive interrupt */ + DL_I2CC_IIDX_PREEMPT_INT_RX = UNICOMMI2CC_IIDX_STAT_DMA_PREIRQ_RX, + /*! Interrupt index for I2CC SMBus/PMBus PEC Receive Error Event */ + DL_I2CC_IIDX_PEC_RX_ERROR = UNICOMMI2CC_IIDX_STAT_PEC_RX_ERR, + /*! Interrupt index for I2CC Timeout A Event */ + DL_I2CC_IIDX_TIMEOUT_A = UNICOMMI2CC_IIDX_STAT_TIMEOUTA, + /*! Interrupt index for I2CC Timeout B Event */ + DL_I2CC_IIDX_TIMEOUT_B = UNICOMMI2CC_IIDX_STAT_TIMEOUTB, +} DL_I2CC_IIDX; + +/** + * @brief Configuration struct for @ref DL_I2CC_setClockConfig. + */ +typedef struct { + /*! I2CC module clock source. One of @ref DL_I2CC_CLOCK */ + DL_I2CC_CLOCK clockSel; + /*! I2CC clock divider selection. One of @ref DL_I2CC_CLOCK_DIVIDE */ + DL_I2CC_CLOCK_DIVIDE divideRatio; +} DL_I2CC_ClockConfig; + +/** + * @brief Configure I2CC source clock + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_I2CC_ClockConfig. + */ +void DL_I2CC_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_ClockConfig *config); + +/** + * @brief Get I2CC source clock configuration + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_I2CC_ClockConfig. + */ +void DL_I2CC_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_ClockConfig *config); + +/** + * @brief Fills the TX FIFO with data + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] buffer Pointer to buffer of bytes + * @param[in] count Number of bytes to fill TX FIFO from buffer + * [0x00, 0xFFF] + * + * @return Number of bytes that were successfully written + */ +uint16_t DL_I2CC_fillTXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint16_t count); + +/** + * @brief Flushes/removes all elements in the TX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +void DL_I2CC_flushTXFIFO(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Flushes/removes all elements in the RX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +void DL_I2CC_flushRXFIFO(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Stop TX FIFO flush + * + * Before stopping the flush, check if @ref DL_I2CC_isTXFIFOEmpty, + * indicating flush is complete. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_stopFlushTXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->IFLS &= ~(UNICOMMI2CC_IFLS_TXCLR_MASK); +} + +/** + * @brief Start TX FIFO flush + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_startFlushTXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->IFLS |= UNICOMMI2CC_IFLS_TXCLR_MASK; +} + +/** + * @brief Stop RX FIFO flush + * + * Before stopping the flush, check if @ref DL_I2CC_isRXFIFOEmpty, + * indicating flush is complete. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_stopFlushRXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->IFLS &= ~(UNICOMMI2CC_IFLS_RXCLR_MASK); +} + +/** + * @brief Start RX FIFO flush + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_startFlushRXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->IFLS |= UNICOMMI2CC_IFLS_RXCLR_MASK; +} + +/** + * @brief Checks if TX FIFO is full + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If TX FIFO is full + * + * @retval true if TX FIFO is full + * @retval false if TX FIFO is not full + */ +__STATIC_INLINE bool DL_I2CC_isTXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->SR & UNICOMMI2CC_SR_TXFF_MASK) == + UNICOMMI2CC_SR_TXFF_SET); +} + +/** + * @brief Checks if TX FIFO is empty + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If TX FIFO is empty + * + * @retval true if TX FIFO is empty + * @retval false if TX FIFO is not empty + */ +__STATIC_INLINE bool DL_I2CC_isTXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->SR & UNICOMMI2CC_SR_TXFE_MASK) == + UNICOMMI2CC_SR_TXFE_SET); +} + +/** + * @brief Checks if RX FIFO is full + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If RX FIFO is full + * + * @retval true if RX FIFO is full + * @retval false if RX FIFO is not full + */ +__STATIC_INLINE bool DL_I2CC_isRXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->SR & UNICOMMI2CC_SR_RXFF_MASK) == + UNICOMMI2CC_SR_RXFF_SET); +} + +/** + * @brief Checks if RX FIFO is empty + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If RX FIFO is empty + * + * @retval true if RX FIFO is empty + * @retval false if RX FIFO is not empty + */ +__STATIC_INLINE bool DL_I2CC_isRXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->SR & UNICOMMI2CC_SR_RXFE_MASK) == + UNICOMMI2CC_SR_RXFE_SET); +} + +/** + * @brief Reset transfers from from UNICOMMI2CC + * + * Resets transfer register to initialize UNICOMMI2CC + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_resetTransfer(UNICOMM_Inst_Regs *unicomm) +{ + // Resets all functionality + unicomm->i2cc->CTR = 0x00; +} + +/** + * @brief Sets up a transfer from UNICOMMI2CC + * + * Set target address, transfer direction, burst length, START+STOP generation. + * @note Reading/writing data must be done separately. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] targetAddr Target address [0x00, 0x3FF] + * @param[in] direction One of @ref DL_I2CC_DIRECTION + * @param[in] length Intended burst length in number of bytes + * [0x00, 0xFFF] + */ +__STATIC_INLINE void DL_I2CC_startTransfer(UNICOMM_Inst_Regs *unicomm, + uint32_t targetAddr, DL_I2CC_DIRECTION direction, uint16_t length) +{ + // Specify target address and read/write mode + DL_Common_updateReg(&unicomm->i2cc->TA, + ((targetAddr << UNICOMMI2CC_TA_ADDR_OFS) | (uint32_t) direction), + (UNICOMMI2CC_TA_ADDR_MASK | UNICOMMI2CC_TA_DIR_MASK)); + + // STOP bit is generated after burst length number of bytes transferred + DL_Common_updateReg(&unicomm->i2cc->CTR, + (((uint32_t) length << UNICOMMI2CC_CTR_BLEN_OFS) | + UNICOMMI2CC_CTR_FRM_START_ENABLE | UNICOMMI2CC_CTR_START_ENABLE | + UNICOMMI2CC_CTR_STOP_ENABLE), + (UNICOMMI2CC_CTR_BLEN_MASK | UNICOMMI2CC_CTR_FRM_START_MASK | + UNICOMMI2CC_CTR_START_MASK | UNICOMMI2CC_CTR_STOP_MASK)); +} + +/** + * @brief Sets up a transfer from I2CC with control of START, + * STOP and ACK + * + * @note Reading/writing data must be done separately. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] targetAddr 7-bit target address [0x00, 0x7f] + * @param[in] direction One of @ref DL_I2CC_DIRECTION + * @param[in] length Intended burst length in number of bytes + * @param[in] start One of @ref DL_I2CC_START + * @param[in] stop One of @ref DL_I2CC_STOP + * @param[in] ack One of @ref DL_I2CC_ACK + */ +__STATIC_INLINE void DL_I2CC_startTransferAdvanced(UNICOMM_Inst_Regs *unicomm, + uint32_t targetAddr, DL_I2CC_DIRECTION direction, uint16_t length, + DL_I2CC_START start, DL_I2CC_STOP stop, DL_I2CC_ACK ack) +{ + // Specify target address and read/write mode + DL_Common_updateReg(&unicomm->i2cc->TA, + ((targetAddr << UNICOMMI2CC_TA_ADDR_OFS) | (uint32_t) direction), + (UNICOMMI2CC_TA_ADDR_MASK | UNICOMMI2CC_TA_DIR_MASK)); + + DL_Common_updateReg(&unicomm->i2cc->CTR, + (((uint32_t) length << UNICOMMI2CC_CTR_BLEN_OFS) | + UNICOMMI2CC_CTR_FRM_START_ENABLE | (uint32_t) start | + (uint32_t) stop | (uint32_t) ack), + (UNICOMMI2CC_CTR_BLEN_MASK | UNICOMMI2CC_INTCTL_INTEVAL_MASK | + UNICOMMI2CC_CTR_START_MASK | UNICOMMI2CC_CTR_STOP_MASK | + UNICOMMI2CC_CTR_ACK_MASK)); +} + +/** + * @brief Enables power on UNICOMM I2C module + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_enablePower(unicomm); + if (unicomm->fixedMode == false) { + DL_UNICOMM_setIPMode(unicomm, DL_UNICOMM_I2C_CONTROLLER); + } +} + +/** + * @brief Disables power on UNICOMM I2C module + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_disablePower(unicomm); +} + +/** + * @brief Returns if power on UNICOMM I2C module + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return true if power is enabled + * @return false if power is disabled + */ +__STATIC_INLINE bool DL_I2CC_isPowerEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isPowerEnabled(unicomm); +} + +/** + * @brief Resets UNICOMM I2C peripheral + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_reset(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_reset(unicomm); +} + +/** + * @brief Returns if UNICOMM I2C peripheral was reset + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return true if peripheral was reset + * @return false if peripheral wasn't reset + * + */ +__STATIC_INLINE bool DL_I2CC_isReset(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isReset(unicomm); +} + +/** + * @brief Set Clock Source + * + * Clock sources depend on device and clock should be enabled + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] clockSource One of @ref DL_I2CC_CLOCK. + * + */ +__STATIC_INLINE void DL_I2CC_selectClockSource( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_CLOCK clockSource) +{ + DL_Common_updateReg(&unicomm->i2cc->CLKSEL, (uint32_t) clockSource, + UNICOMMI2CC_CLKSEL_BUSCLK_SEL_MASK | + UNICOMMI2CC_CLKSEL_MFCLK_SEL_MASK); +} + +/** + * @brief Set Clock Divider + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] clockDivider One of @ref DL_I2CC_CLOCK_DIVIDE. + * + */ +__STATIC_INLINE void DL_I2CC_selectClockDivider( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_CLOCK_DIVIDE clockDivider) +{ + DL_Common_updateReg(&unicomm->i2cc->CLKDIV, (uint32_t) clockDivider, + UNICOMMI2CC_CLKDIV_RATIO_MASK); +} + +/** + * @brief Get Digital Glitch Suppression Pulse Width + * + * Pulse width for the digital glitch suppression on SCL/SDA lines. + * Values are in terms of functional clock ticks. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Digital glitch suppression pulse width + * + * @retval One of @ref DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH. + */ +__STATIC_INLINE DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH +DL_I2CC_getDigitalGlitchFilterPulseWidth(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t filterWidth = + unicomm->i2cc->GFCTL & UNICOMMI2CC_GFCTL_DGFSEL_MASK; + + return (DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH)(filterWidth); +} + +/** + * @brief Set Digital Glitch Suppression Pulse Width + * + * Pulse width for the digital glitch suppression on SCL/SDA lines. + * Values are in terms of functional clock ticks. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] filterWidth One of @ref DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH. + */ +__STATIC_INLINE void DL_I2CC_setDigitalGlitchFilterPulseWidth( + UNICOMM_Inst_Regs *unicomm, + DL_I2CC_DIGITAL_GLITCH_FILTER_WIDTH filterWidth) +{ + DL_Common_updateReg(&unicomm->i2cc->GFCTL, (uint32_t) filterWidth, + UNICOMMI2CC_GFCTL_DGFSEL_MASK); +} + +/** + * @brief Disable Analog Glitch Suppression + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableAnalogGlitchFilter( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->GFCTL &= ~(UNICOMMI2CC_GFCTL_AGFEN_MASK); +} + +/** + * @brief Checks if analog glitch suppression is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If analog glitch suppression is enabled + * + * @retval true if analog glitch suppression is enabled + * @retval false if analog glitch suppression is disabled + */ +__STATIC_INLINE bool DL_I2CC_isAnalogGlitchFilterEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->GFCTL & UNICOMMI2CC_GFCTL_AGFEN_MASK) == + UNICOMMI2CC_GFCTL_AGFEN_ENABLE); +} + +/** + * @brief Enable Analog Glitch Suppression + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableAnalogGlitchFilter( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->GFCTL |= UNICOMMI2CC_GFCTL_AGFEN_ENABLE; +} + +/** + * @brief Get direction of next operation + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Direction of next operation + * + * @retval One of @ref DL_I2CC_DIRECTION + */ +__STATIC_INLINE DL_I2CC_DIRECTION DL_I2CC_getDirection( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t direction = unicomm->i2cc->TA & UNICOMMI2CC_TA_DIR_MASK; + + return (DL_I2CC_DIRECTION)(direction); +} + +/** + * @brief Set direction of next operation + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @param[in] direction Direction of next operation. + * One of @ref DL_I2CC_DIRECTION. + */ +__STATIC_INLINE void DL_I2CC_setDirection( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_DIRECTION direction) +{ + DL_Common_updateReg( + &unicomm->i2cc->TA, (uint32_t) direction, UNICOMMI2CC_TA_DIR_MASK); +} + +/** + * @brief Get the address of the target being addressed when configured + * as an UNICOMMI2CC + * + * Specifies bits A9 through A0 of the target address. + * In 7-bit addressing mode as selected by @ref DL_I2CC_setAddressingMode, + * the top 3 bits are don't care. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The target address + * + * @retval [0x00, 0x07FE] + * + * @sa DL_I2CC_setAddressingMode + */ +__STATIC_INLINE uint32_t DL_I2CC_getTargetAddress(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->TA & UNICOMMI2CC_TA_ADDR_MASK) >> + UNICOMMI2CC_TA_ADDR_OFS); +} + +/** + * @brief Set the address of the target being addressed when configured + * as an UNICOMMI2CC + * + * Specifies bits A9 through A0 of the target address. + * In 7-bit addressing mode as selected by @ref DL_I2CC_setAddressingMode, + * the top 3 bits are don't care. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] targetAddress Target address to set [0x00, 0x07FE] + * + * @sa DL_I2CC_setAddressingMode + */ +__STATIC_INLINE void DL_I2CC_setTargetAddress( + UNICOMM_Inst_Regs *unicomm, uint32_t targetAddress) +{ + DL_Common_updateReg(&unicomm->i2cc->TA, + (targetAddress << UNICOMMI2CC_TA_ADDR_OFS), UNICOMMI2CC_TA_ADDR_MASK); +} + +/** + * @brief Get addressing mode + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Addressing mode the is set to + * + * @retval One of @ref DL_I2CC_ADDRESSING_MODE + * + */ +__STATIC_INLINE DL_I2CC_ADDRESSING_MODE DL_I2CC_getAddressingMode( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t mode = unicomm->i2cc->TA & UNICOMMI2CC_TA_MODE_MASK; + + return (DL_I2CC_ADDRESSING_MODE)(mode); +} + +/** + * @brief Set addressing mode between 7-bit and 10-bit mode + * + * Selects the addressing mode between 7-bit and 10-bit mode to be used when + * device is configured as a + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] mode Addressing mode to set the target to. + * One of @ref DL_I2CC_ADDRESSING_MODE. + */ +__STATIC_INLINE void DL_I2CC_setAddressingMode( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_ADDRESSING_MODE mode) +{ + DL_Common_updateReg( + &unicomm->i2cc->TA, (uint32_t) mode, UNICOMMI2CC_TA_MODE_MASK); +} + +/** + * @brief Disable ACK override + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableACKOverride(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR &= ~(UNICOMMI2CC_CTR_ACKOEN_MASK); +} + +/** + * @brief Checks if ACK override is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If ACK override is enabled + * + * @retval true if ACK override is enabled + * @retval false if ACK override is disabled + */ +__STATIC_INLINE bool DL_I2CC_isACKOverrideEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CTR & UNICOMMI2CC_CTR_ACKOEN_MASK) == + UNICOMMI2CC_CTR_ACKOEN_ENABLE); +} + +/** + * @brief Enable ACK override + * + * When enabled and the is receiving data and the number of bytes + * indicated in CTR.MBLEN have been received, the state machine will generate + * an RXDONE interrupt and wait at the start of the ACK for FW to indicate if + * an ACK or NACK should be sent. The ACK or NACK is selected by writing the + * CTR register and setting ACK accordingly. The other fields in this register + * can also be written at this time to continue on with the transaction. If a + * NACK is sent the state machine will automatically send a Stop. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CC_setTransactionLength + */ +__STATIC_INLINE void DL_I2CC_enableACKOverride(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR |= UNICOMMI2CC_CTR_ACKOEN_ENABLE; +} + +/** + * @brief Disable read on TX empty + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableReadOnTXEmpty(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR &= ~(UNICOMMI2CC_CTR_RD_ON_TXEMPTY_MASK); +} + +/** + * @brief Checks if read on TX empty is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If read on TX empty is enabled + * + * @retval true if read on TX empty is enabled + * @retval false if read on TX empty is disabled + */ +__STATIC_INLINE bool DL_I2CC_isReadOnTXEmptyEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CTR & UNICOMMI2CC_CTR_RD_ON_TXEMPTY_MASK) == + UNICOMMI2CC_CTR_RD_ON_TXEMPTY_ENABLE); +} + +/** + * @brief Enable read on TX empty + * + * When enabled, the will transmit all bytes from the TX FIFO + * before continuing with the programmed Burst Run Read. If the DIR is not + * set to Read in the MSA then this bit is ignored. The Start must be set in + * the CTR for proper I2CC protocol. The will first send the Start + * Condition, I2CC Address with R/W bit set to write, before sending the bytes + * in the TX FIFO. When the TX FIFO is empty, the I2CC transaction will + * continue as programmed in MTCR and MSA without sending a Stop Condition. + * This is intended to be used to perform simple I2CC command based reads + * transition that will complete after initiating them without having to get + * an interrupt to turn the bus around. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + */ +__STATIC_INLINE void DL_I2CC_enableReadOnTXEmpty(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR |= UNICOMMI2CC_CTR_RD_ON_TXEMPTY_ENABLE; +} + +/** + * @brief Get the SMBus/PMBus Packet Error Checking (PEC) count value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The value the PEC count is set to + * + * @retval Value between [0x0, 0x01FF] + */ +__STATIC_INLINE uint32_t DL_I2CC_getPECCountValue(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2cc->PECCTL & UNICOMMI2CC_PECCTL_PECCNT_MASK); +} + +/** + * @brief Set the SMBus/PMBus Packet Error Checking (PEC) count value + * + * When this field is non zero, the number of I2CC data bytes are counted. + * Refer to the device TRM for more details. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] count The value to set the PEC count to. + * Value between [0x0, 0x01FF] + */ +__STATIC_INLINE void DL_I2CC_setPECCountValue( + UNICOMM_Inst_Regs *unicomm, uint32_t count) +{ + DL_Common_updateReg( + &unicomm->i2cc->PECCTL, count, UNICOMMI2CC_PECCTL_PECCNT_MASK); +} + +/** + * @brief Disable SMBus/PMBus Packet Error Checking (PEC) + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disablePEC(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->PECCTL &= ~(UNICOMMI2CC_PECCTL_PECEN_MASK); +} + +/** + * @brief Checks if SMBus/PMBus Packet Error Checking (PEC) + * is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If PEC is enabled + * + * @retval true if PEC is enabled + * @retval false if PEC is disabled + */ +__STATIC_INLINE bool DL_I2CC_isPECEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->PECCTL & UNICOMMI2CC_PECCTL_PECEN_MASK) == + UNICOMMI2CC_PECCTL_PECEN_ENABLE); +} + +/** + * @brief Enable SMBus/PMBus Packet Error Checking (PEC) + * + * When enabled, the PEC is calculated on all bits accept the Start, Stop, ACK + * and NACK. The PEC LSFR and the Byte Counter is set to 0 when the State + * Machine is in the IDLE state, which occurs following a Stop or when a + * timeout occurs. The Counter is also set to 0 after the PEC byte is sent or + * received. Note that the NACK is automatically sent following a PEC byte + * that results in a PEC error. + * The PEC Polynomial is x^8 + x^2 + x^1 + 1. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + */ +__STATIC_INLINE void DL_I2CC_enablePEC(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->PECCTL |= UNICOMMI2CC_PECCTL_PECEN_ENABLE; +} + +/** + * @brief Get the current SMBus/PMBus PEC byte count of the + * state machine + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The current PEC byte count of the state machine + * + * @retval Value between [0x0, 0x01FF] + */ +__STATIC_INLINE uint32_t DL_I2CC_getCurrentPECCount(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2cc->PECSR & UNICOMMI2CC_PECSR_PECSTS_CHECK_MASK); +} + +/** + * @brief If SMBus/PMBus PEC was checked in last transaction + * + * The status of if the PEC was checked in the transaction that + * occurred before the last Stop. Latched on Stop. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of PEC checked in last transaction + * + * @retval One of @ref DL_I2CC_PEC_STATUS + */ +__STATIC_INLINE DL_I2CC_PEC_STATUS DL_I2CC_getPECCheckedStatus( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t status = + unicomm->i2cc->PECSR & UNICOMMI2CC_PECSR_PECSTS_CHECK_MASK; + + return (DL_I2CC_PEC_STATUS)(status); +} + +/** + * @brief Get the status of the SMBus/PMBus PEC Check error + * + * The status of if a PEC check error occurred in the transaction that + * occurred before the last Stop. Latched on Stop. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of PEC check error + * + * @retval One of @ref DL_I2CC_PEC_CHECK_ERROR + */ +__STATIC_INLINE DL_I2CC_PEC_CHECK_ERROR DL_I2CC_getPECCheckError( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t error = + unicomm->i2cc->PECSR & UNICOMMI2CC_PECSR_PECSTS_ERROR_MASK; + + return (DL_I2CC_PEC_CHECK_ERROR)(error); +} + +/** + * @brief Disable I2CC START generation + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableStartCondition(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR &= ~(UNICOMMI2CC_CTR_START_MASK); +} + +/** + * @brief Checks if I2CC START generation is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If I2CC START generation is enabled + * + * @retval true if I2CC START generation is enabled + * @retval false if I2CC START generation is disabled + */ +__STATIC_INLINE bool DL_I2CC_isStartConditionEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CTR & UNICOMMI2CC_CTR_START_MASK) == + UNICOMMI2CC_CTR_START_ENABLE); +} + +/** + * @brief Enable I2CC START generation + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableStartCondition(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR |= UNICOMMI2CC_CTR_START_ENABLE; +} + +/** + * @brief Disable I2CC STOP generation + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableStopCondition(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR &= ~(UNICOMMI2CC_CTR_STOP_MASK); +} + +/** + * @brief Checks if I2CC STOP generation is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If I2CC STOP generation is enabled + * + * @retval true if I2CC STOP generation is enabled + * @retval false if I2CC STOP generation is disabled + */ +__STATIC_INLINE bool DL_I2CC_isStopConditionEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CTR & UNICOMMI2CC_CTR_STOP_MASK) == + UNICOMMI2CC_CTR_STOP_ENABLE); +} + +/** + * @brief Enable I2CC STOP generation + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableStopCondition(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR |= UNICOMMI2CC_CTR_STOP_ENABLE; +} + +/** + * @brief Disable I2CC data acknowledge (ACK or NACK) + * + * When the I2CC module operates in receiver mode, the ACK bit can be + * cleared when no further data needs to be received from the target + * transmitter. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableACK(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR &= ~(UNICOMMI2CC_CTR_ACK_MASK); +} + +/** + * @brief Checks if I2CC data acknowledge (ACK or NACK) is + * enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If I2CC data acknowledge is enabled + * + * @retval true if I2CC data acknowledge is enabled + * @retval false if I2CC data acknowledge is disabled + */ +__STATIC_INLINE bool DL_I2CC_isACKEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CTR & UNICOMMI2CC_CTR_ACK_MASK) == + UNICOMMI2CC_CTR_ACK_ENABLE); +} + +/** + * @brief Enable I2CC data acknowledge (ACK or NACK) + * + * When the I2CC module operates in receiver mode, the ACK bit is + * normally set causing the I2CC bus to transmit an acknowledge + * automatically after each byte. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableACK(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CTR |= UNICOMMI2CC_CTR_ACK_MASK; +} + +/** + * @brief Get transaction length in bytes + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Length of I2CC transaction in bytes + * + * @retval [0x000, 0xfff] + */ +__STATIC_INLINE uint32_t DL_I2CC_getTransactionLength( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CTR & UNICOMMI2CC_CTR_BLEN_MASK) >> + UNICOMMI2CC_CTR_BLEN_OFS); +} + +/** + * @brief Set transaction length in bytes + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @param[in] length Length of I2CC transaction in bytes [0x000, 0xfff] + */ +__STATIC_INLINE void DL_I2CC_setTransactionLength( + UNICOMM_Inst_Regs *unicomm, uint32_t length) +{ + DL_Common_updateReg(&unicomm->i2cc->CTR, + (length << UNICOMMI2CC_CTR_BLEN_OFS), UNICOMMI2CC_CTR_BLEN_MASK); +} + +/** + * @brief Get status of I2CC bus for + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of I2CC bus for + * + * @retval Bitwise OR of @ref DL_I2CC_STATUS + */ +__STATIC_INLINE uint32_t DL_I2CC_getStatus(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2cc->SR); +} + +/** + * @brief Get transaction count in bytes + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Current 12-bit countdown value of the transaction + * + * @retval [0x000, 0xfff] + */ +__STATIC_INLINE uint16_t DL_I2CC_getTransactionCount( + UNICOMM_Inst_Regs *unicomm) +{ + return ((uint16_t)((unicomm->i2cc->SR & UNICOMMI2CC_SR_BCNT_MASK) >> + UNICOMMI2CC_SR_BCNT_OFS)); +} + +/** + * @brief Get byte of data from UNICOMMI2CC + * + * If using FIFO, it is first byte from the RX FIFO. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Last received byte of data + * + * @retval [0x00, 0xff] + */ +__STATIC_INLINE uint8_t DL_I2CC_receiveData(UNICOMM_Inst_Regs *unicomm) +{ + return ((uint8_t)(unicomm->i2cc->RXDATA & UNICOMMI2CC_RXDATA_DATA_MASK)); +} + +/** + * @brief Set next byte to be transferred during the next transaction + * + * Does not transmit data until @ref DL_I2CC_startTransfer + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] data Data to be transferred during the next transaction. + * [0x00, 0xff] + */ +__STATIC_INLINE void DL_I2CC_transmitData( + UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + unicomm->i2cc->TXDATA = data; +} + +/** + * @brief Get timer period + * This field is used in the equation to configure SCL_PERIOD: + * + * SCL_PERIOD = (1 + TPR) * (SCL_LP + SCL_HP) * INT_CLK_PRD + * + * where: + * SCL_PRD is the SCL line period (I2CC clock) + * + * TPR is the Timer Period register value (range of 1 to 127) + * + * SCL_LP is the SCL Low period (fixed at 6) + * SCL_HP is the SCL High period (fixed at 4) + * + * CLK_PRD is the functional clock period in ns + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @return Timer period + * + * @retval [0x00, 0x7f] + */ +__STATIC_INLINE uint8_t DL_I2CC_getTimerPeriod(UNICOMM_Inst_Regs *unicomm) +{ + return ((uint8_t)(unicomm->i2cc->TPR & UNICOMMI2CC_TPR_TPR_MASK)); +} + +/** + * @brief Set timer period + * This field is used in the equation to configure SCL_PERIOD: + * + * SCL_PERIOD = (1 + TPR) * (SCL_LP + SCL_HP) * INT_CLK_PRD + * + * where: + * SCL_PRD is the SCL line period (I2CC clock) + * + * TPR is the Timer Period register value (range of 1 to 127) + * + * SCL_LP is the SCL Low period (fixed at 6) + * SCL_HP is the SCL High period (fixed at 4) + * + * CLK_PRD is the functional clock period in ns + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] period Timer period [0x00, 0x7f] + */ +__STATIC_INLINE void DL_I2CC_setTimerPeriod( + UNICOMM_Inst_Regs *unicomm, uint8_t period) +{ + unicomm->i2cc->TPR = period; +} + +/** + * @brief Disable multimode + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableMultiMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CR &= ~(UNICOMMI2CC_CR_MCTL_MASK); +} + +/** + * @brief Checks if multimode is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If multimode is enabled + * + * @retval true if multimode is enabled + * @retval false if multimode is disabled + */ +__STATIC_INLINE bool DL_I2CC_isMultiModeEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CR & UNICOMMI2CC_CR_MCTL_MASK) == + UNICOMMI2CC_CR_MCTL_ENABLE); +} + +/** + * @brief Enable multimode + * + * In multimode, the SCL high time counts once the SCL line has been + * detected high. If this is not enabled, the high time counts as soon as the + * SCL line has been set high by the UNICOMMI2CC + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableMultiMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CR |= UNICOMMI2CC_CR_MCTL_ENABLE; +} + +/** + * @brief Disable controller + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CR &= ~(UNICOMMI2CC_CR_ENABLE_MASK); +} + +/** + * @brief Checks if controller is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If is enabled + * + * @retval true if is enabled + * @retval false if is disabled + */ +__STATIC_INLINE bool DL_I2CC_isEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CR & UNICOMMI2CC_CR_ENABLE_MASK) == + UNICOMMI2CC_CR_ENABLE_ENABLE); +} + +/** + * @brief Enable controller + * + * After has enabled, it should not be re-enabled unless it has been + * disabled or by a reset, otherwise transfer failures may occur. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CR |= UNICOMMI2CC_CR_ENABLE_ENABLE; +} + +/** + * @brief Disable clock stretching + * + * Clock stretching can be disabled if no target on the bus supports clock + * stretching; however, it should be typically enabled to be compliant with + * I2CC specification. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableClockStretching(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CR &= ~(UNICOMMI2CC_CR_CLKSTRETCH_MASK); +} + +/** + * @brief Checks if clock stretching is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If clock stretching is enabled + * + * @retval true if clock stretching is enabled + * @retval false if clock stretching is disabled + */ +__STATIC_INLINE bool DL_I2CC_isClockStretchingEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->CR & UNICOMMI2CC_CR_CLKSTRETCH_MASK) == + UNICOMMI2CC_CR_CLKSTRETCH_ENABLE); +} + +/** + * @brief Enable clock stretching + * + * Clock stretching can be disabled if no target on the bus supports clock + * stretching; however, it should be typically enabled to be compliant with UNICOMMI2CC + * specification. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableClockStretching(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->CR |= UNICOMMI2CC_CR_CLKSTRETCH_ENABLE; +} + +/** + * @brief Get SCL signal status + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of SCL signal + * + * @retval One of @ref DL_I2CC_SCL + */ +__STATIC_INLINE DL_I2CC_SCL DL_I2CC_getSCLStatus(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t sclStatus = unicomm->i2cc->BMON & UNICOMMI2CC_BMON_SCL_MASK; + + return (DL_I2CC_SCL)(sclStatus); +} + +/** + * @brief Get SDA signal status + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of SDA signal + * + * @retval One of @ref DL_I2CC_SDA + */ +__STATIC_INLINE DL_I2CC_SDA DL_I2CC_getSDAStatus(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t sdaStatus = unicomm->i2cc->BMON & UNICOMMI2CC_BMON_SDA_MASK; + + return (DL_I2CC_SDA)(sdaStatus); +} + +/** + * @brief Get TX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @return Indicates at what fill level in the TX FIFO a threshold will be + * generated + * + * @retval One of @ref DL_I2CC_TX_FIFO_LEVEL + */ +__STATIC_INLINE DL_I2CC_TX_FIFO_LEVEL DL_I2CC_getTXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t level = unicomm->i2cc->IFLS & UNICOMMI2CC_IFLS_TXIFLSEL_MASK; + + return (DL_I2CC_TX_FIFO_LEVEL)(level); +} + +/** + * @brief Set TX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] level Indicates at what fill level in the TX FIFO a threshold + * will be generated. + * One of @ref DL_I2CC_TX_FIFO_LEVEL. + */ +__STATIC_INLINE void DL_I2CC_setTXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_TX_FIFO_LEVEL level) +{ + DL_Common_updateReg(&unicomm->i2cc->IFLS, (uint32_t) level, + UNICOMMI2CC_IFLS_TXIFLSEL_MASK); +} + +/** + * @brief Get RX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @return Indicates at what fill level in the RX FIFO a threshold will be + * generated + * + * @retval One of @ref DL_I2CC_RX_FIFO_LEVEL + */ +__STATIC_INLINE DL_I2CC_RX_FIFO_LEVEL DL_I2CC_getRXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t level = unicomm->i2cc->IFLS & UNICOMMI2CC_IFLS_RXIFLSEL_MASK; + + return (DL_I2CC_RX_FIFO_LEVEL)(level); +} + +/** + * @brief Set RX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] level Indicates at what fill level in the RX FIFO a threshold + * will be generated. + * One of @ref DL_I2CC_RX_FIFO_LEVEL. + */ +__STATIC_INLINE void DL_I2CC_setRXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_RX_FIFO_LEVEL level) +{ + DL_Common_updateReg(&unicomm->i2cc->IFLS, (uint32_t) level, + UNICOMMI2CC_IFLS_RXIFLSEL_MASK); +} + +/** + * @brief Get number of bytes which can be read from RX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Number of bytes which can be read from RX FIFO + * + * @retval [0x0, 0x8] + */ +__STATIC_INLINE uint32_t DL_I2CC_getRXFIFOCounter(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2cc->SR & UNICOMMI2CC_SR_BCNT_MASK); +} + +/** + * @brief Get number of bytes which can be put into TX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Number of bytes which can be put into TX FIFO + * + * @retval [0x0, 0x8] + */ +__STATIC_INLINE uint32_t DL_I2CC_getTXFIFOCounter(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2cc->SR & UNICOMMI2CC_SR_BCNT_MASK) >> + UNICOMMI2CC_SR_BCNT_OFS); +} + +/** + * @brief Enable I2CC interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_I2CC_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CC_enableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->i2cc->CPU_INT.IMASK |= interruptMask; +} + +/** + * @brief Disable I2CC interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to disable. Bitwise OR of + * @ref DL_I2CC_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CC_disableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->i2cc->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which I2CC interrupts are enabled + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CC_INTERRUPT. + * + * @return Which of the requested I2CC interrupts are enabled + * + * @retval Bitwise OR of @ref DL_I2CC_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2CC_getEnabledInterrupts( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->i2cc->CPU_INT.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled I2CC interrupts + * + * Checks if any of the I2CC interrupts that were previously enabled are + * pending. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CC_INTERRUPT. + * + * @return Which of the requested I2CC interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2CC_INTERRUPT values + * + * @sa DL_I2CC_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_I2CC_getEnabledInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->i2cc->CPU_INT.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any I2CC interrupt + * + * Checks if any of the I2CC interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CC_INTERRUPT. + * + * @return Which of the requested I2CC interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2CC_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2CC_getRawInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->i2cc->CPU_INT.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending I2CC interrupt + * + * Checks if any of the I2CC interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The highest priority pending I2CC interrupt + * + * @retval One of @ref DL_I2CC_IIDX + */ +__STATIC_INLINE DL_I2CC_IIDX DL_I2CC_getPendingInterrupt( + UNICOMM_Inst_Regs *unicomm) +{ + return ((DL_I2CC_IIDX) unicomm->i2cc->CPU_INT.IIDX); +} + +/** + * @brief Clear pending I2CC interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_I2CC_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CC_clearInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->i2cc->CPU_INT.ICLR = interruptMask; +} + +/** + * @brief Enables I2CC interrupt for triggering DMA events + * + * Enables the I2CC interrupt to be used as the condition to generate an + * event to directly trigger the DMA. + * + * Each event publisher @ref DL_I2CC_EVENT_ROUTE can set any one of + * @ref DL_I2CC_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interrupt Interrupt to enable as the trigger condition for + * the DMA. One of @ref DL_I2CC_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CC_enableDMAEvent( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_EVENT_ROUTE index, uint32_t interrupt) +{ + switch (index) { + case DL_I2CC_EVENT_ROUTE_1: + unicomm->i2cc->DMA_TRIG1.IMASK = interrupt; + break; + case DL_I2CC_EVENT_ROUTE_2: + unicomm->i2cc->DMA_TRIG0.IMASK = interrupt; + break; + default: + break; + } +} + +/** + * @brief Disables I2CC interrupt from triggering DMA events + * + * Disables the I2CC interrupt from being used as the condition to generate an + * event to directly trigger the DMA. + * + * Each event publisher @ref DL_I2CC_EVENT_ROUTE can set any one of + * @ref DL_I2CC_DMA_INTERRUPT. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interrupt Interrupt to disable as the trigger condition for + * the DMA. One of @ref DL_I2CC_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CC_disableDMAEvent( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_EVENT_ROUTE index, uint32_t interrupt) +{ + switch (index) { + case DL_I2CC_EVENT_ROUTE_1: + unicomm->i2cc->DMA_TRIG1.IMASK &= ~(interrupt); + break; + case DL_I2CC_EVENT_ROUTE_2: + unicomm->i2cc->DMA_TRIG0.IMASK &= ~(interrupt); + break; + default: + break; + } +} + +/** + * @brief Check which I2CC interrupt for DMA receive events is enabled + * + * This API checks the event publisher register as selected by + * @ref DL_I2CC_EVENT_ROUTE, which are used for triggering the DMA for + * or Target and receive or transmit events. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CC_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2CC interrupt status + * + * @retval One of @ref DL_I2CC_DMA_INTERRUPT + */ +__STATIC_INLINE uint32_t DL_I2CC_getEnabledDMAEvents( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_EVENT_ROUTE index, + uint32_t interruptMask) +{ + volatile uint32_t *pReg = &unicomm->i2cc->DMA_TRIG1.IMASK; + + return ((*(pReg + (uint32_t) index) & interruptMask)); +} + +/** + * @brief Check interrupt flag of enabled I2CC interrupt for DMA event + * + * Checks if any of the I2CC interrupts for the DMA receive event that were + * previously enabled are pending. + * This API checks the event publisher register as selected by + * @ref DL_I2CC_EVENT_ROUTE, which are used for triggering the DMA for + * or Target and receive or transmit events. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CC_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2CC interrupt status + * + * @retval One of @ref DL_I2CC_DMA_INTERRUPT + * + * @sa DL_I2CC_enableDMAEvent + */ +__STATIC_INLINE uint32_t DL_I2CC_getEnabledDMAEventStatus( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_EVENT_ROUTE index, + uint32_t interruptMask) +{ + const volatile uint32_t *pReg = &unicomm->i2cc->DMA_TRIG1.MIS; + + return ((*(pReg + (uint32_t) index) & interruptMask)); +} + +/** + * @brief Check interrupt flag of any I2CC interrupt for DMA event + * + * Checks if any of the I2CC interrupts for DMA receive event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the event publisher register as selected by + * @ref DL_I2CC_EVENT_ROUTE, which are used for triggering the DMA for + * or Target and receive or transmit events. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CC_DMA_INTERRUPT. + * + * @return Which of the requested I2CC interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2CC_DMA_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2CC_getRawDMAEventStatus( + UNICOMM_Inst_Regs *unicomm, DL_I2CC_EVENT_ROUTE index, + uint32_t interruptMask) +{ + const volatile uint32_t *pReg = &unicomm->i2cc->DMA_TRIG1.RIS; + + return ((*(pReg + (uint32_t) index) & interruptMask)); +} + +/** + * @brief Get the Timeout Counter A value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout A counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CC_getTimeoutACount(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2cc->TIMEOUT_CTL & UNICOMMI2CC_TIMEOUT_CTL_TCNTLA_MASK); +} + +/** + * @brief Set the Timeout Counter A value + * + * Timeout A is used for SCL low detection. This field contains the upper 8 + * bits of a 12-bit pre-load value for the Timeout A count. + * NOTE: The value of the counter must be greater than 1 to enable the + * timeout. Each count is equal to 520 times the timeout period of the + * functional clock. For example, with 8MHz functional clock and a + * 100KHz operating I2CC clock, one timeout period will be equal to + * (1 / 8MHz) * 520 = 65us. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] count The value to set the Timeout A counter to. + * Value between [0x0, 0xFF] + */ +__STATIC_INLINE void DL_I2CC_setTimeoutACount( + UNICOMM_Inst_Regs *unicomm, uint32_t count) +{ + DL_Common_updateReg(&unicomm->i2cc->TIMEOUT_CTL, count, + UNICOMMI2CC_TIMEOUT_CTL_TCNTLA_MASK); +} + +/** + * @brief Disable Timeout Counter A + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableTimeoutA(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->TIMEOUT_CTL &= ~(UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_MASK); +} + +/** + * @brief Checks if Timeout Counter A is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If Timeout Counter A is enabled + * + * @retval true if Timeout Counter A is enabled + * @retval false if Timeout Counter A is disabled + */ +__STATIC_INLINE bool DL_I2CC_isTimeoutAEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2cc->TIMEOUT_CTL & UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_MASK) == + UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_ENABLE); +} + +/** + * @brief Enable Timeout Counter A + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableTimeoutA(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->TIMEOUT_CTL |= UNICOMMI2CC_TIMEOUT_CTL_TCNTAEN_ENABLE; +} + +/** + * @brief Get the current Timer Counter A value + * + * This field contains the upper 8 bits of a 12-bit current counter for + * Timeout Counter A. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout A counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CC_getCurrentTimeoutACounter( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2cc->TIMEOUT_CNT & UNICOMMI2CC_TIMEOUT_CNT_TCNTA_MASK); +} + +/** + * @brief Get the Timeout Counter B value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout B counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CC_getTimeoutBCount(UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2cc->TIMEOUT_CTL & UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_MASK) >> + UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_OFS); +} + +/** + * @brief Set the Timeout Counter B value + * + * Timeout B is used for SCL high detection. This field contains the upper 8 + * bits of a 12-bit pre-load value for the Timeout A count. + * NOTE: The value of the counter must be greater than 1 to enable the + * timeout. Each count is equal to 1* clock period. For example, with 10MHz + * functional clock one timeout period will be equal to 1 * 10ns. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] count The value to set the Timeout A counter to. + * Value between [0x0, 0xFF] + */ +__STATIC_INLINE void DL_I2CC_setTimeoutBCount( + UNICOMM_Inst_Regs *unicomm, uint32_t count) +{ + DL_Common_updateReg(&unicomm->i2cc->TIMEOUT_CTL, + (count << UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_OFS), + UNICOMMI2CC_TIMEOUT_CTL_TCNTLB_MASK); +} + +/** + * @brief Disable Timeout Counter B + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_disableTimeoutB(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->TIMEOUT_CTL &= ~(UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_MASK); +} + +/** + * @brief Checks if Timeout Counter B is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If Timeout Counter B is enabled + * + * @retval true if Timeout Counter B is enabled + * @retval false if Timeout Counter B is disabled + */ +__STATIC_INLINE bool DL_I2CC_isTimeoutBEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2cc->TIMEOUT_CTL & UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_MASK) == + UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_ENABLE); +} + +/** + * @brief Enable Timeout Counter B + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CC_enableTimeoutB(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2cc->TIMEOUT_CTL |= UNICOMMI2CC_TIMEOUT_CTL_TCNTBEN_ENABLE; +} + +/** + * @brief Get the current Timer Counter B value + * + * This field contains the upper 8 bits of a 12-bit current counter for + * Timeout Counter B. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout B counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CC_getCurrentTimeoutBCounter( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2cc->TIMEOUT_CNT & UNICOMMI2CC_TIMEOUT_CNT_TCNTB_MASK); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_HAS_UNICOMMI2CC__ */ + +#endif /* ti_dl_dl_unicomm__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_unicommi2ct.c b/mspm0/source/ti/driverlib/dl_unicommi2ct.c new file mode 100644 index 0000000..1fe598a --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommi2ct.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MCU_HAS_UNICOMMI2CT__ + +void DL_I2CT_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_ClockConfig *config) +{ + DL_Common_updateReg(&unicomm->i2ct->CLKSEL, (uint32_t) config->clockSel, + UNICOMMI2CT_CLKSEL_BUSCLK_SEL_MASK | + UNICOMMI2CT_CLKSEL_MFCLK_SEL_MASK); + + DL_Common_updateReg(&unicomm->i2ct->CLKDIV, (uint32_t) config->divideRatio, + UNICOMMI2CT_CLKDIV_RATIO_MASK); +} + +void DL_I2CT_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_ClockConfig *config) +{ + uint32_t clockSel = + unicomm->i2ct->CLKSEL & (UNICOMMI2CT_CLKSEL_BUSCLK_SEL_MASK | + UNICOMMI2CT_CLKSEL_MFCLK_SEL_MASK); + config->clockSel = (DL_I2CT_CLOCK)(clockSel); + + uint32_t divideRatio = + unicomm->i2ct->CLKDIV & UNICOMMI2CT_CLKDIV_RATIO_MASK; + config->divideRatio = (DL_I2CT_CLOCK_DIVIDE)(divideRatio); +} + +uint8_t DL_I2CT_fillTXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint8_t count) +{ + uint8_t i; + for (i = (uint8_t) 0; i < count; i++) { + if (DL_I2CT_isTXFIFOFull(unicomm) == false) { + DL_I2CT_transmitData(unicomm, buffer[i]); + } else { // TX FIFO is full + break; + } + } + return i; +} + +void DL_I2CT_transmitDataBlocking(UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + while ((DL_I2CT_getStatus(unicomm) & DL_I2CT_STATUS_TRANSMIT_REQUEST) != + DL_I2CT_STATUS_TRANSMIT_REQUEST) { + ; + } + DL_I2CT_transmitData(unicomm, data); + while ((DL_I2CT_getStatus(unicomm) & DL_I2CT_STATUS_BUS_BUSY) == + DL_I2CT_STATUS_BUS_BUSY) { + ; + } +} + +bool DL_I2CT_transmitDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + bool status; + if (DL_I2CT_isTXFIFOFull(unicomm)) { + status = false; + } else { + DL_I2CT_transmitData(unicomm, data); + status = true; + } + return status; +} + +uint8_t DL_I2CT_receiveDataBlocking(UNICOMM_Inst_Regs *unicomm) +{ + while ((DL_I2CT_getStatus(unicomm) & DL_I2CT_STATUS_RECEIVE_REQUEST) != + DL_I2CT_STATUS_RECEIVE_REQUEST) { + ; + } + return DL_I2CT_receiveData(unicomm); +} + +bool DL_I2CT_receiveDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t *buffer) +{ + bool status; + if (DL_I2CT_isRXFIFOEmpty(unicomm)) { + status = false; + } else { + *buffer = DL_I2CT_receiveData(unicomm); + status = true; + } + return status; +} + +void DL_I2CT_flushTXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + DL_I2CT_startFlushTXFIFO(unicomm); + while (DL_I2CT_isTXFIFOEmpty(unicomm) == false) { + ; + } + DL_I2CT_stopFlushTXFIFO(unicomm); +} + +void DL_I2CT_flushRXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + DL_I2CT_startFlushRXFIFO(unicomm); + while (DL_I2CT_isRXFIFOEmpty(unicomm) == false) { + ; + } + DL_I2CT_stopFlushRXFIFO(unicomm); +} + +#endif /* __MCU_HAS_UNICOMMI2CT__ */ diff --git a/mspm0/source/ti/driverlib/dl_unicommi2ct.h b/mspm0/source/ti/driverlib/dl_unicommi2ct.h new file mode 100644 index 0000000..9743ac6 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommi2ct.h @@ -0,0 +1,2555 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_unicommi2ct.h + * @brief Unified Communication Module (UNICOMM) - Inter-Integrated Circuit Target (I2CT) Driver Library + * @defgroup UNICOMMI2CT Unified Communication Module (UNICOMM) - Inter-Integrated Circuit Target (I2CT) + * + * @anchor ti_dl_dl_unicommi2ct_Overview + * # Overview + * + * Unified Communication Module Inter-Integrated Circuit Target Driver Library allows + * full configuration of the UNICOMM I2CT module. + * + * This Inter-Integrated Circuit Target (I2CT) module provides a standardized + * interface to transfer data, as a target, between devices and other external + * devices with the I2C interface. + * + *
+ ****************************************************************************** + */ +/** @addtogroup UNICOMMI2CT + * @{ + */ +#ifndef ti_dl_dl_unicommi2ct__include +#define ti_dl_dl_unicommi2ct__include + +#include +#include + +#include +#include +#include + +#ifdef __MCU_HAS_UNICOMMI2CT__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/*! + * @brief I2CT number of bytes which could be put into the TX FIFO + * + * This variable is device specific and is calculated using the system parameter + * UNICOMMI2CT_SYS_FENTRIES defined in each devices header file. +*/ +#define DL_I2CT_TX_FIFO_COUNT_MAXIMUM ((uint32_t)UNICOMMI2CT_SYS_FENTRIES << 8) + +/*! + * @brief I2CT number of bytes which could be put into the RX FIFO + * + * This variable is device specific and is calculated using the system parameter + * UNICOMMI2CT_SYS_FENTRIES defined in each devices header file. +*/ +#define DL_I2CT_RX_FIFO_COUNT_MAXIMUM ((uint32_t)UNICOMMI2CT_SYS_FENTRIES) + +/** @addtogroup DL_I2CT_STATUS + * @{ + */ + +/*! + * @brief Indicates the address for which address match happened + */ +#define DL_I2CT_STATUS_ADDRESS_MATCH (UNICOMMI2CT_SR_ADDRMATCH_MASK) + +/*! + * @brief I2CT Stale TX FIFO + * + * Set = The TX FIFO data is stale. This occurs when the TX FIFO was not + * emptied during the previous I2CT transaction + * Clear = The TX FIFO data is not stale + */ +#define DL_I2CT_STATUS_STALE_TX_FIFO (UNICOMMI2CT_SR_STALE_TXFIFO_MASK) + +/*! + * @brief I2CT TX Mode + * + * Set = is in the TX_DATA, TX_ACK, TX_WAIT, or ADDR_ACK state with the + * bus direction set to read + * Clear = is not in the TX_DATA, TX_ACK, TX_WAIT, or ADDR_ACK state + * with the bus direction set to read + */ +#define DL_I2CT_STATUS_TX_MODE (UNICOMMI2CT_SR_TXMODE_MASK) + +/*! + * @brief I2CT Bus Busy + * + * Set = The I2CT bus is busy. This is cleared on a timeout + * Clear = The I2CT bus is not busy. This bit is cleared when a STOP condition is + * detected on the bus. + */ +#define DL_I2CT_STATUS_BUS_BUSY (UNICOMMI2CT_SR_BUSBSY_MASK) + +/*! + * @brief I2CT RX Mode + * + * Set = is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK + * state with the bus direction set to write + * Clear = is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK + * state with the bus direction set to write + */ +#define DL_I2CT_STATUS_RX_MODE (UNICOMMI2CT_SR_RXMODE_MASK) + + +/*! + * @brief Direction of I2CT Quick Command + * Only valid when QCMDST is set. @sa DL_I2CT_STATUS_QUICK_COMMAND_STATUS. + * Set = Quick command was a read + * Clear = Quick command was a write + */ +#define DL_I2CT_STATUS_QUICK_COMMAND_READ_WRITE (UNICOMMI2CT_SR_QCMDRW_MASK) + +/*! + * @brief Status of I2CT Quick Command + * @sa DL_I2CT_STATUS_QUICK_COMMAND_READ_WRITE. + * Set = Last transaction was a Quick Comand transaction + * Clear = Last transaction was normal or has not occurred + */ +#define DL_I2CT_STATUS_QUICK_COMMAND_STATUS (UNICOMMI2CT_SR_QCMDST_MASK) + +/*! + * @brief I2CT Own Address Alternate Matched + */ +#define DL_I2CT_STATUS_OWN_ADDR_ALTERNATE_MATCHED (UNICOMMI2CT_SR_OAR2SEL_MASK) + +/*! + * @brief I2CT Transmit Request + */ +#define DL_I2CT_STATUS_TRANSMIT_REQUEST (UNICOMMI2CT_SR_TREQ_MASK) + +/*! + * @brief I2CT Receive Request + */ +#define DL_I2CT_STATUS_RECEIVE_REQUEST (UNICOMMI2CT_SR_RREQ_MASK) + +/** @}*/ + +/** @addtogroup DL_I2CT_INTERRUPT + * @{ + */ +/*! + * @brief Receive Data Interrupt (byte has been received) + */ +#define DL_I2CT_INTERRUPT_RX_DONE (UNICOMMI2CT_CPU_INT_IMASK_RXDONE_SET) + +/*! + * @brief Transmit Transaction completed Interrupt + */ +#define DL_I2CT_INTERRUPT_TX_DONE (UNICOMMI2CT_CPU_INT_IMASK_TXDONE_SET) + +/*! + * @brief Receive FIFO Trigger + */ +#define DL_I2CT_INTERRUPT_RXFIFO_TRIGGER \ + (UNICOMMI2CT_CPU_INT_IMASK_RXTRG_SET) + +/*! + * @brief Transmit FIFO Trigger + */ +#define DL_I2CT_INTERRUPT_TXFIFO_TRIGGER \ + (UNICOMMI2CT_CPU_INT_IMASK_TXTRG_SET) + +/*! + * @brief RX FIFO full + */ +#define DL_I2CT_INTERRUPT_RXFIFO_FULL \ + (UNICOMMI2CT_CPU_INT_IMASK_RXFULL_SET) + +/*! + * @brief TX FIFO empty. All data in Transmit FIFO shifted out and + * transmit goes into idle mode. + */ +#define DL_I2CT_INTERRUPT_TXFIFO_EMPTY \ + (UNICOMMI2CT_CPU_INT_IMASK_TXEMPTY_SET) + +/*! + * @brief Start Condition detected + */ +#define DL_I2CT_INTERRUPT_START \ + (UNICOMMI2CT_CPU_INT_IMASK_START_SET) + +/*! + * @brief Stop Condition detected + */ +#define DL_I2CT_INTERRUPT_STOP (UNICOMMI2CT_CPU_INT_IMASK_STOP_SET) + +/*! + * @brief General Call Interrupt + */ +#define DL_I2CT_INTERRUPT_GENERAL_CALL \ + (UNICOMMI2CT_CPU_INT_IMASK_GENCALL_SET) + +/*! + * @brief DMA Done on Event 1 Publisher + */ +#define DL_I2CT_INTERRUPT_EVENT1_DMA_DONE \ + (UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_TX_SET) + +/*! + * @brief DMA Done on Event 2 Publisher + */ +#define DL_I2CT_INTERRUPT_EVENT2_DMA_DONE \ + (UNICOMMI2CT_CPU_INT_IMASK_DMA_DONE_RX_SET) + + +/*! + * @brief SMBus/PMBus PEC Receive Error Interrupt + */ +#define DL_I2CT_INTERRUPT_PEC_RX_ERROR \ + (UNICOMMI2CT_CPU_INT_IMASK_PEC_RX_ERR_SET) + +/*! + * @brief TX FIFO Underflow Interrupt + */ +#define DL_I2CT_INTERRUPT_TXFIFO_UNDERFLOW \ + (UNICOMMI2CT_CPU_INT_IMASK_TX_UNFL_SET) + +/*! + * @brief RX FIFO Overflow Interrupt + */ +#define DL_I2CT_INTERRUPT_RXFIFO_OVERFLOW \ + (UNICOMMI2CT_CPU_INT_IMASK_RX_OVFL_SET) + +/*! + * @brief Arbitration Lost Interrupt + */ +#define DL_I2CT_INTERRUPT_ARBITRATION_LOST \ + (UNICOMMI2CT_CPU_INT_IMASK_ARBLOST_SET) + +/*! + * @brief Interrupt Overflow Interrupt. Occurs when START or STOP + * interrupts overflow (i.e. occurs twice without being serviced) + */ +#define DL_I2CT_INTERRUPT_OVERFLOW (UNICOMMI2CT_CPU_INT_IMASK_RX_OVFL_SET) + +/*! + * @brief Timeout A Interrupt + */ +#define DL_I2CT_INTERRUPT_TIMEOUT_A (UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTA_SET) + +/*! + * @brief Timeout B Interrupt + */ +#define DL_I2CT_INTERRUPT_TIMEOUT_B (UNICOMMI2CT_CPU_INT_IMASK_TIMEOUTB_SET) + + +/** @}*/ + +/** @addtogroup DL_I2CT_DMA_INTERRUPT + * @{ + */ +/*! + * @brief Peripheral Transmit FIFO Trigger interrupt for DMA trigger + */ +#define DL_I2CT_DMA_INTERRUPT_TXFIFO_TRIGGER \ + (UNICOMMI2CT_DMA_TRIG0_IMASK_TXTRG_SET) + +/*! + * @brief Peripheral Receive FIFO Trigger interrupt for DMA trigger + */ +#define DL_I2CT_DMA_INTERRUPT_RXFIFO_TRIGGER \ + (UNICOMMI2CT_DMA_TRIG1_IMASK_RXTRG_SET) + +/** @}*/ + +/* clang-format on */ + +/** @enum DL_I2CT_EVENT_ROUTE */ +typedef enum { + /*! I2CT event route 1 */ + DL_I2CT_EVENT_ROUTE_1 = 0, + /*! I2CT event route 2 */ + DL_I2CT_EVENT_ROUTE_2 = 12 +} DL_I2CT_EVENT_ROUTE; + +/** @enum DL_I2CT_CLOCK */ +typedef enum { + /*! BUSCLK enabled as I2CT clock source */ + DL_I2CT_CLOCK_BUSCLK = UNICOMMI2CT_CLKSEL_BUSCLK_SEL_ENABLE, + /*! MFCLK enabled as I2CT clock source */ + DL_I2CT_CLOCK_MFCLK = UNICOMMI2CT_CLKSEL_MFCLK_SEL_ENABLE, + /*! Asynchronous SYSCLK enabled as I2CT clock source */ + DL_I2CT_CLOCK_ASYNC_SYSCLK = UNICOMMI2CT_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE, + /*! Asynchronous HFCLK enabled as I2CT clock source */ + DL_I2CT_CLOCK_ASYNC_HFCLK = UNICOMMI2CT_CLKSEL_ASYNC_HFCLK_SEL_ENABLE, + /*! Asynchronous PLL enabled as I2CT clock source */ + DL_I2CT_CLOCK_ASYNC_PLL = UNICOMMI2CT_CLKSEL_ASYNC_PLL_SEL_ENABLE, +} DL_I2CT_CLOCK; + +/** @enum DL_I2CT_CLOCK_DIVIDE */ +typedef enum { + /*! I2CT Clock Divided by 1 */ + DL_I2CT_CLOCK_DIVIDE_1 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_1, + /*! I2CT Clock Divided by 2 */ + DL_I2CT_CLOCK_DIVIDE_2 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_2, + /*! I2CT Clock Divided by 3 */ + DL_I2CT_CLOCK_DIVIDE_3 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_3, + /*! I2CT Clock Divided by 4 */ + DL_I2CT_CLOCK_DIVIDE_4 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_4, + /*! I2CT Clock Divided by 5 */ + DL_I2CT_CLOCK_DIVIDE_5 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_5, + /*! I2CT Clock Divided by 6 */ + DL_I2CT_CLOCK_DIVIDE_6 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_6, + /*! I2CT Clock Divided by 7 */ + DL_I2CT_CLOCK_DIVIDE_7 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_7, + /*! I2CT Clock Divided by 8 */ + DL_I2CT_CLOCK_DIVIDE_8 = UNICOMMI2CT_CLKDIV_RATIO_DIV_BY_8, +} DL_I2CT_CLOCK_DIVIDE; + +/** @enum DL_I2CT_ADDRESSING_MODE */ +typedef enum { + /*! Enable in 7-bit addressing mode */ + DL_I2CT_ADDRESSING_MODE_7_BIT = UNICOMMI2CT_OAR_MODE_MODE7, + /*! Enable in 10-bit addressing mode */ + DL_I2CT_ADDRESSING_MODE_10_BIT = UNICOMMI2CT_OAR_MODE_MODE10, +} DL_I2CT_ADDRESSING_MODE; + +/** @enum DL_I2CT_PEC_STATUS */ +typedef enum { + /*! I2CT SMBus/PMBus PEC was checked in the transaction that occurred + * before the last Stop */ + DL_I2CT_PEC_STATUS_CHECKED = UNICOMMI2CT_PECSR_PECSTS_CHECK_SET, + /*! I2CT SMBus/PMBus PEC was not checked in the transaction that + * occurred before the last Stop */ + DL_I2CT_PEC_STATUS_NOT_CHECKED = UNICOMMI2CT_PECSR_PECSTS_CHECK_CLEARED, +} DL_I2CT_PEC_STATUS; + +/** @enum DL_I2CT_PEC_CHECK_ERROR */ +typedef enum { + /*! Indicates PEC check error did not occurr in the transaction that + * occurred before the last Stop */ + DL_I2CT_PEC_CHECK_ERROR_CLEARED = UNICOMMI2CT_PECSR_PECSTS_ERROR_CLEARED, + /*! Indicates PEC check error occurred in the transaction that + * occurred before the last Stop */ + DL_I2CT_PEC_CHECK_ERROR_SET = UNICOMMI2CT_PECSR_PECSTS_ERROR_SET, +} DL_I2CT_PEC_CHECK_ERROR; + +/** @enum DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH */ +typedef enum { + /*! Pulses filtering disabled. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_DISABLED = + UNICOMMI2CT_GFCTL_DGFSEL_DISABLED, + /*! Pulses shorter than 1 functional clock tick in length are filtered. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_1 = + UNICOMMI2CT_GFCTL_DGFSEL_CLK_1, + /*! Pulses shorter than 2 functional clock ticks in length are filtered. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_2 = + UNICOMMI2CT_GFCTL_DGFSEL_CLK_2, + /*! Pulses shorter than 3 functional clock ticks in length are filtered. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_3 = + UNICOMMI2CT_GFCTL_DGFSEL_CLK_3, + /*! Pulses shorter than 4 functional clock ticks in length are filtered. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_4 = + UNICOMMI2CT_GFCTL_DGFSEL_CLK_4, + /*! Pulses shorter than 8 functional clock ticks in length are filtered. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_8 = + UNICOMMI2CT_GFCTL_DGFSEL_CLK_8, + /*! Pulses shorter than 16 functional clock ticks in length are filtered. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_16 = + UNICOMMI2CT_GFCTL_DGFSEL_CLK_16, + /*! Pulses shorter than 31 functional clock ticks in length are filtered. */ + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_31 = + UNICOMMI2CT_GFCTL_DGFSEL_CLK_31, +} DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH; + +/** @enum DL_I2CT_TX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when FIFO <= 3/4 empty */ + DL_I2CT_TX_FIFO_LEVEL_3_4_EMPTY = UNICOMMI2CT_IFLS_TXIFLSEL_LVL_3_4, + /*! Interrupt triggers when FIFO <= 1/2 empty */ + DL_I2CT_TX_FIFO_LEVEL_1_2_EMPTY = UNICOMMI2CT_IFLS_TXIFLSEL_LVL_1_2, + /*! Interrupt triggers when FIFO <= 1/4 empty */ + DL_I2CT_TX_FIFO_LEVEL_1_4_EMPTY = UNICOMMI2CT_IFLS_TXIFLSEL_LVL_1_4, + /*! Interrupt triggers when FIFO is not full */ + DL_I2CT_TX_FIFO_LEVEL_ONE_ENTRY = UNICOMMI2CT_IFLS_TXIFLSEL_LVL_NOT_FULL, + /*! Interrupt triggers when FIFO is empty */ + DL_I2CT_TX_FIFO_LEVEL_EMPTY = UNICOMMI2CT_IFLS_TXIFLSEL_LVL_EMPTY, + /*! Interrupt triggers when FIFO is almost empty (FIFO <= 1) */ + DL_I2CT_TX_FIFO_LEVEL_ALMOST_EMPTY = + UNICOMMI2CT_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY, + /*! Interrupt triggers when FIFO is almost full (FIFO >= (MAX_FIFO_LEN - 1)) */ + DL_I2CT_TX_FIFO_LEVEL_ALMOST_FULL = + UNICOMMI2CT_IFLS_TXIFLSEL_LVL_ALMOST_FULL +} DL_I2CT_TX_FIFO_LEVEL; + +/** @enum DL_I2CT_RX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when FIFO >= 3/4 full */ + DL_I2CT_RX_FIFO_LEVEL_3_4_FULL = UNICOMMI2CT_IFLS_RXIFLSEL_LVL_3_4, + /*! Interrupt triggers when FIFO >= 1/2 full */ + DL_I2CT_RX_FIFO_LEVEL_1_2_FULL = UNICOMMI2CT_IFLS_RXIFLSEL_LVL_1_2, + /*! Interrupt triggers when FIFO >= 1/4 full */ + DL_I2CT_RX_FIFO_LEVEL_1_4_FULL = UNICOMMI2CT_IFLS_RXIFLSEL_LVL_1_4, + /*! Interrupt triggers when FIFO is not empty */ + DL_I2CT_RX_FIFO_LEVEL_ONE_ENTRY = UNICOMMI2CT_IFLS_RXIFLSEL_LVL_NOT_EMPTY, + /*! Interrupt triggers when FIFO is full */ + DL_I2CT_RX_FIFO_LEVEL_FULL = UNICOMMI2CT_IFLS_RXIFLSEL_LVL_FULL, + /*! Interrupt triggers when FIFO is almost full (FIFO >= (MAX_FIFO_LEN - 1)) */ + DL_I2CT_RX_FIFO_LEVEL_ALMOST_FULL = + UNICOMMI2CT_IFLS_RXIFLSEL_LVL_ALMOST_FULL, + /*! Interrupt triggers when FIFO is almost empty (FIFO <= 1) */ + DL_I2CT_RX_FIFO_LEVEL_ALMOST_EMPTY = + UNICOMMI2CT_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY +} DL_I2CT_RX_FIFO_LEVEL; + +/** @enum DL_I2CT_RESPONSE_OVERRIDE_VALUE */ +typedef enum { + /*! manual ACK for valid data or command. */ + DL_I2CT_RESPONSE_OVERRIDE_VALUE_ACK = UNICOMMI2CT_ACKCTL_ACKOVAL_DISABLE, + /*! manual NACK for invalid data or command. */ + DL_I2CT_RESPONSE_OVERRIDE_VALUE_NACK = UNICOMMI2CT_ACKCTL_ACKOVAL_ENABLE, +} DL_I2CT_RESPONSE_OVERRIDE_VALUE; + +/*! @enum DL_I2CT_IIDX */ +typedef enum { + /*! Interrupt index for I2CT if no interrupt is pending */ + DL_I2CT_IIDX_NO_INT = UNICOMMI2CT_IIDX_STAT_NO_INTR, + /*! Interrupt index for I2CT Timeout A Event */ + DL_I2CT_IIDX_TIMEOUT_A = UNICOMMI2CT_IIDX_STAT_TIMEOUTA, + /*! Interrupt index for I2CT Timeout B Event */ + DL_I2CT_IIDX_TIMEOUT_B = UNICOMMI2CT_IIDX_STAT_TIMEOUTB, + + /*! Interrupt index for I2CT Receive Data */ + DL_I2CT_IIDX_RX_DONE = UNICOMMI2CT_IIDX_STAT_RXDONEFG, + /*! Interrupt index for I2CT Transmit Transaction completed */ + DL_I2CT_IIDX_TX_DONE = UNICOMMI2CT_IIDX_STAT_TXDONEFG, + /*! Interrupt index for I2CT Receive FIFO Trigger */ + DL_I2CT_IIDX_RXFIFO_TRIGGER = UNICOMMI2CT_IIDX_STAT_RXTRG, + /*! Interrupt index for I2CT Transmit FIFO Trigger */ + DL_I2CT_IIDX_TXFIFO_TRIGGER = UNICOMMI2CT_IIDX_STAT_TXTRG, + /*! Interrupt index for I2CT RX FIFO full */ + DL_I2CT_IIDX_RXFIFO_FULL = UNICOMMI2CT_IIDX_STAT_RXFULL, + /*! Interrupt index for I2CT TX FIFO empty. + * All data in Transmit FIFO shifted out and transmit goes into idle mode. */ + DL_I2CT_IIDX_TXFIFO_EMPTY = UNICOMMI2CT_IIDX_STAT_TXEMPTY, + /*! Interrupt index for I2CT Start Condition detected */ + DL_I2CT_IIDX_START = UNICOMMI2CT_IIDX_STAT_STARTFG, + /*! Interrupt index for I2CT Stop Condition detected */ + DL_I2CT_IIDX_STOP = UNICOMMI2CT_IIDX_STAT_STOPFG, + /*! Interrupt index for I2CT General Call */ + DL_I2CT_IIDX_GENERAL_CALL = UNICOMMI2CT_IIDX_STAT_GENCALL, + /*! Interrupt index for I2CT Event 1 DMA Done */ + DL_I2CT_IIDX_EVENT1_DMA_DONE = UNICOMMI2CT_IIDX_STAT_DMA_DONE_TX, + /*! Interrupt index for I2CT Event 2 DMA Done */ + DL_I2CT_IIDX_EVENT2_DMA_DONE = UNICOMMI2CT_IIDX_STAT_DMA_DONE_RX, + /*! Interrupt index for I2CT receive pre-emptive interrupt */ + DL_I2CT_IIDX_PREEMPT_INT_TX = UNICOMMI2CT_IIDX_STAT_DMA_PREIRQ_TX, + /*! Interrupt index for I2CT receive pre-emptive interrupt */ + DL_I2CT_IIDX_PREEMPT_INT_RX = UNICOMMI2CT_IIDX_STAT_DMA_PREIRQ_RX, + /*! Interrupt index for I2CT SMBus/PMBus PEC Receive Error Event */ + DL_I2CT_IIDX_PEC_RX_ERROR = UNICOMMI2CT_IIDX_STAT_PEC_RX_ERR, + /*! Interrupt index for I2CT TX FIFO underflow event */ + DL_I2CT_IIDX_TXFIFO_UNDERFLOW = UNICOMMI2CT_IIDX_STAT_TX_UNFL, + /*! Interrupt index for I2CT RX FIFO overflow event */ + DL_I2CT_IIDX_RXFIFO_OVERFLOW = UNICOMMI2CT_IIDX_STAT_RX_OVFL, + /*! Interrupt index for I2CT arbitration lost event */ + DL_I2CT_IIDX_ARBITRATION_LOST = UNICOMMI2CT_IIDX_STAT_ARBLOSTFG, + +} DL_I2CT_IIDX; + +/** + * @brief Configuration struct for @ref DL_I2CT_setClockConfig. + */ +typedef struct { + /*! I2CT module clock source. One of @ref DL_I2CT_CLOCK */ + DL_I2CT_CLOCK clockSel; + /*! I2CT clock divider selection. One of @ref DL_I2CT_CLOCK_DIVIDE */ + DL_I2CT_CLOCK_DIVIDE divideRatio; +} DL_I2CT_ClockConfig; + +/** + * @brief Configure I2CT source clock + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_I2CT_ClockConfig. + */ +void DL_I2CT_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_ClockConfig *config); + +/** + * @brief Get I2CT source clock configuration + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_I2CT_ClockConfig. + */ +void DL_I2CT_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_ClockConfig *config); + +/** + * @brief Checks if TX FIFO is full + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If TX FIFO is full + * + * @retval true if TX FIFO is full + * @retval false if TX FIFO is not full + */ +__STATIC_INLINE bool DL_I2CT_isTXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->SR & UNICOMMI2CT_SR_TXFF_MASK) == + UNICOMMI2CT_SR_TXFF_SET); +} + +/** + * @brief Checks if TX FIFO is empty + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If TX FIFO is empty + * + * @retval true if TX FIFO is empty + * @retval false if TX FIFO is not empty + */ +__STATIC_INLINE bool DL_I2CT_isTXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->SR & UNICOMMI2CT_SR_TXFE_MASK) == + UNICOMMI2CT_SR_TXFE_SET); +} + +/** + * @brief Checks if RX FIFO is full + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If RX FIFO is full + * + * @retval true if RX FIFO is full + * @retval false if RX FIFO is not full + */ +__STATIC_INLINE bool DL_I2CT_isRXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->SR & UNICOMMI2CT_SR_RXFF_MASK) == + UNICOMMI2CT_SR_RXFF_SET); +} + +/** + * @brief Checks if RX FIFO is empty + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If RX FIFO is empty + * + * @retval true if RX FIFO is empty + * @retval false if RX FIFO is not empty + */ +__STATIC_INLINE bool DL_I2CT_isRXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->SR & UNICOMMI2CT_SR_RXFE_MASK) == + UNICOMMI2CT_SR_RXFE_SET); +} + +/** + * @brief Fills the TX FIFO with data + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] buffer Pointer to buffer of bytes + * @param[in] count Number of bytes to fill TX FIFO from buffer + * + * @return Number of bytes that were successfully written + */ +uint8_t DL_I2CT_fillTXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint8_t count); + +/** + * @brief Flushes/removes all elements in the TX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +void DL_I2CT_flushTXFIFO(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Flushes/removes all elements in the RX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +void DL_I2CT_flushRXFIFO(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Stop TX FIFO flush + * + * Before stopping the flush, check if @ref DL_I2CT_isTXFIFOEmpty, + * indicating flush is complete. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_stopFlushTXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->IFLS &= ~(UNICOMMI2CT_IFLS_TXCLR_MASK); +} + +/** + * @brief Start TX FIFO flush + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_startFlushTXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->IFLS |= UNICOMMI2CT_IFLS_TXCLR_MASK; +} + +/** + * @brief Stop RX FIFO flush + * + * Before stopping the flush, check if @ref DL_I2CT_isRXFIFOEmpty, + * indicating flush is complete. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_stopFlushRXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->IFLS &= ~(UNICOMMI2CT_IFLS_RXCLR_MASK); +} + +/** + * @brief Start RX FIFO flush + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_startFlushRXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->IFLS |= UNICOMMI2CT_IFLS_RXCLR_MASK; +} + +/** + * @brief Transmit data, waiting until transmit request + * + * @note Setting own addresses and enabling should be done + * separately. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] data Byte of data to transmit + */ +void DL_I2CT_transmitDataBlocking(UNICOMM_Inst_Regs *unicomm, uint8_t data); + +/** + * @brief Transmit data + * + * @note Setting own addresses and enabling should be done + * separately. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] data Byte of data to transmit + * + * @return Whether data could be transmitted or not + * @retval true if data could be transmitted + * @retval false if data could not be transmitted + */ +bool DL_I2CT_transmitDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t data); + +/** + * @brief Receive data, waiting until receive request + * + * @note Setting own addresses and enabling should be done + * separately. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Data received from + */ +uint8_t DL_I2CT_receiveDataBlocking(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Receive data + * + * @note Setting own addresses and enabling should be done + * separately. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] buffer Pointer to where byte of received data should be stored + * + * @return Whether data could be received or not + * @retval true if data could be received + * @retval false if data could not be received + */ +bool DL_I2CT_receiveDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t *buffer); + +/** + * @brief Enables power on UNICOMM I2C module + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_enablePower(unicomm); + if (unicomm->fixedMode == false) { + DL_UNICOMM_setIPMode(unicomm, DL_UNICOMM_I2C_TARGET); + } +} + +/** + * @brief Disables power on UNICOMM I2C module + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_disablePower(unicomm); +} + +/** + * @brief Returns if power on UNICOMM I2C module + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return true if power is enabled + * @return false if power is disabled + */ +__STATIC_INLINE bool DL_I2CT_isPowerEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isPowerEnabled(unicomm); +} + +/** + * @brief Resets UNICOMM I2C peripheral + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_reset(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_reset(unicomm); +} + +/** + * @brief Returns if UNICOMM I2C peripheral was reset + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return true if peripheral was reset + * @return false if peripheral wasn't reset + * + */ +__STATIC_INLINE bool DL_I2CT_isReset(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isReset(unicomm); +} + +/** + * @brief Set Clock Source + * + * Clock sources depend on device and clock should be enabled + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] clockSource One of @ref DL_I2CT_CLOCK. + * + */ +__STATIC_INLINE void DL_I2CT_selectClockSource( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_CLOCK clockSource) +{ + DL_Common_updateReg(&unicomm->i2ct->CLKSEL, (uint32_t) clockSource, + UNICOMMI2CT_CLKSEL_BUSCLK_SEL_MASK | + UNICOMMI2CT_CLKSEL_MFCLK_SEL_MASK); +} + +/** + * @brief Set Clock Divider + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] clockDivider One of @ref DL_I2CT_CLOCK_DIVIDE. + * + */ +__STATIC_INLINE void DL_I2CT_selectClockDivider( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_CLOCK_DIVIDE clockDivider) +{ + DL_Common_updateReg(&unicomm->i2ct->CLKDIV, (uint32_t) clockDivider, + UNICOMMI2CT_CLKDIV_RATIO_MASK); +} + +/** + * @brief Get Digital Glitch Suppression Pulse Width + * + * Pulse width for the digital glitch suppression on SCL/SDA lines. + * Values are in terms of functional clock ticks. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Digital glitch suppression pulse width + * + * @retval One of @ref DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH. + */ +__STATIC_INLINE DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH +DL_I2CT_getDigitalGlitchFilterPulseWidth(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t filterWidth = + unicomm->i2ct->GFCTL & UNICOMMI2CT_GFCTL_DGFSEL_MASK; + + return (DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH)(filterWidth); +} + +/** + * @brief Set Digital Glitch Suppression Pulse Width + * + * Pulse width for the digital glitch suppression on SCL/SDA lines. + * Values are in terms of functional clock ticks. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] filterWidth One of @ref DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH. + */ +__STATIC_INLINE void DL_I2CT_setDigitalGlitchFilterPulseWidth( + UNICOMM_Inst_Regs *unicomm, + DL_I2CT_DIGITAL_GLITCH_FILTER_WIDTH filterWidth) +{ + DL_Common_updateReg(&unicomm->i2ct->GFCTL, (uint32_t) filterWidth, + UNICOMMI2CT_GFCTL_DGFSEL_MASK); +} + +/** + * @brief Disable Analog Glitch Suppression + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableAnalogGlitchFilter( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->GFCTL &= ~(UNICOMMI2CT_GFCTL_AGFEN_MASK); +} + +/** + * @brief Checks if analog glitch suppression is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If analog glitch suppression is enabled + * + * @retval true if analog glitch suppression is enabled + * @retval false if analog glitch suppression is disabled + */ +__STATIC_INLINE bool DL_I2CT_isAnalogGlitchFilterEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->GFCTL & UNICOMMI2CT_GFCTL_AGFEN_MASK) == + UNICOMMI2CT_GFCTL_AGFEN_ENABLE); +} + +/** + * @brief Enable Analog Glitch Suppression + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableAnalogGlitchFilter( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->GFCTL |= UNICOMMI2CT_GFCTL_AGFEN_ENABLE; +} + +/** + * @brief Set own address + * + * This field specifies bits A9 through A0 of the own address. + * + * In 7-bit addressing mode as selected by @ref DL_I2CT_setAddressingMode, + * the top 3 bits are don't care + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] addr Value of own address [0x00, 0x3FF] + */ +__STATIC_INLINE void DL_I2CT_setOwnAddress( + UNICOMM_Inst_Regs *unicomm, uint32_t addr) +{ + DL_Common_updateReg(&unicomm->i2ct->OAR, addr, UNICOMMI2CT_OAR_OAR_MASK); +} + +/** + * @brief Get own address + * + * Get bits A9 through A0 of the own address. + * + * In 7-bit addressing mode as selected by @ref DL_I2CT_setAddressingMode, + * the top 3 bits are don't care + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @return own address + * + * @retval [0x00, 0x3FF] + */ +__STATIC_INLINE uint32_t DL_I2CT_getOwnAddress(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->OAR & UNICOMMI2CT_OAR_OAR_MASK); +} + +/** + * @brief Enable own address + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_setOwnAddress + */ +__STATIC_INLINE void DL_I2CT_enableOwnAddress(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->OAR |= UNICOMMI2CT_OAR_OAREN_ENABLE; +} + +/** + * @brief Disable own address + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableOwnAddress(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->OAR &= ~(UNICOMMI2CT_OAR_OAR_MASK); +} + +/** + * @brief Checks if own address is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If own address is enabled + * + * @retval true if own address is enabled + * @retval false if own address is disabled + */ +__STATIC_INLINE bool DL_I2CT_isOwnAddressEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->OAR & UNICOMMI2CT_OAR_OAREN_MASK) == + UNICOMMI2CT_OAR_OAREN_ENABLE); +} + +/** + * @brief Set addressing mode + * + * Selects the addressing mode to be used when device is configured as a + * + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] mode Addressing mode to set the to. + * One of @ref DL_I2CT_ADDRESSING_MODE. + */ +__STATIC_INLINE void DL_I2CT_setAddressingMode( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_ADDRESSING_MODE mode) +{ + DL_Common_updateReg( + &unicomm->i2ct->OAR, (uint32_t) mode, UNICOMMI2CT_OAR_MODE_MASK); +} + +/** + * @brief Get addressing mode + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Addressing mode the is set to + * + * @retval One of @ref DL_I2CT_ADDRESSING_MODE + */ +__STATIC_INLINE DL_I2CT_ADDRESSING_MODE DL_I2CT_getAddressingMode( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t mode = unicomm->i2ct->OAR & UNICOMMI2CT_OAR_MODE_MASK; + + return (DL_I2CT_ADDRESSING_MODE)(mode); +} + +/** + * @brief Get own address alternate + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @return own address alternate + * + * @retval [0x00, 0x7f] + */ +__STATIC_INLINE uint32_t UNICOMMI2CT_getOwnAddressAlternate( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->OAR2 & UNICOMMI2CT_OAR2_OAR2_MASK); +} + +/** + * @brief Set own address alternate + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] addr Value of own address alternate [0x00, 0x7f] + */ +__STATIC_INLINE void DL_I2CT_setOwnAddressAlternate( + UNICOMM_Inst_Regs *unicomm, uint32_t addr) +{ + DL_Common_updateReg( + &unicomm->i2ct->OAR2, addr, UNICOMMI2CT_OAR2_OAR2_MASK); +} + +/** + * @brief Get own address alternate mask + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Which bits of the address are matched + * + * @retval Bit mask with each bit corresponding to bits A6 through A0 of + * the address. Value between [0x00, 0x7F] + */ +__STATIC_INLINE uint32_t DL_I2CT_getOwnAddressAlternateMask( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->OAR2 & UNICOMMI2CT_OAR2_OAR2_MASK_MASK) >> + UNICOMMI2CT_OAR2_OAR2_MASK_OFS); +} + +/** + * @brief Set own address alternate mask + * + * This field specifies bits A6 through A0 of the address. The bits with + * a value of 1 in the SOAR2.OAR2_MASK field will make the corresponding + * incoming address bits to match by default regardless of the value inside + * SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a don't care. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] addressMask Bit mask of address bits to match. + * Value between [0x00, 0x7F] + */ +__STATIC_INLINE void DL_I2CT_setOwnAddressAlternateMask( + UNICOMM_Inst_Regs *unicomm, uint32_t addressMask) +{ + DL_Common_updateReg(&unicomm->i2ct->OAR2, + addressMask << UNICOMMI2CT_OAR2_OAR2_MASK_OFS, + UNICOMMI2CT_OAR2_OAR2_MASK_MASK); +} + +/** + * @brief Disable usage of own address alternate + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableOwnAddressAlternate( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->OAR2 &= ~(UNICOMMI2CT_OAR2_OAR2EN_MASK); +} + +/** + * @brief Checks if own address alternate is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If own address alternate is enabled + * + * @retval true if own address alternate is enabled + * @retval false if own address alternate is disabled + */ +__STATIC_INLINE bool DL_I2CT_isOwnAddressAlternateEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->OAR2 & UNICOMMI2CT_OAR2_OAR2EN_MASK) == + UNICOMMI2CT_OAR2_OAR2EN_ENABLE); +} + +/** + * @brief Enable usage of own address alternate + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableOwnAddressAlternate( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->OAR2 |= UNICOMMI2CT_OAR2_OAR2EN_ENABLE; +} + +/** + * @brief Get the address for which address match happened + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Matched address + * + * @retval Bit mask with each bit corresponding to the address. + * Value between [0x00, 0x7F] in 7-bit mode, or [0x00, 0x3FF] in 10-bit mode. + */ +__STATIC_INLINE uint32_t DL_I2CT_getAddressMatch(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->SR & UNICOMMI2CT_SR_ADDRMATCH_MASK) >> + UNICOMMI2CT_SR_ADDRMATCH_OFS); +} + +/** + * @brief Disable clock stretching + * + * Clock stretching should be enabled to be compliant with I2CT specification + * and the SCL will be stretched when data must be read or written from the + * FIFO. It can optionally be disabled if a controller does not support it or + * to achieve maximum I2CT frequency; however the developer should ensure that + * the FIFO is written or read on time. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableClockStretching(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_CLKSTRETCH_MASK); +} + +/** + * @brief Checks if clock stretching is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If clock stretching is enabled + * + * @retval true if clock stretching is enabled + * @retval false if clock stretching is disabled + */ +__STATIC_INLINE bool DL_I2CT_isClockStretchingEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_CLKSTRETCH_MASK) == + UNICOMMI2CT_CTR_CLKSTRETCH_ENABLE); +} + +/** + * @brief Enable clock stretching + * + * Clock stretching should be enabled to be compliant with I2CT specification + * and the SCL will be stretched when data must be read or written from the + * FIFO. It can optionally be disabled if a controller does not support it or + * to achieve maximum I2CT frequency; however the developer should ensure that + * the FIFO is written or read on time. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableClockStretching(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_CLKSTRETCH_ENABLE; +} + +/** + * @brief Disable TX empty interrupt on transmit request + * + * When disabled, RIS.STXEMPTY will be set when only the TX FIFO is + * empty. This allows the STXEMPTY interrupt to be used to indicate that the + * I2CT bus is being clock stretched and that TX data is required. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_isClockStretchEnabled + */ +__STATIC_INLINE void DL_I2CT_disableTXEmptyOnTXRequest( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_MASK); +} + +/** + * @brief Checks if TX empty interrupt on transmit request is + * enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If TX empty interrupt on transmit request is enabled + * + * @retval true if TX empty interrupt on transmit request is enabled + * @retval false if TX empty interrupt on transmit request disabled + */ +__STATIC_INLINE bool DL_I2CT_isTXEmptyOnTXRequestEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_MASK) == + UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_ENABLE); +} + +/** + * @brief Enable TX empty interrupt on transmit request + * + * When enabled, RIS.STXEMPTY will be set when the state machine is in + * the TX_WAIT state which occurs when the TX FIFO is empty AND the UNICOMMI2CT + * transaction is clock stretched waiting for the FIFO to receive data. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableTXEmptyOnTXRequest( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_TXEMPTY_ON_TREQ_ENABLE; +} + +/** + * @brief Disable TX trigger in TX mode + * + * When disabled, RIS.TXFIFOTRG will only be set when the TX FIFO is at + * or above the trigger level. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableTXTriggerInTXMode( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_TXTRIG_TXMODE_MASK); +} + +/** + * @brief Checks if TX trigger in TX mode is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If TX trigger in TX mode is enabled + * + * @retval true if TX trigger in TX mode is enabled + * @retval false if TX trigger in TX mode is disabled + */ +__STATIC_INLINE bool DL_I2CT_isTXTriggerInTXModeEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_TXTRIG_TXMODE_MASK) == + UNICOMMI2CT_CTR_TXTRIG_TXMODE_ENABLE); +} + +/** + * @brief Enable TX trigger when is in TX mode + * + * When enabled, RIS.TXFIFOTRG will be set when the TX FIFO has reached + * the trigger level AND the state machine is in the TXMODE as defined + * in the SSR register. When cleared RIS.TXFIFOTRG will be set when the + * TX FIFO is at or above the trigger level. This setting can be used to hold + * off the TX DMA until a transaction starts. This allows the DMA to be + * configured when the I2CT is idle but have it wait till the transaction + * starts to load the TX FIFO, so it can load from a memory buffer that + * might be changing over time. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_INTERRUPT_TXFIFO_TRIGGER + */ +__STATIC_INLINE void DL_I2CT_enableTXTriggerInTXMode( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_TXTRIG_TXMODE_ENABLE; +} + +/** + * @brief Disable TX transfer waits when stale data in TX FIFO + * + * When disabled, the TX FIFO empty signal to the state machine + * indicates that the TX FIFO is empty. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableTXWaitWhenTXFIFOStale( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_MASK); +} + +/** + * @brief Checks if TX transfer waits when stale data in TX FIFO + * is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If TX transfer waits when stale data in TX FIFO is + * enabled + * + * @retval true if TX transfer waits when stale data in TX FIFO + * is enabled + * @retval false if TX transfer waits when stale data in TX FIFO + * is disabled + */ +__STATIC_INLINE bool DL_I2CT_isTXWaitWhenTXFIFOStaleEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_MASK) == + UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_ENABLE); +} + +/** + * @brief Enable TX transfer waits when stale data in TX FIFO + * + * When enabled, the TX FIFO empty signal to the state machine will + * indicate that the TX FIFO is empty or that the TX FIFO data is stale. The + * TX FIFO data is determined to be stale when there is data in the TX FIFO + * when the state machine leaves the TXMODE as defined in the SSR + * register. This can occur is a Stop or timeout occur when there are bytes + * left in the TX FIFO. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableTXWaitWhenTXFIFOStale( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_TXWAIT_STALE_TXFIFO_ENABLE; +} + +/** + * @brief Disable RX full interrupt on receive request + * + * When disabled, RIS.SRXFULL will be set when only the RX FIFO is + * full. This allows the SRXFULL interrupt to be used to indicate that the + * I2CT bus is being clock stretched and that the FW must either read the RX + * FIFO or ACK/NACK the current RX byte. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_isClockStretchEnabled + */ +__STATIC_INLINE void DL_I2CT_disableRXFullOnRXRequest( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_RXFULL_ON_RREQ_MASK); +} + +/** + * @brief Checks if RX full interrupt on receive request is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If RX full interrupt on receive request enabled + * + * @retval true if RX full interrupt on receive request enabled + * @retval false if RX full interrupt on receive request disabled + */ +__STATIC_INLINE bool DL_I2CT_isRXFullOnRXRequestEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_RXFULL_ON_RREQ_MASK) == + UNICOMMI2CT_CTR_RXFULL_ON_RREQ_ENABLE); +} + +/** + * @brief Enable RX full interrupt on receive request + * + * When enabled, RIS.SRXFULL will be set when the state machine is in + * the RX_WAIT or RX_ACK_WAIT states which occurs when the I2CT transaction is + * clock stretched because the RX FIFO is full or the ACKOEN has been set and + * the state machine is waiting for FW to ACK/NACK the current byte. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + */ +__STATIC_INLINE void DL_I2CT_enableRXFullOnRXRequest( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_RXFULL_ON_RREQ_ENABLE; +} + +/** + * @brief Disable SMBus/PMBus default host address of 000 1000b + * + * When disabled, the default host address is not matched. + * NOTE: The host address may still be matched if programmed as an own address. + * The I2CT module can still be addressed as a if enabled and own + * address match is enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableDefaultHostAddress( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_EN_DEFHOSTADR_MASK); +} + +/** + * @brief Checks if SMBus/PMBus default host address of 000 1000b is + * enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If default host address is enabled + * + * @retval true if default host address is enabled + * @retval false if default host address disabled + */ +__STATIC_INLINE bool DL_I2CT_isDefaultHostAddressEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_EN_DEFHOSTADR_MASK) == + UNICOMMI2CT_CTR_EN_DEFHOSTADR_ENABLE); +} + +/** + * @brief Enable SMBus/PMBus default host address of 000 1000b + * + * When enabled, default host address of 0x0001000 is always matched by the + * address match logic + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableDefaultHostAddress( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_EN_DEFHOSTADR_ENABLE; +} + +/** + * @brief Disable SMBus/PMBus Alert response address (ARA) of 000 1100b + * + * When disabled, the alert response address 0x0001100 is not matched. + * NOTE: The alert response address may still be matched if programmed as an + * own address. + * The I2CT module can still be addressed as a if enabled and own + * address match is enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableAlertResponseAddress( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_EN_ALRESPADR_MASK); +} + +/** + * @brief Checks if SMBus/PMBus Alert response address (ARA) of 000 1100b + * is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If alert response address is enabled + * + * @retval true if alert response address is enabled + * @retval false if alert response address disabled + */ +__STATIC_INLINE bool DL_I2CT_isAlertResponseAddressEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_EN_ALRESPADR_MASK) == + UNICOMMI2CT_CTR_EN_ALRESPADR_ENABLE); +} + +/** + * @brief Enable SMBus/PMBus Alert response address (ARA) of 000 1100b + * + * When enabled, default alert response address of 0x0001100 is always matched + * by the address match logic + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableAlertResponseAddress( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_EN_ALRESPADR_ENABLE; +} + +/** + * @brief Disable SMBus/PMBus default device address of 110 0001b + * + * Used for Address Resolution Protocol. When disabled, the default device + * address is not matched. + * NOTE: The host address may still be matched if programmed as an own address. + * The I2CT module can still be addressed as a if enabled and own + * address match is enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableDefaultDeviceAddress( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_EN_DEFDEVADR_MASK); +} + +/** + * @brief Checks SMBus/PMBus default device address of 110 0001b is + * enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If default device address is enabled + * + * @retval true if default device address is enabled + * @retval false if default device address disabled + */ +__STATIC_INLINE bool DL_I2CT_isDefaultDeviceAddressEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_EN_DEFDEVADR_MASK) == + UNICOMMI2CT_CTR_EN_DEFDEVADR_ENABLE); +} + +/** + * @brief Enable SMBus/PMBus default device address of 110 0001b + * + * Used for Address Resolution Protocol. When enabled, default device address + * of 110 0001b is always matched by the address match logic. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableDefaultDeviceAddress( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_EN_DEFDEVADR_ENABLE; +} + +/** + * @brief Disable wakeup + * + * When disabled, the is not allowed to clock stretch on START + * detection. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableWakeup(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_WUEN_MASK); +} + +/** + * @brief Checks if wakeup is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If wakeup is enabled + * + * @retval true if wakeup is enabled + * @retval false if wakeup disabled + */ +__STATIC_INLINE bool DL_I2CT_isWakeupEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_WUEN_MASK) == + UNICOMMI2CT_CTR_WUEN_ENABLE); +} + +/** + * @brief Enable wakeup + * + * Enables low-power wake-up, however it is recommended to enable clock + * stretching to stretch the clock while the module is waking up. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_enableClockStretching + */ +__STATIC_INLINE void DL_I2CT_enableWakeup(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_WUEN_ENABLE; +} + +/** + * @brief Disable target + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_ENABLE_MASK); +} + +/** + * @brief Checks if target is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If functionality is enabled + * + * @retval true if functionality is enabled + * @retval false if functionality is disabled + */ +__STATIC_INLINE bool DL_I2CT_isEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_ENABLE_MASK) == + UNICOMMI2CT_CTR_ENABLE_ENABLE); +} + +/** + * @brief Enable target + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_ENABLE_ENABLE; +} + +/** + * @brief Disable general call address of 000 0000b + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableGeneralCall(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR &= ~(UNICOMMI2CT_CTR_GENCALL_MASK); +} + +/** + * @brief Checks if general call address of 000 0000b is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If general call is enabled + * + * @retval true if general call is enabled + * @retval false if general call is disabled + */ +__STATIC_INLINE bool DL_I2CT_isGeneralCallEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->CTR & UNICOMMI2CT_CTR_GENCALL_MASK) == + UNICOMMI2CT_CTR_GENCALL_ENABLE); +} + +/** + * @brief Enable usage of general call address of 000 0000b + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableGeneralCall(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->CTR |= UNICOMMI2CT_CTR_GENCALL_ENABLE; +} + +/** + * @brief Get status of I2CT bus controller for target + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of I2CT bus controller for target + * + * @retval Bitwise OR of @ref DL_I2CT_STATUS + */ +__STATIC_INLINE uint32_t DL_I2CT_getStatus(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->SR); +} + +/** + * @brief Get byte of data from UNICOMMI2CT + * + * If using FIFO, it is first byte from the RX FIFO. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Last received byte of data + * + * @retval [0x00, 0xff] + */ +__STATIC_INLINE uint8_t DL_I2CT_receiveData(UNICOMM_Inst_Regs *unicomm) +{ + return (uint8_t)(unicomm->i2ct->RXDATA & UNICOMMI2CT_RXDATA_DATA_MASK); +} + +/** + * @brief Set next byte to be transferred during the next transaction + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] data Byte of data to be transferred during the next + * transaction. [0x00, 0xff] + */ +__STATIC_INLINE void DL_I2CT_transmitData( + UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + unicomm->i2ct->TTXDATA = data; +} + +/** + * @brief Disable ACK override + * + * Disable manual ACK override to automatically ACK all received bytes until + * the RX FIFO is full. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableACKOverride(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL &= ~(UNICOMMI2CT_ACKCTL_ACKOEN_MASK); +} + +/** + * @brief Checks if ACK override is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If ACK override is enabled + * + * @retval true if ACK override is enabled + * @retval false if ACK override is disabled + */ +__STATIC_INLINE bool DL_I2CT_isACKOverrideEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->ACKCTL & UNICOMMI2CT_ACKCTL_ACKOEN_MASK) == + UNICOMMI2CT_ACKCTL_ACKOEN_ENABLE); +} + +/** + * @brief Enable ACK override + * + * When manual ACK override is enabled, the I2CT SCL is pulled low after + * the last data is received until the ACK override value (through + * @ref DL_I2CT_setACKOverrideValue) is written. + * Disable manual ACK override to automatically ACK all received bytes until + * the RX FIFO is full. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableACKOverride(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL |= UNICOMMI2CT_ACKCTL_ACKOEN_ENABLE; +} + +/** + * @brief Get acknowledge override value + * + * @note for General Call this bit will be ignored if set to NACK and + * continues to receive data. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return What type of response will be generated + * + * @retval One of @ref DL_I2CT_RESPONSE_OVERRIDE_VALUE. + */ +__STATIC_INLINE DL_I2CT_RESPONSE_OVERRIDE_VALUE DL_I2CT_getACKOverrideValue( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t value = unicomm->i2ct->ACKCTL & UNICOMMI2CT_ACKCTL_ACKOVAL_MASK; + + return (DL_I2CT_RESPONSE_OVERRIDE_VALUE)(value); +} + +/** + * @brief Set acknowledge override value + * + * @note for General Call this bit will be ignored if set to NACK and + * continues to receive data. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] value Indicates what type of response will be generated. + * One of @ref DL_I2CT_RESPONSE_OVERRIDE_VALUE. + * + * @sa DL_I2CT_enableACKOverride + */ +__STATIC_INLINE void DL_I2CT_setACKOverrideValue( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_RESPONSE_OVERRIDE_VALUE value) +{ + DL_Common_updateReg(&unicomm->i2ct->ACKCTL, (uint32_t) value, + UNICOMMI2CT_ACKCTL_ACKOVAL_MASK); +} + +/** + * @brief Disable ACK override on Start Condition + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableACKOverrideOnStart( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL &= ~(UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_MASK); +} + +/** + * @brief Checks if ACK override on Start condition is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If ACK override on Start condition is enabled + * + * @retval true if ACK override on Start condition is enabled + * @retval false if ACK override on Start condition is disabled + */ +__STATIC_INLINE bool DL_I2CT_isACKOverrideOnStartEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2ct->ACKCTL & UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_MASK) == + UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_ENABLE); +} + +/** + * @brief Enable ACK override on Start condition + * + * When enabled, this bit will automatically turn on the ACKOEN field + * following a Start condition. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_enableACKOverride + */ +__STATIC_INLINE void DL_I2CT_enableACKOverrideOnStart( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL |= UNICOMMI2CT_ACKCTL_ACKOEN_ON_START_ENABLE; +} + +/** + * @brief Disable ACK override when SMBus/PMBus PEC is next byte + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableACKOverrideOnPECNext( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL &= ~(UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_MASK); +} + +/** + * @brief Checks if ACK override when SMBus/PMBus PEC is next byte + * is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If ACK override when PEC is next byte is enabled + * + * @retval true if ACK override when PEC is next byte is enabled + * @retval false if ACK override when PEC is next byte is disabled + */ +__STATIC_INLINE bool DL_I2CT_isACKOverrideOnPECNextEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2ct->ACKCTL & UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_MASK) == + UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_ENABLE); +} + +/** + * @brief Enable ACK override when SMBus/PMBus PEC is next byte + * + * When enabled, this bit will automatically turn on the ACKOEN field + * following the ACK/NACK of the byte received just prior to the PEC byte. + * Note that when ACKOEN is set, the PEC byte will not automatically be + * ACKed/NACKed by the state machine and FW must perform this function by + * writing SLAVE_SACKCTL. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_enableACKOverride + */ +__STATIC_INLINE void DL_I2CT_enableACKOverrideOnPECNext( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL |= UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECNEXT_ENABLE; +} + +/** + * @brief Disable ACK override when SMBus/PMBus PEC is next byte + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableACKOverrideOnPECDone( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL &= ~(UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_MASK); +} + +/** + * @brief Checks if ACK override when SMBus/PMBus PEC is next byte + * is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If ACK override when PEC is next byte is enabled + * + * @retval true if ACK override when PEC is next byte is enabled + * @retval false if ACK override when PEC is next byte is disabled + */ +__STATIC_INLINE bool DL_I2CT_isACKOverrideOnPECDoneEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2ct->ACKCTL & UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_MASK) == + UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_ENABLE); +} + +/** + * @brief Enable ACK override when SMBus/PMBus PEC is done + * + * When enabled, this bit will automatically turn on the ACKOEN field + * following the ACK/NACK of the received PEC byte. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_I2CT_enableACKOverride + */ +__STATIC_INLINE void DL_I2CT_enableACKOverrideOnPECDone( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->ACKCTL |= UNICOMMI2CT_ACKCTL_ACKOEN_ON_PECDONE_ENABLE; +} + +/** + * @brief Get the SMBus/PMBus Packet Error Checking (PEC) count + * value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The value the PEC count is set to + * + * @retval Value between [0x0, 0x01FF] + */ +__STATIC_INLINE uint32_t DL_I2CT_getPECCountValue(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->PECCTL & UNICOMMI2CT_PECCTL_PECCNT_MASK); +} + +/** + * @brief Set the SMBus/PMBus Packet Error Checking (PEC) count + * value + * + * When this field is non zero, the number of I2CT data bytes are counted. + * Refer to the device TRM for more details. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] count The value to set the PEC count to. + * Value between [0x0, 0x01FF] + */ +__STATIC_INLINE void DL_I2CT_setPECCountValue( + UNICOMM_Inst_Regs *unicomm, uint32_t count) +{ + DL_Common_updateReg( + &unicomm->i2ct->PECCTL, count, UNICOMMI2CT_PECCTL_PECCNT_MASK); +} + +/** + * @brief Disable SMBus/PMBus Packet Error Checking (PEC) + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disablePEC(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->PECCTL &= ~(UNICOMMI2CT_PECCTL_PECEN_MASK); +} + +/** + * @brief Checks if SMBus/PMBus Packet Error Checking (PEC) is + * enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If PEC is enabled + * + * @retval true if PEC is enabled + * @retval false if PEC is disabled + */ +__STATIC_INLINE bool DL_I2CT_isPECEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->i2ct->PECCTL & UNICOMMI2CT_PECCTL_PECEN_MASK) == + UNICOMMI2CT_PECCTL_PECEN_ENABLE); +} + +/** + * @brief Enable SMBus/PMBus Packet Error Checking (PEC) + * + * When enabled, the PEC is calculated on all bits accept the Start, Stop, ACK + * and NACK. The PEC LSFR and the Byte Counter is set to 0 when the State + * Machine is in the IDLE state, which occurs following a Stop or when a + * timeout occurs. The Counter is also set to 0 after the PEC byte is sent or + * received. Note that the NACK is automatically sent following a PEC byte + * that results in a PEC error. + * The PEC Polynomial is x^8 + x^2 + x^1 + 1. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + */ +__STATIC_INLINE void DL_I2CT_enablePEC(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->PECCTL |= UNICOMMI2CT_PECCTL_PECEN_ENABLE; +} + +/** + * @brief Get the current SMBus/PMBus PEC byte count of the state + * machine + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The current PEC byte count of the state macione + * + * @retval Value between [0x0, 0x01FF] + */ +__STATIC_INLINE uint32_t DL_I2CT_getCurrentPECCount(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->PECSR & UNICOMMI2CT_PECSR_PECBYTECNT_MASK); +} + +/** + * @brief Get status if SMBus/PMBus PEC was checked in last + * transaction + * + * The status indicates if the PEC was checked in the transaction that + * occurred before the last Stop. Latched on Stop. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of PEC checked + * + * @retval One of @ref DL_I2CT_PEC_STATUS + */ +__STATIC_INLINE DL_I2CT_PEC_STATUS DL_I2CT_getPECCheckedStatus( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t status = + unicomm->i2ct->PECSR & UNICOMMI2CT_PECSR_PECSTS_CHECK_MASK; + + return (DL_I2CT_PEC_STATUS)(status); +} + +/** + * @brief Get status if SMBus/PMBus PEC had an error + * + * The status indicates if a PEC check error occurred in the transaction that + * occurred before the last Stop. Latched on Stop. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Status of PEC error check + * + * @retval One of @ref DL_I2CT_PEC_CHECK_ERROR + */ +__STATIC_INLINE DL_I2CT_PEC_CHECK_ERROR DL_I2CT_getPECCheckError( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t status = + unicomm->i2ct->PECSR & UNICOMMI2CT_PECSR_PECSTS_ERROR_MASK; + + return (DL_I2CT_PEC_CHECK_ERROR)(status); +} + +/** + * @brief Get TX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @return Indicates at what fill level in the TX FIFO a threshold will be + * generated + * + * @retval One of @ref DL_I2CT_TX_FIFO_LEVEL + */ +__STATIC_INLINE DL_I2CT_TX_FIFO_LEVEL DL_I2CT_getTXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t level = unicomm->i2ct->IFLS & UNICOMMI2CT_IFLS_TXIFLSEL_MASK; + + return (DL_I2CT_TX_FIFO_LEVEL)(level); +} + +/** + * @brief Set TX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] level Indicates at what fill level in the TX FIFO a threshold + * will be generated. + * One of @ref DL_I2CT_TX_FIFO_LEVEL. + */ +__STATIC_INLINE void DL_I2CT_setTXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_TX_FIFO_LEVEL level) +{ + DL_Common_updateReg(&unicomm->i2ct->IFLS, (uint32_t) level, + (uint32_t) UNICOMMI2CT_IFLS_TXIFLSEL_MASK); +} + +/** + * @brief Get RX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @return Indicates at what fill level in the RX FIFO a threshold will be + * generated + * + * @retval One of @ref DL_I2CT_RX_FIFO_LEVEL + */ +__STATIC_INLINE DL_I2CT_RX_FIFO_LEVEL DL_I2CT_getRXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t level = unicomm->i2ct->IFLS & UNICOMMI2CT_IFLS_RXIFLSEL_MASK; + + return (DL_I2CT_RX_FIFO_LEVEL)(level); +} + +/** + * @brief Set RX FIFO threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] level Indicates at what fill level in the RX FIFO a threshold + * will be generated. + * One of @ref DL_I2CT_RX_FIFO_LEVEL. + */ +__STATIC_INLINE void DL_I2CT_setRXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_RX_FIFO_LEVEL level) +{ + DL_Common_updateReg(&unicomm->i2ct->IFLS, (uint32_t) level, + UNICOMMI2CT_IFLS_RXIFLSEL_MASK); +} + +/** + * @brief Enable I2CT interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_I2CT_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CT_enableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->i2ct->CPU_INT.IMASK |= interruptMask; +} + +/** + * @brief Disable I2CT interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to disable. Bitwise OR of + * @ref DL_I2CT_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CT_disableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->i2ct->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which I2CT interrupts are enabled + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CT_INTERRUPT. + * + * @return Which of the requested I2CT interrupts are enabled + * + * @retval Bitwise OR of @ref DL_I2CT_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2CT_getEnabledInterrupts( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->i2ct->CPU_INT.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled I2CT interrupts + * + * Checks if any of the I2CT interrupts that were previously enabled are + * pending. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CT_INTERRUPT. + * + * @return Which of the requested I2CT interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2CT_INTERRUPT values + * + * @sa DL_I2CT_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_I2CT_getEnabledInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->i2ct->CPU_INT.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any I2CT interrupt + * + * Checks if any of the I2CT interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CT_INTERRUPT. + * + * @return Which of the requested I2CT interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2CT_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2CT_getRawInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->i2ct->CPU_INT.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending I2CT interrupt + * + * Checks if any of the I2CT interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The highest priority pending I2CT interrupt + * + * @retval One of @ref DL_I2CT_IIDX + */ +__STATIC_INLINE DL_I2CT_IIDX DL_I2CT_getPendingInterrupt( + UNICOMM_Inst_Regs *unicomm) +{ + return ((DL_I2CT_IIDX) unicomm->i2ct->CPU_INT.IIDX); +} + +/** + * @brief Clear pending I2CT interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_I2CT_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CT_clearInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->i2ct->CPU_INT.ICLR = interruptMask; +} + +/** + * @brief Enables I2CT interrupt for triggering DMA events + * + * Enables the I2CT interrupt to be used as the condition to generate an + * event to directly trigger the DMA. + * + * Each event publisher @ref DL_I2CT_EVENT_ROUTE can set any one of + * @ref DL_I2CT_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interrupt Interrupt to enable as the trigger condition for + * the DMA. One of @ref DL_I2CT_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CT_enableDMAEvent( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_EVENT_ROUTE index, uint32_t interrupt) +{ + switch (index) { + case DL_I2CT_EVENT_ROUTE_1: + unicomm->i2ct->DMA_TRIG1.IMASK = interrupt; + break; + case DL_I2CT_EVENT_ROUTE_2: + unicomm->i2ct->DMA_TRIG0.IMASK = interrupt; + break; + default: + break; + } +} + +/** + * @brief Disables I2CT interrupt from triggering DMA events + * + * Disables the I2CT interrupt from being used as the condition to generate an + * event to directly trigger the DMA. + * + * Each event publisher @ref DL_I2CT_EVENT_ROUTE can set any one of + * @ref DL_I2CT_DMA_INTERRUPT. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interrupt Interrupt to disable as the trigger condition for + * the DMA. One of @ref DL_I2CT_DMA_INTERRUPT. + */ +__STATIC_INLINE void DL_I2CT_disableDMAEvent( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_EVENT_ROUTE index, uint32_t interrupt) +{ + switch (index) { + case DL_I2CT_EVENT_ROUTE_1: + unicomm->i2ct->DMA_TRIG1.IMASK &= ~(interrupt); + break; + case DL_I2CT_EVENT_ROUTE_2: + unicomm->i2ct->DMA_TRIG0.IMASK &= ~(interrupt); + break; + default: + break; + } +} + +/** + * @brief Check which I2CT interrupt for DMA receive events is enabled + * + * This API checks the event publisher register as selected by + * @ref DL_I2CT_EVENT_ROUTE, which are used for triggering the DMA for + * Controller or and receive or transmit events. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CT_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2CT interrupt status + * + * @retval One of @ref DL_I2CT_DMA_INTERRUPT + */ +__STATIC_INLINE uint32_t DL_I2CT_getEnabledDMAEvents( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_EVENT_ROUTE index, + uint32_t interruptMask) +{ + volatile uint32_t *pReg = &unicomm->i2ct->DMA_TRIG1.IMASK; + + return ((*(pReg + (uint32_t) index) & interruptMask)); +} + +/** + * @brief Check interrupt flag of enabled I2CT interrupt for DMA event + * + * Checks if any of the I2CT interrupts for the DMA receive event that were + * previously enabled are pending. + * This API checks the event publisher register as selected by + * @ref DL_I2CT_EVENT_ROUTE, which are used for triggering the DMA for + * Controller or and receive or transmit events. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CT_DMA_INTERRUPT. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested I2CT interrupt status + * + * @retval One of @ref DL_I2CT_DMA_INTERRUPT + * + * @sa DL_I2CT_enableDMAEvent + */ +__STATIC_INLINE uint32_t DL_I2CT_getEnabledDMAEventStatus( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_EVENT_ROUTE index, + uint32_t interruptMask) +{ + const volatile uint32_t *pReg = &unicomm->i2ct->DMA_TRIG1.MIS; + + return ((*(pReg + (uint32_t) index) & interruptMask)); +} + +/** + * @brief Check interrupt flag of any I2CT interrupt for DMA event + * + * Checks if any of the I2CT interrupts for DMA receive event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the event publisher register as selected by + * @ref DL_I2CT_EVENT_ROUTE, which are used for triggering the DMA for + * Controller or and receive or transmit events. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] index Specifies the register event publisher to configure + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_I2CT_DMA_INTERRUPT. + * + * @return Which of the requested I2CT interrupts are pending + * + * @retval Bitwise OR of @ref DL_I2CT_DMA_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_I2CT_getRawDMAEventStatus( + UNICOMM_Inst_Regs *unicomm, DL_I2CT_EVENT_ROUTE index, + uint32_t interruptMask) +{ + const volatile uint32_t *pReg = &unicomm->i2ct->DMA_TRIG1.RIS; + + return ((*(pReg + (uint32_t) index) & interruptMask)); +} + +/** + * @brief Get the Timeout Counter A value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout A counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CT_getTimeoutACount(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->TIMEOUT_CTL & UNICOMMI2CT_TIMEOUT_CTL_TCNTLA_MASK); +} + +/** + * @brief Set the Timeout Counter A value + * + * Timeout A is used for SCL low detection. This field contains the upper 8 + * bits of a 12-bit pre-load value for the Timeout A count. + * NOTE: The value of the counter must be greater than 1 to enable the + * timeout. Each count is equal to 520 times the timeout period of the + * functional clock. For example, with 8MHz functional clock and a + * 100KHz operating I2CT clock, one timeout period will be equal to + * (1 / 8MHz) * 520 = 65us. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] count The value to set the Timeout A counter to. + * Value between [0x0, 0xFF] + */ +__STATIC_INLINE void DL_I2CT_setTimeoutACount( + UNICOMM_Inst_Regs *unicomm, uint32_t count) +{ + DL_Common_updateReg(&unicomm->i2ct->TIMEOUT_CTL, count, + UNICOMMI2CT_TIMEOUT_CTL_TCNTLA_MASK); +} + +/** + * @brief Disable Timeout Counter A + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableTimeoutA(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->TIMEOUT_CTL &= ~(UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_MASK); +} + +/** + * @brief Checks if Timeout Counter A is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If Timeout Counter A is enabled + * + * @retval true if Timeout Counter A is enabled + * @retval false if Timeout Counter A is disabled + */ +__STATIC_INLINE bool DL_I2CT_isTimeoutAEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2ct->TIMEOUT_CTL & UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_MASK) == + UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_ENABLE); +} + +/** + * @brief Enable Timeout Counter A + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableTimeoutA(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->TIMEOUT_CTL |= UNICOMMI2CT_TIMEOUT_CTL_TCNTAEN_ENABLE; +} + +/** + * @brief Get the current Timer Counter A value + * + * This field contains the upper 8 bits of a 12-bit current counter for + * Timeout Counter A. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout A counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CT_getCurrentTimeoutACounter( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->TIMEOUT_CNT & UNICOMMI2CT_TIMEOUT_CNT_TCNTA_MASK); +} + +/** + * @brief Get the Timeout Counter B value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout B counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CT_getTimeoutBCount(UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2ct->TIMEOUT_CTL & UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_MASK) >> + UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_OFS); +} + +/** + * @brief Set the Timeout Counter B value + * + * Timeout B is used for SCL high detection. This field contains the upper 8 + * bits of a 12-bit pre-load value for the Timeout A count. + * NOTE: The value of the counter must be greater than 1 to enable the + * timeout. Each count is equal to 1* clock period. For example, with 10MHz + * functional clock one timeout period will be equal to 1 * 10ns. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] count The value to set the Timeout A counter to. + * Value between [0x0, 0xFF] + */ +__STATIC_INLINE void DL_I2CT_setTimeoutBCount( + UNICOMM_Inst_Regs *unicomm, uint32_t count) +{ + DL_Common_updateReg(&unicomm->i2ct->TIMEOUT_CTL, + (count << UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_OFS), + UNICOMMI2CT_TIMEOUT_CTL_TCNTLB_MASK); +} + +/** + * @brief Disable Timeout Counter B + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_disableTimeoutB(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->TIMEOUT_CTL &= ~(UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_MASK); +} + +/** + * @brief Checks if Timeout Counter B is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return If Timeout Counter B is enabled + * + * @retval true if Timeout Counter B is enabled + * @retval false if Timeout Counter B is disabled + */ +__STATIC_INLINE bool DL_I2CT_isTimeoutBEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ( + (unicomm->i2ct->TIMEOUT_CTL & UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_MASK) == + UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_ENABLE); +} + +/** + * @brief Enable Timeout Counter B + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_I2CT_enableTimeoutB(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->i2ct->TIMEOUT_CTL |= UNICOMMI2CT_TIMEOUT_CTL_TCNTBEN_ENABLE; +} + +/** + * @brief Get the current Timer Counter B value + * + * This field contains the upper 8 bits of a 12-bit current counter for + * Timeout Counter B. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The Timeout B counter value + * + * @retval Value between [0x0, 0xFF] + */ +__STATIC_INLINE uint32_t DL_I2CT_getCurrentTimeoutBCounter( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->i2ct->TIMEOUT_CNT & UNICOMMI2CT_TIMEOUT_CNT_TCNTB_MASK); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_HAS_UNICOMMI2CT__ */ + +#endif /* ti_dl_dl_unicommi2ct__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_unicommspi.c b/mspm0/source/ti/driverlib/dl_unicommspi.c new file mode 100644 index 0000000..598fb11 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommspi.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2025, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MCU_HAS_UNICOMMSPI__ + +void DL_SPI_init(UNICOMM_Inst_Regs *unicomm, DL_SPI_Config *config) +{ + DL_Common_updateReg(&unicomm->spi->CTL0, + (uint32_t) config->chipSelectPin | (uint32_t) config->frameFormat | + (uint32_t) config->dataSize, + UNICOMMSPI_CTL0_CSSEL_MASK | UNICOMMSPI_CTL0_FRF_MASK | + UNICOMMSPI_CTL0_SPO_MASK | UNICOMMSPI_CTL0_SPH_MASK | + UNICOMMSPI_CTL0_DSS_MASK); + + DL_Common_updateReg(&unicomm->spi->CTL1, + (uint32_t) config->parity | (uint32_t) config->bitOrder | + (uint32_t) config->mode, + UNICOMMSPI_CTL1_PES_MASK | UNICOMMSPI_CTL1_PREN_MASK | + UNICOMMSPI_CTL1_PTEN_MASK | UNICOMMSPI_CTL1_MSB_MASK | + UNICOMMSPI_CTL1_CP_MASK); +} + +void DL_SPI_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_SPI_ClockConfig *config) +{ + unicomm->spi->CLKSEL = (uint32_t) config->clockSel; + + unicomm->spi->CLKDIV = (uint32_t) config->divideRatio; +} + +void DL_SPI_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_SPI_ClockConfig *config) +{ + config->clockSel = (DL_SPI_CLOCK) unicomm->spi->CLKSEL; + + config->divideRatio = (DL_SPI_CLOCK_DIVIDE_RATIO) unicomm->spi->CLKDIV; +} + +uint8_t DL_SPI_receiveDataBlocking8(UNICOMM_Inst_Regs *unicomm) +{ + while (DL_SPI_isRXFIFOEmpty(unicomm)) { + }; + + return DL_SPI_receiveData8(unicomm); +} + +uint16_t DL_SPI_receiveDataBlocking16(UNICOMM_Inst_Regs *unicomm) +{ + while (DL_SPI_isRXFIFOEmpty(unicomm)) { + }; + return DL_SPI_receiveData16(unicomm); +} + +void DL_SPI_transmitDataBlocking8(UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + while (DL_SPI_isTXFIFOFull(unicomm)) { + }; + DL_SPI_transmitData8(unicomm, data); + while (DL_SPI_isBusy(unicomm)) { + }; +} + +void DL_SPI_transmitDataBlocking16(UNICOMM_Inst_Regs *unicomm, uint16_t data) +{ + while (DL_SPI_isTXFIFOFull(unicomm)) { + }; + DL_SPI_transmitData16(unicomm, data); + while (DL_SPI_isBusy(unicomm)) { + }; +} + +void DL_SPI_transmitDataBlocking32(UNICOMM_Inst_Regs *unicomm, uint32_t data) +{ + while (DL_SPI_isTXFIFOFull(unicomm)) { + }; + DL_SPI_transmitData32(unicomm, data); + while (DL_SPI_isBusy(unicomm)) { + }; +} + +bool DL_SPI_receiveDataCheck8(UNICOMM_Inst_Regs *unicomm, uint8_t *buffer) +{ + bool status; + if (DL_SPI_isRXFIFOEmpty(unicomm)) { + status = false; + } else { + *buffer = DL_SPI_receiveData8(unicomm); + status = true; + } + + return status; +} + +bool DL_SPI_receiveDataCheck16(UNICOMM_Inst_Regs *unicomm, uint16_t *buffer) +{ + bool status; + if (DL_SPI_isRXFIFOEmpty(unicomm)) { + status = false; + } else { + *buffer = DL_SPI_receiveData16(unicomm); + status = true; + } + + return status; +} + +bool DL_SPI_transmitDataCheck8(UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + bool status; + if (DL_SPI_isTXFIFOFull(unicomm)) { + status = false; + } else { + DL_SPI_transmitData8(unicomm, data); + status = true; + } + + return status; +} + +bool DL_SPI_transmitDataCheck16(UNICOMM_Inst_Regs *unicomm, uint16_t data) +{ + bool status; + if (DL_SPI_isTXFIFOFull(unicomm)) { + status = false; + } else { + DL_SPI_transmitData16(unicomm, data); + status = true; + } + + return status; +} + +bool DL_SPI_transmitDataCheck32(UNICOMM_Inst_Regs *unicomm, uint32_t data) +{ + bool status; + if (DL_SPI_isTXFIFOFull(unicomm)) { + status = false; + } else { + DL_SPI_transmitData32(unicomm, data); + status = true; + } + + return status; +} + +uint32_t DL_SPI_drainRXFIFO8( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t maxCount) +{ + uint32_t i; + for (i = 0; i < maxCount; i++) { + if (!DL_SPI_isRXFIFOEmpty(unicomm)) { + buffer[i] = DL_SPI_receiveData8(unicomm); + } else { + break; + } + } + + return i; +} + +uint32_t DL_SPI_drainRXFIFO16( + UNICOMM_Inst_Regs *unicomm, uint16_t *buffer, uint32_t maxCount) +{ + uint32_t i; + for (i = 0; i < maxCount; i++) { + if (!DL_SPI_isRXFIFOEmpty(unicomm)) { + buffer[i] = DL_SPI_receiveData16(unicomm); + } else { + break; + } + } + + return i; +} + +uint32_t DL_SPI_fillTXFIFO8( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) { + if (!DL_SPI_isTXFIFOFull(unicomm)) { + DL_SPI_transmitData8(unicomm, buffer[i]); + } else { + break; + } + } + + return i; +} + +uint32_t DL_SPI_fillTXFIFO16( + UNICOMM_Inst_Regs *unicomm, uint16_t *buffer, uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) { + if (!DL_SPI_isTXFIFOFull(unicomm)) { + DL_SPI_transmitData16(unicomm, buffer[i]); + } else { + break; + } + } + + return i; +} + +bool DL_SPI_saveConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_SPI_backupConfig *ptr) +{ + bool stateSaved = !ptr->backupRdy; + if (stateSaved) { + ptr->controlWord0 = unicomm->spi->CTL0; + ptr->controlWord1 = unicomm->spi->CTL1; + ptr->clockControl = unicomm->spi->CLKCTL; + ptr->clockSel = unicomm->spi->CLKSEL; + ptr->divideRatio = unicomm->spi->CLKDIV; + ptr->interruptFifoLevelSelectWord = unicomm->spi->IFLS; + ptr->interruptMask0 = unicomm->spi->CPU_INT.IMASK; + ptr->interruptMask1 = unicomm->spi->DMA_TRIG_RX.IMASK; + ptr->interruptMask2 = unicomm->spi->DMA_TRIG_TX.IMASK; + ptr->backupRdy = true; + } + return stateSaved; +} + +bool DL_SPI_restoreConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_SPI_backupConfig *ptr) +{ + bool stateRestored = ptr->backupRdy; + if (stateRestored) { + /* Set CTL1.ENABLE=0 during initialization */ + unicomm->spi->CTL1 = + ptr->controlWord1 & ~(UNICOMMSPI_CTL1_ENABLE_MASK); + unicomm->spi->CTL0 = ptr->controlWord0; + unicomm->spi->CLKCTL = ptr->clockControl; + unicomm->spi->CLKSEL = ptr->clockSel; + unicomm->spi->CLKDIV = ptr->divideRatio; + unicomm->spi->IFLS = ptr->interruptFifoLevelSelectWord; + unicomm->spi->CPU_INT.IMASK = ptr->interruptMask0; + unicomm->spi->DMA_TRIG_RX.IMASK = ptr->interruptMask1; + unicomm->spi->DMA_TRIG_TX.IMASK = ptr->interruptMask2; + + /* Re-enable SPI if it was originally enabled */ + if ((ptr->controlWord1 & UNICOMMSPI_CTL1_ENABLE_MASK) == + UNICOMMSPI_CTL1_ENABLE_MASK) { + DL_SPI_enable(unicomm); + } + ptr->backupRdy = false; + } + return stateRestored; +} + +uint32_t DL_SPI_fillTXFIFO32( + UNICOMM_Inst_Regs *unicomm, uint32_t *buffer, uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) { + if (!DL_SPI_isTXFIFOFull(unicomm)) { + DL_SPI_transmitData32(unicomm, buffer[i]); + } else { + break; + } + } + + return i; +} + +#endif /* __MCU_HAS_UNICOMMSPI__ */ diff --git a/mspm0/source/ti/driverlib/dl_unicommspi.h b/mspm0/source/ti/driverlib/dl_unicommspi.h new file mode 100644 index 0000000..9bfcb53 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommspi.h @@ -0,0 +1,2336 @@ +/* + * Copyright (c) 2025, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_unicommspi.h + * @brief Unified Communication Module (UNICOMM) - Serial Peripheral Interface (SPI) Driver Library + * @defgroup UNICOMMSPI Unified Communication Module (UNICOMM) - Serial Peripheral Interface (SPI) + * + * @anchor ti_dl_dl_unicommspi_Overview + * # Overview + * + * The Unified Communication Module Serial Peripheral Interface Driver Library allows + * full configuration of the UNICOMM SPI module. + * + * This Serial Peripheral Interface (SPI) module provides a standardized + * serial interface to transfer data between devices and other external + * devices with SPI interface. + * + *
+ ****************************************************************************** + */ +/** @addtogroup UNICOMMSPI + * @{ + */ +#ifndef ti_dl_dl_unicommspi__include +#define ti_dl_dl_unicommspi__include + +#include +#include + +#include +#include +#include + +#ifdef __MCU_HAS_UNICOMMSPI__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_SPI_CD_MODE + * @{ + */ +/*! + * @brief Data mode + */ +#define DL_SPI_CD_MODE_DATA (UNICOMMSPI_CTL1_CDMODE_DATA >> UNICOMMSPI_CTL1_CDMODE_OFS) + +/*! + * @brief Command mode + */ +#define DL_SPI_CD_MODE_COMMAND (UNICOMMSPI_CTL1_CDMODE_COMMAND >> UNICOMMSPI_CTL1_CDMODE_OFS) + + +/** @}*/ + +/** @addtogroup DL_SPI_INTERRUPT + * @{ + */ + +/*! + * @brief DMA done 1 event for transmit interrupt + */ +#define DL_SPI_INTERRUPT_DMA_DONE_TX (UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_TX_SET) + +/*! + * @brief DMA done 1 event for receive interrupt + */ +#define DL_SPI_INTERRUPT_DMA_DONE_RX (UNICOMMSPI_CPU_INT_IMASK_DMA_DONE_RX_SET) + +/*! + * @brief DMA done 1 event for PREIRQ RX interrupt + */ +#define DL_SPI_INTERRUPT_DMA_PREIRQ_RX (UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_RX_SET) + +/*! + * @brief DMA done 1 event for PREIRQ TX interrupt + */ +#define DL_SPI_INTERRUPT_DMA_PREIRQ_TX (UNICOMMSPI_CPU_INT_IMASK_DMA_PREIRQ_TX_SET) + +/*! + * @brief DMA done 1 event for LTOUT interrupt + */ +#define DL_SPI_INTERRUPT_LTOUT (UNICOMMSPI_CPU_INT_IMASK_LTOUT_SET) + +/*! + * @brief SPI has finished transfers and changed into idle mode interrupt + */ +#define DL_SPI_INTERRUPT_IDLE (UNICOMMSPI_CPU_INT_IMASK_IDLE_SET) + +/*! + * @brief Transmit FIFO empty interrupt + */ +#define DL_SPI_INTERRUPT_TX_EMPTY (UNICOMMSPI_CPU_INT_IMASK_TXEMPTY_SET) + +/*! + * @brief Transmit FIFO interrupt + */ +#define DL_SPI_INTERRUPT_TX (UNICOMMSPI_CPU_INT_IMASK_TX_SET) + +/*! + * @brief Receive FIFO interrupt + */ +#define DL_SPI_INTERRUPT_RX (UNICOMMSPI_CPU_INT_IMASK_RX_SET) + +/*! + * @brief Receive timeout interrupt + */ +#define DL_SPI_INTERRUPT_RX_TIMEOUT (UNICOMMSPI_CPU_INT_IMASK_RTOUT_SET) + +/*! + * @brief Receive FIFO full interrupt + */ +#define DL_SPI_INTERRUPT_RX_FULL (UNICOMMSPI_CPU_INT_IMASK_RXFULL_SET) + +/*! + * @brief Transmit FIFO underflow interrupt + */ +#define DL_SPI_INTERRUPT_TX_UNDERFLOW (UNICOMMSPI_CPU_INT_IMASK_TXFIFO_UNF_SET) + +/*! + * @brief Parity error + */ +#define DL_SPI_INTERRUPT_PARITY_ERROR (UNICOMMSPI_CPU_INT_IMASK_PER_SET) + +/*! + * @brief Receive FIFO overflow interrupt + */ +#define DL_SPI_INTERRUPT_RX_OVERFLOW (UNICOMMSPI_CPU_INT_IMASK_RXFIFO_OVF_SET) + +/** @}*/ + + +/** @addtogroup DL_SPI_DMA_INTERRUPT_RX + * @{ + */ +/*! + * @brief SPI interrupt for enabling SPI receive as DMA trigger + */ +#define DL_SPI_DMA_INTERRUPT_RX (UNICOMMSPI_DMA_TRIG_RX_IMASK_RX_SET) + +/*! + * @brief SPI interrupt for enabling SPI receive timeout as DMA trigger + */ +#define DL_SPI_DMA_INTERRUPT_RX_TIMEOUT (UNICOMMSPI_DMA_TRIG_RX_IMASK_RTOUT_SET) + +/** @}*/ + +/*! + * @brief SPI interrupt for enabling SPI transmit as DMA trigger + */ +#define DL_SPI_DMA_INTERRUPT_TX (UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_SET) + +/* clang-format on */ + +/*! @enum DL_SPI_PARITY */ +typedef enum { + /*! Use even parity, enable transmit and receive parity */ + DL_SPI_PARITY_EVEN = + (UNICOMMSPI_CTL1_PES_ENABLE | UNICOMMSPI_CTL1_PREN_ENABLE | + UNICOMMSPI_CTL1_PTEN_ENABLE), + /*! Use odd parity, enable transmit and receive parity */ + DL_SPI_PARITY_ODD = + (UNICOMMSPI_CTL1_PES_DISABLE | UNICOMMSPI_CTL1_PREN_ENABLE | + UNICOMMSPI_CTL1_PTEN_ENABLE), + /*! Disable receive and transmit parity */ + DL_SPI_PARITY_NONE = + (UNICOMMSPI_CTL1_PREN_DISABLE | UNICOMMSPI_CTL1_PTEN_DISABLE) +} DL_SPI_PARITY; + +/*! @enum DL_SPI_FRAME_FORMAT */ +typedef enum { + /*! Motorola 3 Wire with Polarity 0, Phase 0 */ + DL_SPI_FRAME_FORMAT_MOTO3_POL0_PHA0 = + (UNICOMMSPI_CTL0_SPO_LOW | UNICOMMSPI_CTL0_SPH_FIRST | + UNICOMMSPI_CTL0_FRF_MOTOROLA_3WIRE), + /*! Motorola 3 Wire with Polarity 0, Phase 1 */ + DL_SPI_FRAME_FORMAT_MOTO3_POL0_PHA1 = + (UNICOMMSPI_CTL0_SPO_LOW | UNICOMMSPI_CTL0_SPH_SECOND | + UNICOMMSPI_CTL0_FRF_MOTOROLA_3WIRE), + /*! Motorola 3 Wire with Polarity 1, Phase 0 */ + DL_SPI_FRAME_FORMAT_MOTO3_POL1_PHA0 = + (UNICOMMSPI_CTL0_SPO_HIGH | UNICOMMSPI_CTL0_SPH_FIRST | + UNICOMMSPI_CTL0_FRF_MOTOROLA_3WIRE), + /*! Motorola 3 Wire with Polarity 1, Phase 1 */ + DL_SPI_FRAME_FORMAT_MOTO3_POL1_PHA1 = + (UNICOMMSPI_CTL0_SPO_HIGH | UNICOMMSPI_CTL0_SPH_SECOND | + UNICOMMSPI_CTL0_FRF_MOTOROLA_3WIRE), + /*! Motorola 4 Wire with Polarity 0, Phase 0 */ + DL_SPI_FRAME_FORMAT_MOTO4_POL0_PHA0 = + (UNICOMMSPI_CTL0_SPO_LOW | UNICOMMSPI_CTL0_SPH_FIRST | + UNICOMMSPI_CTL0_FRF_MOTOROLA_4WIRE), + /*! Motorola 4 Wire with Polarity 0, Phase 1 */ + DL_SPI_FRAME_FORMAT_MOTO4_POL0_PHA1 = + (UNICOMMSPI_CTL0_SPO_LOW | UNICOMMSPI_CTL0_SPH_SECOND | + UNICOMMSPI_CTL0_FRF_MOTOROLA_4WIRE), + /*! Motorola 4 Wire with Polarity 1, Phase 0 */ + DL_SPI_FRAME_FORMAT_MOTO4_POL1_PHA0 = + (UNICOMMSPI_CTL0_SPO_HIGH | UNICOMMSPI_CTL0_SPH_FIRST | + UNICOMMSPI_CTL0_FRF_MOTOROLA_4WIRE), + /*! Motorola 4 Wire with Polarity 1, Phase 1 */ + DL_SPI_FRAME_FORMAT_MOTO4_POL1_PHA1 = + (UNICOMMSPI_CTL0_SPO_HIGH | UNICOMMSPI_CTL0_SPH_SECOND | + UNICOMMSPI_CTL0_FRF_MOTOROLA_4WIRE), + /*! TI Sync Frame Format */ + DL_SPI_FRAME_FORMAT_TI_SYNC = (UNICOMMSPI_CTL0_FRF_TI_SYNC), +} DL_SPI_FRAME_FORMAT; + +/*! @enum DL_SPI_MODE */ +typedef enum { + /*! Controller mode */ + DL_SPI_MODE_CONTROLLER = (UNICOMMSPI_CTL1_CP_ENABLE), + /*! Peripheral mode */ + DL_SPI_MODE_PERIPHERAL = (UNICOMMSPI_CTL1_CP_DISABLE) +} DL_SPI_MODE; + +/*! @enum DL_SPI_BIT_ORDER */ +typedef enum { + /*! MSB First */ + DL_SPI_BIT_ORDER_MSB_FIRST = (UNICOMMSPI_CTL1_MSB_ENABLE), + /*! LSB First */ + DL_SPI_BIT_ORDER_LSB_FIRST = (UNICOMMSPI_CTL1_MSB_DISABLE) +} DL_SPI_BIT_ORDER; + +/*! @enum DL_SPI_DATA_SIZE */ +typedef enum { + /*! Data size 4 bits */ + DL_SPI_DATA_SIZE_4 = (UNICOMMSPI_CTL0_DSS_DSS_4), + /*! Data size 5 bits */ + DL_SPI_DATA_SIZE_5 = (UNICOMMSPI_CTL0_DSS_DSS_5), + /*! Data size 6 bits */ + DL_SPI_DATA_SIZE_6 = (UNICOMMSPI_CTL0_DSS_DSS_6), + /*! Data size 7 bits */ + DL_SPI_DATA_SIZE_7 = (UNICOMMSPI_CTL0_DSS_DSS_7), + /*! Data size 8 bits */ + DL_SPI_DATA_SIZE_8 = (UNICOMMSPI_CTL0_DSS_DSS_8), + /*! Data size 9 bits */ + DL_SPI_DATA_SIZE_9 = (UNICOMMSPI_CTL0_DSS_DSS_9), + /*! Data size 10 bits */ + DL_SPI_DATA_SIZE_10 = (UNICOMMSPI_CTL0_DSS_DSS_10), + /*! Data size 11 bits */ + DL_SPI_DATA_SIZE_11 = (UNICOMMSPI_CTL0_DSS_DSS_11), + /*! Data size 12 bits */ + DL_SPI_DATA_SIZE_12 = (UNICOMMSPI_CTL0_DSS_DSS_12), + /*! Data size 13 bits */ + DL_SPI_DATA_SIZE_13 = (UNICOMMSPI_CTL0_DSS_DSS_13), + /*! Data size 14 bits */ + DL_SPI_DATA_SIZE_14 = (UNICOMMSPI_CTL0_DSS_DSS_14), + /*! Data size 15 bits */ + DL_SPI_DATA_SIZE_15 = (UNICOMMSPI_CTL0_DSS_DSS_15), + /*! Data size 16 bits */ + DL_SPI_DATA_SIZE_16 = (UNICOMMSPI_CTL0_DSS_DSS_16), +} DL_SPI_DATA_SIZE; + +/*! @enum DL_SPI_CHIP_SELECT */ +typedef enum { + /*! Chip Select 0 */ + DL_SPI_CHIP_SELECT_0 = (UNICOMMSPI_CTL0_CSSEL_CSSEL_0), + /*! Chip Select 1 */ + DL_SPI_CHIP_SELECT_1 = (UNICOMMSPI_CTL0_CSSEL_CSSEL_1), + /*! Chip Select 2 */ + DL_SPI_CHIP_SELECT_2 = (UNICOMMSPI_CTL0_CSSEL_CSSEL_2), + /*! Chip Select 3 */ + DL_SPI_CHIP_SELECT_3 = (UNICOMMSPI_CTL0_CSSEL_CSSEL_3), + /*! No chip select */ + DL_SPI_CHIP_SELECT_NONE = (0) +} DL_SPI_CHIP_SELECT; + +/*! @enum DL_SPI_TX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when TX FIFO <= 3/4 empty */ + DL_SPI_TX_FIFO_LEVEL_3_4_EMPTY = UNICOMMSPI_IFLS_TXIFLSEL_LVL_3_4, + /*! Interrupt triggers when TX FIFO <= 1/2 empty (default) */ + DL_SPI_TX_FIFO_LEVEL_1_2_EMPTY = UNICOMMSPI_IFLS_TXIFLSEL_LVL_1_2, + /*! Interrupt triggers when TX FIFO <= 1/4 empty */ + DL_SPI_TX_FIFO_LEVEL_1_4_EMPTY = UNICOMMSPI_IFLS_TXIFLSEL_LVL_1_4, + /*! Interrupt triggers when TX FIFO is not totally full */ + DL_SPI_TX_FIFO_LEVEL_ONE_FRAME = UNICOMMSPI_IFLS_TXIFLSEL_LVL_NOT_FULL, + /*! Interrupt triggers when TX FIFO is empty */ + DL_SPI_TX_FIFO_LEVEL_EMPTY = UNICOMMSPI_IFLS_TXIFLSEL_LVL_EMPTY, + /*! Interrupt triggers when TX FIFO <= 1 */ + DL_SPI_TX_FIFO_LEVEL_ALMOST_EMPTY = + UNICOMMSPI_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY, + /*! Interrupt triggers when TX FIFO >= (MAX FIFO LEN) - 1 */ + DL_SPI_TX_FIFO_LEVEL_ALMOST_FULL = + UNICOMMSPI_IFLS_TXIFLSEL_LVL_ALMOST_FULL, +} DL_SPI_TX_FIFO_LEVEL; + +/*! @enum DL_SPI_RX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when RX FIFO >= 3/4 full */ + DL_SPI_RX_FIFO_LEVEL_3_4_FULL = UNICOMMSPI_IFLS_RXIFLSEL_LVL_3_4, + /*! Interrupt triggers when RX FIFO >= 1/2 full (default) */ + DL_SPI_RX_FIFO_LEVEL_1_2_FULL = UNICOMMSPI_IFLS_RXIFLSEL_LVL_1_2, + /*! Interrupt triggers when RX FIFO >= 1/4 full */ + DL_SPI_RX_FIFO_LEVEL_1_4_FULL = UNICOMMSPI_IFLS_RXIFLSEL_LVL_1_4, + /*! Interrupt triggers when RX FIFO is not empty */ + DL_SPI_RX_FIFO_LEVEL_ONE_FRAME = UNICOMMSPI_IFLS_RXIFLSEL_LVL_NOT_EMPTY, + /*! Interrupt triggers when RX FIFO is full */ + DL_SPI_RX_FIFO_LEVEL_FULL = UNICOMMSPI_IFLS_RXIFLSEL_LVL_FULL, + /*! Interrupt triggers when RX FIFO >= (MAX FIFO LEN) - 1 */ + DL_SPI_RX_FIFO_LEVEL_ALMOST_FULL = + UNICOMMSPI_IFLS_RXIFLSEL_LVL_ALMOST_FULL, + /*! Interrupt triggers when RX FIFO <= 1 */ + DL_SPI_RX_FIFO_LEVEL_ALMOST_EMPTY = + UNICOMMSPI_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY, +} DL_SPI_RX_FIFO_LEVEL; + +/*! @enum DL_SPI_IIDX */ +typedef enum { + + /*! SPI interrupt index for DMA Done 1 event for transmit */ + DL_SPI_IIDX_DMA_DONE_TX = UNICOMMSPI_IIDX_STAT_DMA_DONE_TX, + /*! SPI interrupt index for DMA Done 1 event for receive */ + DL_SPI_IIDX_DMA_DONE_RX = UNICOMMSPI_IIDX_STAT_DMA_DONE_RX, + /*! SPI interrupt index for SPI to signal it has finished transfers and + * changed into idle mode */ + + DL_SPI_IIDX_IDLE = UNICOMMSPI_IIDX_STAT_IDLE_EVT, + /*! SPI interrupt index for transmit FIFO empty */ + DL_SPI_IIDX_TX_EMPTY = UNICOMMSPI_IIDX_STAT_TX_EMPTY, + /*! SPI interrupt index for transmit FIFO */ + DL_SPI_IIDX_TX = UNICOMMSPI_IIDX_STAT_TX_EVT, + /*! SPI interrupt index for receive FIFO */ + DL_SPI_IIDX_RX = UNICOMMSPI_IIDX_STAT_RX_EVT, + /*! SPI interrupt index for receive timeout */ + DL_SPI_IIDX_RX_TIMEOUT = UNICOMMSPI_IIDX_STAT_RTOUT_EVT, + + /*! SPI interrupt index for receive FIFO full */ + DL_SPI_IIDX_RX_FULL = UNICOMMSPI_IIDX_STAT_RXFULL_EVT, + /*! SPI interrupt index for transmit FIFO underflow */ + DL_SPI_IIDX_TX_UNDERFLOW = UNICOMMSPI_IIDX_STAT_TXFIFO_UNF_EVT, + + /*! SPI interrupt index for parity error */ + DL_SPI_IIDX_PARITY_ERROR = UNICOMMSPI_IIDX_STAT_PER_EVT, + /*! SPI interrupt index for receive FIFO overflow */ + DL_SPI_IIDX_RX_OVERFLOW = UNICOMMSPI_IIDX_STAT_RXFIFO_OFV_EVT, + /*! SPI interrupt index for PREIRQ RX*/ + DL_SPI_IIDX_PREIRQ_RX = UNICOMMSPI_IIDX_STAT_DMA_PREIRQ_RX, + /*! SPI interrupt index for PREIRQ TX*/ + DL_SPI_IIDX_PREIRQ_TX = UNICOMMSPI_IIDX_STAT_DMA_PREIRQ_TX, + /*! SPI interrupt index for line time out*/ + DL_SPI_IIDX_LTOUT = UNICOMMSPI_IIDX_STAT_LTOUT, +} DL_SPI_IIDX; + +/*! @enum DL_SPI_CLOCK_DIVIDE_RATIO */ +typedef enum { + /*! SPI source clock divide ratio set to 1 */ + DL_SPI_CLOCK_DIVIDE_RATIO_1 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_1, + /*! SPI source clock divide ratio set to 2 */ + DL_SPI_CLOCK_DIVIDE_RATIO_2 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_2, + /*! SPI source clock divide ratio set to 3 */ + DL_SPI_CLOCK_DIVIDE_RATIO_3 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_3, + /*! SPI source clock divide ratio set to 4 */ + DL_SPI_CLOCK_DIVIDE_RATIO_4 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_4, + /*! SPI source clock divide ratio set to 5 */ + DL_SPI_CLOCK_DIVIDE_RATIO_5 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_5, + /*! SPI source clock divide ratio set to 6 */ + DL_SPI_CLOCK_DIVIDE_RATIO_6 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_6, + /*! SPI source clock divide ratio set to 7 */ + DL_SPI_CLOCK_DIVIDE_RATIO_7 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_7, + /*! SPI source clock divide ratio set to 8 */ + DL_SPI_CLOCK_DIVIDE_RATIO_8 = UNICOMMSPI_CLKDIV_RATIO_DIV_BY_8 +} DL_SPI_CLOCK_DIVIDE_RATIO; + +/*! @enum DL_SPI_CLOCK */ +typedef enum { + /*! Selects BUSCLK as the clock source */ + DL_SPI_CLOCK_BUSCLK = UNICOMMSPI_CLKSEL_BUSCLK_SEL_ENABLE, + /*! Selects MFCLK as the clock source */ + DL_SPI_CLOCK_MFCLK = UNICOMMSPI_CLKSEL_MFCLK_SEL_ENABLE, + /*! Selects LFCLK as the clock source */ + DL_SPI_CLOCK_LFCLK = UNICOMMSPI_CLKSEL_LFCLK_SEL_ENABLE, + /*! Selects ASYNC LFCLK as the clock source */ + DL_SPI_CLOCK_ASYNC_LFCLK = UNICOMMSPI_CLKSEL_ASYNC_LFCLK_SEL_ENABLE, + /*! Selects ASYNC SYSCLK as the clock source */ + DL_SPI_CLOCK_ASYNC_SYSCLK = UNICOMMSPI_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE, + /*! Selects ASYNC HFCLK as the clock source */ + DL_SPI_CLOCK_ASYNC_HFCLK = UNICOMMSPI_CLKSEL_ASYNC_HFCLK_SEL_ENABLE, + /*! Selects ASYNC PLL as the clock source */ + DL_SPI_CLOCK_ASYNC_PLL = UNICOMMSPI_CLKSEL_ASYNC_PLL_SEL_ENABLE +} DL_SPI_CLOCK; + +/*! + * @brief Configuration struct for @ref DL_SPI_init. + */ +typedef struct { + /*! The controller/peripheral mode configuration. One of @ref DL_SPI_MODE */ + DL_SPI_MODE mode; + + /*! + * The frame format to use for data transfer. One of @ref + * DL_SPI_FRAME_FORMAT + */ + DL_SPI_FRAME_FORMAT frameFormat; + + /*! + * The parity configuration to use for data transfer. One of @ref + * DL_SPI_PARITY. + */ + DL_SPI_PARITY parity; + + /*! The size of the data transfer. One of @ref DL_SPI_DATA_SIZE */ + DL_SPI_DATA_SIZE dataSize; + + /*! The order of bits during data transfer. One of @ref DL_SPI_BIT_ORDER */ + DL_SPI_BIT_ORDER bitOrder; + + /*! The pin to use for chip select. Used in Controller or Peripheral modes + * with Motorola 4-Wire or TI Sync frame formats. One of + * @ref DL_SPI_CHIP_SELECT. + */ + DL_SPI_CHIP_SELECT chipSelectPin; + +} DL_SPI_Config; + +/*! + * @brief Configuration struct for @ref DL_SPI_setClockConfig. + */ +typedef struct { + /*! Selects SPI module clock source @ref DL_SPI_CLOCK */ + DL_SPI_CLOCK clockSel; + + /*! Selects the divide ratio. One of @ref DL_SPI_CLOCK_DIVIDE_RATIO */ + DL_SPI_CLOCK_DIVIDE_RATIO divideRatio; + +} DL_SPI_ClockConfig; + +/** + * @brief Configuration structure to backup SPI peripheral state before going + * to STOP/STANDBY mode. Not required after PG 1.0 silicon. Used by + * @ref DL_SPI_saveConfiguration and @ref DL_SPI_restoreConfiguration + */ +typedef struct { + /*! Combination of basic SPI control configurations that are + * compressed to a single word as they are stored in the SPI + * registers See @ref DL_SPI_init for how the peripheral control word 0 + * is created. */ + uint32_t controlWord0; + + /*! Combination of basic SPI control configurations that are + * compressed to a single word as they are stored in the SPI + * registers. See @ref DL_SPI_init for how the peripheral control word 1 + * is created. */ + uint32_t controlWord1; + + /*! Combination of serial clock divider and delayed sampling settings + * compressed to a single word as they are stored in the SPI registers. */ + uint32_t clockControl; + + /*! SPI module clock source. One of @ref DL_SPI_CLOCK */ + uint32_t clockSel; + + /*! SPI clock divider. One of @ref DL_SPI_CLOCK_DIVIDE_RATIO */ + uint32_t divideRatio; + + /*! Combination of SPI interrupt FIFO level select configurations that are + * compressed to a single word as they are stored in the SPI + * registers. */ + uint32_t interruptFifoLevelSelectWord; + + /*! SPI interrupt status for EVENT0. + * Bitwise OR of @ref DL_SPI_INTERRUPT */ + uint32_t interruptMask0; + + /*! SPI interrupt status for EVENT1. + * Bitwise OR of @ref DL_SPI_DMA_INTERRUPT_RX */ + uint32_t interruptMask1; + + /*! SPI interrupt status for EVENT2. + * Bitwise OR of @ref DL_SPI_DMA_INTERRUPT_TX */ + uint32_t interruptMask2; + + /*! Boolean flag indicating whether or not a valid configuration structure + * exists. Should not be modified by the user. */ + bool backupRdy; +} DL_SPI_backupConfig; + +/** + * @brief Initialize the SPI peripheral + * + * Initializes all the common configurable options for the SPI peripheral. Any + * other custom configuration can be done after calling this API. The SPI is + * not enabled in this API. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] config Configuration for SPI peripheral + */ +void DL_SPI_init(UNICOMM_Inst_Regs *unicomm, DL_SPI_Config *config); + +/** + * @brief Enables power on SPI module + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_enablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_enablePower(unicomm); + if (unicomm->fixedMode == false) { + DL_UNICOMM_setIPMode(unicomm, DL_UNICOMM_SPI); + } +} + +/** + * @brief Disables power on spi module + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_disablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_disablePower(unicomm); +} + +/** + * @brief Returns if power on spi module + * + * @param unicomm Pointer to the register overlay for the peripheral + * + * @return true if power is enabled + * @return false if power is disabled + */ +__STATIC_INLINE bool DL_SPI_isPowerEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isPowerEnabled(unicomm); +} + +/** + * @brief Resets spi peripheral + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_reset(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_reset(unicomm); +} + +/** + * @brief Returns if spi peripheral was reset + * + * @param unicomm Pointer to the register overlay for the peripheral + * + * @return true if peripheral was reset + * @return false if peripheral wasn't reset + * + */ +__STATIC_INLINE bool DL_SPI_isReset(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isReset(unicomm); +} + +/** + * @brief Enable the SPI peripheral + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_enable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 |= UNICOMMSPI_CTL1_ENABLE_ENABLE; +} + +/** + * @brief Checks if the SPI peripheral is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the enabled status of the SPI + * + * @retval true The SPI peripheral is enabled + * @retval false The SPI peripheral is disabled + */ +__STATIC_INLINE bool DL_SPI_isEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_ENABLE_MASK) == + UNICOMMSPI_CTL1_ENABLE_ENABLE); +} + +/** + * @brief Disable the SPI peripheral + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_disable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 &= ~(UNICOMMSPI_CTL1_ENABLE_MASK); +} + +/** + * @brief Configure SPI source clock + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_SPI_ClockConfig. + */ +void DL_SPI_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_SPI_ClockConfig *config); + +/** + * @brief Get SPI source clock configuration + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_SPI_ClockConfig. + */ +void DL_SPI_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_SPI_ClockConfig *config); + +/** + * @brief Checks if the SPI is busy transmitting + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the busy status of the SPI + * + * @retval true The SPI is transmitting + * @retval false The SPI is idle + */ +__STATIC_INLINE bool DL_SPI_isBusy(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_BUSY_MASK) == + UNICOMMSPI_STAT_BUSY_ACTIVE); +} + +/** + * @brief Checks if the TX FIFO is empty + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the empty status of the TX FIFO + * + * @retval true The TX FIFO is empty + * @retval false The TX FIFO is not empty + */ +__STATIC_INLINE bool DL_SPI_isTXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_TXFE_MASK) == + UNICOMMSPI_STAT_TXFE_EMPTY); +} + +/** + * @brief Checks if the TX FIFO is full + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the full status of the TX FIFO + * + * @retval true The TX FIFO is full + * @retval false The TX FIFO is not full + */ +__STATIC_INLINE bool DL_SPI_isTXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_TXFF_MASK) == + UNICOMMSPI_STAT_TXFF_SET); +} + +/** + * @brief Checks if the RX FIFO is empty + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the empty status of the RX FIFO + * + * @retval true The RX FIFO is empty + * @retval false The RX FIFO is not empty + */ +__STATIC_INLINE bool DL_SPI_isRXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_RXFE_MASK) == + UNICOMMSPI_STAT_RXFE_EMPTY); +} + +/** + * @brief Checks if the RX FIFO is full + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the full status of the RX FIFO + * + * @retval true The RX FIFO is full + * @retval false The RX FIFO is not full + */ +__STATIC_INLINE bool DL_SPI_isRXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_RXFF_MASK) == + UNICOMMSPI_STAT_RXFF_SET); +} + +/** + * @brief Checks if the TX FIFO is cleared + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns TX FIFO clear status + * + * @retval true The TX FIFO is cleared + * @retval false The TX FIFO is not cleared + */ + +__STATIC_INLINE bool DL_SPI_isTXFIFOCleared(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_TXCLR_MASK) == + UNICOMMSPI_STAT_TXCLR_SET); +} + +/** + * @brief Checks if the RX FIFO is cleared + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns RX FIFO clear status + * + * @retval true The RX FIFO is cleared + * @retval false The RX FIFO is not cleared + */ + +__STATIC_INLINE bool DL_SPI_isRXFIFOCleared(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_RXCLR_MASK) == + UNICOMMSPI_STAT_RXCLR_SET); +} + +/** + * @brief returns current cdmode value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return returns current cdmode value + */ +__STATIC_INLINE uint32_t DL_SPI_getCurrentCDMODEValue( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->STAT & UNICOMMSPI_STAT_CDMODE_MASK) >> + UNICOMMSPI_STAT_CDMODE_OFS); +} + +/** + * @brief Sets the parity configuration used for transactions + * + * This API sets the configuration for both receive parity and transmit parity. + * This includes which bit is used, and whether even or odd parity is set. + * + * To individually enable or dsiable the receive or transmit parity, refer to + * the APIs listed below. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] parity Parity configuration to use. One of @ref DL_SPI_PARITY. + * + * @sa DL_SPI_init + * @sa DL_SPI_enableReceiveParity + * @sa DL_SPI_disableReceiveParity + * @sa DL_SPI_enableTransmitParity + * @sa DL_SPI_disableTransmitParity + */ +__STATIC_INLINE void DL_SPI_setParity( + UNICOMM_Inst_Regs *unicomm, DL_SPI_PARITY parity) +{ + DL_Common_updateReg(&unicomm->spi->CTL1, (uint32_t) parity, + (UNICOMMSPI_CTL1_PREN_MASK | UNICOMMSPI_CTL1_PTEN_MASK | + UNICOMMSPI_CTL1_PES_MASK)); +} + +/** + * @brief Get the current receive and transmit parity configuration + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The current parity configuration being used + * + * @retval One of @ref DL_SPI_PARITY + */ +__STATIC_INLINE DL_SPI_PARITY DL_SPI_getParity(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t parity = unicomm->spi->CTL1 & + (UNICOMMSPI_CTL1_PES_MASK | UNICOMMSPI_CTL1_PREN_MASK | + UNICOMMSPI_CTL1_PTEN_MASK); + + return (DL_SPI_PARITY)(parity); +} + +/** + * @brief Enables receive parity + * + * This API only enables receive parity, it does not configure the parity mode + * used. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @sa DL_SPI_setParity + */ +__STATIC_INLINE void DL_SPI_enableReceiveParity(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 |= UNICOMMSPI_CTL1_PREN_ENABLE; +} + +/** + * @brief Disables receive parity + * + * This API only disable receive parity, it does not configure the parity mode + * used. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @sa DL_SPI_setParity + */ +__STATIC_INLINE void DL_SPI_disableReceiveParity(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 &= ~(UNICOMMSPI_CTL1_PREN_MASK); +} + +/** + * @brief Checks if receive parity is enabled + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return If receive parity is enabled + * + * @retval true Receive parity is enabled + * @retval false Receive parity is disabled + */ +__STATIC_INLINE bool DL_SPI_isReceiveParityEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_PREN_MASK) == + UNICOMMSPI_CTL1_PREN_ENABLE); +} + +/** + * @brief Enables transmit parity + * + * This API only enables transmit parity, it does not configure the parity mode + * used. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @sa DL_SPI_setParity + */ +__STATIC_INLINE void DL_SPI_enableTransmitParity(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 |= UNICOMMSPI_CTL1_PTEN_ENABLE; +} + +/** + * @brief Disables transmit parity + * + * This API only disables transmit parity, it does not configure the parity + * mode used. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @sa DL_SPI_setParity + */ +__STATIC_INLINE void DL_SPI_disableTransmitParity(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 &= ~(UNICOMMSPI_CTL1_PTEN_MASK); +} + +/** + * @brief Checks if transmit parity is enabled + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return If transmit parity is enabled + * + * @retval true Transmit parity is enabled + * @retval false Transmit parity is disabled + */ +__STATIC_INLINE bool DL_SPI_isTransmitParityEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_PTEN_MASK) == + UNICOMMSPI_CTL1_PTEN_ENABLE); +} + +/** + * @brief Set the frame format to use + * + * Configures the frame format to use for transactions. If you are using chip + * select you must use one of the Motorola 4 wire frame formats. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] frameFormat Frame format to use. One of @ref + * DL_SPI_FRAME_FORMAT. + * + * @sa DL_SPI_init + */ +__STATIC_INLINE void DL_SPI_setFrameFormat( + UNICOMM_Inst_Regs *unicomm, DL_SPI_FRAME_FORMAT frameFormat) +{ + DL_Common_updateReg(&unicomm->spi->CTL0, (uint32_t) frameFormat, + (UNICOMMSPI_CTL0_FRF_MASK | UNICOMMSPI_CTL0_SPO_MASK | + UNICOMMSPI_CTL0_SPH_MASK)); +} + +/** + * @brief Get the frame format configuration + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The current frame format being used + * + * @retval One of @ref DL_SPI_FRAME_FORMAT + */ +__STATIC_INLINE DL_SPI_FRAME_FORMAT DL_SPI_getFrameFormat( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t frameFormat = unicomm->spi->CTL0 & (UNICOMMSPI_CTL0_FRF_MASK | + UNICOMMSPI_CTL0_SPO_MASK | + UNICOMMSPI_CTL0_SPH_MASK); + + return (DL_SPI_FRAME_FORMAT)(frameFormat); +} + +/** + * @brief Set the size for transfers + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] dataSize Number of bits used in a transfer. + * One of @ref DL_SPI_DATA_SIZE + * + * @sa DL_SPI_init + */ +__STATIC_INLINE void DL_SPI_setDataSize( + UNICOMM_Inst_Regs *unicomm, DL_SPI_DATA_SIZE dataSize) +{ + DL_Common_updateReg( + &unicomm->spi->CTL0, (uint32_t) dataSize, UNICOMMSPI_CTL0_DSS_MASK); +} + +/** + * @brief Get the configured size for transfers + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The currently configured size for transfers + * + * @retval One of @ref DL_SPI_DATA_SIZE + */ +__STATIC_INLINE DL_SPI_DATA_SIZE DL_SPI_getDataSize(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t dataSize = unicomm->spi->CTL0 & UNICOMMSPI_CTL0_DSS_MASK; + + return (DL_SPI_DATA_SIZE)(dataSize); +} + +/** + * @brief Set whether the device should be in controller/peripheral mode + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] mode Mode to configure the SPI into. One of @ref DL_SPI_MODE. + * + * @sa DL_SPI_init + */ +__STATIC_INLINE void DL_SPI_setMode( + UNICOMM_Inst_Regs *unicomm, DL_SPI_MODE mode) +{ + DL_Common_updateReg( + &unicomm->spi->CTL1, (uint32_t) mode, UNICOMMSPI_CTL1_CP_MASK); +} + +/** + * @brief Get the current mode for the SPI (controller/peripheral) + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The currently configured mode for the SPI (controller/peripheral) + * + * @retval One of @ref DL_SPI_MODE. + */ +__STATIC_INLINE DL_SPI_MODE DL_SPI_getMode(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t mode = unicomm->spi->CTL1 & UNICOMMSPI_CTL1_CP_MASK; + + return (DL_SPI_MODE)(mode); +} + +/** + * @brief Set the bit order used for transfers + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] bitOrder Order for bits to be sent out during transfer. One of + * @ref DL_SPI_BIT_ORDER. + * + * @sa DL_SPI_init + */ +__STATIC_INLINE void DL_SPI_setBitOrder( + UNICOMM_Inst_Regs *unicomm, DL_SPI_BIT_ORDER bitOrder) +{ + DL_Common_updateReg( + &unicomm->spi->CTL1, (uint32_t) bitOrder, UNICOMMSPI_CTL1_MSB_MASK); +} + +/** + * @brief Get the current bit order used for transfers + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The currently configured bit order + * + * @retval One of @ref DL_SPI_BIT_ORDER. + */ +__STATIC_INLINE DL_SPI_BIT_ORDER DL_SPI_getBitOrder(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t bitOrder = unicomm->spi->CTL1 & UNICOMMSPI_CTL1_MSB_MASK; + + return (DL_SPI_BIT_ORDER)(bitOrder); +} + +/** + * @brief Enables loopback mode + * + * Enables the loopback mode. When enabled, the output of the transmit serial + * shifter is connected to the input of the receive serial shifter internally. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_enableLoopbackMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 |= UNICOMMSPI_CTL1_LBM_ENABLE; +} + +/** + * @brief Disables loopback mode + * + * Disables the loopback mode. When disabled, the transmit serial shifter and + * receive serial shifter are not connected internally. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_disableLoopbackMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 &= ~(UNICOMMSPI_CTL1_LBM_MASK); +} + +/** + * @brief Checks if the loopback mode is enabled + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The status of the loopback mode + * + * @retval true if loopback mode is enabled + * @retval false if loopback mode is disabled + */ +__STATIC_INLINE bool DL_SPI_isLoopbackModeEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_LBM_MASK) == + UNICOMMSPI_CTL1_LBM_ENABLE); +} + +/** + * @brief Set counter for repeated transmit + * + * Repeated transmit allows you to send the same data multiple times. This is + * essentially the same as writing the data into the transmit buffer + * repeatedly. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] numRepeats number of times to repeat the transfer. Should be a + * value between 0-255. + * @arg 0 disables the repeated transfer + * @arg 1-255 repeats that many times. So will be sent + * numRepeats + 1 times in total. + */ +__STATIC_INLINE void DL_SPI_setRepeatTransmit( + UNICOMM_Inst_Regs *unicomm, uint32_t numRepeats) +{ + DL_Common_updateReg(&unicomm->spi->CTL1, + numRepeats << UNICOMMSPI_CTL1_REPEATTX_OFS, + UNICOMMSPI_CTL1_REPEATTX_MASK); +} + +/** + * @brief Get counter for repeated transmit + * + * Repeated transmit allows you to send the same data multiple times. This is + * essentially the same as writing the data into the transmit buffer + * repeatedly. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return Number of repeats used for transfer + * + * @retval 0 Repeated transfer is disabled + * @retval 1-255 Repeat that many times. + */ +__STATIC_INLINE uint32_t DL_SPI_getRepeatTransmit(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_REPEATTX_MASK) >> + UNICOMMSPI_CTL1_REPEATTX_OFS); +} + +/** + * @brief Enables data alignment on chip select for peripherals + * + * When enabled, the receieve bit counter is cleared automatically when the + * chip select gets set inactive. This helps the peripheral synchronize again to + * the controller in case of a disturbance or glitch on the clock line or during + * initialization. + * + * This is only relevant when in peripheral mode. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_enablePeripheralAlignDataOnChipSelect( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL0 |= UNICOMMSPI_CTL0_CSCLR_ENABLE; +} + +/** + * @brief Disables data alignment on chip select for peripherals + * + * When disable, the receieve bit counter is not cleared automatically when + * the chip select gets set inactive. + * + * This is only relevant when in peripheral mode. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_disablePeripheralAlignDataOnChipSelect( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL0 &= ~(UNICOMMSPI_CTL0_CSCLR_MASK); +} + +/** + * @brief Checks if data alignment on chip select for peripherals is enabled + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The status of data alignment on chip select + * + * @retval true Data alignment on chip select is enabled + * @retval false Data alignment on chip select is disabled + */ +__STATIC_INLINE bool DL_SPI_isPeripheralAlignDataOnChipSelectEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL0 & UNICOMMSPI_CTL0_CSCLR_MASK) == + UNICOMMSPI_CTL0_CSCLR_ENABLE); +} + +/** + * @brief Set chip select used for controller or peripheral mode + * + * Choose which chip select should be used for data transfer. User must ensure + * one of the 4-wire frame formats were selected using @ref DL_SPI_init or + * @ref DL_SPI_setFrameFormat. + * + * This API is for both controller and peripheral modes, and the chip select + * can be changed in the application by calling this API. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] chipSelect the chip select pin to use. One of @ref + * DL_SPI_CHIP_SELECT. + */ +__STATIC_INLINE void DL_SPI_setChipSelect( + UNICOMM_Inst_Regs *unicomm, DL_SPI_CHIP_SELECT chipSelect) +{ + DL_Common_updateReg(&unicomm->spi->CTL0, (uint32_t) chipSelect, + UNICOMMSPI_CTL0_CSSEL_MASK); +} + +/** + * @brief Get chip select used for controller or peripheral mode + * + * This API is for both controller and peripheral modes. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The current chip selected used for data transfer + * + * @retval One of @ref DL_SPI_CHIP_SELECT. + */ +__STATIC_INLINE DL_SPI_CHIP_SELECT DL_SPI_getChipSelect( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t chipSelect = unicomm->spi->CTL0 & UNICOMMSPI_CTL0_CSSEL_MASK; + + return (DL_SPI_CHIP_SELECT)(chipSelect); +} + +/** + * @brief Set peripheral receive timeout + * + * Sets the number of clock cycles before a receive timeout occurs. + * + * This is only relevant when in peripheral mode. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] timeout Number of clock cycles before a receive timeout + * occurs. Must be between 0-63. + * @arg 0 Disables receive timeout + * @arg 1-63 Number of clock cycles before timeout + */ +__STATIC_INLINE void DL_SPI_setPeripheralReceiveTimeout( + UNICOMM_Inst_Regs *unicomm, uint32_t timeout) +{ + DL_Common_updateReg(&unicomm->spi->CTL1, + timeout << UNICOMMSPI_CTL1_RXTIMEOUT_OFS, + UNICOMMSPI_CTL1_RXTIMEOUT_MASK); +} + +/** + * @brief Get peripheral receive timeout + * + * This is only relevant when in peripheral mode. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The current amount of cycles used for a peripheral timeout + * + * @retval 0 indicating that receive timeout is disabled + * @retval 1-63 number of clock cycles before a receive timeout occurs + */ +__STATIC_INLINE uint32_t DL_SPI_getPeripheralReceiveTimeout( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_RXTIMEOUT_MASK) >> + UNICOMMSPI_CTL1_RXTIMEOUT_OFS); +} + +/** + * @brief Configure the command/data mode + * + * Command/data mode allows the hardware to control the C/D pin to indicate + * whether the data being transferred is a command or just data. The C/D pin + * is low for commands and high for data. + * + * You can use this API to manually set the C/D pin by passing in @ref + * DL_SPI_CD_MODE_DATA or @ref DL_SPI_CD_MODE_COMMAND. You can also have the + * C/D pin switch automatically by passing in how many bytes are part of the + * command transfer. The C/D pin will stay low until that many bytes are sent + * out and then automatically switch to high. + * + * This is only relevant when in controller mode. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] config configuration for command/data mode. One of: + * @arg DL_SPI_CD_MODE_DATA + * @arg DL_SPI_CD_MODE_COMMAND + * @arg A value between 1-14 to indicate how many bytes + * should be sent as command + */ +__STATIC_INLINE void DL_SPI_setControllerCommandDataModeConfig( + UNICOMM_Inst_Regs *unicomm, uint32_t config) +{ + DL_Common_updateReg(&unicomm->spi->CTL1, + config << UNICOMMSPI_CTL1_CDMODE_OFS, UNICOMMSPI_CTL1_CDMODE_MASK); +} + +/** + * @brief Get the command/data mode configuration + * + * Returns the current configuration for command/data mode. When using the + * automatic C/D pin the value read back will be the number of command bytes + * remaining to be sent. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The current configuration for command/data mode + * + * @retval DL_SPI_CD_MODE_DATA if in manual data mode + * @retval DL_SPI_CD_MODE_COMMAND if in manual command mode + * @retval 1-14 indicating how many command bytes still need to be sent + */ +__STATIC_INLINE uint32_t DL_SPI_getControllerCommandDataModeConfig( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_CDMODE_MASK) >> + UNICOMMSPI_CTL1_CDMODE_OFS); +} + +/** + * @brief Enables command/data mode + * + * When command/data mode is enabled, the C/D pin is used to differentiate + * between command and data during the transaction. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @sa DL_SPI_setControllerCommandDataModeConfig + */ +__STATIC_INLINE void DL_SPI_enableControllerCommandDataMode( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 |= UNICOMMSPI_CTL1_CDENABLE_ENABLE; +} + +/** + * @brief Disables command/data mode + * + * @param[in] unicomm pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_disableControllerCommandDataMode( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 &= ~(UNICOMMSPI_CTL1_CDENABLE_MASK); +} + +/** + * @brief Checks if command/data mode is enabled + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The status of command/data mode + * + * @retval true Command/data mode is enabled + * @retval false Command/data mode is disabled + */ +__STATIC_INLINE bool DL_SPI_isControllerCommandDataModeEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_CDENABLE_MASK) == + UNICOMMSPI_CTL1_CDENABLE_ENABLE); +} + +/** + * @brief Enables peripheral data output + * + * When peripheral data output is enabled, the peripheral can drive the POCI output pin. + * This will cause problems if all peripherals have their RXD lines tied together + * and the controller is trying to broadcast a message to all peripherals while + * ensuring only one peripheral drives data onto its serial output line. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_enablePeripheralDataOutput( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 &= ~(UNICOMMSPI_CTL1_POD_MASK); +} + +/** + * @brief Disables peripheral data output + * + * When peripheral data output is disabled, the peripheral cannot drive the POCI output + * pin. This allows multiple peripherals that have their RXD lines tied together to + * receive a broadcasted message from a controller. + * + * This is only relevant when in peripheral mode. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_disablePeripheralDataOutput( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 |= UNICOMMSPI_CTL1_POD_ENABLE; +} + +/** + * @brief Checks if peripheral data output is enabled + * + * This is only relevant when in peripheral mode. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return If peripheral data output is enabled + * + * @retval true if peripheral data output is enabled + * @retval false if peripheral data output is disabled + */ +__STATIC_INLINE bool DL_SPI_isPeripheralDataOutputEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CTL1 & UNICOMMSPI_CTL1_POD_MASK) == + UNICOMMSPI_CTL1_POD_DISABLE); +} + +/** + * @brief Set the delay sampling + * + * In controller mode only, the data on the input pin will be delayed sampled + * by the defined SPI clock cycles. The delay can be adjusted in steps of SPI + * input clock steps. The maximum allowed delay should not exceed the length + * of one data frame + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] delay The number of SPI clock cycles to delay sampling on + * input pin. Value between 0-15. + */ +__STATIC_INLINE void DL_SPI_setDelayedSampling( + UNICOMM_Inst_Regs *unicomm, uint32_t delay) +{ + DL_Common_updateReg(&unicomm->spi->CLKCTL, + delay << UNICOMMSPI_CLKCTL_DSAMPLE_OFS, + UNICOMMSPI_CLKCTL_DSAMPLE_MASK); +} + +/** + * @brief Get the delay sampling + * + * In controller mode only, the data on the input pin will be delayed sampled + * by the defined SPI clock cycles. The delay can be adjusted in steps of SPI + * input clock steps. The maximum allowed delay should not exceed the length + * of one data frame + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The amount of delay sampling on the input pin in SPI + * clock cycles. + * + * @retval 0 - 15. The amount of delay sampling in SPI clock cycles. + */ +__STATIC_INLINE uint32_t DL_SPI_getDelayedSampling(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->spi->CLKCTL & UNICOMMSPI_CLKCTL_DSAMPLE_MASK) >> + UNICOMMSPI_CLKCTL_DSAMPLE_OFS); +} + +/** + * @brief Set the RX and TX FIFO interrupt threshold level + * + * Select the threshold for the receive and transmit FIFO interrupts. The + * interrupts are generated based on a transition through a level rather + * than being based on the level. That is, the interrupts are generated when + * the fill level progresses through the trigger level. + * + * For example, if the trigger level is set to the half-way mark, the interrupt + * is triggered when the FIFO becomes half empty/full. + * + * Out of reset, the FIFOs are triggered to interrupt at half-way mark. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] rxThreshold One of @ref DL_SPI_RX_FIFO_LEVEL + * @param[in] txThreshold One of @ref DL_SPI_TX_FIFO_LEVEL + * + */ +__STATIC_INLINE void DL_SPI_setFIFOThreshold(UNICOMM_Inst_Regs *unicomm, + DL_SPI_RX_FIFO_LEVEL rxThreshold, DL_SPI_TX_FIFO_LEVEL txThreshold) +{ + DL_Common_updateReg(&unicomm->spi->IFLS, + (uint32_t) rxThreshold | (uint32_t) txThreshold, + UNICOMMSPI_IFLS_RXIFLSEL_MASK | UNICOMMSPI_IFLS_TXIFLSEL_MASK); +} + +/** + * @brief Get the TX FIFO interrupt threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The TX FIFO interrupt threshold level + * + * @retval One of @ref DL_SPI_TX_FIFO_LEVEL + */ +__STATIC_INLINE DL_SPI_TX_FIFO_LEVEL DL_SPI_getTXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t txThreshold = unicomm->spi->IFLS & UNICOMMSPI_IFLS_TXIFLSEL_MASK; + + return (DL_SPI_TX_FIFO_LEVEL)(txThreshold); +} + +/** + * @brief Get the RX FIFO interrupt threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The RX FIFO interrupt threshold level + * + * @retval One of @ref DL_SPI_RX_FIFO_LEVEL + */ +__STATIC_INLINE DL_SPI_RX_FIFO_LEVEL DL_SPI_getRXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t rxThreshold = unicomm->spi->IFLS & UNICOMMSPI_IFLS_RXIFLSEL_MASK; + + return (DL_SPI_RX_FIFO_LEVEL)(rxThreshold); +} + +/** + * @brief Flushes/removes all elements in the TX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_flushTXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + DL_Common_updateReg(&unicomm->spi->IFLS, + (uint32_t) UNICOMMSPI_IFLS_TXCLR_ENABLE, UNICOMMSPI_IFLS_TXCLR_MASK); +} + +/** + * @brief Flushes/removes all elements in the RX FIFO + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_flushRXFIFO(UNICOMM_Inst_Regs *unicomm) +{ + DL_Common_updateReg(&unicomm->spi->IFLS, + (uint32_t) UNICOMMSPI_IFLS_RXCLR_ENABLE, UNICOMMSPI_IFLS_RXCLR_MASK); +} + +/** + * @brief Set the SPI bit rate serial clock divider (SCR) + * + * The SPI includes a programmable bit rate clock divider and prescaler to + * generate the serial output clock. The bit rates are supported up to + * FUNCCLK/2. The functional clock selection depends on the specific device, + * please refer to the device datasheet and PMU/Clock section. + * + * The SPI output bit rate is calculated with the following formula: + * SPI bit rate = (SPI functional clock) / ((1 + SCR)*2) + * Given this formula, the SCR can be calculated: + * SCR = (SPI functional clock) / ((2 * SPI bit rate) - 1) + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] SCR The SPI serial clock divider. Value between 0-1023. + */ +__STATIC_INLINE void DL_SPI_setBitRateSerialClockDivider( + UNICOMM_Inst_Regs *unicomm, uint32_t SCR) +{ + DL_Common_updateReg( + &unicomm->spi->CLKCTL, SCR, UNICOMMSPI_CLKCTL_SCR_MASK); +} + +/** + * @brief Get the SPI bit rate serial clock divider (SCR) + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The current bit rate serial clock divider + * + * @retval The SPI SCR. Value from 0-1023 + */ +__STATIC_INLINE uint32_t DL_SPI_getBitRateSerialClockDivider( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->spi->CLKCTL & UNICOMMSPI_CLKCTL_SCR_MASK); +} + +/** + * @brief Writes 8-bit data into the TX FIFO for transmit + * + * Puts the data into the TX FIFO without checking its status. Use if already + * sure the TX FIFO has space for the write. See related APIs for additional + * transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_SPI_transmitDataBlocking8 + * @sa DL_SPI_transmitDataCheck8 + */ +__STATIC_INLINE void DL_SPI_transmitData8( + UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + unicomm->spi->TXDATA = data; +} + +/** + * @brief Writes 16-bit data into the TX FIFO for transmit + * + * Puts the data into the TX FIFO without checking its status. Use if already + * sure the TX FIFO has space for the write. See related APIs for additional + * transmit options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_SPI_transmitDataBlocking16 + * @sa DL_SPI_transmitDataCheck16 + */ +__STATIC_INLINE void DL_SPI_transmitData16( + UNICOMM_Inst_Regs *unicomm, uint16_t data) +{ + unicomm->spi->TXDATA = data; +} + +/** + * @brief Writes 32-bit data into the TX FIFO for transmit + * + * Puts the data into the TX FIFO without checking its status. Use if already + * sure the TX FIFO has space for the write. See related APIs for additional + * transmit options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_SPI_transmitDataBlocking32 + * @sa DL_SPI_transmitDataCheck32 + */ +__STATIC_INLINE void DL_SPI_transmitData32( + UNICOMM_Inst_Regs *unicomm, uint32_t data) +{ + unicomm->spi->TXDATA = data; +} + +/** + * @brief Reads 8-bit data from the RX FIFO + * + * Reads the data from the RX FIFO without checking its status. Use if + * already sure the RX FIFO has data available. See related APIs for + * additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_SPI_receiveDataBlocking8 + * @sa DL_SPI_receiveDataCheck8 + */ +__STATIC_INLINE uint8_t DL_SPI_receiveData8(UNICOMM_Inst_Regs *unicomm) +{ + return ((uint8_t)(unicomm->spi->RXDATA)); +} + +/** + * @brief Reads 16-bit data from the RX FIFO + * + * Reads the data from the RX FIFO without checking its status. Use if + * already sure the RX FIFO has data available. See related APIs for + * additional receive options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_SPI_receiveDataBlocking16 + * @sa DL_SPI_receiveDataCheck16 + */ +__STATIC_INLINE uint16_t DL_SPI_receiveData16(UNICOMM_Inst_Regs *unicomm) +{ + return ((uint16_t)(unicomm->spi->RXDATA)); +} + +/** + * @brief Enable SPI interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SPI_INTERRUPT. + */ +__STATIC_INLINE void DL_SPI_enableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->spi->CPU_INT.IMASK |= interruptMask; +} + +/** + * @brief Disable SPI interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to disable. Bitwise OR of + * @ref DL_SPI_INTERRUPT. + */ +__STATIC_INLINE void DL_SPI_disableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->spi->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which SPI interrupts are enabled + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPI_INTERRUPT. + * + * @return Which of the requested SPI interrupts are enabled + * + * @retval Bitwise OR of @ref DL_SPI_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SPI_getEnabledInterrupts( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->spi->CPU_INT.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SPI interrupts + * + * Checks if any of the SPI interrupts that were previously enabled are + * pending. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPI_INTERRUPT. + * + * @return Which of the requested SPI interrupts are pending + * + * @retval Bitwise OR of @ref DL_SPI_INTERRUPT values + * + * @sa DL_SPI_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_SPI_getEnabledInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->spi->CPU_INT.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SPI interrupt + * + * Checks if any of the SPI interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPI_INTERRUPT. + * + * @return Which of the requested SPI interrupts are pending + * + * @retval Bitwise OR of @ref DL_SPI_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SPI_getRawInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->spi->CPU_INT.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending SPI interrupt + * + * Checks if any of the SPI interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The highest priority pending SPI interrupt. One of @ref + * DL_SPI_IIDX + */ +__STATIC_INLINE DL_SPI_IIDX DL_SPI_getPendingInterrupt( + UNICOMM_Inst_Regs *unicomm) +{ + return ((DL_SPI_IIDX) unicomm->spi->CPU_INT.IIDX); +} + +/** + * @brief Clear pending SPI interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SPI_INTERRUPT. + */ +__STATIC_INLINE void DL_SPI_clearInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->spi->CPU_INT.ICLR = interruptMask; +} + +/** + * @brief Blocks to ensure transmit is ready before sending data + * + * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not + * full. Will wait indefinitely until there is space in the TX FIFO. See + * related APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_SPI_transmitData8 + * @sa DL_SPI_transmitDataCheck8 + */ +void DL_SPI_transmitDataBlocking8(UNICOMM_Inst_Regs *unicomm, uint8_t data); + +/** + * @brief Blocks to ensure transmit is ready before sending data + * + * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not + * full. Will wait indefinitely until there is space in the TX FIFO. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_SPI_transmitData16 + * @sa DL_SPI_transmitDataCheck16 + */ +void DL_SPI_transmitDataBlocking16(UNICOMM_Inst_Regs *unicomm, uint16_t data); + +/** + * @brief Blocks to ensure transmit is ready before sending data + * + * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not + * full. Will wait indefinitely until there is space in the TX FIFO. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_SPI_transmitData32 + * @sa DL_SPI_transmitDataCheck32 + */ +void DL_SPI_transmitDataBlocking32(UNICOMM_Inst_Regs *unicomm, uint32_t data); + +/** + * @brief Blocks to ensure receive is ready before reading data + * + * Reads the data from the RX FIFO after blocking to ensure the RX FIFO is not + * empty. Will wait indefinitely until there is data in the RX FIFO. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_SPI_transmitData8 + * @sa DL_SPI_transmitDataCheck8 + */ +uint8_t DL_SPI_receiveDataBlocking8(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Blocks to ensure receive is ready before reading data + * + * Reads the data from the RX FIFO after blocking to ensure the RX FIFO is not + * empty. Will wait indefinitely until there is data in the RX FIFO. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_SPI_transmitData16 + * @sa DL_SPI_transmitDataCheck16 + */ +uint16_t DL_SPI_receiveDataBlocking16(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Checks the TX FIFO before trying to transmit data + * + * Checks if the TX FIFO is already full before trying to add new data to the + * FIFO. Exits immediately if full rather than trying to block. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @return If the transmit occurred + * + * @retval true if data was added to the TX FIFO + * @retval false if the TX FIFO was full and data was not added + * + * @sa DL_SPI_transmitData8 + * @sa DL_SPI_transmitDataBlocking8 + */ +bool DL_SPI_transmitDataCheck8(UNICOMM_Inst_Regs *unicomm, uint8_t data); + +/** + * @brief Checks the TX FIFO before trying to transmit data + * + * Checks if the TX FIFO is already full before trying to add new data to the + * FIFO. Exits immediately if full rather than trying to block. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @return If the transmit occurred + * + * @retval true if data was added to the TX FIFO + * @retval false if the TX FIFO was full and data was not added + * + * @sa DL_SPI_transmitData16 + * @sa DL_SPI_transmitDataBlocking16 + */ +bool DL_SPI_transmitDataCheck16(UNICOMM_Inst_Regs *unicomm, uint16_t data); + +/** + * @brief Checks the TX FIFO before trying to transmit data + * + * Checks if the TX FIFO is already full before trying to add new data to the + * FIFO. Exits immediately if full rather than trying to block. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 32 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @return If the transmit occurred + * + * @retval true if data was added to the TX FIFO + * @retval false if the TX FIFO was full and data was not added + * + * @sa DL_SPI_transmitData32 + * @sa DL_SPI_transmitDataBlocking32 + */ +bool DL_SPI_transmitDataCheck32(UNICOMM_Inst_Regs *unicomm, uint32_t data); + +/** + * @brief Checks the RX FIFO before trying to transmit data + * + * Checks if the RX FIFO is already empty before trying to read new data from + * the FIFO. Exits immediately if empty rather than trying to block. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] buffer a buffer to write the received data into + * + * @return If the receive occurred + * + * @retval true if data was read from the RX FIFO + * @retval false if the RX FIFO was empty and data was not read + * + * @sa DL_SPI_receiveData8 + * @sa DL_SPI_receiveDataBlocking8 + */ +bool DL_SPI_receiveDataCheck8(UNICOMM_Inst_Regs *unicomm, uint8_t *buffer); + +/** + * @brief Checks the RX FIFO before trying to transmit data + * + * Checks if the RX FIFO is already empty before trying to read new data from + * the FIFO. Exits immediately if empty rather than trying to block. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 16 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] buffer a buffer to write the received data into + * + * @return If the receive occurred + * + * @retval true if data was read from the RX FIFO + * @retval false if the RX FIFO was empty and data was not read + * + * @sa DL_SPI_receiveData16 + * @sa DL_SPI_receiveDataBlocking16 + */ +bool DL_SPI_receiveDataCheck16(UNICOMM_Inst_Regs *unicomm, uint16_t *buffer); + +/** + * @brief Read all available data out of the RX FIFO using 8 bit access + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[out] buffer Buffer to write received data into + * @param[in] maxCount Max number of bytes to read from the RX FIFO + * + * @return Number of bytes read from the RX FIFO + */ +uint32_t DL_SPI_drainRXFIFO8( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t maxCount); + +/** + * @brief Read all available data out of the RX FIFO using 16 bit access + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[out] buffer Buffer to write received data into + * @param[in] maxCount Max number of halfwords to read from the RX FIFO + * + * @return Number of halfwords read from the RX FIFO + */ +uint32_t DL_SPI_drainRXFIFO16( + UNICOMM_Inst_Regs *unicomm, uint16_t *buffer, uint32_t maxCount); + +/** + * @brief Fill the TX FIFO using 8 bit access + * + * Continuously write data into the TX FIFO until it is filled up or count has + * been reached. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] buffer Buffer of data to write to the TX FIFO + * @param[in] count Max number of bytes to write to the TX FIFO + * + * @return Number of bytes written to the TX FIFO + */ +uint32_t DL_SPI_fillTXFIFO8( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t count); + +/** + * @brief Fill the TX FIFO using 16 bit access + * + * Continuously write data into the TX FIFO until it is filled up or count has + * been reached. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] buffer Buffer of data to write to the TX FIFO + * @param[in] count Max number of halfwords to write to the TX FIFO + * + * @return Number of halfwords written to the TX FIFO + */ +uint32_t DL_SPI_fillTXFIFO16( + UNICOMM_Inst_Regs *unicomm, uint16_t *buffer, uint32_t count); + +/** + * @brief Fill the TX FIFO using 32 bit access + * + * Continuously write data into the TX FIFO until it is filled up or count has + * been reached. + * entries. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] buffer Buffer of data to write to the TX FIFO + * @param[in] count Max number of words to write to the TX FIFO + * + * @return Number of words written to the TX FIFO + */ +uint32_t DL_SPI_fillTXFIFO32( + UNICOMM_Inst_Regs *unicomm, uint32_t *buffer, uint32_t count); + +/** + * @brief Enable SPI interrupt for triggering the DMA receive event + * + * Enables the SPI interrupt to be used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_RX + * register, which is the event publisher used for triggering the DMA to do + * a receive data transfer. + * + * @note Only one interrupt source should be enabled at a time. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interrupt Interrupt to enable as the trigger condition for + * the DMA. One of @ref DL_SPI_DMA_INTERRUPT_RX. + */ +__STATIC_INLINE void DL_SPI_enableDMAReceiveEvent( + UNICOMM_Inst_Regs *unicomm, uint32_t interrupt) +{ + unicomm->spi->DMA_TRIG_RX.IMASK = interrupt; +} + +/** + * @brief Enable SPI interrupt for triggering the DMA transmit event + * + * Enables the SPI interrupt to be used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_TX + * register, which is the event publisher used for triggering the DMA to do + * a transmit data transfer. + * + * @note DMA_TRIG_TX only has one transmit interrupt source + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_SPI_enableDMATransmitEvent(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->DMA_TRIG_TX.IMASK = UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_SET; +} + +/** + * @brief Disables SPI interrupt from triggering the DMA receive event + * + * Disables the SPI interrupt as the condition to generate an event to + * directly trigger the DMA. This API configures the DMA_TRIG_RX + * register, which is the event publisher used for triggering the DMA to do + * a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interrupt Interrupt to disable as the trigger condition for + * the DMA. One of @ref DL_SPI_DMA_INTERRUPT_RX. + */ +__STATIC_INLINE void DL_SPI_disableDMAReceiveEvent( + UNICOMM_Inst_Regs *unicomm, uint32_t interrupt) +{ + unicomm->spi->DMA_TRIG_RX.IMASK &= ~(interrupt); +} + +/** + * @brief Disables SPI interrupt from triggering the DMA transmit event + * + * Disables the SPI interrupt as the condition to generate an event to + * directly trigger the DMA. This API configures the DMA_TRIG_TX + * register, which is the event publisher used for triggering the DMA to do + * a transmit data transfer. + * + * @note DMA_TRIG_TX only has one transmit interrupt source + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_SPI_disableDMATransmitEvent(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->DMA_TRIG_TX.IMASK = UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_CLR; +} + +/** + * @brief Check which SPI interrupt for DMA receive events is enabled + * + * This API checks the DMA_TRIG_RX register, which is the event publisher used + * for triggering the DMA to do a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPI_DMA_INTERRUPT_RX. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return Which of the requested SPI interrupts is enabled + * + * @retval One of @ref DL_SPI_DMA_INTERRUPT_RX + */ +__STATIC_INLINE uint32_t DL_SPI_getEnabledDMAReceiveEvent( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->spi->DMA_TRIG_RX.IMASK & interruptMask); +} + +/** + * @brief Check if SPI interrupt for DMA transmit event is enabled + * + * This API checks the DMA_TRIG_TX register, which is the event publisher used + * for triggering the DMA to do a transmit data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The requested SPI interrupt status + * + * @retval DL_SPI_DMA_INTERRUPT_TX if enabled, 0 if not enabled + */ +__STATIC_INLINE uint32_t DL_SPI_getEnabledDMATransmitEvent( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->spi->DMA_TRIG_TX.IMASK & + UNICOMMSPI_DMA_TRIG_TX_IMASK_TX_MASK); +} + +/** + * @brief Check interrupt flag of enabled SPI interrupt for DMA receive event + * + * Checks if any of the SPI interrupts for the DMA receive event that were + * previously enabled are pending. + * This API checks the DMA_TRIG_RX register, which is the event publisher used + * for triggering the DMA to do a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPI_DMA_INTERRUPT_RX. + * + * @note Only one interrupt source should be enabled at a time. + * + * @return The requested SPI interrupt status + * + * @retval One of @ref DL_SPI_DMA_INTERRUPT_RX + * + * @sa DL_SPI_enableDMAReceiveEvent + */ +__STATIC_INLINE uint32_t DL_SPI_getEnabledDMAReceiveEventStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->spi->DMA_TRIG_RX.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SPI interrupt for DMA transmit event + * + * Checks if the SPI interrupt for the DMA transmit event that was + * previously enabled is pending. + * This API checks the DMA_TRIG_TX register, which is the event publisher used + * for triggering the DMA to do a transmit data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The requested SPI interrupt status + * + * @retval DL_SPI_DMA_INTERRUPT_TX if enabled, 0 if not enabled + * + * @sa DL_SPI_enableDMATransmitEvent + */ +__STATIC_INLINE uint32_t DL_SPI_getEnabledDMATransmitEventStatus( + UNICOMM_Inst_Regs *unicomm) +{ + return ( + unicomm->spi->DMA_TRIG_TX.MIS & UNICOMMSPI_DMA_TRIG_TX_MIS_TX_MASK); +} + +/** + * @brief Check interrupt flag of any SPI interrupt for DMA receive event + * + * Checks if any of the SPI interrupts for DMA receive event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the DMA_TRIG_RX register, which is the event publisher used + * for triggering the DMA to do a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SPI_DMA_INTERRUPT_RX. + * + * @return Which of the requested SPI interrupts are pending + * + * @retval Bitwise OR of @ref DL_SPI_DMA_INTERRUPT_RX values + */ +__STATIC_INLINE uint32_t DL_SPI_getRawDMAReceiveEventStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->spi->DMA_TRIG_RX.RIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SPI interrupt for DMA transmit event + * + * Checks if any of the SPI interrupts for DMA transmit event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the DMA_TRIG_TX register, which is the event publisher used + * for triggering the DMA to do a transmit data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The requested SPI interrupt status + * + * @retval DL_SPI_DMA_INTERRUPT_TX if enabled, 0 if not enabled + */ +__STATIC_INLINE uint32_t DL_SPI_getRawDMATransmitEventStatus( + UNICOMM_Inst_Regs *unicomm) +{ + return ( + unicomm->spi->DMA_TRIG_TX.RIS & UNICOMMSPI_DMA_TRIG_TX_RIS_TX_MASK); +} + +/** + * @brief Save SPI configuration before entering a power loss state. + * + * Some peripherals residing in PD1 domain do not retain register + * contents when entering STOP or STANDBY modes. Please refer to the datasheet + * for the full list of peripheral instances that exhibit this behavior. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @param[in] ptr Configuration backup setup structure. See + * @ref DL_SPI_backupConfig. + * + * @retval FALSE if a configuration already exists in ptr (will not be + * overwritten). TRUE if a configuration was successfully saved + * + * @sa DL_SPI_restoreConfiguration + */ +bool DL_SPI_saveConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_SPI_backupConfig *ptr); + +/** + * @brief Restore SPI configuration after leaving a power loss state. + * + * Some peripherals residing in PD1 domain do not retain register + * contents when entering STOP or STANDBY modes. Please refer to the datasheet + * for the full list of peripheral instances that exhibit this behavior. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @param[in] ptr Configuration backup setup structure. See + * @ref DL_SPI_backupConfig. + * + * @retval FALSE if a configuration does not exist in ptr (will not be + * loaded). TRUE if a configuration successfully loaded + * + * @sa DL_SPI_saveConfiguration + */ +bool DL_SPI_restoreConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_SPI_backupConfig *ptr); + +/** + * @brief Suspend external communication + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_enableSuspend(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 |= UNICOMMSPI_CTL1_SUSPEND_ENABLE; +} + +/** + * @brief Resume external communication + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_SPI_disableSuspend(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->spi->CTL1 &= ~(UNICOMMSPI_CTL1_SUSPEND_MASK); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_HAS_UNICOMMSPI__ */ + +#endif /* ti_dl_dl_UNICOMMSPI__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_unicommuart.c b/mspm0/source/ti/driverlib/dl_unicommuart.c new file mode 100644 index 0000000..8848546 --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommuart.c @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#ifdef __MCU_HAS_UNICOMMUART__ + +void DL_UART_init(UNICOMM_Inst_Regs *unicomm, DL_UART_Config *config) +{ + DL_UART_disable(unicomm); + + DL_Common_updateReg(&unicomm->uart->CTL0, + (uint32_t) config->mode | (uint32_t) config->direction | + (uint32_t) config->flowControl, + UNICOMMUART_CTL0_RXE_MASK | UNICOMMUART_CTL0_TXE_MASK | + UNICOMMUART_CTL0_MODE_MASK | UNICOMMUART_CTL0_RTSEN_MASK | + UNICOMMUART_CTL0_CTSEN_MASK); + + DL_Common_updateReg(&unicomm->uart->LCRH, + (uint32_t) config->parity | (uint32_t) config->wordLength | + (uint32_t) config->stopBits, + UNICOMMUART_LCRH_PEN_ENABLE | UNICOMMUART_LCRH_EPS_MASK | + UNICOMMUART_LCRH_SPS_MASK | UNICOMMUART_LCRH_WLEN_MASK | + UNICOMMUART_LCRH_STP2_MASK); +} + +void DL_UART_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_UART_ClockConfig *config) +{ + unicomm->uart->CLKSEL = (uint32_t) config->clockSel; + + unicomm->uart->CLKDIV = (uint32_t) config->divideRatio; +} + +void DL_UART_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_UART_ClockConfig *config) +{ + config->clockSel = (DL_UART_CLOCK) unicomm->uart->CLKSEL; + + config->divideRatio = (DL_UART_CLOCK_DIVIDE_RATIO) unicomm->uart->CLKDIV; +} + +void DL_UART_configBaudRate( + UNICOMM_Inst_Regs *unicomm, uint32_t clockFreq, uint32_t baudRate) +{ + uint32_t divisor; + + /* + * The baud rate divisor, brd, is calculated with the following formula: + * brd = ibrd.fbrd = clockOutput / (OVS * baudRate) + * where ibrd is the integer part, fbrd is the fractional part. + * Since fbrd is 6 bits, multiply brd by 64: + * 64 * brd = (clockOutput * 64) / (16 * baudRate) + * = (clockOutput * 4) / baudRate + * add 1/2 to round the least significant bit of fbrd: + * 64 * brd + 1/2 = (clockOutput * 8 / (2 * baudRate) + 1/2 + * divisor = 64*brd+1/2 = [(clockOutput * 8)/ baudRate + 1] / 2 + * + * The lower 6 bits is fbrd, upper part is ibrd + * Note: If ibrd is 0, FBRD will be ignored and no data will be + * transferred. + */ + + /* Calculate baud rate divisor based on OVS: */ + if ((baudRate * (uint32_t) 8) > clockFreq) { + DL_UART_setOversampling(unicomm, DL_UART_OVERSAMPLING_RATE_3X); + divisor = ((clockFreq * (uint32_t) 64) / (baudRate * (uint32_t) 3)) + + ((uint32_t) 1 / (uint32_t) 2); + + } else if ((baudRate * (uint32_t) 16) > clockFreq) { + DL_UART_setOversampling(unicomm, DL_UART_OVERSAMPLING_RATE_8X); + baudRate = baudRate / (uint32_t) 2; + divisor = (((clockFreq * (uint32_t) 8) / baudRate) + (uint32_t) 1) / + (uint32_t) 2; + + } else { + DL_UART_setOversampling(unicomm, DL_UART_OVERSAMPLING_RATE_16X); + divisor = (((clockFreq * (uint32_t) 8) / baudRate) + (uint32_t) 1) / + (uint32_t) 2; + } + + /* Set the integer and fractional parts of the baud rate divisor */ + DL_UART_setBaudRateDivisor( + unicomm, divisor >> (uint32_t) 6, divisor & (uint32_t) 0x3F); +} + +// TODO: Verify parameters and units +/** + * @brief Set the IrDA configurations + * + * Calculates the baud rate divisor given the clock output of the UNICOMM UART clock + * source and the target baud rate. This API also enables IrDA mode. + * + * @param[in] uart Pointer to the register overlay for the peripheral + * @param[in] polarity The receive input polarity. + * One of @DL_UART_IRDA_POLARITY. + * @param[in] pulseLength The length of the IrDA transmit pulse. + * @param[in] irdaClk The clock used for the transmit pulse. + * One of @DL_UART_IRDA_CLOCK. + */ +void DL_UART_configIrDAMode(UNICOMM_Inst_Regs *unicomm, + DL_UART_IRDA_POLARITY polarity, uint32_t pulseLength, + DL_UART_IRDA_CLOCK irdaClk) +{ + DL_Common_updateReg(&unicomm->uart->IRCTL, + (uint32_t) polarity | UNICOMMUART_IRCTL_IREN_ENABLE, + UNICOMMUART_IRCTL_IRRXPL_MASK | UNICOMMUART_IRCTL_IREN_MASK); + + DL_UART_setIrDAPulseLength(unicomm, pulseLength, irdaClk); +} + +void DL_UART_setIrDAPulseLength(UNICOMM_Inst_Regs *unicomm, + uint32_t pulseLength, DL_UART_IRDA_CLOCK irdaClk) +{ + uint32_t IRTXPL; + + if (pulseLength == DL_UART_PULSE_WIDTH_3_16_BIT_PERIOD) { + // Set IRTXCLK = 0 = BITCLK16 and IRTXPL = 5 + DL_Common_updateReg(&unicomm->uart->IRCTL, 0x14, + UNICOMMUART_IRCTL_IRTXCLK_MASK | UNICOMMUART_IRCTL_IRTXPL_MASK); + } else { + IRTXPL = + pulseLength * (uint32_t) 2 * (uint32_t) irdaClk - (uint32_t) 1; + + DL_Common_updateReg(&unicomm->uart->IRCTL, IRTXPL, + UNICOMMUART_IRCTL_IRTXCLK_MASK | UNICOMMUART_IRCTL_IRTXPL_MASK); + } +} + +uint8_t DL_UART_receiveDataBlocking(UNICOMM_Inst_Regs *unicomm) +{ + while (DL_UART_isRXFIFOEmpty(unicomm)) { + }; + + return DL_UART_receiveData(unicomm); +} + +void DL_UART_transmitDataBlocking(UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + while (DL_UART_isTXFIFOFull(unicomm)) { + }; + DL_UART_transmitData(unicomm, data); + while (DL_UART_isBusy(unicomm)) { + }; +} + +bool DL_UART_receiveDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t *buffer) +{ + bool status; + if (DL_UART_isRXFIFOEmpty(unicomm)) { + status = false; + } else { + *buffer = DL_UART_receiveData(unicomm); + status = true; + } + + return status; +} + +bool DL_UART_transmitDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + bool status; + if (DL_UART_isTXFIFOFull(unicomm)) { + status = false; + } else { + DL_UART_transmitData(unicomm, data); + status = true; + } + + return status; +} + +uint32_t DL_UART_drainRXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t maxCount) +{ + uint32_t i; + for (i = 0; i < maxCount; i++) { + if (!DL_UART_isRXFIFOEmpty(unicomm)) { + buffer[i] = DL_UART_receiveData(unicomm); + } else { + break; + } + } + + return i; +} + +uint32_t DL_UART_fillTXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) { + if (!DL_UART_isTXFIFOFull(unicomm)) { + DL_UART_transmitData(unicomm, buffer[i]); + } else { + break; + } + } + + return i; +} + +bool DL_UART_saveConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_UART_backupConfig *ptr) +{ + bool stateSaved = !ptr->backupRdy; + if (stateSaved) { + ptr->controlWord = unicomm->uart->CTL0; + ptr->clockSel = unicomm->uart->CLKSEL; + ptr->divideRatio = unicomm->uart->CLKDIV; + ptr->interruptFifoLevelSelectWord = unicomm->uart->IFLS; + ptr->ibrd = unicomm->uart->IBRD; + ptr->fbrd = unicomm->uart->FBRD; + ptr->lineControlRegisterWord = unicomm->uart->LCRH; + ptr->glitchFilterControlWord = unicomm->uart->GFCTL; + ptr->linControlWord = unicomm->uart->LINCTL; + ptr->irdaControlWord = unicomm->uart->IRCTL; + ptr->addressMask = unicomm->uart->AMASK; + ptr->address = unicomm->uart->ADDR; + ptr->interruptMask0 = unicomm->uart->CPU_INT.IMASK; + ptr->interruptMask1 = unicomm->uart->DMA_TRIG_RX.IMASK; + ptr->interruptMask2 = unicomm->uart->DMA_TRIG_TX.IMASK; + ptr->backupRdy = true; + } + return stateSaved; +} + +bool DL_UART_restoreConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_UART_backupConfig *ptr) +{ + bool stateRestored = ptr->backupRdy; + if (stateRestored) { + /* Set CTL0.ENABLE=0 during initialization */ + unicomm->uart->CTL0 = + ptr->controlWord & ~(UNICOMMUART_CTL0_ENABLE_MASK); + unicomm->uart->CLKSEL = ptr->clockSel; + unicomm->uart->CLKDIV = ptr->divideRatio; + unicomm->uart->IFLS = ptr->interruptFifoLevelSelectWord; + unicomm->uart->IBRD = ptr->ibrd; + unicomm->uart->FBRD = ptr->fbrd; + unicomm->uart->LCRH = ptr->lineControlRegisterWord; + unicomm->uart->GFCTL = ptr->glitchFilterControlWord; + unicomm->uart->LCRH = ptr->lineControlRegisterWord; + unicomm->uart->IRCTL = ptr->irdaControlWord; + unicomm->uart->AMASK = ptr->addressMask; + unicomm->uart->ADDR = ptr->address; + unicomm->uart->CPU_INT.IMASK = ptr->interruptMask0; + unicomm->uart->DMA_TRIG_RX.IMASK = ptr->interruptMask1; + unicomm->uart->DMA_TRIG_TX.IMASK = ptr->interruptMask2; + + /* Re-enable UNICOMM UART if it was originally enabled */ + if ((ptr->controlWord & UNICOMMUART_CTL0_ENABLE_MASK) == + UNICOMMUART_CTL0_ENABLE_MASK) { + DL_UART_enable(unicomm); + } + ptr->backupRdy = false; + } + return stateRestored; +} + +#endif /* __MCU_HAS_UNICOMMUART__ */ diff --git a/mspm0/source/ti/driverlib/dl_unicommuart.h b/mspm0/source/ti/driverlib/dl_unicommuart.h new file mode 100644 index 0000000..5b9af9f --- /dev/null +++ b/mspm0/source/ti/driverlib/dl_unicommuart.h @@ -0,0 +1,4010 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_unicommuart.h + * @brief Unified Communication Module (UNICOMM) - Universal Asynchronous Receiver/Transmitter (UART) Driver Library + * @defgroup UNICOMMUART Unified Communication Module (UNICOMM) - Universal Asynchronous Receiver/Transmitter (UART) + * + * @anchor ti_dl_dl_m0p_unicommuart_Overview + * # Overview + * + * The Unified Communication Module Universal Asynchronous Receiver/Transmitter + * Driver Library allows full configuration of the UNICOMM UART module. + * + * This Universal Asynchronous Receiver/Transmitter (UART) module provides a standardized + * interface to transfer data between devices and other external devices with + * an asynchronous serial communication protocol like LIN (local interconnection + * network), ISO7816 (Smart card protocol), IrDA (infrared data association), + * hardware flow control (CTS/RTS) and multiprocessor communications. + * + *
+ ****************************************************************************** + */ +/** @addtogroup UNICOMMUART + * @{ + */ +#ifndef ti_dl_dl_unicommuart__include +#define ti_dl_dl_unicommuart__include + +#include +#include + +#include +#include +#include + +#ifdef __MCU_HAS_UNICOMMUART__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_UART_EXTEND_MACROS + * Macros to retain compatibility with standalone dl_uart_extend APIs + * @{ + */ +/*! Redirects to @ref DL_UART_INTERRUPT_DMA_DONE_TX */ +#define DL_UART_EXTEND_INTERRUPT_DMA_DONE_TX DL_UART_INTERRUPT_DMA_DONE_TX +/*! Redirects to @ref DL_UART_INTERRUPT_DMA_DONE_RX */ +#define DL_UART_EXTEND_INTERRUPT_DMA_DONE_RX DL_UART_INTERRUPT_DMA_DONE_RX +/*! Redirects to @ref DL_UART_INTERRUPT_CTS_DONE */ +#define DL_UART_EXTEND_INTERRUPT_CTS_DONE DL_UART_INTERRUPT_CTS_DONE +/*! Redirects to @ref DL_UART_INTERRUPT_ADDRESS_MATCH */ +#define DL_UART_EXTEND_INTERRUPT_ADDRESS_MATCH DL_UART_INTERRUPT_ADDRESS_MATCH +/*! Redirects to @ref DL_UART_INTERRUPT_LINC0_MATCH */ +#define DL_UART_EXTEND_INTERRUPT_LINC0_MATCH DL_UART_INTERRUPT_LINC0_MATCH +/*! Redirects to @ref DL_UART_INTERRUPT_EOT_DONE */ +#define DL_UART_EXTEND_INTERRUPT_EOT_DONE DL_UART_INTERRUPT_EOT_DONE +/*! Redirects to @ref DL_UART_INTERRUPT_TX */ +#define DL_UART_EXTEND_INTERRUPT_TX DL_UART_INTERRUPT_TX +/*! Redirects to @ref DL_UART_INTERRUPT_RX */ +#define DL_UART_EXTEND_INTERRUPT_RX DL_UART_INTERRUPT_RX +/*! Redirects to @ref DL_UART_INTERRUPT_LIN_RISING_EDGE */ +#define DL_UART_EXTEND_INTERRUPT_LIN_RISING_EDGE DL_UART_INTERRUPT_LIN_RISING_EDGE +/*! Redirects to @ref DL_UART_INTERRUPT_LIN_FALLING_EDGE */ +#define DL_UART_EXTEND_INTERRUPT_LIN_FALLING_EDGE DL_UART_INTERRUPT_LIN_FALLING_EDGE +/*! Redirects to @ref DL_UART_INTERRUPT_RXD_POS_EDGE */ +#define DL_UART_EXTEND_INTERRUPT_RXD_POS_EDGE DL_UART_INTERRUPT_RXD_POS_EDGE +/*! Redirects to @ref DL_UART_INTERRUPT_RXD_NEG_EDGE */ +#define DL_UART_EXTEND_INTERRUPT_RXD_NEG_EDGE DL_UART_INTERRUPT_RXD_NEG_EDGE +/*! Redirects to @ref DL_UART_INTERRUPT_OVERRUN_ERROR */ +#define DL_UART_EXTEND_INTERRUPT_OVERRUN_ERROR DL_UART_INTERRUPT_OVERRUN_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_BREAK_ERROR */ +#define DL_UART_EXTEND_INTERRUPT_BREAK_ERROR DL_UART_INTERRUPT_BREAK_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_PARITY_ERROR */ +#define DL_UART_EXTEND_INTERRUPT_PARITY_ERROR DL_UART_INTERRUPT_PARITY_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_FRAMING_ERROR */ +#define DL_UART_EXTEND_INTERRUPT_FRAMING_ERROR DL_UART_INTERRUPT_FRAMING_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_RX_TIMEOUT_ERROR */ +#define DL_UART_EXTEND_INTERRUPT_RX_TIMEOUT_ERROR DL_UART_INTERRUPT_RX_TIMEOUT_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_NOISE_ERROR */ +#define DL_UART_EXTEND_INTERRUPT_NOISE_ERROR DL_UART_INTERRUPT_NOISE_ERROR +/*! Redirects to @ref DL_UART_IIDX_DMA_DONE_TX */ +#define DL_UART_EXTEND_IIDX_DMA_DONE_TX DL_UART_IIDX_DMA_DONE_TX +/*! Redirects to @ref DL_UART_IIDX_DMA_DONE_RX */ +#define DL_UART_EXTEND_IIDX_DMA_DONE_RX DL_UART_IIDX_DMA_DONE_RX +/*! Redirects to @ref DL_UART_IIDX_CTS_DONE */ +#define DL_UART_EXTEND_IIDX_CTS_DONE DL_UART_IIDX_CTS_DONE +/*! Redirects to @ref DL_UART_IIDX_EOT_DONE */ +#define DL_UART_EXTEND_IIDX_EOT_DONE DL_UART_IIDX_EOT_DONE +/*! Redirects to @ref DL_UART_IIDX_TX */ +#define DL_UART_EXTEND_IIDX_TX DL_UART_IIDX_TX +/*! Redirects to @ref DL_UART_IIDX_RX */ +#define DL_UART_EXTEND_IIDX_RX DL_UART_IIDX_RX +/*! Redirects to @ref DL_UART_IIDX_LIN_COUNTER_OVERFLOW */ +#define DL_UART_EXTEND_IIDX_LIN_COUNTER_OVERFLOW DL_UART_IIDX_LIN_COUNTER_OVERFLOW +/*! Redirects to @ref DL_UART_IIDX_LIN_RISING_EDGE */ +#define DL_UART_EXTEND_IIDX_LIN_RISING_EDGE DL_UART_IIDX_LIN_RISING_EDGE +/*! Redirects to @ref DL_UART_IIDX_LIN_FALLING_EDGE */ +#define DL_UART_EXTEND_IIDX_LIN_FALLING_EDGE DL_UART_IIDX_LIN_FALLING_EDGE +/*! Redirects to @ref DL_UART_IIDX_RXD_POS_EDGE */ +#define DL_UART_EXTEND_IIDX_RXD_POS_EDGE DL_UART_IIDX_RXD_POS_EDGE +/*! Redirects to @ref DL_UART_IIDX_RXD_NEG_EDGE */ +#define DL_UART_EXTEND_IIDX_RXD_NEG_EDGE DL_UART_IIDX_RXD_NEG_EDGE +/*! Redirects to @ref DL_UART_IIDX_OVERRUN_ERROR */ +#define DL_UART_EXTEND_IIDX_OVERRUN_ERROR DL_UART_IIDX_OVERRUN_ERROR +/*! Redirects to @ref DL_UART_IIDX_BREAK_ERROR */ +#define DL_UART_EXTEND_IIDX_BREAK_ERROR DL_UART_IIDX_BREAK_ERROR +/*! Redirects to @ref DL_UART_IIDX_PARITY_ERROR */ +#define DL_UART_EXTEND_IIDX_PARITY_ERROR DL_UART_IIDX_PARITY_ERROR +/*! Redirects to @ref DL_UART_IIDX_FRAMING_ERROR */ +#define DL_UART_EXTEND_IIDX_FRAMING_ERROR DL_UART_IIDX_FRAMING_ERROR +/*! Redirects to @ref DL_UART_IIDX_RX_TIMEOUT_ERROR */ +#define DL_UART_EXTEND_IIDX_RX_TIMEOUT_ERROR DL_UART_IIDX_RX_TIMEOUT_ERROR +/*! Redirects to @ref DL_UART_IIDX_NOISE_ERROR */ +#define DL_UART_EXTEND_IIDX_NOISE_ERROR DL_UART_IIDX_NOISE_ERROR +/*! Redirects to @ref DL_UART_IIDX_NO_INTERRUPT */ +#define DL_UART_EXTEND_IIDX_NO_INTERRUPT DL_UART_IIDX_NO_INTERRUPT +/*! Redirects to @ref DL_UART_DMA_INTERRUPT_RX */ +#define DL_UART_EXTEND_DMA_INTERRUPT_RX DL_UART_DMA_INTERRUPT_RX +/*! Redirects to @ref DL_UART_DMA_INTERRUPT_RX_TIMEOUT */ +#define DL_UART_EXTEND_DMA_INTERRUPT_RX_TIMEOUT DL_UART_DMA_INTERRUPT_RX_TIMEOUT +/*! Redirects to @ref DL_UART_DMA_INTERRUPT_TX */ +#define DL_UART_EXTEND_DMA_INTERRUPT_TX DL_UART_DMA_INTERRUPT_TX +/*! Redirects to @ref DL_UART_ERROR_OVERRUN */ +#define DL_UART_EXTEND_ERROR_OVERRUN DL_UART_ERROR_OVERRUN +/*! Redirects to @ref DL_UART_ERROR_BREAK */ +#define DL_UART_EXTEND_ERROR_BREAK DL_UART_ERROR_BREAK +/*! Redirects to @ref DL_UART_ERROR_PARITY */ +#define DL_UART_EXTEND_ERROR_PARITY DL_UART_ERROR_PARITY +/*! Redirects to @ref DL_UART_ERROR_FRAMING */ +#define DL_UART_EXTEND_ERROR_FRAMING DL_UART_ERROR_FRAMING +/*! Redirects to @ref DL_UART_OVERSAMPLING_RATE_16X */ +#define DL_UART_EXTEND_OVERSAMPLING_RATE_16X DL_UART_OVERSAMPLING_RATE_16X +/*! Redirects to @ref DL_UART_OVERSAMPLING_RATE_8X */ +#define DL_UART_EXTEND_OVERSAMPLING_RATE_8X DL_UART_OVERSAMPLING_RATE_8X +/*! Redirects to @ref DL_UART_OVERSAMPLING_RATE_3X */ +#define DL_UART_EXTEND_OVERSAMPLING_RATE_3X DL_UART_OVERSAMPLING_RATE_3X +/*! Redirects to @ref DL_UART_PARITY_EVEN */ +#define DL_UART_EXTEND_PARITY_EVEN DL_UART_PARITY_EVEN +/*! Redirects to @ref DL_UART_PARITY_ODD */ +#define DL_UART_EXTEND_PARITY_ODD DL_UART_PARITY_ODD +/*! Redirects to @ref DL_UART_PARITY_STICK_ONE */ +#define DL_UART_EXTEND_PARITY_STICK_ONE DL_UART_PARITY_STICK_ONE +/*! Redirects to @ref DL_UART_PARITY_STICK_ZERO */ +#define DL_UART_EXTEND_PARITY_STICK_ZERO DL_UART_PARITY_STICK_ZERO +/*! Redirects to @ref DL_UART_PARITY_NONE */ +#define DL_UART_EXTEND_PARITY_NONE DL_UART_PARITY_NONE +/*! Redirects to @ref DL_UART_WORD_LENGTH_5_BITS */ +#define DL_UART_EXTEND_WORD_LENGTH_5_BITS DL_UART_WORD_LENGTH_5_BITS +/*! Redirects to @ref DL_UART_WORD_LENGTH_6_BITS */ +#define DL_UART_EXTEND_WORD_LENGTH_6_BITS DL_UART_WORD_LENGTH_6_BITS +/*! Redirects to @ref DL_UART_WORD_LENGTH_7_BITS */ +#define DL_UART_EXTEND_WORD_LENGTH_7_BITS DL_UART_WORD_LENGTH_7_BITS +/*! Redirects to @ref DL_UART_WORD_LENGTH_8_BITS */ +#define DL_UART_EXTEND_WORD_LENGTH_8_BITS DL_UART_WORD_LENGTH_8_BITS +/*! Redirects to @ref DL_UART_MODE_NORMAL */ +#define DL_UART_EXTEND_MODE_NORMAL DL_UART_MODE_NORMAL +/*! Redirects to @ref DL_UART_MODE_RS485 */ +#define DL_UART_EXTEND_MODE_RS485 DL_UART_MODE_RS485 +/*! Redirects to @ref DL_UART_MODE_IDLE_LINE */ +#define DL_UART_EXTEND_MODE_IDLE_LINE DL_UART_MODE_IDLE_LINE +/*! Redirects to @ref DL_UART_MODE_ADDR_9_BIT */ +#define DL_UART_EXTEND_MODE_ADDR_9_BIT DL_UART_MODE_ADDR_9_BIT +/*! Redirects to @ref DL_UART_MODE_SMART_CARD */ +#define DL_UART_EXTEND_MODE_SMART_CARD DL_UART_MODE_SMART_CARD +/*! Redirects to @ref DL_UART_MODE_DALI */ +#define DL_UART_EXTEND_MODE_DALI DL_UART_MODE_DALI +/*! Redirects to @ref DL_UART_DIRECTION_TX */ +#define DL_UART_EXTEND_DIRECTION_TX DL_UART_DIRECTION_TX +/*! Redirects to @ref DL_UART_DIRECTION_RX */ +#define DL_UART_EXTEND_DIRECTION_RX DL_UART_DIRECTION_RX +/*! Redirects to @ref DL_UART_DIRECTION_TX_RX */ +#define DL_UART_EXTEND_DIRECTION_TX_RX DL_UART_DIRECTION_TX_RX +/*! Redirects to @ref DL_UART_DIRECTION_NONE */ +#define DL_UART_EXTEND_DIRECTION_NONE DL_UART_DIRECTION_NONE +/*! Redirects to @ref DL_UART_CLOCK_BUSCLK */ +#define DL_UART_EXTEND_CLOCK_BUSCLK DL_UART_CLOCK_BUSCLK +/*! Redirects to @ref DL_UART_CLOCK_MFCLK */ +#define DL_UART_EXTEND_CLOCK_MFCLK DL_UART_CLOCK_MFCLK +/*! Redirects to @ref DL_UART_CLOCK_LFCLK */ +#define DL_UART_EXTEND_CLOCK_LFCLK DL_UART_CLOCK_LFCLK +/*! Redirects to @ref DL_UART_FLOW_CONTROL_RTS */ +#define DL_UART_EXTEND_FLOW_CONTROL_RTS DL_UART_FLOW_CONTROL_RTS +/*! Redirects to @ref DL_UART_FLOW_CONTROL_CTS */ +#define DL_UART_EXTEND_FLOW_CONTROL_CTS DL_UART_FLOW_CONTROL_CTS +/*! Redirects to @ref DL_UART_FLOW_CONTROL_RTS_CTS */ +#define DL_UART_EXTEND_FLOW_CONTROL_RTS_CTS DL_UART_FLOW_CONTROL_RTS_CTS +/*! Redirects to @ref DL_UART_FLOW_CONTROL_NONE */ +#define DL_UART_EXTEND_FLOW_CONTROL_NONE DL_UART_FLOW_CONTROL_NONE +/*! Redirects to @ref DL_UART_RTS_ASSERT */ +#define DL_UART_EXTEND_RTS_ASSERT DL_UART_RTS_ASSERT +/*! Redirects to @ref DL_UART_RTS_DEASSERT */ +#define DL_UART_EXTEND_RTS_DEASSERT DL_UART_RTS_DEASSERT +/*! Redirects to @ref DL_UART_STOP_BITS_ONE */ +#define DL_UART_EXTEND_STOP_BITS_ONE DL_UART_STOP_BITS_ONE +/*! Redirects to @ref DL_UART_STOP_BITS_TWO */ +#define DL_UART_EXTEND_STOP_BITS_TWO DL_UART_STOP_BITS_TWO +/*! Redirects to @ref DL_UART_TXD_OUT_LOW */ +#define DL_UART_EXTEND_TXD_OUT_LOW DL_UART_TXD_OUT_LOW +/*! Redirects to @ref DL_UART_TXD_OUT_HIGH */ +#define DL_UART_EXTEND_TXD_OUT_HIGH DL_UART_TXD_OUT_HIGH +/*! Redirects to @ref DL_UART_TX_FIFO_LEVEL_3_4_EMPTY */ +#define DL_UART_EXTEND_TX_FIFO_LEVEL_3_4_EMPTY DL_UART_TX_FIFO_LEVEL_3_4_EMPTY +/*! Redirects to @ref DL_UART_TX_FIFO_LEVEL_1_4_EMPTY */ +#define DL_UART_EXTEND_TX_FIFO_LEVEL_1_4_EMPTY DL_UART_TX_FIFO_LEVEL_1_4_EMPTY +/*! Redirects to @ref DL_UART_TX_FIFO_LEVEL_EMPTY */ +#define DL_UART_EXTEND_TX_FIFO_LEVEL_EMPTY DL_UART_TX_FIFO_LEVEL_EMPTY +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_FULL */ +#define DL_UART_EXTEND_RX_FIFO_LEVEL_FULL DL_UART_RX_FIFO_LEVEL_FULL +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_3_4_FULL */ +#define DL_UART_EXTEND_RX_FIFO_LEVEL_3_4_FULL DL_UART_RX_FIFO_LEVEL_3_4_FULL +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_1_2_FULL */ +#define DL_UART_EXTEND_RX_FIFO_LEVEL_1_2_FULL DL_UART_RX_FIFO_LEVEL_1_2_FULL +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_1_4_FULL */ +#define DL_UART_EXTEND_RX_FIFO_LEVEL_1_4_FULL DL_UART_RX_FIFO_LEVEL_1_4_FULL +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_1 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_1 DL_UART_CLOCK_DIVIDE_RATIO_1 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_2 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_2 DL_UART_CLOCK_DIVIDE_RATIO_2 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_3 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_3 DL_UART_CLOCK_DIVIDE_RATIO_3 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_4 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_4 DL_UART_CLOCK_DIVIDE_RATIO_4 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_5 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_5 DL_UART_CLOCK_DIVIDE_RATIO_5 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_6 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_6 DL_UART_CLOCK_DIVIDE_RATIO_6 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_7 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_7 DL_UART_CLOCK_DIVIDE_RATIO_7 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_8 */ +#define DL_UART_EXTEND_CLOCK_DIVIDE_RATIO_8 DL_UART_CLOCK_DIVIDE_RATIO_8 +/*! Redirects to @ref DL_UART_INTERRUPT_LIN_COUNTER_OVERFLOW */ +#define DL_UART_EXTEND_INTERRUPT_LIN_COUNTER_OVERFLOW DL_UART_INTERRUPT_LIN_COUNTER_OVERFLOW +/*! Redirects to @ref DL_UART_INTERRUPT_LIN_RISING_EDGE */ +#define DL_UART_EXTEND_INTERRUPT_LIN_RISING_EDGE DL_UART_INTERRUPT_LIN_RISING_EDGE +/*! Redirects to @ref DL_UART_INTERRUPT_LIN_FALLING_EDGE */ +#define DL_UART_EXTEND_INTERRUPT_LIN_FALLING_EDGE DL_UART_INTERRUPT_LIN_FALLING_EDGE +/*! Redirects to @ref DL_UART_IRDA_CLOCK_BAUD_RATE */ +#define DL_UART_EXTEND_IRDA_CLOCK_BAUD_RATE DL_UART_IRDA_CLOCK_BAUD_RATE +/*! Redirects to @ref DL_UART_IRDA_CLOCK_FUNCTIONAL */ +#define DL_UART_EXTEND_IRDA_CLOCK_FUNCTIONAL DL_UART_IRDA_CLOCK_FUNCTIONAL +/*! Redirects to @ref DL_UART_IRDA_POLARITY_LOW */ +#define DL_UART_EXTEND_IRDA_POLARITY_LOW DL_UART_IRDA_POLARITY_LOW +/*! Redirects to @ref DL_UART_IRDA_POLARITY_HIGH */ +#define DL_UART_EXTEND_IRDA_POLARITY_HIGH DL_UART_IRDA_POLARITY_HIGH +/*! Redirects to @ref DL_UART_PULSE_WIDTH_3_16_BIT_PERIOD */ +#define DL_UART_EXTEND_PULSE_WIDTH_3_16_BIT_PERIOD DL_UART_PULSE_WIDTH_3_16_BIT_PERIOD +/*! Redirects to @ref DL_UART_Config */ +#define DL_UART_Extend_Config DL_UART_Config +/*! Redirects to @ref DL_UART_ClockConfig */ +#define DL_UART_Extend_ClockConfig DL_UART_ClockConfig +/*! Redirects to @ref DL_UART_init */ +#define DL_UART_Extend_init DL_UART_init +/*! Redirects to @ref DL_UART_enablePower */ +#define DL_UART_Extend_enablePower DL_UART_enablePower +/*! Redirects to @ref DL_UART_disablePower */ +#define DL_UART_Extend_disablePower DL_UART_disablePower +/*! Redirects to @ref DL_UART_isPowerEnabled */ +#define DL_UART_Extend_isPowerEnabled DL_UART_isPowerEnabled +/*! Redirects to @ref DL_UART_reset */ +#define DL_UART_Extend_reset DL_UART_reset +/*! Redirects to @ref DL_UART_enable */ +#define DL_UART_Extend_enable DL_UART_enable +/*! Redirects to @ref DL_UART_isEnabled */ +#define DL_UART_Extend_isEnabled DL_UART_isEnabled +/*! Redirects to @ref DL_UART_disable */ +#define DL_UART_Extend_disable DL_UART_disable +/*! Redirects to @ref DL_UART_setClockConfig */ +#define DL_UART_Extend_setClockConfig DL_UART_setClockConfig +/*! Redirects to @ref DL_UART_getClockConfig */ +#define DL_UART_Extend_getClockConfig DL_UART_getClockConfig +/*! Redirects to @ref DL_UART_configBaudRate */ +#define DL_UART_Extend_configBaudRate DL_UART_configBaudRate +/*! Redirects to @ref DL_UART_setOversampling */ +#define DL_UART_Extend_setOversampling DL_UART_setOversampling +/*! Redirects to @ref DL_UART_getOversampling */ +#define DL_UART_Extend_getOversampling DL_UART_getOversampling +/*! Redirects to @ref DL_UART_enableLoopbackMode */ +#define DL_UART_Extend_enableLoopbackMode DL_UART_enableLoopbackMode +/*! Redirects to @ref DL_UART_isLoopbackModeEnabled */ +#define DL_UART_Extend_isLoopbackModeEnabled DL_UART_isLoopbackModeEnabled +/*! Redirects to @ref DL_UART_disableLoopbackMode */ +#define DL_UART_Extend_disableLoopbackMode DL_UART_disableLoopbackMode +/*! Redirects to @ref DL_UART_setDirection */ +#define DL_UART_Extend_setDirection DL_UART_setDirection +/*! Redirects to @ref DL_UART_getDirection */ +#define DL_UART_Extend_getDirection DL_UART_getDirection +/*! Redirects to @ref DL_UART_enableMajorityVoting */ +#define DL_UART_Extend_enableMajorityVoting DL_UART_enableMajorityVoting +/*! Redirects to @ref DL_UART_isMajorityVotingEnabled */ +#define DL_UART_Extend_isMajorityVotingEnabled DL_UART_isMajorityVotingEnabled +/*! Redirects to @ref DL_UART_disableMajorityVoting */ +#define DL_UART_Extend_disableMajorityVoting DL_UART_disableMajorityVoting +/*! Redirects to @ref DL_UART_enableMSBFirst */ +#define DL_UART_Extend_enableMSBFirst DL_UART_enableMSBFirst +/*! Redirects to @ref DL_UART_isMSBFirstEnabled */ +#define DL_UART_Extend_isMSBFirstEnabled DL_UART_isMSBFirstEnabled +/*! Redirects to @ref DL_UART_disableMSBFirst */ +#define DL_UART_Extend_disableMSBFirst DL_UART_disableMSBFirst +/*! Redirects to @ref DL_UART_enableTransmitPinManualControl */ +#define DL_UART_Extend_enableTransmitPinManualContro DL_UART_enableTransmitPinManualControl +/*! Redirects to @ref DL_UART_isTransmitPinManualControlEnabled */ +#define DL_UART_Extend_isTransmitPinManualControlEna DL_UART_isTransmitPinManualControlEnabled +/*! Redirects to @ref DL_UART_disableTransmitPinManualControl */ +#define DL_UART_Extend_disableTransmitPinManualContr DL_UART_disableTransmitPinManualControl +/*! Redirects to @ref DL_UART_setTransmitPinManualOutput */ +#define DL_UART_Extend_setTransmitPinManualOutput DL_UART_setTransmitPinManualOutput +/*! Redirects to @ref DL_UART_getTransmitPinManualOutput */ +#define DL_UART_Extend_getTransmitPinManualOutput DL_UART_getTransmitPinManualOutput +/*! Redirects to @ref DL_UART_setCommunicationMode */ +#define DL_UART_Extend_setCommunicationMode DL_UART_setCommunicationMode +/*! Redirects to @ref DL_UART_getCommunicationMode */ +#define DL_UART_Extend_getCommunicationMode DL_UART_getCommunicationMode +/*! Redirects to @ref DL_UART_setFlowControl */ +#define DL_UART_Extend_setFlowControl DL_UART_setFlowControl +/*! Redirects to @ref DL_UART_getFlowControl */ +#define DL_UART_Extend_getFlowControl DL_UART_getFlowControl +/*! Redirects to @ref DL_UART_setRTSOutput */ +#define DL_UART_Extend_setRTSOutput DL_UART_setRTSOutput +/*! Redirects to @ref DL_UART_enableFIFOs */ +#define DL_UART_Extend_enableFIFOs DL_UART_enableFIFOs +/*! Redirects to @ref DL_UART_disableFIFOs */ +#define DL_UART_Extend_disableFIFOs DL_UART_disableFIFOs +/*! Redirects to @ref DL_UART_isFIFOsEnabled */ +#define DL_UART_Extend_isFIFOsEnabled DL_UART_isFIFOsEnabled +/*! Redirects to @ref DL_UART_isParityEnabled */ +#define DL_UART_Extend_isParityEnabled DL_UART_isParityEnabled +/*! Redirects to @ref DL_UART_setParityMode */ +#define DL_UART_Extend_setParityMode DL_UART_setParityMode +/*! Redirects to @ref DL_UART_getParityMode */ +#define DL_UART_Extend_getParityMode DL_UART_getParityMode +/*! Redirects to @ref DL_UART_setStopBits */ +#define DL_UART_Extend_setStopBits DL_UART_setStopBits +/*! Redirects to @ref DL_UART_getStopBits */ +#define DL_UART_Extend_getStopBits DL_UART_getStopBits +/*! Redirects to @ref DL_UART_setWordLength */ +#define DL_UART_Extend_setWordLength DL_UART_setWordLength +/*! Redirects to @ref DL_UART_getWordLength */ +#define DL_UART_Extend_getWordLength DL_UART_getWordLength +/*! Redirects to @ref DL_UART_enableSendIdlePattern */ +#define DL_UART_Extend_enableSendIdlePattern DL_UART_enableSendIdlePattern +/*! Redirects to @ref DL_UART_disableSendIdlePattern */ +#define DL_UART_Extend_disableSendIdlePattern DL_UART_disableSendIdlePattern +/*! Redirects to @ref DL_UART_isSendIdlePatternEnabled */ +#define DL_UART_Extend_isSendIdlePatternEnabled DL_UART_isSendIdlePatternEnabled +/*! Redirects to @ref DL_UART_setExternalDriverSetup */ +#define DL_UART_Extend_setExternalDriverSetup DL_UART_setExternalDriverSetup +/*! Redirects to @ref DL_UART_getExternalDriverSetup */ +#define DL_UART_Extend_getExternalDriverSetup DL_UART_getExternalDriverSetup +/*! Redirects to @ref DL_UART_setExternalDriverHold */ +#define DL_UART_Extend_setExternalDriverHold DL_UART_setExternalDriverHold +/*! Redirects to @ref DL_UART_getExternalDriverHold */ +#define DL_UART_Extend_getExternalDriverHold DL_UART_getExternalDriverHold +/*! Redirects to @ref DL_UART_isBusy */ +#define DL_UART_Extend_isBusy DL_UART_isBusy +/*! Redirects to @ref DL_UART_isRXFIFOEmpty */ +#define DL_UART_Extend_isRXFIFOEmpty DL_UART_isRXFIFOEmpty +/*! Redirects to @ref DL_UART_isRXFIFOFull */ +#define DL_UART_Extend_isRXFIFOFull DL_UART_isRXFIFOFull +/*! Redirects to @ref DL_UART_isTXFIFOEmpty */ +#define DL_UART_Extend_isTXFIFOEmpty DL_UART_isTXFIFOEmpty +/*! Redirects to @ref DL_UART_isTXFIFOFull */ +#define DL_UART_Extend_isTXFIFOFull DL_UART_isTXFIFOFull +/*! Redirects to @ref DL_UART_isClearToSend */ +#define DL_UART_Extend_isClearToSend DL_UART_isClearToSend +/*! Redirects to @ref DL_UART_isIdleModeDetected */ +#define DL_UART_Extend_isIdleModeDetected DL_UART_isIdleModeDetected +/*! Redirects to @ref DL_UART_setTXFIFOThreshold */ +#define DL_UART_Extend_setTXFIFOThreshold DL_UART_setTXFIFOThreshold +/*! Redirects to @ref DL_UART_getTXFIFOThreshold */ +#define DL_UART_Extend_getTXFIFOThreshold DL_UART_getTXFIFOThreshold +/*! Redirects to @ref DL_UART_setRXFIFOThreshold */ +#define DL_UART_Extend_setRXFIFOThreshold DL_UART_setRXFIFOThreshold +/*! Redirects to @ref DL_UART_getRXFIFOThreshold */ +#define DL_UART_Extend_getRXFIFOThreshold DL_UART_getRXFIFOThreshold +/*! Redirects to @ref DL_UART_setRXInterruptTimeout */ +#define DL_UART_Extend_setRXInterruptTimeout DL_UART_setRXInterruptTimeout +/*! Redirects to @ref DL_UART_getRXInterruptTimeout */ +#define DL_UART_Extend_getRXInterruptTimeout DL_UART_getRXInterruptTimeout +/*! Redirects to @ref DL_UART_getIntegerBaudRateDivisor */ +#define DL_UART_Extend_getIntegerBaudRateDivisor DL_UART_getIntegerBaudRateDivisor +/*! Redirects to @ref DL_UART_getFractionalBaudRateDivisor */ +#define DL_UART_Extend_getFractionalBaudRateDivisor DL_UART_getFractionalBaudRateDivisor +/*! Redirects to @ref DL_UART_setBaudRateDivisor */ +#define DL_UART_Extend_setBaudRateDivisor DL_UART_setBaudRateDivisor +/*! Redirects to @ref DL_UART_transmitData */ +#define DL_UART_Extend_transmitData DL_UART_transmitData +/*! Redirects to @ref DL_UART_receiveData */ +#define DL_UART_Extend_receiveData DL_UART_receiveData +/*! Redirects to @ref DL_UART_getErrorStatus */ +#define DL_UART_Extend_getErrorStatus DL_UART_getErrorStatus +/*! Redirects to @ref DL_UART_enableInterrupt */ +#define DL_UART_Extend_enableInterrupt DL_UART_enableInterrupt +/*! Redirects to @ref DL_UART_disableInterrupt */ +#define DL_UART_Extend_disableInterrupt DL_UART_disableInterrupt +/*! Redirects to @ref DL_UART_getEnabledInterrupts */ +#define DL_UART_Extend_getEnabledInterrupts DL_UART_getEnabledInterrupts +/*! Redirects to @ref DL_UART_getEnabledInterruptStatus */ +#define DL_UART_Extend_getEnabledInterruptStatus DL_UART_getEnabledInterruptStatus +/*! Redirects to @ref DL_UART_getRawInterruptStatus */ +#define DL_UART_Extend_getRawInterruptStatus DL_UART_getRawInterruptStatus +/*! Redirects to @ref DL_UART_getPendingInterrupt */ +#define DL_UART_Extend_getPendingInterrupt DL_UART_getPendingInterrupt +/*! Redirects to @ref DL_UART_clearInterruptStatus */ +#define DL_UART_Extend_clearInterruptStatus DL_UART_clearInterruptStatus +/*! Redirects to @ref DL_UART_changeConfig */ +#define DL_UART_Extend_changeConfig DL_UART_changeConfig +/*! Redirects to @ref DL_UART_transmitDataBlocking */ +#define DL_UART_Extend_transmitDataBlocking DL_UART_transmitDataBlocking +/*! Redirects to @ref DL_UART_receiveDataBlocking */ +#define DL_UART_Extend_receiveDataBlocking DL_UART_receiveDataBlocking +/*! Redirects to @ref DL_UART_transmitDataCheck */ +#define DL_UART_Extend_transmitDataCheck DL_UART_transmitDataCheck +/*! Redirects to @ref DL_UART_receiveDataCheck */ +#define DL_UART_Extend_receiveDataCheck DL_UART_receiveDataCheck +/*! Redirects to @ref DL_UART_drainRXFIFO */ +#define DL_UART_Extend_drainRXFIFO DL_UART_drainRXFIFO +/*! Redirects to @ref DL_UART_fillTXFIFO */ +#define DL_UART_Extend_fillTXFIFO DL_UART_fillTXFIFO +/*! Redirects to @ref DL_UART_enableDMAReceiveEvent */ +#define DL_UART_Extend_enableDMAReceiveEvent DL_UART_enableDMAReceiveEvent +/*! Redirects to @ref DL_UART_enableDMATransmitEvent */ +#define DL_UART_Extend_enableDMATransmitEvent DL_UART_enableDMATransmitEvent +/*! Redirects to @ref DL_UART_disableDMAReceiveEvent */ +#define DL_UART_Extend_disableDMAReceiveEvent DL_UART_disableDMAReceiveEvent +/*! Redirects to @ref DL_UART_disableDMATransmitEvent */ +#define DL_UART_Extend_disableDMATransmitEvent DL_UART_disableDMATransmitEvent +/*! Redirects to @ref DL_UART_getEnabledDMAReceiveEvent */ +#define DL_UART_Extend_getEnabledDMAReceiveEvent DL_UART_getEnabledDMAReceiveEvent +/*! Redirects to @ref DL_UART_getEnabledDMATransmitEvent */ +#define DL_UART_Extend_getEnabledDMATransmitEvent DL_UART_getEnabledDMATransmitEvent +/*! Redirects to @ref DL_UART_getEnabledDMAReceiveEventStatus */ +#define DL_UART_Extend_getEnabledDMAReceiveEventStat DL_UART_getEnabledDMAReceiveEventStatus +/*! Redirects to @ref DL_UART_getEnabledDMATransmitEventStatus */ +#define DL_UART_Extend_getEnabledDMATransmitEventSta DL_UART_getEnabledDMATransmitEventStatus +/*! Redirects to @ref DL_UART_getRawDMAReceiveEventStatus */ +#define DL_UART_Extend_getRawDMAReceiveEventStatus DL_UART_getRawDMAReceiveEventStatus +/*! Redirects to @ref DL_UART_getRawDMATransmitEventStatus */ +#define DL_UART_Extend_getRawDMATransmitEventStatus DL_UART_getRawDMATransmitEventStatus +/*! Redirects to @ref DL_UART_setLINCounterValue */ +#define DL_UART_Extend_setLINCounterValue DL_UART_setLINCounterValue +/*! Redirects to @ref DL_UART_getLINCounterValue */ +#define DL_UART_Extend_getLINCounterValue DL_UART_getLINCounterValue +/*! Redirects to @ref DL_UART_enableLINCounter */ +#define DL_UART_Extend_enableLINCounter DL_UART_enableLINCounter +/*! Redirects to @ref DL_UART_isLINCounterEnabled */ +#define DL_UART_Extend_isLINCounterEnabled DL_UART_isLINCounterEnabled +/*! Redirects to @ref DL_UART_disableLINCounter */ +#define DL_UART_Extend_disableLINCounter DL_UART_disableLINCounter +/*! Redirects to @ref DL_UART_enableLINCounterClearOnFallingEdge */ +#define DL_UART_Extend_enableLINCounterClearOnFallin DL_UART_enableLINCounterClearOnFallingEdge +/*! Redirects to @ref DL_UART_isLINCounterClearOnFallingEdge */ +#define DL_UART_Extend_isLINCounterClearOnFallingEdg DL_UART_isLINCounterClearOnFallingEdge +/*! Redirects to @ref DL_UART_disableLINCounterClearOnFallingEdge */ +#define DL_UART_Extend_disableLINCounterClearOnFalli DL_UART_disableLINCounterClearOnFallingEdge +/*! Redirects to @ref DL_UART_enableLINCountWhileLow */ +#define DL_UART_Extend_enableLINCountWhileLow DL_UART_enableLINCountWhileLow +/*! Redirects to @ref DL_UART_isLINCountWhileLowEnabled */ +#define DL_UART_Extend_isLINCountWhileLowEnabled DL_UART_isLINCountWhileLowEnabled +/*! Redirects to @ref DL_UART_disableLINCountWhileLow */ +#define DL_UART_Extend_disableLINCountWhileLow DL_UART_disableLINCountWhileLow +/*! Redirects to @ref DL_UART_enableLINFallingEdgeCapture */ +#define DL_UART_Extend_enableLINFallingEdgeCapture DL_UART_enableLINFallingEdgeCapture +/*! Redirects to @ref DL_UART_isLINFallingEdgeCaptureEnabled */ +#define DL_UART_Extend_isLINFallingEdgeCaptureEnable DL_UART_isLINFallingEdgeCaptureEnabled +/*! Redirects to @ref DL_UART_disableLINFallingEdgeCapture */ +#define DL_UART_Extend_disableLINFallingEdgeCapture DL_UART_disableLINFallingEdgeCapture +/*! Redirects to @ref DL_UART_enableLINRisingEdgeCapture */ +#define DL_UART_Extend_enableLINRisingEdgeCapture DL_UART_enableLINRisingEdgeCapture +/*! Redirects to @ref DL_UART_isLINRisingEdgeCaptureEnabled */ +#define DL_UART_Extend_isLINRisingEdgeCaptureEnabled DL_UART_isLINRisingEdgeCaptureEnabled +/*! Redirects to @ref DL_UART_disableLINRisingEdgeCapture */ +#define DL_UART_Extend_disableLINRisingEdgeCapture DL_UART_disableLINRisingEdgeCapture +/*! Redirects to @ref DL_UART_enableLINCounterCompareMatch */ +#define DL_UART_Extend_enableLINCounterCompareMatch DL_UART_enableLINCounterCompareMatch +/*! Redirects to @ref DL_UART_enableLINSyncFieldValidationCounterControl */ +#define DL_UART_Extend_enableLINSyncFieldValidationC DL_UART_enableLINSyncFieldValidationCounterControl +/*! Redirects to @ref DL_UART_enableLINReceptionCountControl */ +#define DL_UART_Extend_enableLINReceptionCountContro DL_UART_enableLINReceptionCountControl +/*! Redirects to @ref DL_UART_isLINCounterCompareMatchEnabled */ +#define DL_UART_Extend_isLINCounterCompareMatchEnabl DL_UART_isLINCounterCompareMatchEnabled +/*! Redirects to @ref DL_UART_disableLINCounterCompareMatch */ +#define DL_UART_Extend_disableLINCounterCompareMatch DL_UART_disableLINCounterCompareMatch +/*! Redirects to @ref DL_UART_setLINCounterCompareValue */ +#define DL_UART_Extend_setLINCounterCompareValue DL_UART_setLINCounterCompareValue +/*! Redirects to @ref DL_UART_getLINFallingEdgeCaptureValue */ +#define DL_UART_Extend_getLINFallingEdgeCaptureValue DL_UART_getLINFallingEdgeCaptureValue +/*! Redirects to @ref DL_UART_getLINRisingEdgeCaptureValue */ +#define DL_UART_Extend_getLINRisingEdgeCaptureValue DL_UART_getLINRisingEdgeCaptureValue +/*! Redirects to @ref DL_UART_enableLINSendBreak */ +#define DL_UART_Extend_enableLINSendBreak DL_UART_enableLINSendBreak +/*! Redirects to @ref DL_UART_disableLINSendBreak */ +#define DL_UART_Extend_disableLINSendBreak DL_UART_disableLINSendBreak +/*! Redirects to @ref DL_UART_isLINSendBreakEnabled */ +#define DL_UART_Extend_isLINSendBreakEnabled DL_UART_isLINSendBreakEnabled +/*! Redirects to @ref DL_UART_enableIrDAMode */ +#define DL_UART_Extend_enableIrDAMode DL_UART_enableIrDAMode +/*! Redirects to @ref DL_UART_isIrDAModeEnabled */ +#define DL_UART_Extend_isIrDAModeEnabled DL_UART_isIrDAModeEnabled +/*! Redirects to @ref DL_UART_disableIrDAMode */ +#define DL_UART_Extend_disableIrDAMode DL_UART_disableIrDAMode +/*! Redirects to @ref DL_UART_setIrDATXPulseClockSelect */ +#define DL_UART_Extend_setIrDATXPulseClockSelect DL_UART_setIrDATXPulseClockSelect +/*! Redirects to @ref DL_UART_getIrDATXPulseClockSelect */ +#define DL_UART_Extend_getIrDATXPulseClockSelect DL_UART_getIrDATXPulseClockSelect +/*! Redirects to @ref DL_UART_configIrDAMode */ +#define DL_UART_Extend_configIrDAMode DL_UART_configIrDAMode +/*! Redirects to @ref DL_UART_setIrDAPulseLength */ +#define DL_UART_Extend_setIrDAPulseLength DL_UART_setIrDAPulseLength +/*! Redirects to @ref DL_UART_getIrDATXPulseLength */ +#define DL_UART_Extend_getIrDATXPulseLength DL_UART_getIrDATXPulseLength +/*! Redirects to @ref DL_UART_setIrDARXPulsePolarity */ +#define DL_UART_Extend_setIrDARXPulsePolarity DL_UART_setIrDARXPulsePolarity +/*! Redirects to @ref DL_UART_getIrDARXPulsePolarity */ +#define DL_UART_Extend_getIrDARXPulsePolarity DL_UART_getIrDARXPulsePolarity +/*! Redirects to @ref DL_UART_setDigitalPulseWidth */ +#define DL_UART_Extend_setDigitalPulseWidth DL_UART_setDigitalPulseWidth +/*! Redirects to @ref DL_UART_getDigitalPulseWidth */ +#define DL_UART_Extend_getDigitalPulseWidth DL_UART_getDigitalPulseWidth +/*! Redirects to @ref DL_UART_setAddressMask */ +#define DL_UART_Extend_setAddressMask DL_UART_setAddressMask +/*! Redirects to @ref DL_UART_getAddressMask */ +#define DL_UART_Extend_getAddressMask DL_UART_getAddressMask +/*! Redirects to @ref DL_UART_setAddress */ +#define DL_UART_Extend_setAddress DL_UART_setAddress +/*! Redirects to @ref DL_UART_getAddress */ +#define DL_UART_Extend_getAddress DL_UART_getAddress +/*! Redirects to @ref DL_UART_enableManchesterEncoding */ +#define DL_UART_Extend_enableManchesterEncoding DL_UART_enableManchesterEncoding +/*! Redirects to @ref DL_UART_disableManchesterEncoding */ +#define DL_UART_Extend_disableManchesterEncoding DL_UART_disableManchesterEncoding +/*! Redirects to @ref DL_UART_isManchesterEncodingEnabled */ +#define DL_UART_Extend_isManchesterEncodingEnabled DL_UART_isManchesterEncodingEnabled +/** @}*/ + +/** @addtogroup DL_UART_MAIN_MACROS + * Macros to retain compatibility with standalone dl_uart_main APIs + * @{ + */ +/*! Redirects to @ref DL_UART_INTERRUPT_DMA_DONE_TX */ +#define DL_UART_MAIN_INTERRUPT_DMA_DONE_TX DL_UART_INTERRUPT_DMA_DONE_TX +/*! Redirects to @ref DL_UART_INTERRUPT_DMA_DONE_RX */ +#define DL_UART_MAIN_INTERRUPT_DMA_DONE_RX DL_UART_INTERRUPT_DMA_DONE_RX +/*! Redirects to @ref DL_UART_INTERRUPT_CTS_DONE */ +#define DL_UART_MAIN_INTERRUPT_CTS_DONE DL_UART_INTERRUPT_CTS_DONE +/*! Redirects to @ref DL_UART_INTERRUPT_EOT_DONE */ +#define DL_UART_MAIN_INTERRUPT_EOT_DONE DL_UART_INTERRUPT_EOT_DONE +/*! Redirects to @ref DL_UART_INTERRUPT_TX */ +#define DL_UART_MAIN_INTERRUPT_TX DL_UART_INTERRUPT_TX +/*! Redirects to @ref DL_UART_INTERRUPT_RX */ +#define DL_UART_MAIN_INTERRUPT_RX DL_UART_INTERRUPT_RX +/*! Redirects to @ref DL_UART_INTERRUPT_RXD_POS_EDGE */ +#define DL_UART_MAIN_INTERRUPT_RXD_POS_EDGE DL_UART_INTERRUPT_RXD_POS_EDGE +/*! Redirects to @ref DL_UART_INTERRUPT_RXD_NEG_EDGE */ +#define DL_UART_MAIN_INTERRUPT_RXD_NEG_EDGE DL_UART_INTERRUPT_RXD_NEG_EDGE +/*! Redirects to @ref DL_UART_INTERRUPT_OVERRUN_ERROR */ +#define DL_UART_MAIN_INTERRUPT_OVERRUN_ERROR DL_UART_INTERRUPT_OVERRUN_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_BREAK_ERROR */ +#define DL_UART_MAIN_INTERRUPT_BREAK_ERROR DL_UART_INTERRUPT_BREAK_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_PARITY_ERROR */ +#define DL_UART_MAIN_INTERRUPT_PARITY_ERROR DL_UART_INTERRUPT_PARITY_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_FRAMING_ERROR */ +#define DL_UART_MAIN_INTERRUPT_FRAMING_ERROR DL_UART_INTERRUPT_FRAMING_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_RX_TIMEOUT_ERROR */ +#define DL_UART_MAIN_INTERRUPT_RX_TIMEOUT_ERROR DL_UART_INTERRUPT_RX_TIMEOUT_ERROR +/*! Redirects to @ref DL_UART_INTERRUPT_NOISE_ERROR */ +#define DL_UART_MAIN_INTERRUPT_NOISE_ERROR DL_UART_INTERRUPT_NOISE_ERROR +/*! Redirects to @ref DL_UART_IIDX_DMA_DONE_TX */ +#define DL_UART_MAIN_IIDX_DMA_DONE_TX DL_UART_IIDX_DMA_DONE_TX +/*! Redirects to @ref DL_UART_IIDX_DMA_DONE_RX */ +#define DL_UART_MAIN_IIDX_DMA_DONE_RX DL_UART_IIDX_DMA_DONE_RX +/*! Redirects to @ref DL_UART_IIDX_CTS_DONE */ +#define DL_UART_MAIN_IIDX_CTS_DONE DL_UART_IIDX_CTS_DONE +/*! Redirects to @ref DL_UART_IIDX_EOT_DONE */ +#define DL_UART_MAIN_IIDX_EOT_DONE DL_UART_IIDX_EOT_DONE +/*! Redirects to @ref DL_UART_IIDX_TX */ +#define DL_UART_MAIN_IIDX_TX DL_UART_IIDX_TX +/*! Redirects to @ref DL_UART_IIDX_RX */ +#define DL_UART_MAIN_IIDX_RX DL_UART_IIDX_RX +/*! Redirects to @ref DL_UART_IIDX_RXD_POS_EDGE */ +#define DL_UART_MAIN_IIDX_RXD_POS_EDGE DL_UART_IIDX_RXD_POS_EDGE +/*! Redirects to @ref DL_UART_IIDX_RXD_NEG_EDGE */ +#define DL_UART_MAIN_IIDX_RXD_NEG_EDGE DL_UART_IIDX_RXD_NEG_EDGE +/*! Redirects to @ref DL_UART_IIDX_OVERRUN_ERROR */ +#define DL_UART_MAIN_IIDX_OVERRUN_ERROR DL_UART_IIDX_OVERRUN_ERROR +/*! Redirects to @ref DL_UART_IIDX_BREAK_ERROR */ +#define DL_UART_MAIN_IIDX_BREAK_ERROR DL_UART_IIDX_BREAK_ERROR +/*! Redirects to @ref DL_UART_IIDX_PARITY_ERROR */ +#define DL_UART_MAIN_IIDX_PARITY_ERROR DL_UART_IIDX_PARITY_ERROR +/*! Redirects to @ref DL_UART_IIDX_FRAMING_ERROR */ +#define DL_UART_MAIN_IIDX_FRAMING_ERROR DL_UART_IIDX_FRAMING_ERROR +/*! Redirects to @ref DL_UART_IIDX_RX_TIMEOUT_ERROR */ +#define DL_UART_MAIN_IIDX_RX_TIMEOUT_ERROR DL_UART_IIDX_RX_TIMEOUT_ERROR +/*! Redirects to @ref DL_UART_IIDX_NOISE_ERROR */ +#define DL_UART_MAIN_IIDX_NOISE_ERROR DL_UART_IIDX_NOISE_ERROR +/*! Redirects to @ref DL_UART_IIDX_NO_INTERRUPT */ +#define DL_UART_MAIN_IIDX_NO_INTERRUPT DL_UART_IIDX_NO_INTERRUPT +/*! Redirects to @ref DL_UART_DMA_INTERRUPT_RX */ +#define DL_UART_MAIN_DMA_INTERRUPT_RX DL_UART_DMA_INTERRUPT_RX +/*! Redirects to @ref DL_UART_DMA_INTERRUPT_RX_TIMEOUT */ +#define DL_UART_MAIN_DMA_INTERRUPT_RX_TIMEOUT DL_UART_DMA_INTERRUPT_RX_TIMEOUT +/*! Redirects to @ref DL_UART_DMA_INTERRUPT_TX */ +#define DL_UART_MAIN_DMA_INTERRUPT_TX DL_UART_DMA_INTERRUPT_TX +/*! Redirects to @ref DL_UART_ERROR_OVERRUN */ +#define DL_UART_MAIN_ERROR_OVERRUN DL_UART_ERROR_OVERRUN +/*! Redirects to @ref DL_UART_ERROR_BREAK */ +#define DL_UART_MAIN_ERROR_BREAK DL_UART_ERROR_BREAK +/*! Redirects to @ref DL_UART_ERROR_PARITY */ +#define DL_UART_MAIN_ERROR_PARITY DL_UART_ERROR_PARITY +/*! Redirects to @ref DL_UART_ERROR_FRAMING */ +#define DL_UART_MAIN_ERROR_FRAMING DL_UART_ERROR_FRAMING +/*! Redirects to @ref DL_UART_OVERSAMPLING_RATE_16X */ +#define DL_UART_MAIN_OVERSAMPLING_RATE_16X DL_UART_OVERSAMPLING_RATE_16X +/*! Redirects to @ref DL_UART_OVERSAMPLING_RATE_8X */ +#define DL_UART_MAIN_OVERSAMPLING_RATE_8X DL_UART_OVERSAMPLING_RATE_8X +/*! Redirects to @ref DL_UART_OVERSAMPLING_RATE_3X */ +#define DL_UART_MAIN_OVERSAMPLING_RATE_3X DL_UART_OVERSAMPLING_RATE_3X +/*! Redirects to @ref DL_UART_PARITY_EVEN */ +#define DL_UART_MAIN_PARITY_EVEN DL_UART_PARITY_EVEN +/*! Redirects to @ref DL_UART_PARITY_ODD */ +#define DL_UART_MAIN_PARITY_ODD DL_UART_PARITY_ODD +/*! Redirects to @ref DL_UART_PARITY_STICK_ONE */ +#define DL_UART_MAIN_PARITY_STICK_ONE DL_UART_PARITY_STICK_ONE +/*! Redirects to @ref DL_UART_PARITY_STICK_ZERO */ +#define DL_UART_MAIN_PARITY_STICK_ZERO DL_UART_PARITY_STICK_ZERO +/*! Redirects to @ref DL_UART_PARITY_NONE */ +#define DL_UART_MAIN_PARITY_NONE DL_UART_PARITY_NONE +/*! Redirects to @ref DL_UART_WORD_LENGTH_5_BITS */ +#define DL_UART_MAIN_WORD_LENGTH_5_BITS DL_UART_WORD_LENGTH_5_BITS +/*! Redirects to @ref DL_UART_WORD_LENGTH_6_BITS */ +#define DL_UART_MAIN_WORD_LENGTH_6_BITS DL_UART_WORD_LENGTH_6_BITS +/*! Redirects to @ref DL_UART_WORD_LENGTH_7_BITS */ +#define DL_UART_MAIN_WORD_LENGTH_7_BITS DL_UART_WORD_LENGTH_7_BITS +/*! Redirects to @ref DL_UART_WORD_LENGTH_8_BITS */ +#define DL_UART_MAIN_WORD_LENGTH_8_BITS DL_UART_WORD_LENGTH_8_BITS +/*! Redirects to @ref DL_UART_MODE_NORMAL */ +#define DL_UART_MAIN_MODE_NORMAL DL_UART_MODE_NORMAL +/*! Redirects to @ref DL_UART_MODE_RS485 */ +#define DL_UART_MAIN_MODE_RS485 DL_UART_MODE_RS485 +/*! Redirects to @ref DL_UART_MODE_IDLE_LINE */ +#define DL_UART_MAIN_MODE_IDLE_LINE DL_UART_MODE_IDLE_LINE +/*! Redirects to @ref DL_UART_MODE_ADDR_9_BIT */ +#define DL_UART_MAIN_MODE_ADDR_9_BIT DL_UART_MODE_ADDR_9_BIT +/*! Redirects to @ref DL_UART_DIRECTION_TX */ +#define DL_UART_MAIN_DIRECTION_TX DL_UART_DIRECTION_TX +/*! Redirects to @ref DL_UART_DIRECTION_RX */ +#define DL_UART_MAIN_DIRECTION_RX DL_UART_DIRECTION_RX +/*! Redirects to @ref DL_UART_DIRECTION_TX_RX */ +#define DL_UART_MAIN_DIRECTION_TX_RX DL_UART_DIRECTION_TX_RX +/*! Redirects to @ref DL_UART_DIRECTION_NONE */ +#define DL_UART_MAIN_DIRECTION_NONE DL_UART_DIRECTION_NONE +/*! Redirects to @ref DL_UART_CLOCK_BUSCLK */ +#define DL_UART_MAIN_CLOCK_BUSCLK DL_UART_CLOCK_BUSCLK +/*! Redirects to @ref DL_UART_CLOCK_MFCLK */ +#define DL_UART_MAIN_CLOCK_MFCLK DL_UART_CLOCK_MFCLK +/*! Redirects to @ref DL_UART_CLOCK_LFCLK */ +#define DL_UART_MAIN_CLOCK_LFCLK DL_UART_CLOCK_LFCLK +/*! Redirects to @ref DL_UART_FLOW_CONTROL_RTS */ +#define DL_UART_MAIN_FLOW_CONTROL_RTS DL_UART_FLOW_CONTROL_RTS +/*! Redirects to @ref DL_UART_FLOW_CONTROL_CTS */ +#define DL_UART_MAIN_FLOW_CONTROL_CTS DL_UART_FLOW_CONTROL_CTS +/*! Redirects to @ref DL_UART_FLOW_CONTROL_RTS_CTS */ +#define DL_UART_MAIN_FLOW_CONTROL_RTS_CTS DL_UART_FLOW_CONTROL_RTS_CTS +/*! Redirects to @ref DL_UART_FLOW_CONTROL_NONE */ +#define DL_UART_MAIN_FLOW_CONTROL_NONE DL_UART_FLOW_CONTROL_NONE +/*! Redirects to @ref DL_UART_RTS_ASSERT */ +#define DL_UART_MAIN_RTS_ASSERT DL_UART_RTS_ASSERT +/*! Redirects to @ref DL_UART_RTS_DEASSERT */ +#define DL_UART_MAIN_RTS_DEASSERT DL_UART_RTS_DEASSERT +/*! Redirects to @ref DL_UART_STOP_BITS_ONE */ +#define DL_UART_MAIN_STOP_BITS_ONE DL_UART_STOP_BITS_ONE +/*! Redirects to @ref DL_UART_STOP_BITS_TWO */ +#define DL_UART_MAIN_STOP_BITS_TWO DL_UART_STOP_BITS_TWO +/*! Redirects to @ref DL_UART_TXD_OUT_LOW */ +#define DL_UART_MAIN_TXD_OUT_LOW DL_UART_TXD_OUT_LOW +/*! Redirects to @ref DL_UART_TXD_OUT_HIGH */ +#define DL_UART_MAIN_TXD_OUT_HIGH DL_UART_TXD_OUT_HIGH +/*! Redirects to @ref DL_UART_TX_FIFO_LEVEL_3_4_EMPTY */ +#define DL_UART_MAIN_TX_FIFO_LEVEL_3_4_EMPTY DL_UART_TX_FIFO_LEVEL_3_4_EMPTY +/*! Redirects to @ref DL_UART_TX_FIFO_LEVEL_1_4_EMPTY */ +#define DL_UART_MAIN_TX_FIFO_LEVEL_1_4_EMPTY DL_UART_TX_FIFO_LEVEL_1_4_EMPTY +/*! Redirects to @ref DL_UART_TX_FIFO_LEVEL_EMPTY */ +#define DL_UART_MAIN_TX_FIFO_LEVEL_EMPTY DL_UART_TX_FIFO_LEVEL_EMPTY +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_FULL */ +#define DL_UART_MAIN_RX_FIFO_LEVEL_FULL DL_UART_RX_FIFO_LEVEL_FULL +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_3_4_FULL */ +#define DL_UART_MAIN_RX_FIFO_LEVEL_3_4_FULL DL_UART_RX_FIFO_LEVEL_3_4_FULL +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_1_2_FULL */ +#define DL_UART_MAIN_RX_FIFO_LEVEL_1_2_FULL DL_UART_RX_FIFO_LEVEL_1_2_FULL +/*! Redirects to @ref DL_UART_RX_FIFO_LEVEL_1_4_FULL */ +#define DL_UART_MAIN_RX_FIFO_LEVEL_1_4_FULL DL_UART_RX_FIFO_LEVEL_1_4_FULL +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_1 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1 DL_UART_CLOCK_DIVIDE_RATIO_1 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_2 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_2 DL_UART_CLOCK_DIVIDE_RATIO_2 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_3 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_3 DL_UART_CLOCK_DIVIDE_RATIO_3 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_4 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_4 DL_UART_CLOCK_DIVIDE_RATIO_4 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_5 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_5 DL_UART_CLOCK_DIVIDE_RATIO_5 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_6 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_6 DL_UART_CLOCK_DIVIDE_RATIO_6 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_7 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_7 DL_UART_CLOCK_DIVIDE_RATIO_7 +/*! Redirects to @ref DL_UART_CLOCK_DIVIDE_RATIO_8 */ +#define DL_UART_MAIN_CLOCK_DIVIDE_RATIO_8 DL_UART_CLOCK_DIVIDE_RATIO_8 +/*! Redirects to @ref DL_UART_Config */ +#define DL_UART_Main_Config DL_UART_Config +/*! Redirects to @ref DL_UART_ClockConfig */ +#define DL_UART_Main_ClockConfig DL_UART_ClockConfig +/*! Redirects to @ref DL_UART_init */ +#define DL_UART_Main_init DL_UART_init +/*! Redirects to @ref DL_UART_enablePower */ +#define DL_UART_Main_enablePower DL_UART_enablePower +/*! Redirects to @ref DL_UART_disablePower */ +#define DL_UART_Main_disablePower DL_UART_disablePower +/*! Redirects to @ref DL_UART_isPowerEnabled */ +#define DL_UART_Main_isPowerEnabled DL_UART_isPowerEnabled +/*! Redirects to @ref DL_UART_reset */ +#define DL_UART_Main_reset DL_UART_reset +/*! Redirects to @ref DL_UART_enable */ +#define DL_UART_Main_enable DL_UART_enable +/*! Redirects to @ref DL_UART_isEnabled */ +#define DL_UART_Main_isEnabled DL_UART_isEnabled +/*! Redirects to @ref DL_UART_disable */ +#define DL_UART_Main_disable DL_UART_disable +/*! Redirects to @ref DL_UART_setClockConfig */ +#define DL_UART_Main_setClockConfig DL_UART_setClockConfig +/*! Redirects to @ref DL_UART_getClockConfig */ +#define DL_UART_Main_getClockConfig DL_UART_getClockConfig +/*! Redirects to @ref DL_UART_configBaudRate */ +#define DL_UART_Main_configBaudRate DL_UART_configBaudRate +/*! Redirects to @ref DL_UART_setOversampling */ +#define DL_UART_Main_setOversampling DL_UART_setOversampling +/*! Redirects to @ref DL_UART_getOversampling */ +#define DL_UART_Main_getOversampling DL_UART_getOversampling +/*! Redirects to @ref DL_UART_enableLoopbackMode */ +#define DL_UART_Main_enableLoopbackMode DL_UART_enableLoopbackMode +/*! Redirects to @ref DL_UART_isLoopbackModeEnabled */ +#define DL_UART_Main_isLoopbackModeEnabled DL_UART_isLoopbackModeEnabled +/*! Redirects to @ref DL_UART_disableLoopbackMode */ +#define DL_UART_Main_disableLoopbackMode DL_UART_disableLoopbackMode +/*! Redirects to @ref DL_UART_setDirection */ +#define DL_UART_Main_setDirection DL_UART_setDirection +/*! Redirects to @ref DL_UART_getDirection */ +#define DL_UART_Main_getDirection DL_UART_getDirection +/*! Redirects to @ref DL_UART_enableMajorityVoting */ +#define DL_UART_Main_enableMajorityVoting DL_UART_enableMajorityVoting +/*! Redirects to @ref DL_UART_isMajorityVotingEnabled */ +#define DL_UART_Main_isMajorityVotingEnabled DL_UART_isMajorityVotingEnabled +/*! Redirects to @ref DL_UART_disableMajorityVoting */ +#define DL_UART_Main_disableMajorityVoting DL_UART_disableMajorityVoting +/*! Redirects to @ref DL_UART_enableMSBFirst */ +#define DL_UART_Main_enableMSBFirst DL_UART_enableMSBFirst +/*! Redirects to @ref DL_UART_isMSBFirstEnabled */ +#define DL_UART_Main_isMSBFirstEnabled DL_UART_isMSBFirstEnabled +/*! Redirects to @ref DL_UART_disableMSBFirst */ +#define DL_UART_Main_disableMSBFirst DL_UART_disableMSBFirst +/*! Redirects to @ref DL_UART_enableTransmitPinManualControl */ +#define DL_UART_Main_enableTransmitPinManualControl DL_UART_enableTransmitPinManualControl +/*! Redirects to @ref DL_UART_isTransmitPinManualControlEnabled */ +#define DL_UART_Main_isTransmitPinManualControlEnabl DL_UART_isTransmitPinManualControlEnabled +/*! Redirects to @ref DL_UART_disableTransmitPinManualControl */ +#define DL_UART_Main_disableTransmitPinManualControl DL_UART_disableTransmitPinManualControl +/*! Redirects to @ref DL_UART_setTransmitPinManualOutput */ +#define DL_UART_Main_setTransmitPinManualOutput DL_UART_setTransmitPinManualOutput +/*! Redirects to @ref DL_UART_getTransmitPinManualOutput */ +#define DL_UART_Main_getTransmitPinManualOutput DL_UART_getTransmitPinManualOutput +/*! Redirects to @ref DL_UART_setCommunicationMode */ +#define DL_UART_Main_setCommunicationMode DL_UART_setCommunicationMode +/*! Redirects to @ref DL_UART_getCommunicationMode */ +#define DL_UART_Main_getCommunicationMode DL_UART_getCommunicationMode +/*! Redirects to @ref DL_UART_setFlowControl */ +#define DL_UART_Main_setFlowControl DL_UART_setFlowControl +/*! Redirects to @ref DL_UART_getFlowControl */ +#define DL_UART_Main_getFlowControl DL_UART_getFlowControl +/*! Redirects to @ref DL_UART_setRTSOutput */ +#define DL_UART_Main_setRTSOutput DL_UART_setRTSOutput +/*! Redirects to @ref DL_UART_enableFIFOs */ +#define DL_UART_Main_enableFIFOs DL_UART_enableFIFOs +/*! Redirects to @ref DL_UART_disableFIFOs */ +#define DL_UART_Main_disableFIFOs DL_UART_disableFIFOs +/*! Redirects to @ref DL_UART_isFIFOsEnabled */ +#define DL_UART_Main_isFIFOsEnabled DL_UART_isFIFOsEnabled +/*! Redirects to @ref DL_UART_isParityEnabled */ +#define DL_UART_Main_isParityEnabled DL_UART_isParityEnabled +/*! Redirects to @ref DL_UART_setParityMode */ +#define DL_UART_Main_setParityMode DL_UART_setParityMode +/*! Redirects to @ref DL_UART_getParityMode */ +#define DL_UART_Main_getParityMode DL_UART_getParityMode +/*! Redirects to @ref DL_UART_setStopBits */ +#define DL_UART_Main_setStopBits DL_UART_setStopBits +/*! Redirects to @ref DL_UART_getStopBits */ +#define DL_UART_Main_getStopBits DL_UART_getStopBits +/*! Redirects to @ref DL_UART_setWordLength */ +#define DL_UART_Main_setWordLength DL_UART_setWordLength +/*! Redirects to @ref DL_UART_getWordLength */ +#define DL_UART_Main_getWordLength DL_UART_getWordLength +/*! Redirects to @ref DL_UART_enableSendIdlePattern */ +#define DL_UART_Main_enableSendIdlePattern DL_UART_enableSendIdlePattern +/*! Redirects to @ref DL_UART_disableSendIdlePattern */ +#define DL_UART_Main_disableSendIdlePattern DL_UART_disableSendIdlePattern +/*! Redirects to @ref DL_UART_isSendIdlePatternEnabled */ +#define DL_UART_Main_isSendIdlePatternEnabled DL_UART_isSendIdlePatternEnabled +/*! Redirects to @ref DL_UART_setExternalDriverSetup */ +#define DL_UART_Main_setExternalDriverSetup DL_UART_setExternalDriverSetup +/*! Redirects to @ref DL_UART_getExternalDriverSetup */ +#define DL_UART_Main_getExternalDriverSetup DL_UART_getExternalDriverSetup +/*! Redirects to @ref DL_UART_setExternalDriverHold */ +#define DL_UART_Main_setExternalDriverHold DL_UART_setExternalDriverHold +/*! Redirects to @ref DL_UART_getExternalDriverHold */ +#define DL_UART_Main_getExternalDriverHold DL_UART_getExternalDriverHold +/*! Redirects to @ref DL_UART_isBusy */ +#define DL_UART_Main_isBusy DL_UART_isBusy +/*! Redirects to @ref DL_UART_isRXFIFOEmpty */ +#define DL_UART_Main_isRXFIFOEmpty DL_UART_isRXFIFOEmpty +/*! Redirects to @ref DL_UART_isRXFIFOFull */ +#define DL_UART_Main_isRXFIFOFull DL_UART_isRXFIFOFull +/*! Redirects to @ref DL_UART_isTXFIFOEmpty */ +#define DL_UART_Main_isTXFIFOEmpty DL_UART_isTXFIFOEmpty +/*! Redirects to @ref DL_UART_isTXFIFOFull */ +#define DL_UART_Main_isTXFIFOFull DL_UART_isTXFIFOFull +/*! Redirects to @ref DL_UART_isClearToSend */ +#define DL_UART_Main_isClearToSend DL_UART_isClearToSend +/*! Redirects to @ref DL_UART_isIdleModeDetected */ +#define DL_UART_Main_isIdleModeDetected DL_UART_isIdleModeDetected +/*! Redirects to @ref DL_UART_setTXFIFOThreshold */ +#define DL_UART_Main_setTXFIFOThreshold DL_UART_setTXFIFOThreshold +/*! Redirects to @ref DL_UART_getTXFIFOThreshold */ +#define DL_UART_Main_getTXFIFOThreshold DL_UART_getTXFIFOThreshold +/*! Redirects to @ref DL_UART_setRXFIFOThreshold */ +#define DL_UART_Main_setRXFIFOThreshold DL_UART_setRXFIFOThreshold +/*! Redirects to @ref DL_UART_getRXFIFOThreshold */ +#define DL_UART_Main_getRXFIFOThreshold DL_UART_getRXFIFOThreshold +/*! Redirects to @ref DL_UART_setRXInterruptTimeout */ +#define DL_UART_Main_setRXInterruptTimeout DL_UART_setRXInterruptTimeout +/*! Redirects to @ref DL_UART_getRXInterruptTimeout */ +#define DL_UART_Main_getRXInterruptTimeout DL_UART_getRXInterruptTimeout +/*! Redirects to @ref DL_UART_getIntegerBaudRateDivisor */ +#define DL_UART_Main_getIntegerBaudRateDivisor DL_UART_getIntegerBaudRateDivisor +/*! Redirects to @ref DL_UART_getFractionalBaudRateDivisor */ +#define DL_UART_Main_getFractionalBaudRateDivisor DL_UART_getFractionalBaudRateDivisor +/*! Redirects to @ref DL_UART_setBaudRateDivisor */ +#define DL_UART_Main_setBaudRateDivisor DL_UART_setBaudRateDivisor +/*! Redirects to @ref DL_UART_transmitData */ +#define DL_UART_Main_transmitData DL_UART_transmitData +/*! Redirects to @ref DL_UART_receiveData */ +#define DL_UART_Main_receiveData DL_UART_receiveData +/*! Redirects to @ref DL_UART_getErrorStatus */ +#define DL_UART_Main_getErrorStatus DL_UART_getErrorStatus +/*! Redirects to @ref DL_UART_enableInterrupt */ +#define DL_UART_Main_enableInterrupt DL_UART_enableInterrupt +/*! Redirects to @ref DL_UART_disableInterrupt */ +#define DL_UART_Main_disableInterrupt DL_UART_disableInterrupt +/*! Redirects to @ref DL_UART_getEnabledInterrupts */ +#define DL_UART_Main_getEnabledInterrupts DL_UART_getEnabledInterrupts +/*! Redirects to @ref DL_UART_getEnabledInterruptStatus */ +#define DL_UART_Main_getEnabledInterruptStatus DL_UART_getEnabledInterruptStatus +/*! Redirects to @ref DL_UART_getRawInterruptStatus */ +#define DL_UART_Main_getRawInterruptStatus DL_UART_getRawInterruptStatus +/*! Redirects to @ref DL_UART_getPendingInterrupt */ +#define DL_UART_Main_getPendingInterrupt DL_UART_getPendingInterrupt +/*! Redirects to @ref DL_UART_clearInterruptStatus */ +#define DL_UART_Main_clearInterruptStatus DL_UART_clearInterruptStatus +/*! Redirects to @ref DL_UART_changeConfig */ +#define DL_UART_Main_changeConfig DL_UART_changeConfig +/*! Redirects to @ref DL_UART_transmitDataBlocking */ +#define DL_UART_Main_transmitDataBlocking DL_UART_transmitDataBlocking +/*! Redirects to @ref DL_UART_receiveDataBlocking */ +#define DL_UART_Main_receiveDataBlocking DL_UART_receiveDataBlocking +/*! Redirects to @ref DL_UART_transmitDataCheck */ +#define DL_UART_Main_transmitDataCheck DL_UART_transmitDataCheck +/*! Redirects to @ref DL_UART_receiveDataCheck */ +#define DL_UART_Main_receiveDataCheck DL_UART_receiveDataCheck +/*! Redirects to @ref DL_UART_drainRXFIFO */ +#define DL_UART_Main_drainRXFIFO DL_UART_drainRXFIFO +/*! Redirects to @ref DL_UART_fillTXFIFO */ +#define DL_UART_Main_fillTXFIFO DL_UART_fillTXFIFO +/*! Redirects to @ref DL_UART_enableDMAReceiveEvent */ +#define DL_UART_Main_enableDMAReceiveEvent DL_UART_enableDMAReceiveEvent +/*! Redirects to @ref DL_UART_enableDMATransmitEvent */ +#define DL_UART_Main_enableDMATransmitEvent DL_UART_enableDMATransmitEvent +/*! Redirects to @ref DL_UART_disableDMAReceiveEvent */ +#define DL_UART_Main_disableDMAReceiveEvent DL_UART_disableDMAReceiveEvent +/*! Redirects to @ref DL_UART_disableDMATransmitEvent */ +#define DL_UART_Main_disableDMATransmitEvent DL_UART_disableDMATransmitEvent +/*! Redirects to @ref DL_UART_getEnabledDMAReceiveEvent */ +#define DL_UART_Main_getEnabledDMAReceiveEvent DL_UART_getEnabledDMAReceiveEvent +/*! Redirects to @ref DL_UART_getEnabledDMATransmitEvent */ +#define DL_UART_Main_getEnabledDMATransmitEvent DL_UART_getEnabledDMATransmitEvent +/*! Redirects to @ref DL_UART_getEnabledDMAReceiveEventStatus */ +#define DL_UART_Main_getEnabledDMAReceiveEventStatus DL_UART_getEnabledDMAReceiveEventStatus +/*! Redirects to @ref DL_UART_getEnabledDMATransmitEventStatus */ +#define DL_UART_Main_getEnabledDMATransmitEventStatu DL_UART_getEnabledDMATransmitEventStatus +/*! Redirects to @ref DL_UART_getRawDMAReceiveEventStatus */ +#define DL_UART_Main_getRawDMAReceiveEventStatus DL_UART_getRawDMAReceiveEventStatus +/*! Redirects to @ref DL_UART_getRawDMATransmitEventStatus */ +#define DL_UART_Main_getRawDMATransmitEventStatus DL_UART_getRawDMATransmitEventStatus +/** @}*/ + +/** @addtogroup DL_UART_INTERRUPT + * @{ + */ +/*! + * @brief DMA done on transmit interrupt + */ +#define DL_UART_INTERRUPT_DMA_DONE_TX (UNICOMMUART_CPU_INT_IMASK_DMA_DONE_TX_SET) + +/*! + * @brief DMA done on receive interrupt + */ +#define DL_UART_INTERRUPT_DMA_DONE_RX (UNICOMMUART_CPU_INT_IMASK_DMA_DONE_RX_SET) + +/*! + * @brief Clear to send interrupt + */ +#define DL_UART_INTERRUPT_CTS_DONE (UNICOMMUART_CPU_INT_IMASK_CTS_SET) + +/*! + * @brief 9-bit mode address match interrupt + */ +#define DL_UART_INTERRUPT_ADDRESS_MATCH (UNICOMMUART_CPU_INT_IMASK_ADDR_MATCH_SET) + +/*! + * @brief LINC0 match interrupt + */ +#define DL_UART_INTERRUPT_LINC0_MATCH (UNICOMMUART_CPU_INT_IMASK_LINC0_SET) + +/*! + * @brief End of transmission interrupt + */ +#define DL_UART_INTERRUPT_EOT_DONE (UNICOMMUART_CPU_INT_IMASK_EOT_SET) + +/*! + * @brief UART transmit interrupt + */ +#define DL_UART_INTERRUPT_TX (UNICOMMUART_CPU_INT_IMASK_TXINT_SET) + +/*! + * @brief UART receive interrupt + */ +#define DL_UART_INTERRUPT_RX (UNICOMMUART_CPU_INT_IMASK_RXINT_SET) + +/*! + * @brief LIN hardware counter overflow interrupt + */ +#define DL_UART_INTERRUPT_LIN_COUNTER_OVERFLOW \ + (UNICOMMUART_CPU_INT_IMASK_LINOVF_SET) + +/*! + * @brief LIN rising edge LINC1 interrupt + */ +#define DL_UART_INTERRUPT_LIN_RISING_EDGE \ + (UNICOMMUART_CPU_INT_IMASK_LINC1_SET) + +/*! + * @brief LIN falling edge LINC0 interrupt + */ +#define DL_UART_INTERRUPT_LIN_FALLING_EDGE \ + (UNICOMMUART_CPU_INT_IMASK_LINC0_SET) + +/*! + * @brief Positive Edge on UNICOMMUARTxRXD interrupt + */ +#define DL_UART_INTERRUPT_RXD_POS_EDGE (UNICOMMUART_CPU_INT_IMASK_RXPE_SET) + +/*! + * @brief Negative Edge on UNICOMMUARTxRXD interrupt + */ +#define DL_UART_INTERRUPT_RXD_NEG_EDGE (UNICOMMUART_CPU_INT_IMASK_RXNE_SET) + +/*! + * @brief Overrun error interrupt + */ +#define DL_UART_INTERRUPT_OVERRUN_ERROR (UNICOMMUART_CPU_INT_IMASK_OVRERR_SET) + +/*! + * @brief Break error interrupt + */ +#define DL_UART_INTERRUPT_BREAK_ERROR (UNICOMMUART_CPU_INT_IMASK_BRKERR_SET) + +/*! + * @brief Parity error interrupt + */ +#define DL_UART_INTERRUPT_PARITY_ERROR (UNICOMMUART_CPU_INT_IMASK_PARERR_SET) + +/*! + * @brief Framing error interrupt + */ +#define DL_UART_INTERRUPT_FRAMING_ERROR (UNICOMMUART_CPU_INT_IMASK_FRMERR_SET) + +/*! + * @brief Receive timeout interrupt + */ +#define DL_UART_INTERRUPT_RX_TIMEOUT_ERROR (UNICOMMUART_CPU_INT_IMASK_RTOUT_SET) + +/*! + * @brief Noise error interrupt + */ +#define DL_UART_INTERRUPT_NOISE_ERROR (UNICOMMUART_CPU_INT_IMASK_NERR_SET) + +/*! + * @brief Line timeout interrupt + */ +#define DL_UART_INTERRUPT_LINE_TIMEOUT (UNICOMMUART_CPU_INT_IMASK_LTOUT_SET) + +/** @}*/ + +/*! @enum DL_UART_IIDX */ +typedef enum { + /*! UART interrupt index for DMA done on transmit */ + DL_UART_IIDX_DMA_DONE_TX = UNICOMMUART_IIDX_STAT_DMA_DONE_TX, + /*! UART interrupt index for DMA done on receive */ + DL_UART_IIDX_DMA_DONE_RX = UNICOMMUART_IIDX_STAT_DMA_DONE_RX, + /*! Interrupt index for UART receive pre-emptive interrupt */ + DL_UART_IIDX_PREEMPT_INT_TX = UNICOMMUART_IIDX_STAT_DMA_PREIRQ_TX, + /*! Interrupt index for UART receive pre-emptive interrupt */ + DL_UART_IIDX_PREEMPT_INT_RX = UNICOMMUART_IIDX_STAT_DMA_PREIRQ_RX, + /*! UART interrupt index for clear to send */ + DL_UART_IIDX_CTS_DONE = UNICOMMUART_IIDX_STAT_CTS, + /*! UART interrupt index for end of transmission */ + DL_UART_IIDX_EOT_DONE = UNICOMMUART_IIDX_STAT_EOT, + /*! UART interrupt index for UART transmit */ + DL_UART_IIDX_TX = UNICOMMUART_IIDX_STAT_TXIFG, + /*! UART interrupt index for UART receive */ + DL_UART_IIDX_RX = UNICOMMUART_IIDX_STAT_RXIFG, + /*! UART interrupt index for LIN hardware counter overflow */ + DL_UART_IIDX_LIN_COUNTER_OVERFLOW = UNICOMMUART_IIDX_STAT_LINOVF, + /*! UART interrupt index for LIN rising edge LINC1 */ + DL_UART_IIDX_LIN_RISING_EDGE = UNICOMMUART_IIDX_STAT_LINC1, + /*! UART interrupt index for LINC0 match */ + DL_UART_IIDX_LINC0_MATCH = UNICOMMUART_IIDX_STAT_LINC0, + /*! UART interrupt index for LIN falling edge LINC0 */ + DL_UART_IIDX_LIN_FALLING_EDGE = UNICOMMUART_IIDX_STAT_LINC0, + /*! UART interrupt index for positive edge on UNICOMMUARTxRXD */ + DL_UART_IIDX_RXD_POS_EDGE = UNICOMMUART_IIDX_STAT_RXPE, + /*! UART interrupt index for negative edge on UNICOMMUARTxRXD */ + DL_UART_IIDX_RXD_NEG_EDGE = UNICOMMUART_IIDX_STAT_RXNE, + /*! UART interrupt index for overrun error */ + DL_UART_IIDX_OVERRUN_ERROR = UNICOMMUART_IIDX_STAT_OEFG, + /*! UART interrupt index for break error */ + DL_UART_IIDX_BREAK_ERROR = UNICOMMUART_IIDX_STAT_BEFG, + /*! UART interrupt index for parity error */ + DL_UART_IIDX_PARITY_ERROR = UNICOMMUART_IIDX_STAT_PEFG, + /*! UART interrupt index for framing error */ + DL_UART_IIDX_FRAMING_ERROR = UNICOMMUART_IIDX_STAT_FEFG, + /*! UART interrupt index for receive timeout */ + DL_UART_IIDX_RX_TIMEOUT_ERROR = UNICOMMUART_IIDX_STAT_RTFG, + /*! UART interrupt index for noise error */ + DL_UART_IIDX_NOISE_ERROR = UNICOMMUART_IIDX_STAT_NERR_EVT, + /*! UART interrupt index for no interrupt */ + DL_UART_IIDX_NO_INTERRUPT = UNICOMMUART_IIDX_STAT_NO_INTR, + /*! UART interrupt index for 9-bit mode address match */ + DL_UART_IIDX_ADDRESS_MATCH = UNICOMMUART_IIDX_STAT_ADDR_MATCH, + /*! UART interrupt index for line time-out */ + DL_UART_IIDX_LINE_TIMEOUT = UNICOMMUART_IIDX_STAT_LTFG +} DL_UART_IIDX; + +/** @addtogroup DL_UART_DMA_INTERRUPT_RX + * @{ + */ +/*! + * @brief UART interrupt for enabling UART receive as DMA trigger + */ +#define DL_UART_DMA_INTERRUPT_RX (UNICOMMUART_DMA_TRIG_RX_IMASK_RXINT_SET) + +/*! + * @brief UART interrupt for enabling UART receive timeout as DMA trigger + */ +#define DL_UART_DMA_INTERRUPT_RX_TIMEOUT (UNICOMMUART_DMA_TRIG_RX_IMASK_RTOUT_SET) + +/** @}*/ + +/*! + * @brief UART interrupt for enabling UART transmit as DMA trigger + */ +#define DL_UART_DMA_INTERRUPT_TX (UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_SET) + +/** @addtogroup DL_UART_ERROR + * @{ + */ +/*! + * @brief Overrun error ocurred + */ +#define DL_UART_ERROR_OVERRUN (UNICOMMUART_RXDATA_OVRERR_SET) + +/*! + * @brief Break error ocurred + */ +#define DL_UART_ERROR_BREAK (UNICOMMUART_RXDATA_BRKERR_SET) + +/*! + * @brief Parity error ocurred + */ +#define DL_UART_ERROR_PARITY (UNICOMMUART_RXDATA_PARERR_SET) + +/*! + * @brief Framing error ocurred + */ +#define DL_UART_ERROR_FRAMING (UNICOMMUART_RXDATA_FRMERR_SET) + +/** @}*/ + +/*! @enum DL_UART_OVERSAMPLING_RATE */ +typedef enum { + /*! Set oversampling rate to 16x */ + DL_UART_OVERSAMPLING_RATE_16X = UNICOMMUART_CTL0_HSE_OVS16, + /*! Set oversampling rate to 8x */ + DL_UART_OVERSAMPLING_RATE_8X = UNICOMMUART_CTL0_HSE_OVS8, + /*! Set oversampling rate to 3x. + * IrDA, Manchester and DALI are not supported when 3x oversampling is + * enabled. */ + DL_UART_OVERSAMPLING_RATE_3X = UNICOMMUART_CTL0_HSE_OVS3 +} DL_UART_OVERSAMPLING_RATE; + +/*! @enum DL_UART_PARITY */ +typedef enum { + /*! Enable even parity generation, checks for an even number of 1s */ + DL_UART_PARITY_EVEN = (UNICOMMUART_LCRH_PEN_ENABLE | UNICOMMUART_LCRH_EPS_EVEN), + /*! Enable odd parity generation, checks for an odd number of 1s */ + DL_UART_PARITY_ODD = (UNICOMMUART_LCRH_PEN_ENABLE | UNICOMMUART_LCRH_EPS_ODD), + /*! Enable stick parity with a parity bit of '1' + * When enabled, a permanent '1' is set as parity when transmitting and + * checked as '1' when receiving data. */ + DL_UART_PARITY_STICK_ONE = (UNICOMMUART_LCRH_PEN_ENABLE | UNICOMMUART_LCRH_SPS_ENABLE | UNICOMMUART_LCRH_EPS_ODD), + /*! Enable stick parity with a parity bit of '0' + * When enabled, a permanent '0' is set as parity when transmitting and + * checked as '0' when receiving data. */ + DL_UART_PARITY_STICK_ZERO = (UNICOMMUART_LCRH_PEN_ENABLE | UNICOMMUART_LCRH_SPS_ENABLE | UNICOMMUART_LCRH_EPS_EVEN), + /*! Disable parity checking and generation */ + DL_UART_PARITY_NONE = UNICOMMUART_LCRH_PEN_DISABLE +} DL_UART_PARITY; + +/*! @enum DL_UART_WORD_LENGTH */ +typedef enum { + /*! Word length is 5 bits */ + DL_UART_WORD_LENGTH_5_BITS = UNICOMMUART_LCRH_WLEN_DATABIT5, + /*! Word length is 6 bits */ + DL_UART_WORD_LENGTH_6_BITS = UNICOMMUART_LCRH_WLEN_DATABIT6, + /*! Word length is 7 bits */ + DL_UART_WORD_LENGTH_7_BITS = UNICOMMUART_LCRH_WLEN_DATABIT7, + /*! Word length is 8 bits */ + DL_UART_WORD_LENGTH_8_BITS = UNICOMMUART_LCRH_WLEN_DATABIT8 +} DL_UART_WORD_LENGTH; + +/*! @enum DL_UART_MODE */ +typedef enum { + /*! Normal operation */ + DL_UART_MODE_NORMAL = UNICOMMUART_CTL0_MODE_UART, + /*! Operate in RS485 mode */ + DL_UART_MODE_RS485 = UNICOMMUART_CTL0_MODE_RS485, + /*! Operate in Idle Line mode */ + DL_UART_MODE_IDLE_LINE = UNICOMMUART_CTL0_MODE_IDLELINE, + /*! Operate in 9 Bit Address mode */ + DL_UART_MODE_ADDR_9_BIT = UNICOMMUART_CTL0_MODE_ADDR9BIT, + /*! Operate in ISO7816 Smart Card Support mode */ + DL_UART_MODE_SMART_CARD = UNICOMMUART_CTL0_MODE_SMART, + /*! Operate in DALI mode */ + DL_UART_MODE_DALI = UNICOMMUART_CTL0_MODE_DALI +} DL_UART_MODE; + +/*! @enum DL_UART_DIRECTION */ +typedef enum { + /*! Enable UART transmitter */ + DL_UART_DIRECTION_TX = UNICOMMUART_CTL0_TXE_ENABLE, + /*! Enable UART receiver */ + DL_UART_DIRECTION_RX = UNICOMMUART_CTL0_RXE_ENABLE, + /*! Enable UART transmitter and receiver */ + DL_UART_DIRECTION_TX_RX = (UNICOMMUART_CTL0_RXE_ENABLE | UNICOMMUART_CTL0_TXE_ENABLE), + /*! Disable UART transmitter and receiver */ + DL_UART_DIRECTION_NONE = (UNICOMMUART_CTL0_RXE_DISABLE | UNICOMMUART_CTL0_TXE_DISABLE) +} DL_UART_DIRECTION; + +/*! @enum DL_UART_CLOCK */ +typedef enum { + /*! Selects BUSCLK as the clock source */ + DL_UART_CLOCK_BUSCLK = UNICOMMUART_CLKSEL_BUSCLK_SEL_ENABLE, + /*! Selects MFCLK as the clock source */ + DL_UART_CLOCK_MFCLK = UNICOMMUART_CLKSEL_MFCLK_SEL_ENABLE, + /*! Selects LFCLK as the clock source */ + DL_UART_CLOCK_LFCLK = UNICOMMUART_CLKSEL_LFCLK_SEL_ENABLE, + /*! Selects asynchronous LFCLK as the clock source */ + DL_UART_CLOCK_ASYNC_LFCLK = UNICOMMUART_CLKSEL_ASYNC_LFCLK_SEL_ENABLE, + /*! Selects asynchronous SYSCLK as the clock source */ + DL_UART_CLOCK_ASYNC_SYSCLK = UNICOMMUART_CLKSEL_ASYNC_SYSCLK_SEL_ENABLE, + /*! Selects asynchronous HFCLK as the clock source */ + DL_UART_CLOCK_ASYNC_HFCLK = UNICOMMUART_CLKSEL_ASYNC_HFCLK_SEL_ENABLE, + /*! Selects asynchronous PLL as the clock source */ + DL_UART_CLOCK_ASYNC_PLL = UNICOMMUART_CLKSEL_ASYNC_PLL_SEL_ENABLE +} DL_UART_CLOCK; + +/*! @enum DL_UART_CLOCK_DIVIDE_RATIO */ +typedef enum { + /*! UART source clock divide ratio set to 1 */ + DL_UART_CLOCK_DIVIDE_RATIO_1 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_1, + /*! UART source clock divide ratio set to 2 */ + DL_UART_CLOCK_DIVIDE_RATIO_2 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_2, + /*! UART source clock divide ratio set to 3 */ + DL_UART_CLOCK_DIVIDE_RATIO_3 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_3, + /*! UART source clock divide ratio set to 4 */ + DL_UART_CLOCK_DIVIDE_RATIO_4 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_4, + /*! UART source clock divide ratio set to 5 */ + DL_UART_CLOCK_DIVIDE_RATIO_5 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_5, + /*! UART source clock divide ratio set to 6 */ + DL_UART_CLOCK_DIVIDE_RATIO_6 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_6, + /*! UART source clock divide ratio set to 7 */ + DL_UART_CLOCK_DIVIDE_RATIO_7 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_7, + /*! UART source clock divide ratio set to 8 */ + DL_UART_CLOCK_DIVIDE_RATIO_8 = UNICOMMUART_CLKDIV_RATIO_DIV_BY_8 +} DL_UART_CLOCK_DIVIDE_RATIO; + +/*! @enum DL_UART_FLOW_CONTROL */ +typedef enum { + /*! Enable request to send */ + DL_UART_FLOW_CONTROL_RTS = UNICOMMUART_CTL0_RTSEN_ENABLE, + /*! Enable clear to send */ + DL_UART_FLOW_CONTROL_CTS = UNICOMMUART_CTL0_CTSEN_ENABLE, + /*! Enable request to send and clear to send */ + DL_UART_FLOW_CONTROL_RTS_CTS = (UNICOMMUART_CTL0_RTSEN_ENABLE | UNICOMMUART_CTL0_CTSEN_ENABLE), + /*! Disable flow control */ + DL_UART_FLOW_CONTROL_NONE = (UNICOMMUART_CTL0_CTSEN_DISABLE | UNICOMMUART_CTL0_RTSEN_DISABLE) +} DL_UART_FLOW_CONTROL; + +/*! @enum DL_UART_RTS */ +typedef enum { + /*! RTS is asserted indicating data in RX FIFO is below threshold */ + DL_UART_RTS_ASSERT = UNICOMMUART_CTL0_RTS_SET, + /*! RTS is deasserted indicating data in RX FIFO is at or above threshold */ + DL_UART_RTS_DEASSERT = UNICOMMUART_CTL0_RTS_CLR +} DL_UART_RTS; + +/*! @enum DL_UART_STOP_BITS */ +typedef enum { + /*! One stop bit is transmitted at the end of the frame */ + DL_UART_STOP_BITS_ONE = UNICOMMUART_LCRH_STP2_DISABLE, + /*! Two stop bits are transmitted at the end of the frame */ + DL_UART_STOP_BITS_TWO = UNICOMMUART_LCRH_STP2_ENABLE +} DL_UART_STOP_BITS; + +/*! @enum DL_UART_TXD_OUT */ +typedef enum { + /*! TXD pin is low */ + DL_UART_TXD_OUT_LOW = UNICOMMUART_CTL0_TXD_OUT_LOW, + /*! TXD pin is high */ + DL_UART_TXD_OUT_HIGH = UNICOMMUART_CTL0_TXD_OUT_HIGH +} DL_UART_TXD_OUT; + +/*! @enum DL_UART_TX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when FIFO <= 3/4 empty */ + DL_UART_TX_FIFO_LEVEL_3_4_EMPTY = UNICOMMUART_IFLS_TXIFLSEL_LVL_3_4, + /*! Interrupt triggers when FIFO <= 1/2 empty */ + DL_UART_TX_FIFO_LEVEL_1_2_EMPTY = UNICOMMUART_IFLS_TXIFLSEL_LVL_1_2, + /*! Interrupt triggers when FIFO <= 1/4 empty */ + DL_UART_TX_FIFO_LEVEL_1_4_EMPTY = UNICOMMUART_IFLS_TXIFLSEL_LVL_1_4, + /*! Interrupt triggers when FIFO is not full */ + DL_UART_TX_FIFO_LEVEL_ONE_ENTRY = UNICOMMUART_IFLS_TXIFLSEL_LVL_NOT_FULL, + /*! Interrupt triggers when FIFO is empty */ + DL_UART_TX_FIFO_LEVEL_EMPTY = UNICOMMUART_IFLS_TXIFLSEL_LVL_EMPTY, + /*! Interrupt triggers when FIFO is almost empty (FIFO <= 1) */ + DL_UART_TX_FIFO_LEVEL_ALMOST_EMPTY = UNICOMMUART_IFLS_TXIFLSEL_LVL_ALMOST_EMPTY, + /*! Interrupt triggers when FIFO is almost full (FIFO >= (MAX_FIFO_LEN - 1)) */ + DL_UART_TX_FIFO_LEVEL_ALMOST_FULL = UNICOMMUART_IFLS_TXIFLSEL_LVL_ALMOST_FULL +} DL_UART_TX_FIFO_LEVEL; + +/*! @enum DL_UART_RX_FIFO_LEVEL */ +typedef enum { + /*! Interrupt triggers when FIFO >= 1/4 full */ + DL_UART_RX_FIFO_LEVEL_1_4_FULL = UNICOMMUART_IFLS_RXIFLSEL_LVL_1_4, + /*! Interrupt triggers when FIFO >= 1/2 full */ + DL_UART_RX_FIFO_LEVEL_1_2_FULL = UNICOMMUART_IFLS_RXIFLSEL_LVL_1_2, + /*! Interrupt triggers when FIFO >= 3/4 full */ + DL_UART_RX_FIFO_LEVEL_3_4_FULL = UNICOMMUART_IFLS_RXIFLSEL_LVL_3_4, + /*! Interrupt triggers when FIFO is not empty */ + DL_UART_RX_FIFO_LEVEL_ONE_ENTRY = UNICOMMUART_IFLS_RXIFLSEL_LVL_NOT_EMPTY, + /*! Interrupt triggers when FIFO is full */ + DL_UART_RX_FIFO_LEVEL_FULL = UNICOMMUART_IFLS_RXIFLSEL_LVL_FULL, + /*! Interrupt triggers when FIFO is almost full (FIFO >= (MAX_FIFO_LEN - 1)) */ + DL_UART_RX_FIFO_LEVEL_ALMOST_FULL = UNICOMMUART_IFLS_RXIFLSEL_LVL_ALMOST_FULL, + /*! Interrupt triggers when FIFO is almost empty (FIFO <= 1) */ + DL_UART_RX_FIFO_LEVEL_ALMOST_EMPTY = UNICOMMUART_IFLS_RXIFLSEL_LVL_ALMOST_EMPTY +} DL_UART_RX_FIFO_LEVEL; + +/*! @enum DL_UART_IRDA_CLOCK */ +typedef enum { + /*! IrDA encode data is based on the Baud Rate clock */ + DL_UART_IRDA_CLOCK_BAUD_RATE = UNICOMMUART_IRCTL_IRTXCLK_BRCLK, + /*! IrDA encode data is based on the Functional clock */ + DL_UART_IRDA_CLOCK_FUNCTIONAL = UNICOMMUART_IRCTL_IRTXCLK_BITCLK +} DL_UART_IRDA_CLOCK; + +/*! @enum DL_UART_IRDA_POLARITY */ +typedef enum { + /*! IrDA transceiver delivers a low pulse when a light pulse is seen */ + DL_UART_IRDA_POLARITY_LOW = UNICOMMUART_IRCTL_IRRXPL_LOW, + /*! IrDA transceiver delivers a high pulse when a light pulse is seen */ + DL_UART_IRDA_POLARITY_HIGH = UNICOMMUART_IRCTL_IRRXPL_HIGH +} DL_UART_IRDA_POLARITY; + +/*! + * @brief Sets the IrDA pulse width to 3/16 bit period when using the BITCLK16 + */ +#define DL_UART_PULSE_WIDTH_3_16_BIT_PERIOD ((uint32_t) 0x00000000U) + +/* clang-format on */ + +/*! + * @brief Configuration struct for @ref DL_UART_init + */ +typedef struct { + /*! The communication mode and protocol used. One of @ref DL_UART_MODE */ + DL_UART_MODE mode; + + /*! The communication direction. One of @ref DL_UART_DIRECTION. */ + DL_UART_DIRECTION direction; + + /*! The flow control configuration. One of @ref DL_UART_FLOW_CONTROL */ + DL_UART_FLOW_CONTROL flowControl; + + /*! The parity configuration. One of @ref DL_UART_PARITY */ + DL_UART_PARITY parity; + + /*! The size of the data transfer. One of @ref DL_UART_WORD_LENGTH */ + DL_UART_WORD_LENGTH wordLength; + + /*! One of @ref DL_UART_STOP_BITS */ + DL_UART_STOP_BITS stopBits; + +} DL_UART_Config; + +/*! + * @brief Configuration struct for @ref DL_UART_setClockConfig. + */ +typedef struct { + /*! Selects uart module clock source @ref DL_UART_CLOCK */ + DL_UART_CLOCK clockSel; + + /*! Selects the divide ratio. One of @ref DL_UART_CLOCK_DIVIDE_RATIO */ + DL_UART_CLOCK_DIVIDE_RATIO divideRatio; + +} DL_UART_ClockConfig; + +/** + * @brief Configuration structure to backup UART Extend peripheral state before + * going to STOP/STANDBY mode. Used by + * @ref DL_UART_saveConfiguration and + * @ref DL_UART_restoreConfiguration + */ +typedef struct { + /*! Combination of basic UART control configurations that are + * compressed to a single word as they are stored in the UNICOMMUART + * registers. See @ref DL_UART_init for how the peripheral control word + * is created. */ + uint32_t controlWord; + + /*! UART module clock source. One of @ref DL_UART_CLOCK */ + uint32_t clockSel; + + /*! UART clock divider. One of @ref DL_UART_CLOCK_DIVIDE_RATIO */ + uint32_t divideRatio; + + /*! Combination of UART Line Control Register configurations that are + * compressed to a single word as they are stored in the UNICOMMUART + * registers. See @ref DL_UART_init for how the peripheral control word + * is created. */ + uint32_t lineControlRegisterWord; + + /*! Combination of UART interrupt FIFO level select configurations that are + * compressed to a single word as they are stored in the UNICOMMUART + * registers. */ + uint32_t interruptFifoLevelSelectWord; + + /*! UART integer baud rate divisor. Value between 0 - 65535. */ + uint32_t ibrd; + + /*! UART fractional baud rate divisor. Value between 0 - 63. */ + uint32_t fbrd; + + /*! Combination of UART glitch filter configurations that are + * compressed to a single word as they are stored in the UNICOMMUART + * registers. */ + uint32_t glitchFilterControlWord; + + /*! Combination of UART LIN basic configurations that are + * compressed to a single word as they are stored in the UNICOMMUART + * registers. */ + uint32_t linControlWord; + + /*! Combination of UART IrDA basic configurations that are + * compressed to a single word as they are stored in the UNICOMMUART + * registers. */ + uint32_t irdaControlWord; + + /*! UART address mask for 9-bit or Idle mode. */ + uint32_t addressMask; + + /*! UART address that should be matched for 9-bit or Idle mode. */ + uint32_t address; + + /*! UART interrupt status for EVENT0. + * Bitwise OR of @ref DL_UART_INTERRUPT */ + uint32_t interruptMask0; + + /*! UART interrupt status for EVENT1. + * Bitwise OR of @ref DL_UART_DMA_INTERRUPT_RX */ + uint32_t interruptMask1; + + /*! UART interrupt status for EVENT2. + * Bitwise OR of @ref DL_UART_DMA_INTERRUPT_TX */ + uint32_t interruptMask2; + + /*! Boolean flag indicating whether or not a valid configuration structure + * exists. Should not be modified by the user. */ + bool backupRdy; +} DL_UART_backupConfig; +/** + * @brief Initialize the UART peripheral + * + * Initializes all the common configurable options for the UART peripheral. Any + * other custom configuration can be done after calling this API. The UART is + * not enabled in this API. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] config Configuration for UART peripheral + */ +void DL_UART_init(UNICOMM_Inst_Regs *unicomm, DL_UART_Config *config); + +/** + * @brief Enables power on UART module + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_enablePower(unicomm); + if (unicomm->fixedMode == false) { + DL_UNICOMM_setIPMode(unicomm, DL_UNICOMM_UART); + } +} + +/** + * @brief Disables power on unicomm module + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disablePower(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_disablePower(unicomm); +} + +/** + * @brief Returns if power on unicomm module + * + * @param unicomm Pointer to the register overlay for the peripheral + * + * @return true if power is enabled + * @return false if power is disabled + */ +__STATIC_INLINE bool DL_UART_isPowerEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isPowerEnabled(unicomm); +} + +/** + * @brief Resets unicomm peripheral + * + * @param unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_reset(UNICOMM_Inst_Regs *unicomm) +{ + DL_UNICOMM_reset(unicomm); +} + +/** + * @brief Returns if unicomm peripheral was reset + * + * @param unicomm Pointer to the register overlay for the peripheral + * + * @return true if peripheral was reset + * @return false if peripheral wasn't reset + * + */ +__STATIC_INLINE bool DL_UART_isReset(UNICOMM_Inst_Regs *unicomm) +{ + return DL_UNICOMM_isReset(unicomm); +} + +/** + * @brief Enable the UART peripheral + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 |= UNICOMMUART_CTL0_ENABLE_ENABLE; +} + +/** + * @brief Checks if the UART peripheral is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the enabled status of the UNICOMMUART + * + * @retval true The UART peripheral is enabled + * @retval false The UART peripheral is disabled + + */ +__STATIC_INLINE bool DL_UART_isEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->CTL0 & UNICOMMUART_CTL0_ENABLE_MASK) == + UNICOMMUART_CTL0_ENABLE_ENABLE); +} + +/** + * @brief Disable the UART peripheral + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disable(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 &= ~(UNICOMMUART_CTL0_ENABLE_MASK); +} + +/** + * @brief Configure UART source clock + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_UART_ClockConfig. + */ +void DL_UART_setClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_UART_ClockConfig *config); + +/** + * @brief Get UART source clock configuration + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] config Pointer to the clock configuration struct + * @ref DL_UART_ClockConfig. + */ +void DL_UART_getClockConfig( + UNICOMM_Inst_Regs *unicomm, DL_UART_ClockConfig *config); + +/** + * @brief Configure the baud rate + * + * Given the target baud rate and the frequency of the UART clock source, this + * API determines and sets the recommended oversampling setting, and then + * calculates and sets the required baud rate divisors. + * + * The oversampling rate that will be set is the highest possible oversampling + * rate given the target baud rate and UART clock frequency. + * + * If the user wishes to avoid having the CPU calculate the baud rate divisors + * or not use the recommended calculated values, the user can call + * @ref DL_UART_setOversampling and @ref DL_UART_setBaudRateDivisor directly. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] clockFreq The clock frequency in Hz of the UART clock source + * @param[in] baudRate The target baud rate + * + * @sa DL_UART_setOversampling + * @sa DL_UART_setBaudRateDivisor + */ +void DL_UART_configBaudRate( + UNICOMM_Inst_Regs *unicomm, uint32_t clockFreq, uint32_t baudRate); + +/** + * @brief Set the oversampling rate + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] rate The oversampling rate to use. + * One of @ref DL_UART_OVERSAMPLING_RATE + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_setOversampling( + UNICOMM_Inst_Regs *unicomm, DL_UART_OVERSAMPLING_RATE rate) +{ + DL_Common_updateReg( + &unicomm->uart->CTL0, (uint32_t) rate, UNICOMMUART_CTL0_HSE_MASK); +} + +/** + * @brief Get the oversampling rate + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The current oversampling rate + * + * @retval One of @ref DL_UART_OVERSAMPLING_RATE + * + */ +__STATIC_INLINE DL_UART_OVERSAMPLING_RATE DL_UART_getOversampling( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t rate = unicomm->uart->CTL0 & UNICOMMUART_CTL0_HSE_MASK; + + return (DL_UART_OVERSAMPLING_RATE)(rate); +} + +/** + * @brief Enable loopback mode + * + * Enables the loopback mode. When enabled, the UNICOMMUARTxTXD path is fed through + * the UNICOMMUARTxRXD path. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_enableLoopbackMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 |= UNICOMMUART_CTL0_LBE_ENABLE; +} + +/** + * @brief Check if loopback mode is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of loopback mode + * + * @retval true Loopback mode is enabled + * @retval false Loopback mode is disabled + */ +__STATIC_INLINE bool DL_UART_isLoopbackModeEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->CTL0 & UNICOMMUART_CTL0_LBE_MASK) == + UNICOMMUART_CTL0_LBE_ENABLE); +} + +/** + * @brief Disable loopback mode + * + * Disables the loopback mode. When disabled, the UNICOMMUARTxTXD path is not fed through + * the UNICOMMUARTxRXD path. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_disableLoopbackMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 &= ~(UNICOMMUART_CTL0_LBE_MASK); +} + +/** + * @brief Set the direction of the UART communication + * + * If the UART is disabled in the middle of a transmit or receive, it + * completes the current character before stopping. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] direction Direction to set UART communication to. + * One of @ref DL_UART_DIRECTION. + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + * + */ +__STATIC_INLINE void DL_UART_setDirection( + UNICOMM_Inst_Regs *unicomm, DL_UART_DIRECTION direction) +{ + DL_Common_updateReg(&unicomm->uart->CTL0, (uint32_t) direction, + UNICOMMUART_CTL0_TXE_MASK | UNICOMMUART_CTL0_RXE_MASK); +} + +/** + * @brief Get the direction of the UART communication + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The direction of UART communication. + * + * @retval One of @ref DL_UART_DIRECTION + */ +__STATIC_INLINE DL_UART_DIRECTION DL_UART_getDirection( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t direction = unicomm->uart->CTL0 & (UNICOMMUART_CTL0_TXE_MASK | + UNICOMMUART_CTL0_RXE_MASK); + + return (DL_UART_DIRECTION)(direction); +} + +/** + * @brief Enable majority voting control + * + * When enabled, the three center bits are used to determine received sample + * value. The value corresponding to at least two of the three samples is + * considered to be the received value.In case of error (i.e. all 3 bits are + * not the same), noise error is detected and bits RIS.NERR and register + * RXDATA.NERR are set. + * + * When enabled with oversampling of 16, samples 7, 8, and 9 are + * majority voted to decide the sampled bit value. + * + * When enabled with oversampling of 8, samples 3, 4, and 5 are majority + * voted to decide the sampled bit value. The value corresponding to at least 2 + * of the 3 samples is considered to be the received value. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + * + * @sa DL_UART_setOversampling + */ +__STATIC_INLINE void DL_UART_enableMajorityVoting(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 |= UNICOMMUART_CTL0_MAJVOTE_ENABLE; +} + +/** + * @brief Check if majority voting is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of majority control feature + * + * @retval true Majority voting is enabled + * @retval false Majority voting is disabled + */ +__STATIC_INLINE bool DL_UART_isMajorityVotingEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->CTL0 & UNICOMMUART_CTL0_MAJVOTE_MASK) == + UNICOMMUART_CTL0_MAJVOTE_ENABLE); +} + +/** + * @brief Disable majority voting control + * + * When disabled, only a single sample of the received bit of is taken. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_disableMajorityVoting(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 &= ~(UNICOMMUART_CTL0_MAJVOTE_MASK); +} + +/** + * @brief Enable most significant bit (MSB) first + * + * When enabled, the most significant bit (MSB) is sent first in the protocol + * packet. This bit has effect on both the way the protocol byte is + * transmitted and received. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_enableMSBFirst(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 |= UNICOMMUART_CTL0_MSBFIRST_ENABLE; +} + +/** + * @brief Check if most significant bit (MSB) first is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of majority control feature + * + * @retval true MSB first is enabled + * @retval false MSB first is disabled + */ +__STATIC_INLINE bool DL_UART_isMSBFirstEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->CTL0 & UNICOMMUART_CTL0_MSBFIRST_MASK) == + UNICOMMUART_CTL0_MSBFIRST_ENABLE); +} + +/** + * @brief Disable most significant bit (MSB) first + * + * When disabled, the least significant bit (LSB) is sent first in the protocol + * packet. This bit has effect on both the way the protocol byte is + * transmitted and received. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_disableMSBFirst(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 &= ~(UNICOMMUART_CTL0_MSBFIRST_MASK); +} + +/** + * @brief Enable control of the TXD pin + * + * When enabled, the TXD pin can be controlled by the TXD_OUT bit. The UNICOMMUART + * transmit section must first be disabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + * + * @sa DL_UART_setDirection + * @sa DL_UART_setTXDPin + */ +__STATIC_INLINE void DL_UART_enableTransmitPinManualControl( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 |= UNICOMMUART_CTL0_TXD_OUT_EN_ENABLE; +} + +/** + * @brief Check if control of the TXD pin is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of control of the TXD pin + * + * @retval true Control of the TXD pin is enabled + * @retval false Control of the TXD pin is disabled + */ +__STATIC_INLINE bool DL_UART_isTransmitPinManualControlEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->CTL0 & UNICOMMUART_CTL0_TXD_OUT_EN_MASK) == + UNICOMMUART_CTL0_TXD_OUT_EN_ENABLE); +} + +/** + * @brief Disable control of the TXD pin + * + * When disabled, the TXD pin can not be controlled by the TXD_OUT bit + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_disableTransmitPinManualControl( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 &= ~(UNICOMMUART_CTL0_TXD_OUT_EN_MASK); +} + +/** + * @brief Set the output of the TXD pin + * + * Control the output transmit data pin only when TXD_OUT_EN is enabled and + * TXE is disabled. + * + * The TXD pin is set to manual control if it hadn't been + * previously set. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] txdOutVal Value to set the TXD pin output to. + * One of @ref DL_UART_TXD_OUT + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + * + * @sa DL_UART_disableTransmitPinManualControl + * @sa DL_UART_enableTransmitPinManualControl + */ +__STATIC_INLINE void DL_UART_setTransmitPinManualOutput( + UNICOMM_Inst_Regs *unicomm, DL_UART_TXD_OUT txdOutVal) +{ + DL_Common_updateReg(&unicomm->uart->CTL0, + UNICOMMUART_CTL0_TXD_OUT_EN_ENABLE | (uint32_t) txdOutVal, + UNICOMMUART_CTL0_TXD_OUT_EN_MASK | UNICOMMUART_CTL0_TXD_OUT_MASK); +} + +/** + * @brief Get the output value of the TXD pin + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The value of the TXD pin + * + * @retval One of @ref DL_UART_TXD_OUT + */ +__STATIC_INLINE DL_UART_TXD_OUT DL_UART_getTransmitPinManualOutput( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t txdOutVal = unicomm->uart->CTL0 & UNICOMMUART_CTL0_TXD_OUT_MASK; + + return (DL_UART_TXD_OUT)(txdOutVal); +} + +/** + * @brief Enable Manchester encoding + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableManchesterEncoding( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 |= UNICOMMUART_CTL0_MENC_ENABLE; +} + +/** + * @brief Disable Manchester encoding + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableManchesterEncoding( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->CTL0 &= ~(UNICOMMUART_CTL0_MENC_MASK); +} + +/** + * @brief Check if Manchester encoding is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of Manchester encode + * + * @retval true Manchester encoding is enabled + * @retval false Manchester encoding is disabled + */ +__STATIC_INLINE bool DL_UART_isManchesterEncodingEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->CTL0 & UNICOMMUART_CTL0_MENC_MASK) == + UNICOMMUART_CTL0_MENC_ENABLE); +} + +/** + * @brief Set the communication mode/protocol to use + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] mode Value to set the UART communication protocol to. + * One of @ref DL_UART_MODE + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_setCommunicationMode( + UNICOMM_Inst_Regs *unicomm, DL_UART_MODE mode) +{ + DL_Common_updateReg( + &unicomm->uart->CTL0, (uint32_t) mode, UNICOMMUART_CTL0_MODE_MASK); +} + +/** + * @brief Get the communication mode/protocol being used + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The communication mode/protocol being used by the UNICOMMUART + * + * @retval One of @ref DL_UART_MODE + */ +__STATIC_INLINE DL_UART_MODE DL_UART_getCommunicationMode( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t mode = unicomm->uart->CTL0 & UNICOMMUART_CTL0_MODE_MASK; + + return (DL_UART_MODE)(mode); +} + +/** + * @brief Set the flow control configuration + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] config The flow control configuration to use. + * One of @ref DL_UART_FLOW_CONTROL. + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + */ +__STATIC_INLINE void DL_UART_setFlowControl( + UNICOMM_Inst_Regs *unicomm, DL_UART_FLOW_CONTROL config) +{ + DL_Common_updateReg(&unicomm->uart->CTL0, (uint32_t) config, + UNICOMMUART_CTL0_RTSEN_MASK | UNICOMMUART_CTL0_CTSEN_MASK); +} + +/** + * @brief Check the flow control configuration + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The flow control configuration + * + * @retval One of @ref DL_UART_FLOW_CONTROL values + */ +__STATIC_INLINE DL_UART_FLOW_CONTROL DL_UART_getFlowControl( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t config = unicomm->uart->CTL0 & (UNICOMMUART_CTL0_RTSEN_MASK | + UNICOMMUART_CTL0_CTSEN_MASK); + + return (DL_UART_FLOW_CONTROL)(config); +} + +/** + * @brief Set the request to send output signal + * + * The RTS output signal indicates the state of the RX FIFO, and is + * linked to the programmable receive FIFO threshold levels. When RTS flow + * control is enabled, the RTS signal is asserted (low) when the data in the + * RX FIFO is less than the threshold level. When the RX FIFO threshold level + * is reached, the RTS signal is deasserted (high). The RTS signal is + * reasserted (low) when data has been read out of the RX FIFO so it is less + * than the threshold. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] val The RTS output signal. One of @ref DL_UART_RTS + * + * @pre If the UART has already been enabled, then it must be made ready for + * configuration by first calling @ref DL_UART_changeConfig + * @post If @ref DL_UART_changeConfig was called, then the UART must be + * re-enabled by calling @ref DL_UART_enable + * + * @sa DL_UART_setTXFIFOThreshold + */ +__STATIC_INLINE void DL_UART_setRTSOutput( + UNICOMM_Inst_Regs *unicomm, DL_UART_RTS val) +{ + DL_Common_updateReg( + &unicomm->uart->CTL0, (uint32_t) val, UNICOMMUART_CTL0_RTS_MASK); +} + +/** + * @brief Get the request to send output signal + * + * The RTS output signal indicates the state of the RX FIFO, and is + * linked to the programmable receive FIFO threshold levels. When RTS flow + * control is enabled, the RTS signal is asserted (low) when the data in the + * RX FIFO is less than the threshold level. When the RX FIFO threshold level + * is reached, the RTS signal is deasserted (high). The RTS signal is + * reasserted (low) when data has been read out of the RX FIFO so it is less + * than the threshold. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The RTS signal status + * + * @retval One of @ref DL_UART_RTS + * + * @sa DL_UART_setTXFIFOThreshold + */ +__STATIC_INLINE DL_UART_RTS DL_UART_getRTSOutput(UNICOMM_Inst_Regs *unicomm) +{ + uint32_t val = unicomm->uart->CTL0 & UNICOMMUART_CTL0_RTS_MASK; + + return (DL_UART_RTS)(val); +} + +/** + * @brief Enable FIFOs + * + * @deprecated UNICOMM FIFOs are always enabled. This API is provided for backwards compatiblity ONLY. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableFIFOs(UNICOMM_Inst_Regs *unicomm) +{ + return; +} + +/** + * @brief Disable FIFOs + * + * @deprecated UNICOMM FIFOs are always enabled. This API is provided for backwards compatiblity ONLY. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableFIFOs(UNICOMM_Inst_Regs *unicomm) +{ + return; +} + +/** + * @brief Check if FIFOs are enabled + * + * @deprecated UNICOMM FIFOs are always eanbled. This API is provided for backwards compatiblity ONLY. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Always returns true + */ +__STATIC_INLINE bool DL_UART_isFIFOsEnabled(const UNICOMM_Inst_Regs *unicomm) +{ + return true; +} + +/** + * @brief Enable send break (for LIN protocol) + * + * When enabled, a low level is continually output on the TXD signal after completing + * transmission of the current character. For the proper execution of the + * break command, software must set this bit for at least two frames (character periods). + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableLINSendBreak(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LCRH |= UNICOMMUART_LCRH_BRK_ENABLE; +} + +/** + * @brief Disable send break + * + * When disabled, a low level is not continually output on the TXD signal + * after completing transmission of the current character. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableLINSendBreak(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LCRH &= ~(UNICOMMUART_LCRH_BRK_MASK); +} + +/** + * @brief Check if send break is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of send break + * + * @retval true Send break is enabled + * @retval false Send break is disabled + */ +__STATIC_INLINE bool DL_UART_isLINSendBreakEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LCRH & UNICOMMUART_LCRH_BRK_MASK) == + UNICOMMUART_LCRH_BRK_ENABLE); +} + +/** + * @brief Check if parity is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of parity + * + * @retval true Parity is enabled + * @retval false Parity is disabled + */ +__STATIC_INLINE bool DL_UART_isParityEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LCRH & UNICOMMUART_LCRH_PEN_MASK) == + UNICOMMUART_LCRH_PEN_ENABLE); +} + +/** + * @brief Set the parity mode + * + * For 9-bit UART mode transmissions, the parity mode affects the address + * byte and data byte indication (9th bit). If DL_UART_PARITY_EVEN or + * DL_UART_PARITY_STICK_ZERO is enabled, then the transferred byte is a data + * byte. If DL_UART_PARITY_EVEN or DL_UART_PARITY_STICK_ZERO is not enabled, + * then the transferred byte is an address byte. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] parity Parity mode to set UART to. + * One of @ref DL_UART_PARITY + */ +__STATIC_INLINE void DL_UART_setParityMode( + UNICOMM_Inst_Regs *unicomm, DL_UART_PARITY parity) +{ + DL_Common_updateReg(&unicomm->uart->LCRH, (uint32_t) parity, + (UNICOMMUART_LCRH_PEN_MASK | UNICOMMUART_LCRH_EPS_MASK | + UNICOMMUART_LCRH_SPS_MASK)); +} + +/** + * @brief Get parity mode + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The current parity mode being used + * + * @retval One of @ref DL_UART_PARITY + * + */ +__STATIC_INLINE DL_UART_PARITY DL_UART_getParityMode( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t parity = unicomm->uart->LCRH & + (UNICOMMUART_LCRH_PEN_MASK | UNICOMMUART_LCRH_EPS_MASK | + UNICOMMUART_LCRH_SPS_MASK); + + return (DL_UART_PARITY)(parity); +} + +/** + * @brief Set the number of stop bits + * + * When in 7816 smart code mode (DL_UART_MODE_SMART_CARD mode), the number of + * stop bits is forced to 2 + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] numStopBits The number of stop bits transmitted. + * One of @ref DL_UART_STOP_BITS + */ +__STATIC_INLINE void DL_UART_setStopBits( + UNICOMM_Inst_Regs *unicomm, DL_UART_STOP_BITS numStopBits) +{ + DL_Common_updateReg(&unicomm->uart->LCRH, (uint32_t) numStopBits, + UNICOMMUART_LCRH_STP2_MASK); +} + +/** + * @brief Get the number of stop bits + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The number of stop bits transmitted. + * + * @retval One of @ref DL_UART_STOP_BITS + */ +__STATIC_INLINE DL_UART_STOP_BITS DL_UART_getStopBits( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t numStopBits = unicomm->uart->LCRH & UNICOMMUART_LCRH_STP2_MASK; + + return (DL_UART_STOP_BITS)(numStopBits); +} + +/** + * @brief Set the word length + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] wordLength The number of data bits transmitted or received in + * a frame. One of @ref DL_UART_WORD_LENGTH + */ +__STATIC_INLINE void DL_UART_setWordLength( + UNICOMM_Inst_Regs *unicomm, DL_UART_WORD_LENGTH wordLength) +{ + DL_Common_updateReg(&unicomm->uart->LCRH, (uint32_t) wordLength, + UNICOMMUART_LCRH_WLEN_MASK); +} + +/** + * @brief Get the word length + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The length of the data bits transmitted or received in a frame + * + * @retval One of @ref DL_UART_WORD_LENGTH + */ +__STATIC_INLINE DL_UART_WORD_LENGTH DL_UART_getWordLength( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t wordLength = unicomm->uart->LCRH & UNICOMMUART_LCRH_WLEN_MASK; + + return (DL_UART_WORD_LENGTH)(wordLength); +} + +/** + * @brief Send idle pattern + * + * When enabled, a SENDIDLE period of 11 bit times will be sent on the TX + * line. The bit is cleared by hardware afterwards. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableSendIdlePattern(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LCRH |= UNICOMMUART_LCRH_SENDIDLE_ENABLE; +} + +/** + * @brief Disable send idle pattern + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableSendIdlePattern(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LCRH &= ~(UNICOMMUART_LCRH_SENDIDLE_MASK); +} + +/** + * @brief Check if send idle pattern is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of the send idle pattern + * + * @retval true Send idle pattern is enabled + * @retval false Send idle pattern is disabled + */ +__STATIC_INLINE bool DL_UART_isSendIdlePatternEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LCRH & UNICOMMUART_LCRH_SENDIDLE_MASK) == + UNICOMMUART_LCRH_SENDIDLE_ENABLE); +} + +/** + * @brief Set external driver setup value + * + * Defines the number of UNICOMMUARTclk ticks the signal to control the external + * driver for the RS485 will be set before the START bit is sent + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] val The number of UNICOMMUARTclk ticks the signal before the RS485 + * is setup. Value between 0 - 31. + */ +__STATIC_INLINE void DL_UART_setExternalDriverSetup( + UNICOMM_Inst_Regs *unicomm, uint32_t val) +{ + DL_Common_updateReg(&unicomm->uart->LCRH, + val << UNICOMMUART_LCRH_EXTDIR_SETUP_OFS, + UNICOMMUART_LCRH_EXTDIR_SETUP_MASK); +} + +/** + * @brief Get the external driver setup value + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The number of UNICOMMUARTclk ticks the signal to control the + * external driver + * + * @retval 0 - 31 The number of UNICOMMUARTclk ticks + */ +__STATIC_INLINE uint32_t DL_UART_getExternalDriverSetup( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LCRH & UNICOMMUART_LCRH_EXTDIR_SETUP_MASK) >> + UNICOMMUART_LCRH_EXTDIR_SETUP_OFS); +} + +/** + * @brief Set external driver setup hold + * + * Defines the number of UNICOMMUARTclk ticks the signal to control the external + * driver for the RS485 will be reset after the beginning of the stop bit. + * If 2 STOP bits are enabled, the RS485 will be reset at the beginning of + * the 2nd STOP bit. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] val The number of UNICOMMUARTclk ticks the signal to hold the + * external driver before the RS485 will be reset. + * Value between 0 - 31. + */ +__STATIC_INLINE void DL_UART_setExternalDriverHold( + UNICOMM_Inst_Regs *unicomm, uint32_t val) +{ + DL_Common_updateReg(&unicomm->uart->LCRH, + val << UNICOMMUART_LCRH_EXTDIR_HOLD_OFS, + UNICOMMUART_LCRH_EXTDIR_HOLD_MASK); +} + +/** + * @brief Get the external driver setup hold + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The number of UNICOMMUARTclk ticks the signal to hold the + * external driver before the RS485 will be reset + * + * @retval 0 - 31 The number of UNICOMMUARTclk ticks + */ +__STATIC_INLINE uint32_t DL_UART_getExternalDriverHold( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LCRH & UNICOMMUART_LCRH_EXTDIR_HOLD_MASK) >> + UNICOMMUART_LCRH_EXTDIR_HOLD_OFS); +} + +/** + * @brief Checks if the UART is busy + * + * This bit is set as soon as the transmit FIFO or TXDATA register becomes + * non-empty (regardless of whether UART is enabled) or if a receive data is + * currently ongoing (after the start edge have been detected until a complete + * byte, including all stop bits, has been received by the shift register). + * + * In IDLE Line mode the Busy signal also stays set during the idle time + * generation. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of the UART Busy bit + * + * @retval true The UART is busy + * @retval false The UART is not busy + * + */ +__STATIC_INLINE bool DL_UART_isBusy(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->STAT & UNICOMMUART_STAT_BUSY_MASK) == + UNICOMMUART_STAT_BUSY_SET); +} + +/** + * @brief Checks if the RX FIFO is empty + * + * The meaning of this bit depends on if the FIFOs were enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the empty status of the RX FIFO + * + * @retval true If the FIFO is enabled, the receive FIFO is empty. + * If the FIFO is disabled, the receiver has no data. + * @retval false The receiver is not empty + */ +__STATIC_INLINE bool DL_UART_isRXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->STAT & UNICOMMUART_STAT_RXFE_MASK) == + UNICOMMUART_STAT_RXFE_SET); +} + +/** + * @brief Checks if the RX FIFO is full + * + * The meaning of this bit depends on if the FIFOs were enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the full status of the RX FIFO + * + * @retval true If the FIFO is enabled, the receive FIFO is full. + * If the FIFO is disabled, the receiver has 1-byte + * of data. + * @retval false The receiver is not full + */ +__STATIC_INLINE bool DL_UART_isRXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->STAT & UNICOMMUART_STAT_RXFF_MASK) == + UNICOMMUART_STAT_RXFF_SET); +} + +/** + * @brief Checks if the TX FIFO is empty + * + * The meaning of this bit depends on if the FIFOs were enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the empty status of the TX FIFO + * + * @retval true If the FIFO is enabled, the transmit FIFO is empty. + * If the FIFO is disabled, the transmitter has no data. + * @retval false The transmitter is not empty + */ +__STATIC_INLINE bool DL_UART_isTXFIFOEmpty(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->STAT & UNICOMMUART_STAT_TXFE_MASK) == + UNICOMMUART_STAT_TXFE_SET); +} + +/** + * @brief Checks if the TX FIFO is full + * + * The meaning of this bit depends on if the FIFOs were enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the full status of the TX FIFO + * + * @retval true If the FIFO is enabled, the transmit FIFO is full. + * If the FIFO is disabled, the transmitter has 1-byte + * of data. + * @retval false The transmitter is not full + */ +__STATIC_INLINE bool DL_UART_isTXFIFOFull(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->STAT & UNICOMMUART_STAT_TXFF_MASK) == + UNICOMMUART_STAT_TXFF_SET); +} + +/** + * @brief Checks if UART is clear to send + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the status of the CTS signal + * + * @retval true The CTS signal is asserted (low) + * @retval false The CTS signal is not asserted (high) + * + * @sa DL_UART_isClearToSendEnabled + */ +__STATIC_INLINE bool DL_UART_isClearToSend(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->STAT & UNICOMMUART_STAT_CTS_MASK) == + UNICOMMUART_STAT_CTS_SET); +} + +/** + * @brief Checks if Idle mode has been detected + * + * Idle mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit + * is used as an address tag for each block of characters. In idle-line + * multiprocessor format, this bit is set when a received character is an + * address. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return Returns the status if Idle mode has been detected + * + * @retval true Idle has been detected before last received character + * @retval false Idle has not been detected before last received character + * + */ +__STATIC_INLINE bool DL_UART_isIdleModeDetected(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->STAT & UNICOMMUART_STAT_IDLE_MASK) == + UNICOMMUART_STAT_IDLE_SET); +} + +/** + * @brief Set the TX FIFO interrupt threshold level + * + * Select the threshold for the transmit FIFO interrupt. The interrupts are + * generated based on a transition through a level rather than being based on + * the level. That is, the interrupts are generated when the fill level + * progresses through the trigger level. For example, if the transmit trigger + * level is set to the half-way mark, the interrupt is triggered when the + * transmit FIFO becomes half empty. In other words, if the transmit FIFO was + * filled with four characters, the interrupt would trigger once there are + * two or less characters after transmitting. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] threshold One of @ref DL_UART_TX_FIFO_LEVEL + * + */ +__STATIC_INLINE void DL_UART_setTXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm, DL_UART_TX_FIFO_LEVEL threshold) +{ + DL_Common_updateReg(&unicomm->uart->IFLS, (uint32_t) threshold, + UNICOMMUART_IFLS_TXIFLSEL_MASK); +} + +/** + * @brief Get the TX FIFO interrupt threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The TX FIFO interrupt threshold level + * + * @retval One of @ref DL_UART_TX_FIFO_LEVEL + */ +__STATIC_INLINE DL_UART_TX_FIFO_LEVEL DL_UART_getTXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t threshold = unicomm->uart->IFLS & UNICOMMUART_IFLS_TXIFLSEL_MASK; + + return (DL_UART_TX_FIFO_LEVEL)(threshold); +} + +/** + * @brief Set the RX FIFO interrupt threshold level. The interrupts are + * generated based on a transition through a level rather than being based on + * the level. That is, the interrupts are generated when the fill level + * progresses through the trigger level. For example, if the receive trigger + * level is set to the half-way mark, the interrupt is triggered when the + * receive FIFO becomes half full. In other words, the interrupt is triggered + * after the receive FIFO is filled with two or more characters. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] threshold One of @ref DL_UART_RX_FIFO_LEVEL + */ +__STATIC_INLINE void DL_UART_setRXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm, DL_UART_RX_FIFO_LEVEL threshold) +{ + DL_Common_updateReg(&unicomm->uart->IFLS, (uint32_t) threshold, + UNICOMMUART_IFLS_RXIFLSEL_MASK); +} + +/** + * @brief Get the RX FIFO interrupt threshold level + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The RX FIFO interrupt threshold level + * + * @retval One of @ref DL_UART_RX_FIFO_LEVEL + */ +__STATIC_INLINE DL_UART_RX_FIFO_LEVEL DL_UART_getRXFIFOThreshold( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t threshold = unicomm->uart->IFLS & UNICOMMUART_IFLS_RXIFLSEL_MASK; + + return (DL_UART_RX_FIFO_LEVEL)(threshold); +} + +/** + * @brief Set the RX interrupt timeout + * + * When an additional character has not been received within the set + * timeout, a RX interrupt will still trigger even if the FIFO level has not + * been reached. A value of 0 disables this function. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] timeout Timeout to set the RX interrupt to. + * Value between 0 - 15 + */ +__STATIC_INLINE void DL_UART_setRXInterruptTimeout( + UNICOMM_Inst_Regs *unicomm, uint32_t timeout) +{ + DL_Common_updateReg(&unicomm->uart->IFLS, + timeout << UNICOMMUART_IFLS_RXTOSEL_OFS, + UNICOMMUART_IFLS_RXTOSEL_MASK); +} + +/** + * @brief Get the RX interrupt timeout + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The RX interrupt timeout value + * + * @retval 0 - 15 The RX interrupt timeout value + * + */ +__STATIC_INLINE uint32_t DL_UART_getRXInterruptTimeout( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->IFLS & UNICOMMUART_IFLS_RXTOSEL_MASK) >> + UNICOMMUART_IFLS_RXTOSEL_OFS); +} + +/** + * @brief Get Integer Baud-Rate Divisor + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The integer component of the baud rate divisor + * + * @retval 0 - 65535 The integer baud date divisor + */ +__STATIC_INLINE uint32_t DL_UART_getIntegerBaudRateDivisor( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->IBRD & UNICOMMUART_IBRD_DIVINT_MASK); +} + +/** + * @brief Get Fractional Baud-Rate Divisor + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The fractional component of the baud rate divisor + * + * @retval 0 - 63 The fractional baud date divisor + */ +__STATIC_INLINE uint32_t DL_UART_getFractionalBaudRateDivisor( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->FBRD & UNICOMMUART_FBRD_DIVFRAC_MASK); +} + +/** + * @brief Set the baud rate divisor + * + * Set the integer baud rate divisor and fractional baud rate divisor + * components of the baud rate divisor + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] integerDivisor The integer component of the baud rate + * divisor + * @param[in] fractionalDivisor The fractional component of the baud rate + * divisor + */ +__STATIC_INLINE void DL_UART_setBaudRateDivisor(UNICOMM_Inst_Regs *unicomm, + uint32_t integerDivisor, uint32_t fractionalDivisor) +{ + DL_Common_updateReg( + &unicomm->uart->IBRD, integerDivisor, UNICOMMUART_IBRD_DIVINT_MASK); + DL_Common_updateReg(&unicomm->uart->FBRD, fractionalDivisor, + UNICOMMUART_FBRD_DIVFRAC_MASK); + + // When updating the baud-rate divisor (UNICOMMUARTIBRD or UNICOMMUARTIFRD), + // the LCRH register must also be written to (any bit in LCRH can + // be written to for updating the baud-rate divisor). + DL_Common_updateReg(&unicomm->uart->LCRH, + (unicomm->uart->LCRH & UNICOMMUART_LCRH_BRK_MASK), + UNICOMMUART_LCRH_BRK_MASK); +} + +/** + * @brief Set the pulse width select for the digital glitch suppresion + * + * Controls the pulse width select for glitch suppression on the RX line. + * The glitch suppression values are in terms of functional clocks. + * + * In IrDA mode, this sets the receive filter length. The minimum pulse + * length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK) + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] pulseWidth Pulse width select for the glitch suppresion. + * Value between 0 - 63. + */ +__STATIC_INLINE void DL_UART_setDigitalPulseWidth( + UNICOMM_Inst_Regs *unicomm, uint32_t pulseWidth) +{ + DL_Common_updateReg( + &unicomm->uart->GFCTL, pulseWidth, UNICOMMUART_GFCTL_DGFSEL_MASK); +} + +/** + * @brief Get the pulse width select for the digital glitch suppresion + * + * Gets the pulse width select for glitch suppression on the RX line. + * The glitch suppression values are in terms of functional clocks. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The digital glitch suppression pulse width + * + * @retval 0 indicating digital glitch suppression is disabled + * @retval 1 - 63 the digital glitch suppression pulse width + */ +__STATIC_INLINE uint32_t DL_UART_getDigitalPulseWidth( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->GFCTL & UNICOMMUART_GFCTL_DGFSEL_MASK); +} + +/** + * @brief Writes data into the TX FIFO to transmit + * + * Puts the data into the TX FIFO without checking it's status. Use if already + * sure the TX FIFO has space for the write. See related APIs for additional + * transmit options. + * + * For transmitted data, if the FIFO is enabled, data written to this + * location is pushed onto the transmit FIFO. If the FIFO is disabled, + * data is stored in the 1-byte deep transmitter. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] data The data to transmit + * + * + * @sa DL_UART_transmitDataBlocking + * @sa DL_UART_transmitDataCheck + */ +__STATIC_INLINE void DL_UART_transmitData( + UNICOMM_Inst_Regs *unicomm, uint8_t data) +{ + unicomm->uart->TXDATA = data; +} + +/** + * @brief Reads data from the RX FIFO + * + * Reads the data from the RX FIFO without checking its status. Use if + * already sure the RX FIFO has data available. See related APIs for + * additional receive options. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_UART_receiveDataBlocking + * @sa DL_UART_receiveDataCheck + */ +__STATIC_INLINE uint8_t DL_UART_receiveData(UNICOMM_Inst_Regs *unicomm) +{ + return ((uint8_t)(unicomm->uart->RXDATA & UNICOMMUART_RXDATA_DATA_MASK)); +} + +/** + * @brief Gets the status of the error flags of the received data + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] errorMask Bit mask of error flags to check. Bitwise OR of + * @ref DL_UART_ERROR. + * + * @return The status of the requested UART error flags + * + * @retval Bitwise OR of @ref DL_UART_ERROR values + */ +__STATIC_INLINE uint32_t DL_UART_getErrorStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t errorMask) +{ + return (unicomm->uart->RXDATA & errorMask); +} + +/** + * @brief Set the LIN counter value + * + * The LIN counter is a 16 bit up counter clocked by the functional clock of + * the UNICOMMUART + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] value Pulse width select for the glitch suppresion. + */ +__STATIC_INLINE void DL_UART_setLINCounterValue( + UNICOMM_Inst_Regs *unicomm, uint16_t value) +{ + DL_Common_updateReg( + &unicomm->uart->LINCNT, value, UNICOMMUART_LINCNT_VALUE_MASK); +} + +/** + * @brief Get the LIN counter value + * + * The LIN counter is a 16 bit up counter clocked by the module clock of + * the UNICOMMUART + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The clock counter value + * + * @retval 0 - 65535 The clock counter value + * + */ +__STATIC_INLINE uint16_t DL_UART_getLINCounterValue(UNICOMM_Inst_Regs *unicomm) +{ + return ((uint16_t)(unicomm->uart->LINCNT & UNICOMMUART_LINCNT_VALUE_MASK)); +} + +/** + * @brief Enable the LIN counter + * + * The LIN counter will only count when enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableLINCounter(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL |= UNICOMMUART_LINCTL_CTRENA_ENABLE; +} + +/** + * @brief Check if the LIN counter is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of the LIN counter + * + * @retval true LIN counter is enabled + * @retval false LIN counter is disabled + */ +__STATIC_INLINE bool DL_UART_isLINCounterEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LINCTL & UNICOMMUART_LINCTL_CTRENA_MASK) == + UNICOMMUART_LINCTL_CTRENA_ENABLE); +} + +/** + * @brief Disable the LIN counter + * + * LIN counter will only count when enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableLINCounter(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL &= ~(UNICOMMUART_LINCTL_CTRENA_MASK); +} + +/** + * @brief Enable LIN counter clear and start counting on falling edge of RXD + * + * When enabled, the counter is set to 0 and starts counting on the LIN counter + * on a falling edge of RXD. + * + * The LIN counter will only count when it is enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_UART_enableLINCounter + */ +__STATIC_INLINE void DL_UART_enableLINCounterClearOnFallingEdge( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL |= UNICOMMUART_LINCTL_ZERONE_ENABLE; +} + +/** + * @brief Check if LIN counting on falling edge of RXD is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of counting on falling edge of RXD + * + * @retval true Counting on falling edge is enabled + * @retval false Counting on falling edge is disabled + */ +__STATIC_INLINE bool DL_UART_isLINCounterClearOnFallingEdge( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LINCTL & UNICOMMUART_LINCTL_ZERONE_MASK) == + UNICOMMUART_LINCTL_ZERONE_ENABLE); +} + +/** + * @brief Disable LIN counting on falling edge of RXD + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableLINCounterClearOnFallingEdge( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL &= ~(UNICOMMUART_LINCTL_ZERONE_MASK); +} + +/** + * @brief Enable LIN counter incrementing while RXD signal is low + * + * When LIN counter is enabled and the signal on RXD is low, the counter + * increments + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_UART_enableLINCounter + */ +__STATIC_INLINE void DL_UART_enableLINCountWhileLow(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL |= UNICOMMUART_LINCTL_CNTRXLOW_ENABLE; +} + +/** + * @brief Check if LIN counter increments while RXD signal is low is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of counter increments while RXD signal is low + * + * @retval true Counter increments while RXD signal is low is enabled + * @retval false Counter increments while RXD signal is low is disabled + */ +__STATIC_INLINE bool DL_UART_isLINCountWhileLowEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LINCTL & UNICOMMUART_LINCTL_CNTRXLOW_MASK) == + UNICOMMUART_LINCTL_CNTRXLOW_ENABLE); +} + +/** + * @brief Disable LIN counter increments while RXD signal is low + * + * LIN counter will not increment while the RXD signal is low + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableLINCountWhileLow( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL &= ~(UNICOMMUART_LINCTL_CNTRXLOW_MASK); +} + +/** + * @brief Enable capture of the LIN counter on a falling edge + * + * When enabled, the LIN counter value is captured to the LINC0 register on + * each falling RXD edge. A LINC0 interrupt is triggered when enabled. + * Disables counter compare match mode if enabled. + * + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @sa DL_UART_configLINMode + */ +__STATIC_INLINE void DL_UART_enableLINFallingEdgeCapture( + UNICOMM_Inst_Regs *unicomm) +{ + DL_Common_updateReg(&unicomm->uart->LINCTL, + UNICOMMUART_LINCTL_LINC0CAP_ENABLE | + UNICOMMUART_LINCTL_LINC0_MATCH_DISABLE, + UNICOMMUART_LINCTL_LINC0CAP_MASK | + UNICOMMUART_LINCTL_LINC0_MATCH_MASK); +} + +/** + * @brief Check status of capture of LIN counter on a falling edge + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of capture the LIN counter on a falling edge + * + * @retval true Capture to LINC0 on falling RXD edge is enabled + * @retval false Capture to LINC0 on falling RXD edge is disabled + */ +__STATIC_INLINE bool DL_UART_isLINFallingEdgeCaptureEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LINCTL & UNICOMMUART_LINCTL_LINC0CAP_MASK) == + UNICOMMUART_LINCTL_LINC0CAP_ENABLE); +} + +/** + * @brief Disable capture of LIN counter on a falling edge + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableLINFallingEdgeCapture( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL &= ~(UNICOMMUART_LINCTL_LINC0CAP_MASK); +} + +/** + * @brief Enable capture of the LIN counter on a rising edge + * + * When enabled the LIN counter value is captured to LINC1 register on each + * rising RXD edge. A LINC1 interrupt is triggered when enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + */ +__STATIC_INLINE void DL_UART_enableLINRisingEdgeCapture( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL |= UNICOMMUART_LINCTL_LINC1CAP_ENABLE; +} + +/** + * @brief Check status of capture of LIN counter on a rising edge + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of capture of LIN counter on a rising edge + * + * @retval true Capture to LINC1 on rising RXD edge is enabled + * @retval false Capture to LINC1 on rising RXD edge is disabled + */ +__STATIC_INLINE bool DL_UART_isLINRisingEdgeCaptureEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LINCTL & UNICOMMUART_LINCTL_LINC1CAP_MASK) == + UNICOMMUART_LINCTL_LINC1CAP_ENABLE); +} + +/** + * @brief Disable capture of LIN counter on a rising edge + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableLINRisingEdgeCapture( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL &= ~(UNICOMMUART_LINCTL_LINC1CAP_MASK); +} + +/** + * @brief Enable LIN counter compare match mode + * + * When enabled, a match between a value in LINC0 and the LIN counter can + * trigger a LINC0 interrupt. Disables capture on falling edge if enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableLINCounterCompareMatch( + UNICOMM_Inst_Regs *unicomm) +{ + DL_Common_updateReg(&unicomm->uart->LINCTL, + UNICOMMUART_LINCTL_LINC0_MATCH_ENABLE | + UNICOMMUART_LINCTL_LINC0CAP_DISABLE, + UNICOMMUART_LINCTL_LINC0CAP_MASK | + UNICOMMUART_LINCTL_LINC0_MATCH_MASK); +} + +/** + * @brief Setup LIN counter control for sync field validation + * + * Enable LIN counter capture on rising RX edge. Enable LIN counter capture on falling RX edge. + * Enable LIN counter clearing on RX falling edge. Enable LIN counter. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableLINSyncFieldValidationCounterControl( + UNICOMM_Inst_Regs *unicomm) +{ + DL_Common_updateReg(&unicomm->uart->LINCTL, + UNICOMMUART_LINCTL_LINC0CAP_ENABLE | + UNICOMMUART_LINCTL_LINC1CAP_ENABLE | + UNICOMMUART_LINCTL_ZERONE_ENABLE | + UNICOMMUART_LINCTL_CTRENA_ENABLE, + UNICOMMUART_LINCTL_LINC0CAP_MASK | UNICOMMUART_LINCTL_LINC1CAP_MASK | + UNICOMMUART_LINCTL_ZERONE_MASK | UNICOMMUART_LINCTL_CTRENA_MASK); +} + +/** + * @brief Setup LIN counter control for LIN reception + * + * Enable count while low signal on RXD. Enable LIN counter clearing on RXD falling edge. + * Enable LIN counter. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableLINReceptionCountControl( + UNICOMM_Inst_Regs *unicomm) +{ + DL_Common_updateReg(&unicomm->uart->LINCTL, + UNICOMMUART_LINCTL_CNTRXLOW_ENABLE | UNICOMMUART_LINCTL_ZERONE_ENABLE | + UNICOMMUART_LINCTL_CTRENA_ENABLE, + UNICOMMUART_LINCTL_CNTRXLOW_MASK | UNICOMMUART_LINCTL_ZERONE_MASK | + UNICOMMUART_LINCTL_CTRENA_MASK); +} + +/** + * @brief Check if LIN counter compare match mode is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of counter compare match mode + * + * @retval true LIN counter compare match mode is enabled + * @retval false LIN counter compare match mode is disabled + */ +__STATIC_INLINE bool DL_UART_isLINCounterCompareMatchEnabled( + UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->LINCTL & UNICOMMUART_LINCTL_LINC0_MATCH_MASK) == + UNICOMMUART_LINCTL_LINC0_MATCH_ENABLE); +} + +/** + * @brief Disable LIN counter compare match mode + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableLINCounterCompareMatch( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->LINCTL &= ~(UNICOMMUART_LINCTL_LINC0_MATCH_MASK); +} + +/** + * @brief Set the value to be compared to the LIN counter + * + * Sets the value of LINC0 to be used to compare to the LIN counter. For use + * when LIN counter compare match mode is enabled. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] value Value to be compared to the LIN counter for matching. + * Value between 0 - 65535. + * + * @sa DL_UART_enableLINCounterCompareMatch + */ +__STATIC_INLINE void DL_UART_setLINCounterCompareValue( + UNICOMM_Inst_Regs *unicomm, uint16_t value) +{ + DL_Common_updateReg( + &unicomm->uart->LINC0, value, UNICOMMUART_LINC0_DATA_MASK); +} + +/** + * @brief Get the LINC0 counter value + * + * Captures current LINCTR value on RXD falling edge. + * + * If capture is enabled with @ref DL_UART_enableLINFallingEdgeCapture, a + * capture can generate a LINC0 interrupt. + * If compare mode is enabled with @ref DL_UART_enableLINCounterCompareMatch, + * a counter match can generate a LINC0 interrupt. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The LINC0 counter value + * + * @retval 0 - 65535 The LINC0 counter value + * + * @sa DL_UART_enableLINFallingEdgeCapture + * @sa DL_UART_enableLINCounterCompareMatch + */ +__STATIC_INLINE uint16_t DL_UART_getLINFallingEdgeCaptureValue( + UNICOMM_Inst_Regs *unicomm) +{ + return ((uint16_t)(unicomm->uart->LINC0 & UNICOMMUART_LINC0_DATA_MASK)); +} + +/** + * @brief Get the LINC1 counter value + * + * Captures current LINCTR value on RXD rising edge. For use when LIN rising + * edge capture is enabled. It can generate a LINC1 interrupt on capture. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The LINC1 counter value + * + * @retval 0 - 65535 The LINC1 counter value + * + * @sa DL_UART_enableLINRisingEdgeCapture + */ +__STATIC_INLINE uint16_t DL_UART_getLINRisingEdgeCaptureValue( + UNICOMM_Inst_Regs *unicomm) +{ + return ((uint16_t)(unicomm->uart->LINC1 & UNICOMMUART_LINC1_DATA_MASK)); +} + +/** + * @brief Enable the IrDA encoder/decoder + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_enableIrDAMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->IRCTL |= UNICOMMUART_IRCTL_IREN_ENABLE; +} + +/** + * @brief Check if the IrDA encoder/decoder is enabled + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The status of IrDA mode + * + * @retval true IrDA mode is enabled + * @retval false IrDA mode is disabled + */ +__STATIC_INLINE bool DL_UART_isIrDAModeEnabled(UNICOMM_Inst_Regs *unicomm) +{ + return ((unicomm->uart->IRCTL & UNICOMMUART_IRCTL_IREN_MASK) == + UNICOMMUART_IRCTL_IREN_ENABLE); +} + +/** + * @brief Disable the IrDA encoder/decoder + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_disableIrDAMode(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->IRCTL &= ~(UNICOMMUART_IRCTL_IREN_MASK); +} + +/** + * @brief Set the IrDA transmit pulse clock select + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] uartClock The clock select for the IrDA pulse data to be based on. + * One of @ref DL_UART_IRDA_CLOCK + */ +__STATIC_INLINE void DL_UART_setIrDATXPulseClockSelect( + UNICOMM_Inst_Regs *unicomm, DL_UART_IRDA_CLOCK uartClock) +{ + DL_Common_updateReg(&unicomm->uart->IRCTL, (uint32_t) uartClock, + UNICOMMUART_IRCTL_IRTXCLK_MASK); +} + +/** + * @brief Get the IrDA transmit pulse clock select + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The clock select that the IrDA pulse data is based on + * + * @retval One of @ref DL_UART_IRDA_CLOCK + * + */ +__STATIC_INLINE DL_UART_IRDA_CLOCK DL_UART_getIrDATXPulseClockSelect( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t uartClock = unicomm->uart->IRCTL & UNICOMMUART_IRCTL_IRTXCLK_MASK; + + return (DL_UART_IRDA_CLOCK)(uartClock); +} + +/** + * @brief Set the IrDA configurations + * + * Calculates the baud rate divisor given the clock output of the UART clock + * source and the target baud rate. This API also enables IrDA mode. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] polarity The receive input polarity. + * One of @ref DL_UART_IRDA_POLARITY. + * @param[in] pulseLength The length of the IrDA transmit pulse. + * @param[in] irdaClk The clock used for the transmit pulse. + * One of @ref DL_UART_IRDA_CLOCK. + */ +void DL_UART_configIrDAMode(UNICOMM_Inst_Regs *unicomm, + DL_UART_IRDA_POLARITY polarity, uint32_t pulseLength, + DL_UART_IRDA_CLOCK irdaClk); + +/** + * @brief Set the IrDA transmit pulse length + * + * The pulse length can be calculated with the following equation: + * IRTXPLx = pulseLength * 2 * irdaClk - 1 + * (IRTXCLK = functional clock of the UNICOMMUART) + * + * To set the pulse time of 3/16 bit period required by the IrDA period, + * 16-bit oversampling is selected with HSE = 0, the baud rate clock is + * selected with IRTXCLK = 1, and the pulse length is set to six one-half + * clock cycles with IRTXPLx = 6 - 1 - 5. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] pulseLength The length of the IrDA transmit pulse. + * @param[in] irdaClk The clock used for the transmit pulse. + * One of @ref DL_UART_IRDA_CLOCK. + */ +void DL_UART_setIrDAPulseLength(UNICOMM_Inst_Regs *unicomm, + uint32_t pulseLength, DL_UART_IRDA_CLOCK irdaClk); + +/** + * @brief Get the IrDA transmit pulse length + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The IrDA transmit pulse length is set to + * + * @retval 0 - 63 The IrDA transmit pulse length + */ +__STATIC_INLINE uint32_t DL_UART_getIrDATXPulseLength( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->IRCTL & UNICOMMUART_IRCTL_IRTXPL_MASK); +} + +/** + * @brief Set the IrDA receive input UCAxRXD polarity + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] polarity The value to set the IrDA RX pulse polarity to. + * One of @ref DL_UART_IRDA_POLARITY + */ +__STATIC_INLINE void DL_UART_setIrDARXPulsePolarity( + UNICOMM_Inst_Regs *unicomm, DL_UART_IRDA_POLARITY polarity) +{ + DL_Common_updateReg(&unicomm->uart->IRCTL, (uint32_t) polarity, + UNICOMMUART_IRCTL_IRRXPL_MASK); +} + +/** + * @brief Get the IrDA receive input UCAxRXD polarity + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The IrDA RX pulse polarity + * + * @retval One of @ref DL_UART_IRDA_POLARITY + */ +__STATIC_INLINE DL_UART_IRDA_POLARITY DL_UART_getIrDARXPulsePolarity( + UNICOMM_Inst_Regs *unicomm) +{ + uint32_t polarity = unicomm->uart->IRCTL & UNICOMMUART_IRCTL_IRRXPL_MASK; + + return (DL_UART_IRDA_POLARITY)(polarity); +} + +/** + * @brief Set the address mask for DALI, 9-bit, or Idle-Line mode + * + * The address bits are masked to create a set of addresses to be matched + * with the received address byte. + * + * A 0 bit in the MSK bitfield configures that the corresponding bit in the + * ADDR bitfield of the ADDR register is don't care. + * A 1 bit in the MSK bitfield configures, that the corresponding bit in the + * ADDR bitfield of the ADDR register must match. + * + * Used in DALI, UART 9-Bit or Idle-Line mode. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] addressMask The address mask to set + */ +__STATIC_INLINE void DL_UART_setAddressMask( + UNICOMM_Inst_Regs *unicomm, uint32_t addressMask) +{ + DL_Common_updateReg( + &unicomm->uart->AMASK, addressMask, UNICOMMUART_AMASK_VALUE_MASK); +} + +/** + * @brief Get the address mask being used + * + * The address bits are masked to create a set of addresses to be matched + * with the received address byte. + * + * A 0 bit in the MSK bitfield configures that the corresponding bit in the + * ADDR bitfield of the ADDR register is don't care. + * A 1 bit in the MSK bitfield configures, that the corresponding bit in the + * ADDR bitfield of the ADDR register must match. + * + * Used in DALI, UART 9-Bit or Idle-Line mode. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The address mask being used + * + * @retval 0-255 The address mask + * + */ +__STATIC_INLINE uint32_t DL_UART_getAddressMask(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->AMASK & UNICOMMUART_AMASK_VALUE_MASK); +} + +/** + * @brief Set the address + * + * Used to write the specific address that should be matched with the + * receiving byte when the Address Mask (AMASK) is set to FFh. This register + * is used in conjunction with AMASK to form a match for address-byte + * received. + * + * Used in DALI, UART 9-Bit or Idle-Line mode. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] address The address to set + */ +__STATIC_INLINE void DL_UART_setAddress( + UNICOMM_Inst_Regs *unicomm, uint32_t address) +{ + DL_Common_updateReg( + &unicomm->uart->ADDR, address, UNICOMMUART_ADDR_VALUE_MASK); +} + +/** + * @brief Get the address being used + * + * Used to write the specific address that should be matched with the + * receiving byte when the Address Mask (AMASK) is set to FFh. This register + * is used in conjunction with AMASK to form a match for address-byte + * received. + * + * Used in DALI, UART 9-Bit or Idle-Line mode. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @return The address being used + * + * @retval 0-255 The address being used + * + */ +__STATIC_INLINE uint32_t DL_UART_getAddress(UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->ADDR & UNICOMMUART_ADDR_VALUE_MASK); +} + +/** + * @brief Enable UART interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_UART_INTERRUPT. + */ +__STATIC_INLINE void DL_UART_enableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->uart->CPU_INT.IMASK |= interruptMask; +} + +/** + * @brief Disable UART interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to disable. Bitwise OR of + * @ref DL_UART_INTERRUPT. + */ +__STATIC_INLINE void DL_UART_disableInterrupt( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->uart->CPU_INT.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which UART interrupts are enabled + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_UART_INTERRUPT. + * + * @return Which of the requested UART interrupts are enabled + * + * @retval Bitwise OR of @ref DL_UART_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_UART_getEnabledInterrupts( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->uart->CPU_INT.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled UART interrupts + * + * Checks if any of the UART interrupts that were previously enabled are + * pending. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_UART_INTERRUPT. + * + * @return Which of the requested UART interrupts are pending + * + * @retval Bitwise OR of @ref DL_UART_INTERRUPT values + * + * @sa DL_UART_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_UART_getEnabledInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->uart->CPU_INT.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any UART interrupt + * + * Checks if any of the UART interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_UART_INTERRUPT. + * + * @return Which of the requested UART interrupts are pending + * + * @retval Bitwise OR of @ref DL_UART_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_UART_getRawInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->uart->CPU_INT.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending UART interrupt + * + * Checks if any of the UART interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The highest priority pending UART interrupt + * + * @retval TBD + */ +__STATIC_INLINE DL_UART_IIDX DL_UART_getPendingInterrupt( + UNICOMM_Inst_Regs *unicomm) +{ + return (DL_UART_IIDX)(unicomm->uart->CPU_INT.IIDX); +} + +/** + * @brief Clear pending UART interrupts + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_UART_INTERRUPT. + */ +__STATIC_INLINE void DL_UART_clearInterruptStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + unicomm->uart->CPU_INT.ICLR = interruptMask; +} + +/** + * @brief Prepares the UART to change the configuration + * + * If the UART has already been enabled, then it is recommended to call this + * function before calling other APIs that make changes to the CTL0 register. + * If changes are made to the CTL0 register without disabling the UNICOMMUART, then + * results are unpredictable. This API performs the following: + * 1. Disable the UNICOMMUART. + * 2. Wait for the end of transmission or reception of the current character. + * 3. Flush the transmit FIFO by clearing bit FEN in the UART control + * register CTL0. + * + * @post After calling this API, the user must be re-enabled by calling + * @ref DL_UART_enable. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_UART_changeConfig(UNICOMM_Inst_Regs *unicomm) +{ + DL_UART_disable(unicomm); + while (DL_UART_isBusy(unicomm)) { + ; + } +} + +/** + * @brief Blocks to ensure transmit is ready before sending data + * + * Puts the data into the TX FIFO after blocking to ensure the TX FIFO is not + * full. Will wait indefintely until there is space in the TX FIFO. See + * related APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @sa DL_UART_transmitData + * @sa DL_UART_transmitDataCheck + */ +void DL_UART_transmitDataBlocking(UNICOMM_Inst_Regs *unicomm, uint8_t data); + +/** + * @brief Blocks to ensure receive is ready before reading data + * + * Reads the data from the RX FIFO after blocking to ensure the RX FIFO is not + * empty. Will wait indefintely until there is data in the RX FIFO. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * + * @return The data in the RX FIFO + * + * @sa DL_UART_transmitData + * @sa DL_UART_transmitDataCheck + */ +uint8_t DL_UART_receiveDataBlocking(UNICOMM_Inst_Regs *unicomm); + +/** + * @brief Checks the TX FIFO before trying to transmit data + * + * Checks if the TX FIFO is already full before trying to add new data to the + * FIFO. Exits immediately if full rather than trying to block. See related + * APIs for additional transmit options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] data data to send + * + * @return If the transmit occurred + * + * @retval true if data was added to the TX FIFO + * @retval false if the TX FIFO was full and data was not added + * + * @sa DL_UART_transmitData + * @sa DL_UART_transmitDataBlocking + */ +bool DL_UART_transmitDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t data); + +/** + * @brief Checks the RX FIFO before trying to transmit data + * + * Checks if the RX FIFO is already empty before trying to read new data from + * the FIFO. Exits immediately if empty rather than trying to block. See + * related APIs for additional receive options. + * + * Can be used for any data transfers that are less than or equal to 8 bits. + * + * @param[in] unicomm pointer to the register overlay for the peripheral + * @param[in] buffer a buffer to write the received data into + * + * @return If the receive occurred + * + * @retval true if data was read from the RX FIFO + * @retval false if the RX FIFO was empty and data was not read + * + * @sa DL_UART_receiveData + * @sa DL_UART_receiveDataBlocking + */ +bool DL_UART_receiveDataCheck(UNICOMM_Inst_Regs *unicomm, uint8_t *buffer); + +/** + * @brief Read all available data out of the RX FIFO using 8 bit access + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[out] buffer Buffer to write received data into + * @param[in] maxCount Max number of bytes to read from the RX FIFO + * + * @return Number of bytes read from the RX FIFO + */ +uint32_t DL_UART_drainRXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t maxCount); + +/** + * @brief Fill the TX FIFO until full using 8 bit access + * + * Continuously write data into the TX FIFO until it is filled up or count has + * been reached. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * @param[in] buffer Buffer of data to write to the TX FIFO + * @param[in] count Max number of bytes to write to the TX FIFO + * + * @return Number of bytes written to the TX FIFO + */ +uint32_t DL_UART_fillTXFIFO( + UNICOMM_Inst_Regs *unicomm, uint8_t *buffer, uint32_t count); + +/** + * @brief Enable UART interrupt for triggering the DMA receive event + * + * Enables the UART interrupt to be used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_RX + * register, which is the event publisher used for triggering the DMA to do + * a receive data transfer. + * + * @note Only one interrupt source should be enabled at a time. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interrupt Interrupt to enable as the trigger condition for + * the DMA. One of @ref DL_UART_DMA_INTERRUPT_RX. + */ +__STATIC_INLINE void DL_UART_enableDMAReceiveEvent( + UNICOMM_Inst_Regs *unicomm, uint32_t interrupt) +{ + unicomm->uart->DMA_TRIG_RX.IMASK = interrupt; +} + +/** + * @brief Enable UART interrupt for triggering the DMA transmit event + * + * Enables the UART interrupt to be used as the condition to generate an + * event to directly trigger the DMA. This API configures the DMA_TRIG_TX + * register, which is the event publisher used for triggering the DMA to do + * a transmit data transfer. + * + * @note DMA_TRIG_TX only has one transmit interrupt source + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_UART_enableDMATransmitEvent(UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->DMA_TRIG_TX.IMASK = UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_SET; +} + +/** + * @brief Disables UART interrupt from triggering the DMA receive event + * + * Disables the UART interrupt as the condition to generate an event to + * directly trigger the DMA. This API configures the DMA_TRIG_RX + * register, which is the event publisher used for triggering the DMA to do + * a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interrupt Interrupt to disable as the trigger condition for + * the DMA. One of @ref DL_UART_DMA_INTERRUPT_RX. + */ +__STATIC_INLINE void DL_UART_disableDMAReceiveEvent( + UNICOMM_Inst_Regs *unicomm, uint32_t interrupt) +{ + unicomm->uart->DMA_TRIG_RX.IMASK &= ~(interrupt); +} + +/** + * @brief Disables UART interrupt from triggering the DMA transmit event + * + * Disables the UART interrupt as the condition to generate an event to + * directly trigger the DMA. This API configures the DMA_TRIG_TX + * register, which is the event publisher used for triggering the DMA to do + * a transmit data transfer. + * + * @note DMA_TRIG_TX only has one transmit interrupt source + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + */ +__STATIC_INLINE void DL_UART_disableDMATransmitEvent( + UNICOMM_Inst_Regs *unicomm) +{ + unicomm->uart->DMA_TRIG_TX.IMASK = UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_CLR; +} + +/** + * @brief Check which UART interrupt for DMA receive events is enabled + * + * This API checks the DMA_TRIG_RX register, which is the event publisher used + * for triggering the DMA to do a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check Bitwise OR of + * @ref DL_UART_DMA_INTERRUPT_RX. + * + * @return Which of the requested UART interrupts is enabled + * + * @retval One of @ref DL_UART_DMA_INTERRUPT_RX + */ +__STATIC_INLINE uint32_t DL_UART_getEnabledDMAReceiveEvent( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->uart->DMA_TRIG_RX.IMASK & interruptMask); +} + +/** + * @brief Check if UART interrupt for DMA transmit event is enabled + * + * This API checks the DMA_TRIG_TX register, which is the event publisher used + * for triggering the DMA to do a transmit data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The requested UART interrupt status + * + * @retval DL_UART_DMA_INTERRUPT_TX if enabled, 0 if not enabled + */ +__STATIC_INLINE uint32_t DL_UART_getEnabledDMATransmitEvent( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->DMA_TRIG_TX.IMASK & + UNICOMMUART_DMA_TRIG_TX_IMASK_TXINT_MASK); +} + +/** + * @brief Check interrupt flag of enabled UART interrupt for DMA receive event + * + * Checks if any of the UART interrupts for the DMA receive event that were + * previously enabled are pending. + * This API checks the DMA_TRIG_RX register, which is the event publisher used + * for triggering the DMA to do a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_UART_DMA_INTERRUPT_RX. + * + * @return The requested UART interrupt status + * + * @retval One of @ref DL_UART_DMA_INTERRUPT_RX + * + * @sa DL_UART_enableDMAReceiveEvent + */ +__STATIC_INLINE uint32_t DL_UART_getEnabledDMAReceiveEventStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->uart->DMA_TRIG_RX.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled UART interrupt for DMA transmit event + * + * Checks if the UART interrupt for the DMA transmit event that was + * previously enabled is pending. + * This API checks the DMA_TRIG_TX register, which is the event publisher used + * for triggering the DMA to do a transmit data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The requested UART interrupt status + * + * @retval DL_UART_DMA_INTERRUPT_TX if enabled, 0 if not enabled + * + * @sa DL_UART_enableDMATransmitEvent + */ +__STATIC_INLINE uint32_t DL_UART_getEnabledDMATransmitEventStatus( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->DMA_TRIG_TX.MIS & + UNICOMMUART_DMA_TRIG_TX_MIS_TXINT_MASK); +} + +/** + * @brief Check interrupt flag of any UART interrupt for DMA receive event + * + * Checks if any of the UART interrupts for DMA receive event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the DMA_TRIG_RX register, which is the event publisher used + * for triggering the DMA to do a receive data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_UART_DMA_INTERRUPT_RX. + * + * @return Which of the requested UART interrupts are pending + * + * @retval Bitwise OR of @ref DL_UART_DMA_INTERRUPT_RX values + */ +__STATIC_INLINE uint32_t DL_UART_getRawDMAReceiveEventStatus( + UNICOMM_Inst_Regs *unicomm, uint32_t interruptMask) +{ + return (unicomm->uart->DMA_TRIG_RX.RIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any UART interrupt for DMA transmit event + * + * Checks if any of the UART interrupts for DMA transmit event are pending. + * Interrupts do not have to be previously enabled. + * This API checks the DMA_TRIG_TX register, which is the event publisher used + * for triggering the DMA to do a transmit data transfer. + * + * @param[in] unicomm Pointer to the register overlay for the + * peripheral + * + * @return The requested UART interrupt status + * + * @retval DL_UART_DMA_INTERRUPT_TX if enabled, 0 if not enabled + */ +__STATIC_INLINE uint32_t DL_UART_getRawDMATransmitEventStatus( + UNICOMM_Inst_Regs *unicomm) +{ + return (unicomm->uart->DMA_TRIG_TX.RIS & + UNICOMMUART_DMA_TRIG_TX_RIS_TXINT_MASK); +} + +/** + * @brief Save UART configuration before entering a power loss + * state. + * + * Some MSPM0G peripherals residing in PD1 domain do not retain register + * contents when entering STOP or STANDBY modes. Please refer to the datasheet + * for the full list of peripheral instances that exhibit this behavior. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @param[in] ptr Configuration backup setup structure. See + * @ref DL_UART_backupConfig. + * + * @retval FALSE if a configuration already exists in ptr (will not be + * overwritten). TRUE if a configuration was successfully saved + * + */ +bool DL_UART_saveConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_UART_backupConfig *ptr); + +/** + * @brief Restore UART configuration after leaving a power loss + * state. + * + * Some MSPM0G peripherals residing in PD1 domain do not retain register + * contents when entering STOP or STANDBY modes. Please refer to the datasheet + * for the full list of peripheral instances that exhibit this behavior. + * + * @param[in] unicomm Pointer to the register overlay for the peripheral + * + * @param[in] ptr Configuration backup setup structure. See + * @ref DL_UART_backupConfig. + * + * @retval FALSE if a configuration does not exist in ptr (will not be + * loaded). TRUE if a configuration successfully loaded + * + */ +bool DL_UART_restoreConfiguration( + UNICOMM_Inst_Regs *unicomm, DL_UART_backupConfig *ptr); + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_HAS_UNICOMMUART__ */ + +#endif /* ti_dl_dl_unicomm__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/dl_vref.h b/mspm0/source/ti/driverlib/dl_vref.h index 615df20..39dfd9b 100644 --- a/mspm0/source/ti/driverlib/dl_vref.h +++ b/mspm0/source/ti/driverlib/dl_vref.h @@ -107,12 +107,12 @@ extern "C" { /*! * @brief Minimum value for VREF hold, if enabled */ -#define DL_VREF_HOLD_MIN (VREF_CTL2_HCYCLE_MINIMUM) +#define DL_VREF_HOLD_MIN (0x0000U) /*! * @brief Maximum value for VREF hold, if enabled */ -#define DL_VREF_HOLD_MAX (VREF_CTL2_HCYCLE_MAXIMUM) +#define DL_VREF_HOLD_MAX (0xFFFFU) /** @}*/ @@ -187,9 +187,9 @@ typedef struct { /*! VREF sample and hold enable configuration setting. Either @ref DL_VREF_SHMODE_DISABLE or @ref DL_VREF_SHMODE_ENABLE */ DL_VREF_SHMODE shModeEnable; /*! Number of cycles to sample and hold for, if sample and hold mode is enabled. Minimum @ref DL_VREF_SH_MIN, maximum @ref DL_VREF_SH_MAX */ - uint32_t shCycleCount; + uint16_t shCycleCount; /*! Number of cycles to hold for, if sample and hold mode is enabled. Minimum @ref DL_VREF_HOLD_MIN, maximum @ref DL_VREF_HOLD_MAX */ - uint32_t holdCycleCount; + uint16_t holdCycleCount; } DL_VREF_Config; /** @@ -288,7 +288,7 @@ __STATIC_INLINE bool DL_VREF_isEnabled(const VREF_Regs *vref) return ((vref->CTL0 & VREF_CTL0_ENABLE_MASK) == VREF_CTL0_ENABLE_ENABLE); } -#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X) +#if defined(VREF_SYS_INT_COMP_REF) && (VREF_SYS_INT_COMP_REF == 1) /** * @brief Enable VREF buffer as internal reference input for comparator * @@ -326,6 +326,44 @@ __STATIC_INLINE void DL_VREF_disableInternalRefCOMP(VREF_Regs *vref) } #endif +#if defined(VREF_SYS_INT_ADC_REF) && (VREF_SYS_INT_ADC_REF == 1) +/** + * @brief Enable VREF buffer as internal reference input for ADC + * + * @param vref Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_VREF_enableInternalRefADC(VREF_Regs *vref) +{ + vref->CTL0 |= VREF_CTL0_ADC_VREF_ENABLE_ENABLE; +} + +/** + * @brief Checks if VREF buffer for ADC is enabled + * + * @param vref Pointer to the register overlay for the peripheral + * + * @return Returns if VREF buffer for ADC is enabled + * + * @retval true VREF buffer for ADC is enabled + * @retval false VREF buffer for ADC is disabled + */ +__STATIC_INLINE bool DL_VREF_isInternalRefADCEnabled(const VREF_Regs *vref) +{ + return ((vref->CTL0 & VREF_CTL0_ADC_VREF_ENABLE_MASK) == + VREF_CTL0_ADC_VREF_ENABLE_ENABLE); +} + +/** + * @brief Disable VREF buffer as internal reference input for ADC + * + * @param vref Pointer to the register overlay for the peripheral + */ +__STATIC_INLINE void DL_VREF_disableInternalRefADC(VREF_Regs *vref) +{ + vref->CTL0 &= ~(VREF_CTL0_ADC_VREF_ENABLE_MASK); +} +#endif + /** * @brief Set the clock select and clock divide fields in VREF * diff --git a/mspm0/source/ti/driverlib/driverlib.h b/mspm0/source/ti/driverlib/driverlib.h index a3e5892..33021fa 100644 --- a/mspm0/source/ti/driverlib/driverlib.h +++ b/mspm0/source/ti/driverlib/driverlib.h @@ -46,25 +46,34 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include +#include #include #include #include #include +#include +#include +#include +#include +#include #include #include #include diff --git a/mspm0/source/ti/driverlib/m0p/dl_factoryregion.c b/mspm0/source/ti/driverlib/m0p/dl_factoryregion.c index 0490bb8..adf1cc5 100644 --- a/mspm0/source/ti/driverlib/m0p/dl_factoryregion.c +++ b/mspm0/source/ti/driverlib/m0p/dl_factoryregion.c @@ -34,7 +34,10 @@ #include -#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X) +#if ((DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X)) + +/* Creating a section for structure inside SRAM*/ DL_FACTORYREGION_TrimValues DL_FACTORYREGION_TrimTable; /* Creating a pointer to the structure placed inside SRAM*/ diff --git a/mspm0/source/ti/driverlib/m0p/dl_factoryregion.h b/mspm0/source/ti/driverlib/m0p/dl_factoryregion.h index f6c9068..bc38c95 100644 --- a/mspm0/source/ti/driverlib/m0p/dl_factoryregion.h +++ b/mspm0/source/ti/driverlib/m0p/dl_factoryregion.h @@ -71,12 +71,22 @@ extern "C" { /*! @brief Data struct for @ref DL_FactoryRegion_initTrimTable. */ typedef struct { +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X) + /*! Device variant identifier */ + uint32_t USERID; +#else /*! Trace identifier */ uint32_t TRACEID; +#endif /*! Device identifier */ uint32_t DEVICEID; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X) + /*! Trace identifier */ + uint32_t TRACEID; +#else /*! Device variant identifier */ uint32_t USERID; +#endif /*! BSL UART pin configuration */ uint32_t BSLPIN_UART; /*! BSL I2C pin configuration */ diff --git a/mspm0/source/ti/driverlib/m0p/dl_sysctl.h b/mspm0/source/ti/driverlib/m0p/dl_sysctl.h index 058f5ef..218ff22 100644 --- a/mspm0/source/ti/driverlib/m0p/dl_sysctl.h +++ b/mspm0/source/ti/driverlib/m0p/dl_sysctl.h @@ -59,10 +59,20 @@ #include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X) #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X) +#include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X) #include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X) #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C1105_C1106) +#include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G511X) +#include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G518X) +#include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L211X_L112X) +#include /******************************************************************** * diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c1105_c1106.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c1105_c1106.c new file mode 100644 index 0000000..db56348 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c1105_c1106.c @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C1105_C1106) + +#include + +void DL_SYSCTL_setLFCLKSourceLFXT(DL_SYSCTL_LFCLKConfig *config) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG, + ((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) | + (uint32_t) config->xt1Drive, + (SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK)); + // start the LFXT oscillator + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE); + // wait until LFXT oscillator is stable + // if it does not stabilize, check the hardware/IOMUX settings + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_LFXT_GOOD) { + ; + } + if (config->monitor) { + // set the LFCLK monitor + SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE; + } + + // switch LFCLK source from LFOSC to LFXT + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE); +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) +{ + if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled + DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } else { + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify LFCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void) +{ + // Only one should have been set, but clear both because unknown incoming state + // Clear SYSOSCCFG.DISABLE to get SYSOSC running again + // Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(void) +{ + // Switch MCLK to HSCLK + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify HSCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void) +{ + // Switch MCLK to SYSOSC + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range) +{ + DL_SYSCTL_setHFXTFrequencyRange(range); + /* Set startup time to ~0.512ms based on TYP datasheet recommendation */ + DL_SYSCTL_setHFXTStartupTime(8); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable) +{ + DL_SYSCTL_setHFXTFrequencyRange(range); + DL_SYSCTL_setHFXTStartupTime(startupTime); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + + if (monitorEnable == true) { + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ( + (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } + } else { + DL_SYSCTL_disableHFCLKStartupMonitor(); + } +} + +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void) +{ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy = + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED; + + // Check if SLEEP is enabled + if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) == + SYSCTL_MCLKCFG_USELFCLK_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void) +{ + DL_SYSCTL_POWER_POLICY_STOP policy = + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_STOP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void) +{ + DL_SYSCTL_POWER_POLICY_STANDBY policy = + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) == + SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STANDBY1; + } else { + policy = DL_SYSCTL_POWER_POLICY_STANDBY0; + } + } + return policy; +} + +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc, + SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK | + SYSCTL_GENCLKCFG_FCCSELCLK_MASK); +} + +#endif /* DeviceFamily_PARENT_MSPM0C110X */ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c1105_c1106.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c1105_c1106.h new file mode 100644 index 0000000..46bf8c1 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c1105_c1106.h @@ -0,0 +1,2392 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_sysctl_mspm0c1105_c1106.h + * @brief System Control (SysCtl) + * @defgroup SYSCTL_MSPM0C1105_C1106 MSPM0C1105_C1106 System Control (SYSCTL) + * + * @anchor ti_dl_m0p_mspm0c1105_C1106_dl_sysctl_Overview + * # Overview + * + * The System Control (SysCtl) module enables control over system wide + * settings like clocks and power management. + * + *
+ * + ****************************************************************************** + */ +/** @addtogroup SYSCTL_MSPM0C1105_C1106 + * @{ + */ +#ifndef ti_dl_m0p_dl_sysctl_sysctl__include +#define ti_dl_m0p_dl_sysctl_sysctl__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_SYSCTL_RESET + * @{ + */ +/*! + * @brief Perform a SYSRST + * + * This issues a SYSRST (CPU plus peripherals only) + */ + #define DL_SYSCTL_RESET_SYSRST (SYSCTL_RESETLEVEL_LEVEL_CPU) + +/*! + * @deprecated This API is deprecated. Please refer to @ref DL_SYSCTL_RESET_SYSRST. + */ + #define DL_SYSCTL_RESET_CPU (DL_SYSCTL_RESET_SYSRST) + +/*! + * @brief Perform a Boot reset + * + * This triggers execution of the device boot configuration routine and resets + * the majority of the core logic while also power cycling the SRAM + */ + #define DL_SYSCTL_RESET_BOOT (SYSCTL_RESETLEVEL_LEVEL_BOOT) + +/*! + * @brief Perform a POR reset + * + * This performas a POR reset which is a complete device reset + */ + #define DL_SYSCTL_RESET_POR (SYSCTL_RESETLEVEL_LEVEL_POR) + +/*! + * @brief Perform system reset and exit bootloader to the application + */ + #define DL_SYSCTL_RESET_BOOTLOADER_EXIT \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT) + + /*! + * @brief Perform system reset and run bootloader + */ + #define DL_SYSCTL_RESET_BOOTLOADER_ENTRY \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY) + +/** @}*/ + +/** @addtogroup DL_SYSCTL_INTERRUPT + * @{ + */ +/*! @brief Low Frequency Oscillator is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFOSC_GOOD (SYSCTL_IMASK_LFOSCGOOD_ENABLE) +/*! @brief Analog clocking consistency error */ +#define DL_SYSCTL_INTERRUPT_ANALOG_CLOCK_ERROR (SYSCTL_IMASK_ANACLKERR_ENABLE) +/*! @brief Low Frequency Crystal is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFXT_GOOD (SYSCTL_IMASK_LFXTGOOD_ENABLE) +/*! @brief High Frequency Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HFCLK_GOOD (SYSCTL_IMASK_HFCLKGOOD_ENABLE) +/*! @brief High Speed Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HSCLK_GOOD (SYSCTL_IMASK_HSCLKGOOD_ENABLE) + +/** @}*/ + +/*! @enum DL_SYSCTL_IIDX */ +typedef enum { + /*! @brief Low Frequency Oscillator is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFOSC_GOOD = SYSCTL_IIDX_STAT_LFOSCGOOD, + /*! @brief Analog clocking consistency error */ + DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR = SYSCTL_IIDX_STAT_ANACLKERR, + /*! @brief Low Frequency Crystal is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFXT_GOOD = SYSCTL_IIDX_STAT_LFXTGOOD, + /*! @brief High Frequency Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HFCLK_GOOD = SYSCTL_IIDX_STAT_HFCLKGOOD, + /*! @brief High Speed Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HSCLK_GOOD = SYSCTL_IIDX_STAT_HSCLKGOOD, +} DL_SYSCTL_IIDX; + +/** @addtogroup DL_SYSCTL_NMI + * @{ + */ +/*! @brief Non-maskable interrupt for LFCLK Monitor Fail */ +#define DL_SYSCTL_NMI_LFCLK_FAIL (SYSCTL_NMIISET_LFCLKFAIL_SET) +/*! @brief Non-maskable interrupt for Watchdog 0 Fault */ +#define DL_SYSCTL_NMI_WWDT0_FAULT (SYSCTL_NMIISET_WWDT0_SET) +/*! @brief Non-maskable interrupt for early BOR */ +#define DL_SYSCTL_NMI_BORLVL (SYSCTL_NMIISET_BORLVL_SET) +/** @}*/ + +/** @addtogroup DL_SYSCTL_CLK_STATUS + * @{ + */ +/*! @brief Writes to HFCLKCLKCFG are blocked */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE) +/*! @brief SYSOSC Frequency Correcting Loop Mode ON */ +#define DL_SYSCTL_CLK_STATUS_FCL_ON (SYSCTL_CLKSTATUS_FCLMODE_ENABLED) +/*! @brief Clock Fail for LFXT or EXLF clock source */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_FAIL (SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE) +/*! @brief High Speed Clock Good */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_GOOD (SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE) +/*! @brief High Speed Clock Stuck Fault */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_FAULT (SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE) +/*! @brief HFCLKs is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_OFF (SYSCTL_CLKSTATUS_HFCLKOFF_TRUE) +/*! @brief All HFCLKs are OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_OFF (SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE) +/*! @brief LFOSC is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFOSC_GOOD (SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE) +/*! @brief LFXT is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFXT_GOOD (SYSCTL_CLKSTATUS_LFXTGOOD_TRUE) +/*! @brief High Frequency Clock ON */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_GOOD (SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE) +/*! @brief MCLK now sourced from LFCLK */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK \ + (SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK) +/*! @brief MCLK now sourced from HSCLK, otherwise SYSOSC */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK (SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK) +/*! @brief Analog clocking error */ +#define DL_SYSCTL_CLK_STATUS_ANALOG_CLOCK_ERROR \ + (SYSCTL_CLKSTATUS_ANACLKERR_TRUE) +/*! @brief Frequency Clock Counter (FCC) done */ +#define DL_SYSCTL_CLK_STATUS_FCC_DONE (SYSCTL_CLKSTATUS_FCCDONE_DONE) +/*! @brief = LFCLK sourced from the LFXT (crystal) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_LFXT (SYSCTL_CLKSTATUS_LFCLKMUX_LFXT) +/*! @brief = LFCLK sourced from LFCLK_IN (external digital clock input) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_EXLF (SYSCTL_CLKSTATUS_LFCLKMUX_EXLF) +/*! @brief = SYSOSC is at low frequency (4MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_4MHZ (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M) +/*! @brief = SYSOSC is at the user-trimmed frequency (16 or 24MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_USERTRIM_FREQ \ + (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER) +/** @}*/ + +/** @addtogroup DL_SYSCTL_STATUS + * @{ + */ +/*! @brief IO is locked due to SHUTDOWN */ +#define DL_SYSCTL_STATUS_SHUTDOWN_IO_LOCK_TRUE \ + (SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE) +/*! @brief User has disabled external reset pin */ +#define DL_SYSCTL_STATUS_EXT_RESET_PIN_DISABLED \ + (SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE) +/*! @brief User has disabled SWD port */ +#define DL_SYSCTL_STATUS_SWD_DISABLED (SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE) +/*! @brief PMU IFREF good */ +#define DL_SYSCTL_STATUS_PMU_IFREF_GOOD (SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE) +/*! @brief VBOOST (Analog Charge Pump) started up properly */ +#define DL_SYSCTL_STATUS_VBOOST_GOOD (SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE) +/*! @brief Brown Out Reset event status indicator */ +#define DL_SYSCTL_STATUS_BOR_EVENT (SYSCTL_SYSSTATUS_BORLVL_TRUE) +/*! @brief Current Brown Out Reset minimum level */ +#define DL_SYSCTL_STATUS_BOR_LEVEL0 \ + (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN) +/*! @brief Current Brown Out Reset level 1 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL1 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1) +/*! @brief Current Brown Out Reset level 2 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL2 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2) +/*! @brief Current Brown Out Reset level 3 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL3 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3) +/** @}*/ + +/* clang-format on */ + +/*! @enum DL_SYSCTL_NMI_IIDX */ +typedef enum { + /*! @brief NMI interrupt index for LFCLK Monitor Fail */ + DL_SYSCTL_NMI_IIDX_LFCLK_FAIL = SYSCTL_NMIIIDX_STAT_LFCLKFAIL, + /*! @brief NMI interrupt index for Watchdog 0 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT0_FAULT = SYSCTL_NMIIIDX_STAT_WWDT0, + /*! @brief NMI interrupt index for early BOR */ + DL_SYSCTL_NMI_IIDX_BORLVL = SYSCTL_NMIIIDX_STAT_BORLVL, + /*! @brief NMI interrupt index for no interrupt pending */ + DL_SYSCTL_NMI_IIDX_NO_INT = SYSCTL_NMIIIDX_STAT_NO_INTR, +} DL_SYSCTL_NMI_IIDX; + +/*! @enum DL_SYSCTL_ERROR_BEHAVIOR */ +typedef enum { + /*! @brief The error event will trigger a SYSRST */ + DL_SYSCTL_ERROR_BEHAVIOR_RESET = 0x0, + /*! @brief The error event will trigger an NMI */ + DL_SYSCTL_ERROR_BEHAVIOR_NMI = 0x1, + +} DL_SYSCTL_ERROR_BEHAVIOR; + +/*! @enum DL_SYSCTL_SYSOSC_FREQ */ +typedef enum { + /*! Use 4MHz for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_4M = (SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M), + /*! Use BASE (32MHz) for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_BASE = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE), + /*! User will trim the System Oscillator (SYSOSC) to 16MHz or 24MHz */ + DL_SYSCTL_SYSOSC_FREQ_USERTRIM = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER), +} DL_SYSCTL_SYSOSC_FREQ; + +/** @enum DL_SYSCTL_LFXT_DRIVE_STRENGTH */ +typedef enum { + /*! Lowest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV), + /*! Lower Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWER = (SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV), + /*! Higher Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHER = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV), + /*! Highest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV), +} DL_SYSCTL_LFXT_DRIVE_STRENGTH; + +/*! @brief Configuration struct for @ref DL_SYSCTL_LFCLKConfig. */ +typedef struct { + /*! Enable if CAP is less than 3pF to reduce power consumption */ + bool lowCap; + /*! Enable to use monitor for LFXT, EXLF failure */ + bool monitor; + /*! Drive strength and power consumption option */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH xt1Drive; +} DL_SYSCTL_LFCLKConfig; + +/** @enum DL_SYSCTL_HFXT_RANGE */ +typedef enum { + /*! HFXT frequency range between 4 and 8 MHz */ + DL_SYSCTL_HFXT_RANGE_4_8_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8, + /*! HFXT frequency range between 8.01 and 16 MHz */ + DL_SYSCTL_HFXT_RANGE_8_16_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16, + /*! HFXT frequency range between 16.01 and 32 MHz */ + DL_SYSCTL_HFXT_RANGE_16_32_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32, + /*! HFXT frequency range between 32.01 and 48 MHz */ + DL_SYSCTL_HFXT_RANGE_32_48_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48, +} DL_SYSCTL_HFXT_RANGE; + +/*! @enum DL_SYSCTL_HSCLK_SOURCE */ +typedef enum { + /*! Invalid source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_INVALID = 0x0, + /*! Use HFLK as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_HFCLK = SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK, +} DL_SYSCTL_HSCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MCLK source (default after reset) */ + DL_SYSCTL_MCLK_SOURCE_SYSOSC = SYSCTL_MCLKCFG_USEHSCLK_DISABLE, + /*! Use High Speed Clock (HSCLK) as MCLK source (HFCLK, PLL,...) */ + DL_SYSCTL_MCLK_SOURCE_HSCLK = SYSCTL_MCLKCFG_USEHSCLK_ENABLE, + /*! Use the Low Frequency Clock (LFCLK) as the clock source */ + DL_SYSCTL_MCLK_SOURCE_LFCLK = SYSCTL_MCLKCFG_USELFCLK_ENABLE, +} DL_SYSCTL_MCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_DIVIDER */ +typedef enum { + /*! Disable MCLK divider. Change SYSOSC freq only when MDIV is disabled */ + DL_SYSCTL_MCLK_DIVIDER_DISABLE = 0x0, + /*! Divide MCLK frequency by 2 */ + DL_SYSCTL_MCLK_DIVIDER_2 = 0x1, + /*! Divide MCLK frequency by 3 */ + DL_SYSCTL_MCLK_DIVIDER_3 = 0x2, + /*! Divide MCLK frequency by 4 */ + DL_SYSCTL_MCLK_DIVIDER_4 = 0x3, + /*! Divide MCLK frequency by 5 */ + DL_SYSCTL_MCLK_DIVIDER_5 = 0x4, + /*! Divide MCLK frequency by 6 */ + DL_SYSCTL_MCLK_DIVIDER_6 = 0x5, + /*! Divide MCLK frequency by 7 */ + DL_SYSCTL_MCLK_DIVIDER_7 = 0x6, + /*! Divide MCLK frequency by 8 */ + DL_SYSCTL_MCLK_DIVIDER_8 = 0x7, + /*! Divide MCLK frequency by 9 */ + DL_SYSCTL_MCLK_DIVIDER_9 = 0x8, + /*! Divide MCLK frequency by 10 */ + DL_SYSCTL_MCLK_DIVIDER_10 = 0x9, + /*! Divide MCLK frequency by 11 */ + DL_SYSCTL_MCLK_DIVIDER_11 = 0xA, + /*! Divide MCLK frequency by 12 */ + DL_SYSCTL_MCLK_DIVIDER_12 = 0xB, + /*! Divide MCLK frequency by 13 */ + DL_SYSCTL_MCLK_DIVIDER_13 = 0xC, + /*! Divide MCLK frequency by 14 */ + DL_SYSCTL_MCLK_DIVIDER_14 = 0xD, + /*! Divide MCLK frequency by 15 */ + DL_SYSCTL_MCLK_DIVIDER_15 = 0xE, + /*! Divide MCLK frequency by 16 */ + DL_SYSCTL_MCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_MCLK_DIVIDER; + +/** @enum DL_SYSCTL_CLK_OUT_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC, + /*! Use Ultra Low Power Clock (ULPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_ULPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK, + /*! Use Low Frequency Clock (LFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_LFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK, + /*! Use Middle Frequency Precision Clock (MFPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_MFPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK, + /*! Use High Frequency Clock (HFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_HFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK, +} DL_SYSCTL_CLK_OUT_SOURCE; + +/** @enum DL_SYSCTL_MFPCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC, + /*! Use High Frequency Clock (HFCLK) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK, +} DL_SYSCTL_MFPCLK_SOURCE; + +/** @enum DL_SYSCTL_HFCLK_MFPCLK_DIVIDER */ +typedef enum { + /*! HFCLK is not divided before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_DISABLE = 0x0, + /*! Divide HFCLK by 2 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_2 = 0x1, + /*! Divide HFCLK by 3 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_3 = 0x2, + /*! Divide HFCLK by 4 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_4 = 0x3, + /*! Divide HFCLK by 5 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_5 = 0x4, + /*! Divide HFCLK by 6 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6 = 0x5, + /*! Divide HFCLK by 7 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_7 = 0x6, + /*! Divide HFCLK by 8 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_8 = 0x7, + /*! Divide HFCLK by 9 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_9 = 0x8, + /*! Divide HFCLK by 10 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_10 = 0x9, + /*! Divide HFCLK by 11 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_11 = 0xA, + /*! Divide HFCLK by 12 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_12 = 0xB, + /*! Divide HFCLK by 13 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_13 = 0xC, + /*! Divide HFCLK by 14 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_14 = 0xD, + /*! Divide HFCLK by 15 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_15 = 0xE, + /*! Divide HFCLK by 16 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_HFCLK_MFPCLK_DIVIDER; + +/** @enum DL_SYSCTL_CLK_OUT_DIVIDE */ +typedef enum { + /*! Disable the External Clock (CLK_OUT) output divider */ + DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE = SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU, + /*! Divide External Clock (CLK_OUT) output by 2 */ + DL_SYSCTL_CLK_OUT_DIVIDE_2 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2, + /*! Divide External Clock (CLK_OUT) output by 4 */ + DL_SYSCTL_CLK_OUT_DIVIDE_4 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4, + /*! Divide External Clock (CLK_OUT) output by 6 */ + DL_SYSCTL_CLK_OUT_DIVIDE_6 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6, + /*! Divide External Clock (CLK_OUT) output by 8 */ + DL_SYSCTL_CLK_OUT_DIVIDE_8 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8, + /*! Divide External Clock (CLK_OUT) output by 10 */ + DL_SYSCTL_CLK_OUT_DIVIDE_10 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10, + /*! Divide External Clock (CLK_OUT) output by 12 */ + DL_SYSCTL_CLK_OUT_DIVIDE_12 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12, + /*! Divide External Clock (CLK_OUT) output by 14 */ + DL_SYSCTL_CLK_OUT_DIVIDE_14 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14, + /*! Divide External Clock (CLK_OUT) output by 16 */ + DL_SYSCTL_CLK_OUT_DIVIDE_16 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16, +} DL_SYSCTL_CLK_OUT_DIVIDE; + +/** @enum DL_SYSCTL_VBOOST */ +typedef enum { + /*! VBOOST enabled only when COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONDEMAND = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND, + /*! VBOOST enabled in RUN/SLEEP, and in STOP/STANDBY if COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONACTIVE = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE, + /*! VBOOST enabled in all power modes except SHUTDOWN for fastest startup */ + DL_SYSCTL_VBOOST_ONALWAYS = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS, +} DL_SYSCTL_VBOOST; + +/** @enum DL_SYSCTL_FCC_TRIG_TYPE */ +typedef enum { + /*! FCC trigger is rising-edge to rising-edge pulse */ + DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE = SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE, + /*! FCC trigger is active-high pulse level */ + DL_SYSCTL_FCC_TRIG_TYPE_LEVEL = SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL, +} DL_SYSCTL_FCC_TRIG_TYPE; + +/** @enum DL_SYSCTL_FCC_TRIG_SOURCE */ +typedef enum { + /*! FCC trigger source is FCC_IN external pin */ + DL_SYSCTL_FCC_TRIG_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN, + /*! FCC trigger source is LFCLK */ + DL_SYSCTL_FCC_TRIG_SOURCE_LFCLK = SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK, +} DL_SYSCTL_FCC_TRIG_SOURCE; + +/** @enum DL_SYSCTL_FCC_CLOCK_SOURCE */ +typedef enum { + /*! FCC clock source to capture is MCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_MCLK = SYSCTL_GENCLKCFG_FCCSELCLK_MCLK, + /*! FCC clock source to capture is SYSOSC */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC, + /*! FCC clock source to capture is HFCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK, + /*! FCC clock source to capture is CLK_OUT */ + DL_SYSCTL_FCC_CLOCK_SOURCE_CLK_OUT = SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK, + /*! FCC clock source to capture is FCC_IN */ + DL_SYSCTL_FCC_CLOCK_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN, +} DL_SYSCTL_FCC_CLOCK_SOURCE; + +/** @enum DL_SYSCTL_FCC_TRIG_CNT */ +typedef enum { + /*! One monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_01 = + ((uint32_t) 0 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_02 = + ((uint32_t) 1 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_03 = + ((uint32_t) 2 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_04 = + ((uint32_t) 3 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_05 = + ((uint32_t) 4 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_06 = + ((uint32_t) 5 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_07 = + ((uint32_t) 6 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_08 = + ((uint32_t) 7 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_09 = + ((uint32_t) 8 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Ten monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_10 = + ((uint32_t) 9 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eleven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_11 = + ((uint32_t) 10 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twelve monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_12 = + ((uint32_t) 11 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_13 = + ((uint32_t) 12 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fourteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_14 = + ((uint32_t) 13 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fifteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_15 = + ((uint32_t) 14 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Sixteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_16 = + ((uint32_t) 15 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seventeen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_17 = + ((uint32_t) 16 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eighteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_18 = + ((uint32_t) 17 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nineteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_19 = + ((uint32_t) 18 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_20 = + ((uint32_t) 19 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_21 = + ((uint32_t) 20 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_22 = + ((uint32_t) 21 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_23 = + ((uint32_t) 22 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_24 = + ((uint32_t) 23 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_25 = + ((uint32_t) 24 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_26 = + ((uint32_t) 25 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_27 = + ((uint32_t) 26 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_28 = + ((uint32_t) 27 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_29 = + ((uint32_t) 28 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_30 = + ((uint32_t) 29 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_31 = + ((uint32_t) 30 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_32 = + ((uint32_t) 31 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), +} DL_SYSCTL_FCC_TRIG_CNT; + +/** @enum DL_SYSCTL_FLASH_WAIT_STATE */ +typedef enum { + /*! 0 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_0 = ((uint32_t) 0x00000000U), + /*! 1 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_1 = ((uint32_t) 0x00000100U) +} DL_SYSCTL_FLASH_WAIT_STATE; + +/** @enum DL_SYSCTL_POWER_POLICY_RUN_SLEEP */ +typedef enum { + /*! RUN/SLEEP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED = 0x0, + /*! Enable RUN0/SLEEP0 power mode policy. */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP0 = 0x1, + /*! Enable the RUN1/SLEEP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP1 = 0x2, + /*! Enable the RUN2/SLEEP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_RUN_SLEEP; + +/** @enum DL_SYSCTL_POWER_POLICY_STOP */ +typedef enum { + /*! STOP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED = 0x0, + /*! Enable the STOP0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP0 = 0x1, + /*! Enable the STOP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_STOP; + +/** @enum DL_SYSCTL_POWER_POLICY_STANDBY */ +typedef enum { + /*! STANDBY power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED = 0x0, + /*! Enable the STANDBY0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY0 = 0x1, + /*! Enable the STANDBY1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY1 = 0x2, +} DL_SYSCTL_POWER_POLICY_STANDBY; + +/** @enum DL_SYSCTL_BOR_THRESHOLD_LEVEL */ +typedef enum { + /*! BOR0 threshold level. This is the minimum allowed threshold. + * A BOR0- violation will force a re-boot. */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_0 = SYSCTL_BORTHRESHOLD_LEVEL_BORMIN, + /*! BOR1 threshold level. A BOR1- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_1 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1, + /*! BOR2 threshold level. A BOR2- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_2 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2, + /*! BOR3 threshold level. A BOR3- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_3 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3, +} DL_SYSCTL_BOR_THRESHOLD_LEVEL; + +/** @enum DL_SYSCTL_SHUTDOWN_STORAGE_BYTE */ +typedef enum { + /*! Shutdown Storage Byte 0 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_0 = 0x0, + /*! Shutdown Storage Byte 1 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_1 = 0x1, + /*! Shutdown Storage Byte 2 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_2 = 0x2, + /*! Shutdown Storage Byte 3 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_3 = 0x3, +} DL_SYSCTL_SHUTDOWN_STORAGE_BYTE; + +/** @enum DL_SYSCTL_RESET_CAUSE */ +typedef enum { + /*! No Reset Since Last Read */ + DL_SYSCTL_RESET_CAUSE_NO_RESET = SYSCTL_RSTCAUSE_ID_NORST, + /*! (VDD < POR- violation) or (PMU trim parity fault) or (SHUTDNSTOREx parity fault) */ + DL_SYSCTL_RESET_CAUSE_POR_HW_FAILURE = SYSCTL_RSTCAUSE_ID_PORHWFAIL, + /*! NRST pin reset (>1s) */ + DL_SYSCTL_RESET_CAUSE_POR_EXTERNAL_NRST = SYSCTL_RSTCAUSE_ID_POREXNRST, + /*! Software-triggered POR */ + DL_SYSCTL_RESET_CAUSE_POR_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_PORSW, + /*! VDD < BOR- violation */ + DL_SYSCTL_RESET_CAUSE_BOR_SUPPLY_FAILURE = SYSCTL_RSTCAUSE_ID_BORSUPPLY, + /*! Wake from SHUTDOWN */ + DL_SYSCTL_RESET_CAUSE_BOR_WAKE_FROM_SHUTDOWN = + SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN, + /*! Non-PMU trim parity fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_NON_PMU_PARITY_FAULT = + SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY, + /*! Fatal clock fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_CLOCK_FAULT = SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL, + /*! Software-triggered BOOTRST */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_BOOTSW, + /*! NRST pin reset (<1s) */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_EXTERNAL_NRST = + SYSCTL_RSTCAUSE_ID_BOOTEXNRST, + /*! BSL exit */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_EXIT = SYSCTL_RSTCAUSE_ID_SYSBSLEXIT, + /*! BSL entry */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_ENTRY = SYSCTL_RSTCAUSE_ID_SYSBSLENTRY, + /*! WWDT0 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT0_VIOLATION = + SYSCTL_RSTCAUSE_ID_BOOTWWDT0, + /*! WWDT1 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT1_VIOLATION = SYSCTL_RSTCAUSE_ID_SYSWWDT1, + /*! Uncorrectable flash ECC error */ + DL_SYSCTL_RESET_CAUSE_SYSRST_FLASH_ECC_ERROR = + SYSCTL_RSTCAUSE_ID_SYSFLASHECC, + /*! CPULOCK violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_CPU_LOCKUP_VIOLATION = + SYSCTL_RSTCAUSE_ID_SYSCPULOCK, + /*! Debug-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSDBG, + /*! Software-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSSW, + /*! Debug-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUDBG, + /*! Software-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUSW, +} DL_SYSCTL_RESET_CAUSE; + +/*! @enum DL_SYSCTL_BEEPER_FREQ */ +typedef enum { + /*! Use 1KHz for Beeper output */ + DL_SYSCTL_BEEPER_FREQ_1KHZ = SYSCTL_BEEPCFG_FREQ_1KHZ, + /*! Use 2KHz for Beeper output */ + DL_SYSCTL_BEEPER_FREQ_2KHZ = SYSCTL_BEEPCFG_FREQ_2KHZ, + /*! Use 4KHz for Beeper output */ + DL_SYSCTL_BEEPER_FREQ_4KHZ = SYSCTL_BEEPCFG_FREQ_4KHZ, + /*! Use 8KHz for Beeper output */ + DL_SYSCTL_BEEPER_FREQ_8KHZ = SYSCTL_BEEPCFG_FREQ_8KHZ, +} DL_SYSCTL_BEEPER_FREQ; + +/** + * @brief Enable sleep on exit + * + * Enables sleep on exit when the CPU moves from handler mode to thread mode. + * By enabling, allows an interrupt driven application to avoid returning to + * an empty main application. + */ +__STATIC_INLINE void DL_SYSCTL_enableSleepOnExit(void) +{ + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; +} + +/** + * @brief Disable sleep on exit + * + * Disables sleep on exit when the CPU moves from handler mode to thread mode. + */ +__STATIC_INLINE void DL_SYSCTL_disableSleepOnExit(void) +{ + SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Check if sleep on exit is enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSleepOnExitEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SLEEPONEXIT_Msk) == SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable send event on pending bit + * + * When enabled, any enabled event and all interrupts (including disabled + * interrupts) can wakeup the processor. + */ +__STATIC_INLINE void DL_SYSCTL_enableEventOnPend(void) +{ + SCB->SCR |= SCB_SCR_SEVONPEND_Msk; +} + +/** + * @brief Disable send event on pending bit + * + * When disabled, only enabled interrupts or events can wake up the processor. + * Disabled interrupts are excluded. + */ +__STATIC_INLINE void DL_SYSCTL_disableEventOnPend(void) +{ + SCB->SCR &= ~(SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Check if send event on pending bit is enabled + * + * @return Returns the enabled status of the send event on pending bit + * + * @retval true Send event on pending bit is enabled + * @retval false Send event on pending bit is disabled + */ +__STATIC_INLINE bool DL_SYSCTL_isEventOnPendEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SEVONPEND_Msk) == SCB_SCR_SEVONPEND_Msk); +} + +/*! + * @brief Change MCLK source + * + * To ensure good clocking behavior, these are the recommended steps for transition. + * Valid sources and destinations: LFCLK, SYSOSC, HSCLK + * + * Depending on current MCLK source, steps to switch to next MCLK source can vary. + * This is a macro that redirects to the different possible transitions. + * + * Only valid for RUN modes. In low power modes, MCLK transitions are handled by hardware. + * + * @note Different transition APIs may require different input parameters + * Transitions between LFCLK and HSCLK requires going through SYSOSC. + * + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK + * @sa DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK + * @sa DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC + */ +#define DL_SYSCTL_setMCLKSource(current, next, ...) \ + DL_SYSCTL_switchMCLKfrom##current##to##next(__VA_ARGS__); + +/** + * @brief Change MCLK source from SYSOSC to LFCLK + * + * @pre If disabling SYSOSC, high speed oscillators (SYSPLL, HFXT...) must be disabled beforehand. + * @post MCLK source is switched to LFCLK, function will busy-wait until confirmed. + * + * @param[in] disableSYSOSC Whether to leave SYSOSC running or not + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC); + +/** + * @brief Change MCLK source from LFCLK to SYSOSC + * + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + */ +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void); + +/** + * @brief Change MCLK source from SYSOSC to HSCLK + * + * @pre The desired HSCLK source is enabled beforehand (SYSPLL, HFXT, HFCLK_IN). + * @post MCLK source is switched to HSCLK, function will busy-wait until confirmed. + + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(void); + +/** + * @brief Change MCLK source from HSCLK to SYSOSC + * + * @pre MCLK is sourced from a valid, running HSCLK source (SYSPLL, HFXT, HFCLK_IN) + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + * + * @note No HSCLK sources are disabled by this function + */ +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void); + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN0/SLEEP0 + * + * In RUN0, the MCLK and the CPUCLK run from a fast clock source (SYSOSC, + * HFCLK, or SYSPLL). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN0SLEEP0(void) +{ + DL_SYSCTL_setMCLKSource(LFCLK, SYSOSC); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN1/SLEEP1 + * + * In RUN1, the MCLK and the CPUCLK run from LFCLK (at 32kHz) to reduce active + * power, but SYSOSC is left enabled to service analog modules such as an ADC, + * DAC, OPA, or COMP (in HS mode). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN1SLEEP1(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) false); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN2/SLEEP2 + * + * In RUN2, the MCLK and the CPUCLK run from LFCLK (at 32kHz), and SYSOSC is + * completely disabled to save power. This is the lowest power state with + * the CPU running + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @note Since this turns off SYSOSC, HSCLK sources MUST be disabled before calling + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN2SLEEP2(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) true); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Get the RUN/SLEEP mode power policy + * + * Get which RUN/SLEEP power policy has been set. + * + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. + * + * @return Returns the current RUN/SLEEP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_RUN_SLEEP + + */ +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void); + +/** + * @brief Set the STOP mode power policy to STOP0 + * + * In STOP0, the SYSOSC is left running at the current frequency when entering + * STOP mode (either 32MHz, 24MHz, 16MHz, or 4MHz). ULPCLK is always limited + * to 4MHz automatically by hardware, but SYSOSC is not disturbed to support + * consistent operation of analog peripherals such as the ADC, OPA, or COMP. + * + * There are two STOP mode policy options: STOP0 and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_USELFCLK_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP2 + * + * In STOP2, the SYSOSC is disabled and the ULPCLK is sourced from LFCLK at + * 32kHz. This is the lowest power state in STOP mode. + * + * There are two STOP mode policy options: STOP0 and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP2(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLESTOP_MASK; +} + +/** + * @brief Get the STOP mode power policy + * + * Get which STOP power policy has been set. + * + * @return Returns the current STOP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STOP if a STOP power policy + */ +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void); + +/** + * @brief Set the STANDBY mode power policy to STANDBY0 + * + * In STANDBY0, all PD0 peripherals receive the ULPCLK and LFCLK, and the RTC + * receives RTCCLK. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_STOPCLKSTBY_MASK); +} + +/** + * @brief Set the STANDBY mode power policy to STANDBY1 + * + * In STANDBY1, only TIMG0 and TIMG1 receive ULPCLK/LFCLK. The RTC continues + * to receive RTCCLK. A TIMG0/1 interrupt, RTC interrupt, or ADC trigger in + * STANDBY1 always triggers an asynchronous fast clock request to wake the + * system. Other PD0 peripherals (such as UART, I2C, GPIO, and COMP) can also + * wake the system upon an external event through an asynchronous fast clock + * request, but they are not actively clocked in STANDBY1. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_STOPCLKSTBY_MASK; +} + +/** + * @brief Get the STANDBY mode power policy + * + * Get which STANDBY power policy has been set. + * + * @return Returns the current STANDBY mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STANDBY + */ +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void); + +/** + * @brief Set power policy to SHUTDOWN mode + * + * In SHUTDOWN mode, no clocks are available. The core regulator is completely + * disabled and all SRAM and register contents are lost, with the exception of + * the 4 bytes of general purpose memory in SYSCTL which may be used to store + * state information. The BOR and bandgap circuit are disabled. The device may + * wake up via a wake-up capable IO, a debug connection, or NRST. SHUTDOWN mode + * has the lowest current consumption of any operating mode. Exiting SHUTDOWN + * mode triggers a BOR. + * + * There is only one SHUTDOWN mode policy option: SHUTDOWN. + * + * @post This API does not actually enter SHUTDOWN mode. After using this API + * to enable SHUTDOWN mode, to enter SHUTDOWN mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySHUTDOWN(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_SHUTDOWN; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Set the brown-out reset (BOR) threshold level + * + * Note that this API does NOT activate the BOR threshold. After setting the + * threshold level with this API, call @ref DL_SYSCTL_activateBORThreshold + * to actually activate the new threshold. + * + * During startup, the BOR threshold defaults to BOR0 (the lowet value) to + * ensure the device always starts at the specified VDD minimum. After boot, + * the BOR threshold level can be configured to a different level. When the + * BOR threshold is BOR0, a BOR0- violation always generates a BOR- violation + * signal to SYSCTL, generating a BOR level reset. When the BOR threshold is + * re-configured to BOR1, BOR2, or BOR3 the BOR circuit will generate a SYSCTL + * interrupt rather than asserting a BOR- violation. This may be used to give + * the application an indication that the supply has dropped below a certain + * level without causing a reset. If the BOR is in interrupt mode (threshold + * level of BOR1-3), and VDD drops below the respective BORx- level, an + * interrupt will be generated and the BOR circuit will automatically switch + * the BOR threshold level to BOR0 to ensure that a BOR- violation is + * asserted if VDD drops below BOR0-. + * + * @param[in] thresholdLevel The BOR threshold level to set. + * One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL. + * + * @post DL_SYSCTL_activateBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_setBORThreshold( + DL_SYSCTL_BOR_THRESHOLD_LEVEL thresholdLevel) +{ + SYSCTL->SOCLOCK.BORTHRESHOLD = (uint32_t) thresholdLevel; +} + +/** + * @brief Get the brown-out reset (BOR) threshold level + * + * @return Returns the current BOR threshold level. + * + * @retval One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL + */ +__STATIC_INLINE DL_SYSCTL_BOR_THRESHOLD_LEVEL DL_SYSCTL_getBORThreshold(void) +{ + return (DL_SYSCTL_BOR_THRESHOLD_LEVEL)(SYSCTL->SOCLOCK.BORTHRESHOLD); +} + +/** + * @brief Activate the BOR threshold level + * + * Attempts to change the active BOR mode to the BOR threshold that was set + * via @ref DL_SYSCTL_setBORThreshold. + * + * Setting this bit also clears any prior BOR violation status indications. + * + * After calling this API, the change can be validated by calling + * @ref DL_SYSCTL_getStatus and checking the return value. + * + * @pre DL_SYSCTL_setBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_activateBORThreshold(void) +{ + SYSCTL->SOCLOCK.BORCLRCMD = + SYSCTL_BORCLRCMD_KEY_VALUE | SYSCTL_BORCLRCMD_GO_TRUE; +} + +/** + * @brief Resets the device + * + * Resets the device using the type of reset selected. This function does not + * return, the reset will happen immediately. + * + * @param[in] resetType Type of reset to perform. One of @ref + * DL_SYSCTL_RESET. + */ +__STATIC_INLINE void DL_SYSCTL_resetDevice(uint32_t resetType) +{ + SYSCTL->SOCLOCK.RESETLEVEL = resetType; + SYSCTL->SOCLOCK.RESETCMD = + SYSCTL_RESETCMD_KEY_VALUE | SYSCTL_RESETCMD_GO_TRUE; +} + +/** + * @brief Enable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_enableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK |= interruptMask; +} + +/** + * @brief Disable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_disableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which SYSCTL interrupts are enabled + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are enabled + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterrupts(uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SYSCTL interrupts + * + * Checks if any of the SYSCTL interrupts that were previously enabled are + * pending. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + * + * @sa DL_SYSCTL_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @return The highest priority pending SYSCTL interrupt + * + * @retval One of @ref DL_SYSCTL_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_IIDX DL_SYSCTL_getPendingInterrupt(void) +{ + return (DL_SYSCTL_IIDX)(SYSCTL->SOCLOCK.IIDX); +} + +/** + * @brief Clear pending SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_clearInterruptStatus(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.ICLR = interruptMask; +} + +/** + * @brief Check interrupt flag of any SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_NMI. + * + * @return Which of the requested SYSCTL non-maskable interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_NMI values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.NMIRIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @return The highest priority pending SYSCTL non-maskable interrupt + * + * @retval One of @ref DL_SYSCTL_NMI_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_NMI_IIDX DL_SYSCTL_getPendingNonMaskableInterrupt( + void) +{ + return (DL_SYSCTL_NMI_IIDX)(SYSCTL->SOCLOCK.NMIIIDX); +} + +/** + * @brief Clear pending SYSCTL non-maskable interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_NMI. + */ +__STATIC_INLINE void DL_SYSCTL_clearNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.NMIICLR = interruptMask; +} + +/** + * @brief Set the behavior when a WWDT0 error occurs + * + * Configures whether a WWDT0 error will trigger a BOOTRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a BOOTRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT0ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT0 error occurs + * + * By default, this error will trigger a BOOTRST. + * + * @return The behavior when a WWDT0 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT0ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the Main Clock (MCLK) divider (MDIV) + * + * Additionally, can use this function to disable MDIV. MDIV must be disabled + * before changing SYSOSC frequency. + * + * MDIV is not valid if MCLK source is HSCLK. + * MDIV is not used if MCLK source if LFCLK. + * + * @param[in] divider Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is + * HSCLK, a don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE void DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_MDIV_MASK); +} +/** + * @brief Get the Main Clock (MCLK) divider (MDIV) + * + * @return The value of the Main Clock (MCLK) divider (MDIV) + * + * @retval Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is HSCLK, a + * don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE DL_SYSCTL_MCLK_DIVIDER DL_SYSCTL_getMCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_MDIV_MASK; + + return (DL_SYSCTL_MCLK_DIVIDER)(divider); +} + +/** + * @brief Get the source for the Main Clock (MCLK) + * + * @return The source for the Main Clock (MCLK) + * + * @retval One of @ref DL_SYSCTL_MCLK_SOURCE + */ +__STATIC_INLINE DL_SYSCTL_MCLK_SOURCE DL_SYSCTL_getMCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.MCLKCFG & + (SYSCTL_MCLKCFG_USEHSCLK_MASK | SYSCTL_MCLKCFG_USELFCLK_MASK); + + return (DL_SYSCTL_MCLK_SOURCE)(source); +} + +/** + * @brief Set the target frequency of the System Oscillator (SYSOSC) + * + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * + * The System Oscillator (SYSOSC) is an on-chip, accurate, configurable + * oscillator with factory trimmed support for 32MHz (base frequency) and 4MHz + * (low frequency) operation. + * + * SYSOSC provides a flexible high-speed clock source for the system in cases + * where the HFXT is either not present or not used. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] freq Target frequency to use for the System Oscillator (SYSOSC). + * @ref DL_SYSCTL_SYSOSC_FREQ_4M or @ref DL_SYSCTL_SYSOSC_FREQ_BASE. + * + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ freq) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, (uint32_t) freq, + SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Get the target frequency of the System Oscillator (SYSOSC) + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * This function matches what is input by @ref DL_SYSCTL_setSYSOSCFreq. + * + * @return The target frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getTargetSYSOSCFreq(void) +{ + uint32_t freq = SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_FREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Get the current frequency of the System Oscillator (SYSOSC) + * Current/actual SYSOSC frequency may be different than target/desired SYSOSC + * frequency during gear shift and other operations. + * + * @return The current frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getCurrentSYSOSCFreq(void) +{ + uint32_t freq = + SYSCTL->SOCLOCK.CLKSTATUS & SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Returns status of the different clocks in CKM + * + * @return Full status of all clock selections + * + * @retval Bitwise OR of @ref DL_SYSCTL_CLK_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getClockStatus(void) +{ + return (SYSCTL->SOCLOCK.CLKSTATUS); +} + +/** + * @brief Returns general status of SYSCTL + * + * @return Full status of all general conditions in SYSCTL + * + * @retval Bitwise OR of @ref DL_SYSCTL_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getStatus(void) +{ + return (SYSCTL->SOCLOCK.SYSSTATUS); +} + +/** + * @brief Clear the ECC error bits in SYSSTATUS + * + * The ECC error bits in SYSSTATUS are sticky (they remain set when an ECC + * error occurs even if future reads do not have errors), and can be + * cleared through this API. + */ +__STATIC_INLINE void DL_SYSCTL_clearECCErrorStatus(void) +{ + SYSCTL->SOCLOCK.SYSSTATUSCLR = + (SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR | SYSCTL_SYSSTATUSCLR_KEY_VALUE); +} + +/** + * @brief Change LFCLK source to external crystal LFXT + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFXT is an ultra-low power crystal oscillator which supports driving a + * standard 32.768kHz watch crystal. + * + * To use the LFXT, a watch crystal must be populated between LFXIN and LFXOUT + * pins. Find more info in LFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure LFXT functionality for LFXIN and LFXOUT before + * calling this function. + * + * This basic implementation will busy-wait until LFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the LFXT is + * stabilizing. You can enable LFXTGOOD interrupt, or check CLKSTATUS.LFXTGOOD + * when convenient, as long as you do not switch the source via + * SETUSELFXT until LFXTGOOD is set. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFCLK_IN is disabled (default). + * + * @param[in] config Pointer to the LFCLK configuration struct + * @ref DL_SYSCTL_LFCLKConfig. + */ +void DL_SYSCTL_setLFCLKSourceLFXT(DL_SYSCTL_LFCLKConfig *config); + +/** + * @brief Change LFCLK source to external digital LFCLK_IN + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFCLK_IN is a low frequency digital clock input compatible with 32.768kHz + * typical frequency digital square wave CMOS clock inputs (typical duty + * cycle of 50%). + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * LFCLK_IN. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFXT is disabled (default). + */ +__STATIC_INLINE void DL_SYSCTL_setLFCLKSourceEXLF(void) +{ + SYSCTL->SOCLOCK.EXLFCTL = + (SYSCTL_EXLFCTL_KEY_VALUE | SYSCTL_EXLFCTL_SETUSEEXLF_TRUE); +} + +/** + * @brief Change HFCLK source to external crystal HFXT with default parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * The HFXT startup time is set to ~0.512ms based on the TYP datasheet + * recommendation. Additionally, the HFCLK startup monitor is enabled. + * + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * To modify the default HFXT startup time or disable the startup monitor, use + * @ref DL_SYSCTL_setHFCLKSourceHFXTParams instead of this API. + * + * @param[in] range HFXT frequency range + */ +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range); + +/** + * @brief Change HFCLK source to external crystal HFXT with custom parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * If the HFCLK startup monitor is enabled, then the HFXT will be checked after + * the amount of time specified by the startupTime parameter. + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * If the HFCLK startup monitor is disabled, then this implementation will not + * check if the HFXT oscillator is stabilized. + * + * @param[in] range HFXT frequency range + * @param[in] startupTime HFXT startup time + * @param[in] monitorEnable Whether to enable the HFCLK startup monitor + + */ +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable); + +/** + * @brief Change HFCLK source to external digital HFCLK_IN + * + * HFCLK_IN can be used to bypass the HFXT circuit and bring 4-48MHz typical + * frequency digital clock into the devce as HFCLK source instead of HFXT. + * + * HFCLK_IN is a digital clock input compatible with digital square wave CMOS + * clock inputs and should have typical duty cycle of 50%. + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * HFCLK_IN. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKSourceHFCLKIN(void) +{ + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE; +} + +/** + * @brief Disable the HFXT + * + * If HFXT is already enabled, application software must verify that either an + * HFCLKGOOD indication or an HFCLKOFF (off/dead) indication in the CLKSTATUS + * register was asserted by hardware before attempting to disable the HFXT + * by clearing HFXTEN. When disabling the HFXT by clearing HFXTEN, the HFXT + * must not be re-enabled again until the HFCLKOFF bit in the CLKSTATUS + * register is set by hardware. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableHFXT(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_HFXTEN_MASK); +} + +/** + * @brief Get the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @return The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_HSCLK_SOURCE DL_SYSCTL_getHSCLKSource(void) +{ + uint32_t source = SYSCTL->SOCLOCK.HSCLKCFG & SYSCTL_HSCLKCFG_HSCLKSEL_MASK; + + return (DL_SYSCTL_HSCLK_SOURCE)(source); +} + +/** + * @brief Set the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @param[in] source The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setHSCLKSource(DL_SYSCTL_HSCLK_SOURCE source) +{ + SYSCTL->SOCLOCK.HSCLKCFG = (uint32_t) source; +} + +/** + * @brief Get the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @return The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_MFPCLK_SOURCE DL_SYSCTL_getMFPCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_MFPCLKSRC_MASK; + + return (DL_SYSCTL_MFPCLK_SOURCE)(source); +} + +/** + * @brief Set the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @param[in] source The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE source) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) source, + SYSCTL_GENCLKCFG_MFPCLKSRC_MASK); +} + +/** + * @brief Enable the Medium Frequency Clock (MFCLK) + * + * MFCLK provides a continuous 4MHz clock to drive certain peripherals on the system. + * The 4MHz rate is always derived from SYSOSC, and the divider is automatically + * applied to maintain the 4MHz rate regardless of SYSOSC frequency. + * MCLK is ideal for timers and serial interfaces which require a constant + * clock source in RUN/SLEEP/STOP power modes. + * + * MFCLK can only run if 3 conditions are met: + * + * 1) Power mode must be RUN, SLEEP, or STOP. + * 2) USEMFTICK register bit is set, which this function does + * 3) MDIV must be set to @ref DL_SYSCTL_MCLK_DIVIDER_DISABLE by @ref DL_SYSCTL_setMCLKDivider. + * + * If MCLK source is not SYSOSC, MCLK frequency must be >=32MHz for correct operation of MFCLK. + * + * @sa DL_SYSCTL_setMCLKDivider + * @sa DL_SYSCTL_getMCLKSource + * @sa DL_SYSCTL_getMCLKFreq + */ +__STATIC_INLINE void DL_SYSCTL_enableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEMFTICK_ENABLE; +} + +/** + * @brief Disable the Medium Frequency Clock (MFCLK) + */ +__STATIC_INLINE void DL_SYSCTL_disableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_USEMFTICK_ENABLE); +} + +/** + * @brief Enable the External Clock (CLK_OUT) + * + * CLK_OUT is provided for pushing out digital clocks to external circuits, such + * as an external ADC which does not have its own clock source. + * + * IOMUX setting for CLK_OUT must be configured before using this function. + * + * CLK_OUT has a typical duty cycle of 50% if clock source is HFCLK, SYSPLLOUT1, + * SYSOSC, or LFCLK. If source is MCLK, ULPCLK, or MFCLK, duty cycle is not + * guaranteed to be 50%. + * + * This function performs multiple operations: + * 1) Sets the CLK_OUT source + * 2) Sets the CLK_OUT divider value + * 3) Enables the CLK_OUT divider, which can be disabled by @ref DL_SYSCTL_disableExternalClockDivider + * 4) Enables the CLK_OUT, which can be disabled by @ref DL_SYSCTL_disableExternalClock + * + * @param[in] source The source of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_SOURCE. + * @param[in] divider The divider of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_DIVIDE. + * + * @sa DL_SYSCTL_disableExternalClock + * @sa DL_SYSCTL_disableExternalClockDivider + */ +__STATIC_INLINE void DL_SYSCTL_enableExternalClock( + DL_SYSCTL_CLK_OUT_SOURCE source, DL_SYSCTL_CLK_OUT_DIVIDE divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) divider | (uint32_t) source, + SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK | SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK | + SYSCTL_GENCLKCFG_EXCLKSRC_MASK); + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_EXCLKEN_ENABLE; +} + +/** + * @brief Disable the External Clock (CLK_OUT) + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClock(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_EXCLKEN_ENABLE); +} + +/** + * @brief Disable the External Clock (CLK_OUT) Divider + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClockDivider(void) +{ + SYSCTL->SOCLOCK.GENCLKCFG &= ~(SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE); +} + +/** + * @brief Enable the Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK provides a continuous fixed 4MHz clock to some analog peripherals. + * + * @sa DL_SYSCTL_disableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_enableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_MFPCLKEN_ENABLE; +} + +/** + * @brief Disable the Middle Frequency Precision Clock (MFPCLK) + * @sa DL_SYSCTL_enableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_disableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_MFPCLKEN_ENABLE); +} + +/** + * @brief Set the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @param[in] divider The divider of HFCLK for MFPCLK + * One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKDividerForMFPCLK( + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + ((uint32_t) divider << SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS), + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK); +} + +/** + * @brief Get the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @return Returns the divider for HFCLK for MFPCLK + * + * @retval One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER + */ +__STATIC_INLINE DL_SYSCTL_HFCLK_MFPCLK_DIVIDER +DL_SYSCTL_getHFCLKDividerForMFPCLK(void) +{ + uint32_t divider = + (SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK) >> + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS; + + return (DL_SYSCTL_HFCLK_MFPCLK_DIVIDER)(divider); +} + +/** + * @brief Blocks all asynchronous fast clock requests + * + * To block specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C. + */ +__STATIC_INLINE void DL_SYSCTL_blockAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE; +} + +/** + * @brief Allows all asynchronous fast clock requests + * + * Although this allows all async fast clock requests, individual IPs may still + * be blocking theirs. + * + * To allow specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C, GPIO. + */ +__STATIC_INLINE void DL_SYSCTL_allowAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE); +} + +/** + * @brief Generates an asynchronous fast clock request upon any IRQ request to CPU. + * + * Provides lowest latency interrupt handling regardless of system clock speed. + * Blockable by @ref DL_SYSCTL_blockAllAsyncFastClockRequests + * + * @sa DL_SYSCTL_blockAllAsyncFastClockRequests + */ +__STATIC_INLINE void DL_SYSCTL_enableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE; +} + +/** + * @brief Maintains current system clock speed for IRQ request to CPU. + * + * Latency for interrupt handling will be higher at lower system clock speeds. + */ +__STATIC_INLINE void DL_SYSCTL_disableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE); +} + +/** + * @brief Set the SRAM boundary address to act as partition for read-execute + * permission + * + * Specify the SRAM partition address to protect the code region of SRAM from + * being written to, and prevent the RW ("data") region of SRAM from being + * used for code execution. + * The SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. This is the default + * value. + * + * The address is set with a 32-byte resolution. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @param[in] address Address to act as the SRAM partition address. Value is + * a valid 32-bit SRAM address. Only address bits [19:5] + * i.e. bit 5 to bit 19 are used for the boundary address + */ +__STATIC_INLINE void DL_SYSCTL_setSRAMBoundaryAddress(uint32_t address) +{ + SYSCTL->SOCLOCK.SRAMBOUNDARY = + (((uint32_t) address) & SYSCTL_SRAMBOUNDARY_ADDR_MASK); +} + +/** + * @brief Get the SRAM boundary address + * + * Get the SRAM partition address + * The SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. + * + * The address is set with a 32-byte granularity. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @return The SRAM partition address offset from the SRAM base address + * + * @retval Value is range in [0x0, 0x000FFFE0] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getSRAMBoundaryAddress(void) +{ + return (SYSCTL->SOCLOCK.SRAMBOUNDARY); +} + +/** + * @brief Set flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @param[in] waitState Desired number of flash wait states. One of + * @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE void DL_SYSCTL_setFlashWaitState( + DL_SYSCTL_FLASH_WAIT_STATE waitState) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) waitState, + SYSCTL_MCLKCFG_FLASHWAIT_MASK); +} + +/** + * @brief Get flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @return Number of flash wait states. One of @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE DL_SYSCTL_FLASH_WAIT_STATE DL_SYSCTL_getFlashWaitState(void) +{ + uint32_t waitState = + SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_FLASHWAIT_MASK; + + return (DL_SYSCTL_FLASH_WAIT_STATE)(waitState); +} + +/** + * @brief Read Frequency Clock Counter (FCC) + * @return 22-bit value of Frequency Clock Counter (FCC) + */ +__STATIC_INLINE uint32_t DL_SYSCTL_readFCC(void) +{ + return (SYSCTL->SOCLOCK.FCC); +} + +/** + * @brief Start Frequency Clock Counter (FCC) + * + * If FCC_IN is already logic high, counting starts immediately. + * When using level trigger, FCC_IN should be low when GO is set, and trigger + * pulse should be sent to FCC_IN after starting FCC. + */ +__STATIC_INLINE void DL_SYSCTL_startFCC(void) +{ + SYSCTL->SOCLOCK.FCCCMD = (SYSCTL_FCCCMD_KEY_VALUE | SYSCTL_FCCCMD_GO_TRUE); +} + +/** + * @brief Returns whether FCC is done capturing + * + * When capture completes, FCCDONE is set by hardware. + * FCCDONE is read-only and is automatically cleared by hardware when a new + * capture is started. + * + * @return Whether FCC is done or not + * @retval true or false (boolean) + */ +__STATIC_INLINE bool DL_SYSCTL_isFCCDone(void) +{ + return (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_FCCDONE_DONE) == + SYSCTL_CLKSTATUS_FCCDONE_DONE; +} + +/** + * @brief Configure the Frequency Clock Counter (FCC) + * + * FCC enables flexible in-system testing and calibration of a variety of oscillators + * and clocks on the device. The FCC counts the number of clock periods seen on the + * selected clock source within a known fixed trigger period (derived from a secondary + * reference source) to provide an estimation of the frequency of the source clock. + * + * @param[in] trigLvl Determines if active high level trigger or rising-edge + * to rising-edge. One of @ref DL_SYSCTL_FCC_TRIG_TYPE . + * @param[in] trigSrc Determines which clock source to trigger FCC from. One of + * @ref DL_SYSCTL_FCC_TRIG_SOURCE. + * @param[in] clkSrc Which clock source to capture and measure frequency of. One of + * @ref DL_SYSCTL_FCC_CLOCK_SOURCE. + */ +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc); + +/** + * @brief Sets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * Set the number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @param[in] periods One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE void DL_SYSCTL_setFCCPeriods(DL_SYSCTL_FCC_TRIG_CNT periods) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) periods, + SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK); +} + +/** + * @brief Gets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @return One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT DL_SYSCTL_getFCCPeriods(void) +{ + uint32_t periods = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK; + + return (DL_SYSCTL_FCC_TRIG_CNT)(periods); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in Internal Resistor mode + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + * + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); +} + +/** + * @brief Enable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_enableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_ENABLE; +} + +/** + * @brief Disable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_disableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_DISABLE; +} + +/** + * @brief Sets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @param[in] setting One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE void DL_SYSCTL_setVBOOSTConfig(DL_SYSCTL_VBOOST setting) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) setting, + SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK); +} + +/** + * @brief Gets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @return One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE DL_SYSCTL_VBOOST DL_SYSCTL_getVBOOSTConfig(void) +{ + uint32_t setting = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK; + + return (DL_SYSCTL_VBOOST)(setting); +} + +/** + * @brief Return byte that was saved through SHUTDOWN + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * + * @return 8-bit value of Shutdown Storage Byte. + */ +__STATIC_INLINE uint8_t DL_SYSCTL_getShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index) +{ + const volatile uint32_t *pReg = &SYSCTL->SOCLOCK.SHUTDNSTORE0; + + return (uint8_t)( + *(pReg + (uint32_t) index) & SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Save a byte to SHUTDOWN memory + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * @param[in] data 8-bit data to save in memory + */ +__STATIC_INLINE void DL_SYSCTL_setShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index, uint8_t data) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SHUTDNSTORE0 + (uint32_t) index, data, + SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Enable SHUTDOWN IO Release + * + * After shutdown, IO is locked in previous state. + * + * @note Release IO after re-configuring IO to their proper state. + */ +__STATIC_INLINE void DL_SYSCTL_releaseShutdownIO(void) +{ + SYSCTL->SOCLOCK.SHDNIOREL = + (SYSCTL_SHDNIOREL_KEY_VALUE | SYSCTL_SHDNIOREL_RELEASE_TRUE); +} + +/** + * @brief Disable the reset functionality of the NRST pin + * + * Disabling the NRST pin allows the pin to be configured as a GPIO. + * Once disabled, the reset functionality can only be re-enabled by a POR. + * + * @note The register is write-only, so the EXRSTPIN register + * will always appear as "Disabled" in the debugger + */ +__STATIC_INLINE void DL_SYSCTL_disableNRSTPin(void) +{ + SYSCTL->SOCLOCK.EXRSTPIN = + (SYSCTL_EXRSTPIN_KEY_VALUE | SYSCTL_EXRSTPIN_DISABLE_TRUE); +} + +/** + * @brief Disable Serial Wire Debug (SWD) functionality + * + * SWD pins are enabled by default after cold start to allow a debug connection. + * It is possible to disable SWD on these pins to use for other functionality. + * + * @post SWD is disabled, but pins must be re-configured separately. + * + * @note Cannot debug the device after disabling SWD. Only re-enabled by POR. + */ +__STATIC_INLINE void DL_SYSCTL_disableSWD(void) +{ + SYSCTL->SOCLOCK.SWDCFG = + (SYSCTL_SWDCFG_KEY_VALUE | SYSCTL_SWDCFG_DISABLE_TRUE); +} + +/** + * @brief Return byte that is stored in RSTCAUSE. + * + * @return The cause of reset. One of @ref DL_SYSCTL_RESET_CAUSE + */ +__STATIC_INLINE DL_SYSCTL_RESET_CAUSE DL_SYSCTL_getResetCause(void) +{ + uint32_t resetCause = SYSCTL->SOCLOCK.RSTCAUSE & SYSCTL_RSTCAUSE_ID_MASK; + + return (DL_SYSCTL_RESET_CAUSE)(resetCause); +} + +/** + * @brief Set the HFXT startup time + * + * Specify the HFXT startup time in 64us resolution. If the HFCLK startup + * monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time + * expires. + * + * @param[in] startupTime The HFXT startup time to set in ~64us steps. + * Value between [0x0 (~0s), 0xFF (~16.32ms)]. + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTStartupTime(uint32_t startupTime) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, startupTime, + SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Get the HFXT startup time + * + * @return Returns the HFXT startup time in ~64us steps + * + * @retval Value between [0x0 (~0s), 0xFF (~16.32ms)] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getHFXTStartupTime(void) +{ + return (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Set the HFXT frequency range + * + * The high frequency crystal oscillator (HFXT) can be used with standard + * crystals and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * @param[in] range One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTFrequencyRange( + DL_SYSCTL_HFXT_RANGE range) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, ((uint32_t) range), + SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK); +} + +/** + * @brief Get the HFXT frequency range + * + * @return Returns the HFXT frequency range + * + * @retval One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE DL_SYSCTL_HFXT_RANGE DL_SYSCTL_getHFXTFrequencyRange(void) +{ + uint32_t range = + (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK) >> + SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS; + + return (DL_SYSCTL_HFXT_RANGE)(range); +} + +/** + * @brief Enable the HFCLK startup monitor + * + * The HFXT takes time to start after being enabled. A startup monitor is + * provided to indicate to the application software if the HFXT has successfully + * started, at which point the HFCLK can be selected to source a variety of + * system functions. The HFCLK startup monitor also supports checking the + * HFCLK_IN digital clock input for a clock stuck fault. + * + */ +__STATIC_INLINE void DL_SYSCTL_enableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG |= SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE; +} + +/** + * @brief Disable the HFCLK startup monitor + */ +__STATIC_INLINE void DL_SYSCTL_disableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG &= ~(SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK); +} + +/** + * @brief Retrieves the calibration constant of the temperature sensor to be + * used in temperature calculation. + * + * @retval Temperature sensor calibration data + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getTempCalibrationConstant(void) +{ + return DL_FactoryRegion_getTemperatureVoltage(); +} + +/** + * @brief Enable Beeper output + * + * The Beeper function can be used to generate a square wave output to external + * beepers. + * The frequency of the Beeper output can be configued by calling + * @ref DL_SYSCTL_setBeeperFreq + */ +__STATIC_INLINE void DL_SYSCTL_enableBeeperOutput(void) +{ + SYSCTL->SOCLOCK.BEEPCFG |= SYSCTL_BEEPCFG_EN_ENABLE; +} + +/** + * @brief Disable Beeper output + */ +__STATIC_INLINE void DL_SYSCTL_disableBeeperOutput(void) +{ + SYSCTL->SOCLOCK.BEEPCFG &= ~(SYSCTL_BEEPCFG_EN_MASK); +} + +/** + * @brief Set the target frequency of the Beeper output + * + * @param[in] freq Target frequency to use for the Beeper output. One of + * @ref DL_SYSCTL_BEEPER_FREQ. + */ +__STATIC_INLINE void DL_SYSCTL_setBeeperFreq(DL_SYSCTL_BEEPER_FREQ freq) +{ + DL_Common_updateReg( + &SYSCTL->SOCLOCK.BEEPCFG, (uint32_t) freq, SYSCTL_BEEPCFG_FREQ_MASK); +} + +/** + * @brief Get the target frequency of the the Beeper output + * + * @return Returns the target frequency of the Beeper output. + * + * @retval One of @ref DL_SYSCTL_BEEPER_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_BEEPER_FREQ DL_SYSCTL_getBeeperFreq(void) +{ + uint32_t freq = SYSCTL->SOCLOCK.BEEPCFG & SYSCTL_BEEPCFG_FREQ_MASK; + + return (DL_SYSCTL_BEEPER_FREQ)(freq); +} + +/** + * @brief Check if Beeper is enabled + * + * @return Returns the enabled status of the Beeper output + * + * @retval true The Beeper output is enabled + * @retval false The Beeper output is disabled + */ +__STATIC_INLINE bool DL_SYSCTL_isBeeperEnabled(void) +{ + return ((SYSCTL->SOCLOCK.BEEPCFG & SYSCTL_BEEPCFG_EN_MASK) == + SYSCTL_BEEPCFG_EN_ENABLE); +} + +/** + * @brief Checks if Flash Bank swapping is enabled + * + * @return Whether Flash Bank swap is enabled + * + * @retval false This is not a multi-bank device + */ +__STATIC_INLINE bool DL_SYSCTL_isFlashBankSwapEnabled(void) +{ + return false; +} + +/** + * @brief Checks if executing from upper flash bank + * + * @return Whether executing from upper flash bank + * + * @retval false This is not a multi-bank device. + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromUpperFlashBank(void) +{ + return false; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dl_m0p_dl_sysctl_sysctl__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.c index f0b3b68..f581555 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.c +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.c @@ -39,17 +39,14 @@ void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) { - // Set SYSOSC back to base frequency if left enabled if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); - // Do not set both bits SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; - SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; } else { - // Do not set both bits - SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; // Verify LFCLK -> MCLK while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g352x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g352x.c new file mode 100644 index 0000000..54e8287 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g352x.c @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G352X) + +#include +#include + +void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config) +{ + /* + * PLL configurations are retained in lower reset levels. Set default + * behavior of disabling the PLL to keep a consistent behavior regardless + * of reset level. + */ + DL_SYSCTL_disableSYSPLL(); + + /* + * Before any configuration is done, a check is performed first to + * ensure that the trim table within SRAM has been initialized first. + * If it has not been initialized then the table within SRAM will be + * populated with values from the TRIM region of memory. Otherwise + * if the flag has been set the function will continue as normal. + */ + if (!DL_FactoryRegion_isTrimTableInSram()) { + DL_FactoryRegion_initTrimTable(); + } + + /* Check that SYSPLL is disabled before configuration */ + while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) != + (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) { + ; + } + + // set SYSPLL reference clock + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, + ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK); + + // set predivider PDIV (divides reference clock) + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv), + SYSCTL_SYSPLLCFG1_PDIV_MASK); + + // save CPUSS CTL state and disable the cache + uint32_t ctlTemp = DL_CORE_getInstructionConfig(); + DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED, + DL_CORE_LITERAL_CACHE_ENABLED); + + // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq + SYSCTL->SOCLOCK.SYSPLLPARAM0 = + *(volatile uint32_t *) ((uint32_t) config->inputFreq); + SYSCTL->SOCLOCK.SYSPLLPARAM1 = + *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4); + + // restore CPUSS CTL state + CPUSS->CTL = ctlTemp; + + // set feedback divider QDIV (multiplies to give output frequency) + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, + ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) & + SYSCTL_SYSPLLCFG1_QDIV_MASK), + SYSCTL_SYSPLLCFG1_QDIV_MASK); + + // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0 + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, + (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) | + ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) | + ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) | + config->enableCLK2x | config->enableCLK1 | config->enableCLK0 | + (uint32_t) config->sysPLLMCLK), + (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK | + SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK | + SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK)); + + // enable SYSPLL + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE; + + // wait until SYSPLL startup is stabilized + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) { + ; + } +} + +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG, + ((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) | + (uint32_t) config->xt1Drive, + (SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK)); + // start the LFXT oscillator + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE); + // wait until LFXT oscillator is stable + // if it does not stabilize, check the hardware/IOMUX settings + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_LFXT_GOOD) { + ; + } + if (config->monitor) { + // set the LFCLK monitor + SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE; + } + + // switch LFCLK source from LFOSC to LFXT + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE); +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) +{ + if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled + DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } else { + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify LFCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void) +{ + // Only one should have been set, but clear both because unknown incoming state + // Clear SYSOSCCFG.DISABLE to get SYSOSC running again + // Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source) +{ + // Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN) + // Selected desired HSCLK source + DL_SYSCTL_setHSCLKSource(source); + + // Verify HSCLK source is valid + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) { + ; + } + + // Switch MCLK to HSCLK + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify HSCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void) +{ + // Switch MCLK to SYSOSC + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range) +{ + /* + * Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. + */ + DL_SYSCTL_disableHFXT(); + + /* + * Before any configuration is done, a check is performed first to + * ensure that the trim table within SRAM has been initialized first. + * If it has not been initialized then the table within SRAM will be + * populated with values from the TRIM region of memory. Otherwise + * if the flag has been set the function will continue as normal. + */ + if (!DL_FactoryRegion_isTrimTableInSram()) { + DL_FactoryRegion_initTrimTable(); + } + + DL_SYSCTL_setHFXTFrequencyRange(range); + /* Set startup time to ~0.512ms based on TYP datasheet recommendation */ + DL_SYSCTL_setHFXTStartupTime(8); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable) +{ + /* + * Before any configuration is done, a check is performed first to + * ensure that the trim table within SRAM has been initialized first. + * If it has not been initialized then the table within SRAM will be + * populated with values from the TRIM region of memory. Otherwise + * if the flag has been set the function will continue as normal. + */ + if (!DL_FactoryRegion_isTrimTableInSram()) { + DL_FactoryRegion_initTrimTable(); + } + + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + DL_SYSCTL_setHFXTFrequencyRange(range); + DL_SYSCTL_setHFXTStartupTime(startupTime); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + + if (monitorEnable == true) { + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ( + (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } + } else { + DL_SYSCTL_disableHFCLKStartupMonitor(); + } +} + +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc, + SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK | + SYSCTL_GENCLKCFG_FCCSELCLK_MASK); +} + +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void) +{ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy = + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED; + + // Check if SLEEP is enabled + if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) == + SYSCTL_MCLKCFG_USELFCLK_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void) +{ + DL_SYSCTL_POWER_POLICY_STOP policy = + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) == + SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_STOP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void) +{ + DL_SYSCTL_POWER_POLICY_STANDBY policy = + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) == + SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STANDBY1; + } else { + policy = DL_SYSCTL_POWER_POLICY_STANDBY0; + } + } + return policy; +} + +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableReadExecuteProtectFirewall(); + status = true; + } + return status; +} + +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableIPProtectFirewall(); + status = true; + } + return status; +} + +#endif /* DeviceFamily_PARENT_MSPM0G352X */ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g352x.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g352x.h new file mode 100644 index 0000000..7ecc838 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g352x.h @@ -0,0 +1,3396 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_sysctl_mspm0g352x.h + * @brief System Control (SysCtl) + * @defgroup SYSCTL_mspm0g352x mspm0g352x System Control (SYSCTL) + * + * @anchor ti_dl_m0p_mspm0g352x_dl_sysctl_Overview + * # Overview + * + * The System Control (SysCtl) module enables control over system wide + * settings like clocks and power management. + * + *
+ * + ****************************************************************************** + */ +/** @addtogroup SYSCTL_mspm0g352x + * @{ + */ +#ifndef ti_dl_m0p_dl_sysctl_sysctl__include +#define ti_dl_m0p_dl_sysctl_sysctl__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_SYSCTL_RESET + * @{ + */ +/*! + * @brief Perform a SYSRST + * + * This issues a SYSRST (CPU plus peripherals only) + */ + #define DL_SYSCTL_RESET_SYSRST (SYSCTL_RESETLEVEL_LEVEL_CPU) + +/*! + * @deprecated This API is deprecated. Please refer to @ref DL_SYSCTL_RESET_SYSRST. + */ + #define DL_SYSCTL_RESET_CPU (DL_SYSCTL_RESET_SYSRST) + +/*! + * @brief Perform a Boot reset + * + * This triggers execution of the device boot configuration routine and resets + * the majority of the core logic while also power cycling the SRAM + */ + #define DL_SYSCTL_RESET_BOOT (SYSCTL_RESETLEVEL_LEVEL_BOOT) + +/*! + * @brief Perform a POR reset + * + * This performas a POR reset which is a complete device reset + */ + #define DL_SYSCTL_RESET_POR (SYSCTL_RESETLEVEL_LEVEL_POR) + +/*! + * @brief Perform system reset and exit bootloader to the application + */ + #define DL_SYSCTL_RESET_BOOTLOADER_EXIT \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT) + + /*! + * @brief Perform system reset and run bootloader + */ + #define DL_SYSCTL_RESET_BOOTLOADER_ENTRY \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY) + + +/** @addtogroup DL_SYSCTL_NMI + * @{ + */ +/*! @brief Non-maskable interrupt for SRAM Double Error Detect */ +#define DL_SYSCTL_NMI_SRAM_DED (SYSCTL_NMIISET_SRAMDED_SET) +/*! @brief Non-maskable interrupt for Flash Double Error Detect */ +#define DL_SYSCTL_NMI_FLASH_DED (SYSCTL_NMIISET_FLASHDED_SET) +/*! @brief Non-maskable interrupt for LFCLK Monitor Fail */ +#define DL_SYSCTL_NMI_LFCLK_FAIL (SYSCTL_NMIISET_LFCLKFAIL_SET) +/*! @brief Non-maskable interrupt for Watchdog 1 Fault */ +#define DL_SYSCTL_NMI_WWDT1_FAULT (SYSCTL_NMIISET_WWDT1_SET) +/*! @brief Non-maskable interrupt for Watchdog 0 Fault */ +#define DL_SYSCTL_NMI_WWDT0_FAULT (SYSCTL_NMIISET_WWDT0_SET) +/*! @brief Non-maskable interrupt for early BOR */ +#define DL_SYSCTL_NMI_BORLVL (SYSCTL_NMIISET_BORLVL_SET) +/** @}*/ + +/** @addtogroup DL_SYSCTL_INTERRUPT + * @{ + */ +/*! @brief Low Frequency Oscillator is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFOSC_GOOD (SYSCTL_IMASK_LFOSCGOOD_ENABLE) +/*! @brief Analog clocking consistency error */ +#define DL_SYSCTL_INTERRUPT_ANALOG_CLOCK_ERROR (SYSCTL_IMASK_ANACLKERR_ENABLE) +/*! @brief Flash Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_FLASH_SEC (SYSCTL_IMASK_FLASHSEC_ENABLE) + +/*! @brief SRAM Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_SRAM_SEC (SYSCTL_IMASK_SRAMSEC_ENABLE) + +/*! @brief Low Frequency Crystal is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFXT_GOOD (SYSCTL_IMASK_LFXTGOOD_ENABLE) +/*! @brief High Frequency Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HFCLK_GOOD (SYSCTL_IMASK_HFCLKGOOD_ENABLE) +/*! @brief System PLL is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_SYSPLL_GOOD (SYSCTL_IMASK_SYSPLLGOOD_ENABLE) +/*! @brief High Speed Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HSCLK_GOOD (SYSCTL_IMASK_HSCLKGOOD_ENABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_CLK_STATUS + * @{ + */ +/*! @brief Error with Anacomp High Speed CP Clock Generation - SYSOSC must not + * run at 4MHz */ +#define DL_SYSCTL_CLK_STATUS_ANACOMP_ERROR (SYSCTL_CLKSTATUS_ACOMPHSCLKERR_TRUE) +/*! @brief Error with OPAMP Clock Generation */ +#define DL_SYSCTL_CLK_STATUS_OPAMP_ERROR (SYSCTL_CLKSTATUS_OPAMPCLKERR_TRUE) +/*! @brief Writes to SYSPLLCFG0-1, SYSPLLPARAM0-1 are blocked */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_SYSPLLBLKUPD_TRUE) +/*! @brief Writes to HFCLKCLKCFG are blocked */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE) +/*! @brief SYSOSC Frequency Correcting Loop Mode ON */ +#define DL_SYSCTL_CLK_STATUS_FCL_ON (SYSCTL_CLKSTATUS_FCLMODE_ENABLED) +/*! @brief Clock Fail for LFXT or EXLF clock source */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_FAIL (SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE) +/*! @brief High Speed Clock Good */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_GOOD (SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE) +/*! @brief High Speed Clock Stuck Fault */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_FAULT (SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE) +/*! @brief SYSPLL is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_OFF (SYSCTL_CLKSTATUS_SYSPLLOFF_TRUE) +/*! @brief HFCLKs is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_OFF (SYSCTL_CLKSTATUS_HFCLKOFF_TRUE) +/*! @brief All PLLs, HFCLKs are OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_OFF (SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE) +/*! @brief LFOSC is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFOSC_GOOD (SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE) +/*! @brief LFXT is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFXT_GOOD (SYSCTL_CLKSTATUS_LFXTGOOD_TRUE) +/*! @brief SYSTEM PLL ON */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD (SYSCTL_CLKSTATUS_SYSPLLGOOD_TRUE) +/*! @brief High Frequency Clock ON */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_GOOD (SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE) +/*! @brief MCLK now sourced from HSCLK, otherwise SYSOSC */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK (SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK) +/*! @brief MCLK now sourced from LFCLK */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK \ + (SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK) +/*! @brief Analog clocking error */ +#define DL_SYSCTL_CLK_STATUS_ANALOG_CLOCK_ERROR \ + (SYSCTL_CLKSTATUS_ANACLKERR_TRUE) +/*! @brief Frequency Clock Counter (FCC) done */ +#define DL_SYSCTL_CLK_STATUS_FCC_DONE (SYSCTL_CLKSTATUS_FCCDONE_DONE) +/*! @brief = LFCLK sourced from the LFXT (crystal) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_LFXT (SYSCTL_CLKSTATUS_LFCLKMUX_LFXT) +/*! @brief = LFCLK sourced from LFCLK_IN (external digital clock input) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_EXLF (SYSCTL_CLKSTATUS_LFCLKMUX_EXLF) +/*! @brief = SYSOSC is at low frequency (4MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_4MHZ (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M) +/*! @brief = SYSOSC is at the user-trimmed frequency (16 or 24MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_USERTRIM_FREQ \ + (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER) +/*! @brief = HSCLK current sourced from the HFCLK */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_SOURCE_HFCLK \ + (SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK) +/** @}*/ + +/** @addtogroup DL_SYSCTL_STATUS + * @{ + */ + +/*! @brief IO is locked due to SHUTDOWN */ +#define DL_SYSCTL_STATUS_SHUTDOWN_IO_LOCK_TRUE \ + (SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE) +/*! @brief User has disabled external reset pin */ +#define DL_SYSCTL_STATUS_EXT_RESET_PIN_DISABLED \ + (SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE) +/*! @brief User has disabled SWD port */ +#define DL_SYSCTL_STATUS_SWD_DISABLED (SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE) + +/*! @brief PMU IFREF good */ +#define DL_SYSCTL_STATUS_PMU_IFREF_GOOD (SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE) +/*! @brief VBOOST (Analog Charge Pump) started up properly */ +#define DL_SYSCTL_STATUS_VBOOST_GOOD (SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE) +/*! @brief Brown Out Reset event status indicator */ +#define DL_SYSCTL_STATUS_BOR_EVENT (SYSCTL_SYSSTATUS_BORLVL_TRUE) +/*! @brief MCAN0 ready */ +#define DL_SYSCTL_STATUS_MCAN0_READY (SYSCTL_SYSSTATUS_MCAN0READY_TRUE) +/*! @brief Double Error Detect on Flash */ +#define DL_SYSCTL_STATUS_FLASH_DED (SYSCTL_SYSSTATUS_FLASHDED_TRUE) +/*! @brief Single Error Correction on Flash */ +#define DL_SYSCTL_STATUS_FLASH_SEC (SYSCTL_SYSSTATUS_FLASHSEC_TRUE) +/*! @brief Current Brown Out Reset minimum level */ +#define DL_SYSCTL_STATUS_BOR_LEVEL0 \ + (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN) +/*! @brief Current Brown Out Reset level 1 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL1 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1) +/*! @brief Current Brown Out Reset level 2 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL2 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2) +/*! @brief Current Brown Out Reset level 3 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL3 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK2X + * @{ + */ +/*! @brief Enable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_ENABLE) + +/*! @brief Disable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK1 + * @{ + */ +/*! @brief Enable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_ENABLE) + +/*! @brief Disable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK0 + * @{ + */ +/*! @brief Enable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_ENABLE) + +/*! @brief Disable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_DISABLE) +/** @}*/ + +/* clang-format on */ + +/*! @enum DL_SYSCTL_SYSPLL_MCLK */ +typedef enum { + /*! Use PLL CLK2x as source for MCLK */ + DL_SYSCTL_SYSPLL_MCLK_CLK2X = SYSCTL_SYSPLLCFG0_MCLK2XVCO_ENABLE, + /*! Use PLL CLK0 as source for MCLK */ + DL_SYSCTL_SYSPLL_MCLK_CLK0 = SYSCTL_SYSPLLCFG0_MCLK2XVCO_DISABLE, +} DL_SYSCTL_SYSPLL_MCLK; + +/*! @enum DL_SYSCTL_SYSPLL_REF */ +typedef enum { + /*! Use SYSOSC as input source for SYSPLL */ + DL_SYSCTL_SYSPLL_REF_SYSOSC = SYSCTL_SYSPLLCFG0_SYSPLLREF_SYSOSC, + /*! Use HFCLK as input source for SYSPLL */ + DL_SYSCTL_SYSPLL_REF_HFCLK = SYSCTL_SYSPLLCFG0_SYSPLLREF_HFCLK, +} DL_SYSCTL_SYSPLL_REF; + +/*! @enum DL_SYSCTL_SYSPLL_PDIV */ +typedef enum { + /*! Predivide input reference freq to PLL feedback loop by 1 */ + DL_SYSCTL_SYSPLL_PDIV_1 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV1, + /*! Predivide input reference freq to PLL feedback loop by 2 */ + DL_SYSCTL_SYSPLL_PDIV_2 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV2, + /*! Predivide input reference freq to PLL feedback loop by 4 */ + DL_SYSCTL_SYSPLL_PDIV_4 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV4, + /*! Predivide input reference freq to PLL feedback loop by 8 */ + DL_SYSCTL_SYSPLL_PDIV_8 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV8, +} DL_SYSCTL_SYSPLL_PDIV; + +/** @enum DL_SYSCTL_SYSPLL_INPUT_FREQ */ +typedef enum { + /*! PLL feedback loop input clock frequency [4MHz, 8MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_4_8_MHZ = 0x41C4001C, + /*! PLL feedback loop input clock frequency [8MHz, 16MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ = 0x41C40024, + /*! PLL feedback loop input clock frequency [16MHz, 32MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ = 0x41C4002C, + /*! PLL feedback loop input clock frequency [32MHz, 48MHz] */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ = 0x41C40034, +} DL_SYSCTL_SYSPLL_INPUT_FREQ; + +/*! @brief Configuration struct for @ref DL_SYSCTL_configSYSPLL. */ +typedef struct { + /*! Output divider for CLK2x. [0x0,0xF,0x1] => [/1,/16,1] */ + uint32_t rDivClk2x; + /*! Output divider for CLK1. [0x0,0xF,0x1] => [/2,/32,2] */ + uint32_t rDivClk1; + /*! Output divider for CLK0. [0x0,0xF,0x1] => [/2,/32,2] */ + uint32_t rDivClk0; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK2X */ + uint32_t enableCLK2x; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK1 */ + uint32_t enableCLK1; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK0 */ + uint32_t enableCLK0; + /*! Select which PLL output to use as source for MCLK. @ref DL_SYSCTL_SYSPLL_MCLK */ + DL_SYSCTL_SYSPLL_MCLK sysPLLMCLK; + /*! SYSPLL reference clock source. @ref DL_SYSCTL_SYSPLL_REF */ + DL_SYSCTL_SYSPLL_REF sysPLLRef; + /*! PLL feedback clock divider. [0x01,0x7E,1] => [/2,/127,1] */ + uint32_t qDiv; + /*! PLL reference clock divider. @ref DL_SYSCTL_SYSPLL_PDIV */ + DL_SYSCTL_SYSPLL_PDIV pDiv; + /*! PLL feedback loop input clock frequency. Affects startup time and power consumption. @ref DL_SYSCTL_SYSPLL_INPUT_FREQ */ + DL_SYSCTL_SYSPLL_INPUT_FREQ inputFreq; +} DL_SYSCTL_SYSPLLConfig; + +/*! @enum DL_SYSCTL_NMI_IIDX */ +typedef enum { + /*! @brief NMI interrupt index for SRAM Double Error Detect */ + DL_SYSCTL_NMI_IIDX_SRAM_DED = SYSCTL_NMIIIDX_STAT_SRAMDED, + /*! @brief NMI interrupt index for Flash Double Error Detect */ + DL_SYSCTL_NMI_IIDX_FLASH_DED = SYSCTL_NMIIIDX_STAT_FLASHDED, + /*! @brief NMI interrupt index for LFCLK Monitor Fail */ + DL_SYSCTL_NMI_IIDX_LFCLK_FAIL = SYSCTL_NMIIIDX_STAT_LFCLKFAIL, + /*! @brief NMI interrupt index for Watchdog 1 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT1_FAULT = SYSCTL_NMIIIDX_STAT_WWDT1, + /*! @brief NMI interrupt index for Watchdog 0 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT0_FAULT = SYSCTL_NMIIIDX_STAT_WWDT0, + /*! @brief NMI interrupt index for early BOR */ + DL_SYSCTL_NMI_IIDX_BORLVL = SYSCTL_NMIIIDX_STAT_BORLVL, + /*! @brief NMI interrupt index for no interrupt pending */ + DL_SYSCTL_NMI_IIDX_NO_INT = SYSCTL_NMIIIDX_STAT_NO_INTR, +} DL_SYSCTL_NMI_IIDX; + +/** @}*/ + +/*! @enum DL_SYSCTL_IIDX */ +typedef enum { + /*! @brief Low Frequency Oscillator is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFOSC_GOOD = SYSCTL_IIDX_STAT_LFOSCGOOD, + /*! @brief Analog clocking consistency error */ + DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR = SYSCTL_IIDX_STAT_ANACLKERR, + /*! @brief Flash Single Error Correct */ + DL_SYSCTL_IIDX_FLASH_SEC = SYSCTL_IIDX_STAT_FLASHSEC, + + /*! @brief SRAM Single Error Correct */ + DL_SYSCTL_IIDX_SRAM_SEC = SYSCTL_IIDX_STAT_SRAMSEC, + + /*! @brief Low Frequency Crystal is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFXT_GOOD = SYSCTL_IIDX_STAT_LFXTGOOD, + /*! @brief High Frequency Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HFCLK_GOOD = SYSCTL_IIDX_STAT_HFCLKGOOD, + /*! @brief System PLL is stabilized and ready to use */ + DL_SYSCTL_IIDX_SYSPLL_GOOD = SYSCTL_IIDX_STAT_SYSPLLGOOD, + /*! @brief High Speed Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HSCLK_GOOD = SYSCTL_IIDX_STAT_HSCLKGOOD, +} DL_SYSCTL_IIDX; + +/*! @enum DL_SYSCTL_ERROR_BEHAVIOR */ +typedef enum { + /*! @brief The error event will trigger a SYSRST */ + DL_SYSCTL_ERROR_BEHAVIOR_RESET = 0x0, + /*! @brief The error event will trigger an NMI */ + DL_SYSCTL_ERROR_BEHAVIOR_NMI = 0x1, +} DL_SYSCTL_ERROR_BEHAVIOR; + +/*! @enum DL_SYSCTL_SYSOSC_FREQ */ +typedef enum { + /*! Use 4MHz for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_4M = (SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M), + /*! Use BASE (32MHz) for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_BASE = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE), + /*! User will trim the System Oscillator (SYSOSC) to 16MHz or 24MHz */ + DL_SYSCTL_SYSOSC_FREQ_USERTRIM = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER), +} DL_SYSCTL_SYSOSC_FREQ; + +/** @enum DL_SYSCTL_SYSOSC_USERTRIM_FREQ */ +typedef enum { + /*! Set SYSOSC user trim frequency target to 16MHz */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ_16M = + (SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC16M), + /*! Set SYSOSC user trim frequency target to 24MHz */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ_24M = + (SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC24M), +} DL_SYSCTL_SYSOSC_USERTRIM_FREQ; + +/*! @brief Configuration struct for @ref DL_SYSCTL_configSYSOSCUserTrim. */ +typedef struct { + /*! Frequency Correcting Loop resistor divide value [0x0, 0x1FF] */ + uint32_t rDiv; + /*! Resistor fine trim [0x0, 0xF] */ + uint32_t resistorFine; + /*! Resistor coarse trim [0x0, 0x3F] */ + uint32_t resistorCoarse; + /*! Capacitor trim [0x0, 0x7] */ + uint32_t capacitor; + /*! SYSOSC user trim frequency target */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ freq; +} DL_SYSCTL_SYSOSCUserTrimConfig; + +/** @enum DL_SYSCTL_ULPCLK_DIV */ +typedef enum { + /*! ULPCLK is MCLK */ + DL_SYSCTL_ULPCLK_DIV_1 = (SYSCTL_MCLKCFG_UDIV_NODIVIDE), + /*! ULPCLK is MCLK divided by 2 */ + DL_SYSCTL_ULPCLK_DIV_2 = (SYSCTL_MCLKCFG_UDIV_DIVIDE2), +} DL_SYSCTL_ULPCLK_DIV; + +/** @enum DL_SYSCTL_LFXT_DRIVE_STRENGTH */ +typedef enum { + /*! Lowest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV), + /*! Lower Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWER = (SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV), + /*! Higher Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHER = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV), + /*! Highest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV), +} DL_SYSCTL_LFXT_DRIVE_STRENGTH; + +/*! @brief Configuration struct for @ref DL_SYSCTL_LFCLKConfig. */ +typedef struct { + /*! Enable if CAP is less than 3pF to reduce power consumption */ + bool lowCap; + /*! Enable to use monitor for LFXT, EXLF failure */ + bool monitor; + /*! Drive strength and power consumption option */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH xt1Drive; +} DL_SYSCTL_LFCLKConfig; + +/** @enum DL_SYSCTL_HFXT_RANGE */ +typedef enum { + /*! HFXT frequency range between 4 and 8 MHz */ + DL_SYSCTL_HFXT_RANGE_4_8_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8, + /*! HFXT frequency range between 8.01 and 16 MHz */ + DL_SYSCTL_HFXT_RANGE_8_16_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16, + /*! HFXT frequency range between 16.01 and 32 MHz */ + DL_SYSCTL_HFXT_RANGE_16_32_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32, + /*! HFXT frequency range between 32.01 and 48 MHz */ + DL_SYSCTL_HFXT_RANGE_32_48_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48, +} DL_SYSCTL_HFXT_RANGE; + +/*! @enum DL_SYSCTL_HSCLK_SOURCE */ +typedef enum { + /*! Use SYSPLL as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_SYSPLL = SYSCTL_HSCLKCFG_HSCLKSEL_SYSPLL, + /*! Use HFLK as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_HFCLK = SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK, +} DL_SYSCTL_HSCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MCLK source (default after reset) */ + DL_SYSCTL_MCLK_SOURCE_SYSOSC = SYSCTL_MCLKCFG_USEHSCLK_DISABLE, + /*! Use High Speed Clock (HSCLK) as MCLK source (HFCLK, PLL,...) */ + DL_SYSCTL_MCLK_SOURCE_HSCLK = SYSCTL_MCLKCFG_USEHSCLK_ENABLE, + /*! Use the Low Frequency Clock (LFCLK) as the clock source */ + DL_SYSCTL_MCLK_SOURCE_LFCLK = SYSCTL_MCLKCFG_USELFCLK_ENABLE, +} DL_SYSCTL_MCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_DIVIDER */ +typedef enum { + /*! Disable MCLK divider. Change SYSOSC freq only when MDIV is disabled */ + DL_SYSCTL_MCLK_DIVIDER_DISABLE = 0x0, + /*! Divide MCLK frequency by 2 */ + DL_SYSCTL_MCLK_DIVIDER_2 = 0x1, + /*! Divide MCLK frequency by 3 */ + DL_SYSCTL_MCLK_DIVIDER_3 = 0x2, + /*! Divide MCLK frequency by 4 */ + DL_SYSCTL_MCLK_DIVIDER_4 = 0x3, + /*! Divide MCLK frequency by 5 */ + DL_SYSCTL_MCLK_DIVIDER_5 = 0x4, + /*! Divide MCLK frequency by 6 */ + DL_SYSCTL_MCLK_DIVIDER_6 = 0x5, + /*! Divide MCLK frequency by 7 */ + DL_SYSCTL_MCLK_DIVIDER_7 = 0x6, + /*! Divide MCLK frequency by 8 */ + DL_SYSCTL_MCLK_DIVIDER_8 = 0x7, + /*! Divide MCLK frequency by 9 */ + DL_SYSCTL_MCLK_DIVIDER_9 = 0x8, + /*! Divide MCLK frequency by 10 */ + DL_SYSCTL_MCLK_DIVIDER_10 = 0x9, + /*! Divide MCLK frequency by 11 */ + DL_SYSCTL_MCLK_DIVIDER_11 = 0xA, + /*! Divide MCLK frequency by 12 */ + DL_SYSCTL_MCLK_DIVIDER_12 = 0xB, + /*! Divide MCLK frequency by 13 */ + DL_SYSCTL_MCLK_DIVIDER_13 = 0xC, + /*! Divide MCLK frequency by 14 */ + DL_SYSCTL_MCLK_DIVIDER_14 = 0xD, + /*! Divide MCLK frequency by 15 */ + DL_SYSCTL_MCLK_DIVIDER_15 = 0xE, + /*! Divide MCLK frequency by 16 */ + DL_SYSCTL_MCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_MCLK_DIVIDER; + +/** @enum DL_SYSCTL_CLK_OUT_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC, + /*! Use Ultra Low Power Clock (ULPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_ULPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK, + /*! Use Low Frequency Clock (LFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_LFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK, + /*! Use Middle Frequency Precision Clock (MFPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_MFPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK, + /*! Use High Frequency Clock (HFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_HFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK, + /*! Use System PLL Output 1 (SYSPLLOUT1) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSPLLOUT1 = SYSCTL_GENCLKCFG_EXCLKSRC_SYSPLLOUT1, +} DL_SYSCTL_CLK_OUT_SOURCE; + +/** @enum DL_SYSCTL_CLK_OUT_DIVIDE */ +typedef enum { + /*! Disable the External Clock (CLK_OUT) output divider */ + DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE = SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU, + /*! Divide External Clock (CLK_OUT) output by 2 */ + DL_SYSCTL_CLK_OUT_DIVIDE_2 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2, + /*! Divide External Clock (CLK_OUT) output by 4 */ + DL_SYSCTL_CLK_OUT_DIVIDE_4 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4, + /*! Divide External Clock (CLK_OUT) output by 6 */ + DL_SYSCTL_CLK_OUT_DIVIDE_6 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6, + /*! Divide External Clock (CLK_OUT) output by 8 */ + DL_SYSCTL_CLK_OUT_DIVIDE_8 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8, + /*! Divide External Clock (CLK_OUT) output by 10 */ + DL_SYSCTL_CLK_OUT_DIVIDE_10 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10, + /*! Divide External Clock (CLK_OUT) output by 12 */ + DL_SYSCTL_CLK_OUT_DIVIDE_12 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12, + /*! Divide External Clock (CLK_OUT) output by 14 */ + DL_SYSCTL_CLK_OUT_DIVIDE_14 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14, + /*! Divide External Clock (CLK_OUT) output by 16 */ + DL_SYSCTL_CLK_OUT_DIVIDE_16 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16, +} DL_SYSCTL_CLK_OUT_DIVIDE; + +/** @enum DL_SYSCTL_MFPCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC, + /*! Use High Frequency Clock (HFCLK) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK, +} DL_SYSCTL_MFPCLK_SOURCE; + +/** @enum DL_SYSCTL_HFCLK_MFPCLK_DIVIDER */ +typedef enum { + /*! HFCLK is not divided before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_DISABLE = 0x0, + /*! Divide HFCLK by 2 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_2 = 0x1, + /*! Divide HFCLK by 3 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_3 = 0x2, + /*! Divide HFCLK by 4 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_4 = 0x3, + /*! Divide HFCLK by 5 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_5 = 0x4, + /*! Divide HFCLK by 6 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6 = 0x5, + /*! Divide HFCLK by 7 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_7 = 0x6, + /*! Divide HFCLK by 8 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_8 = 0x7, + /*! Divide HFCLK by 9 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_9 = 0x8, + /*! Divide HFCLK by 10 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_10 = 0x9, + /*! Divide HFCLK by 11 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_11 = 0xA, + /*! Divide HFCLK by 12 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_12 = 0xB, + /*! Divide HFCLK by 13 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_13 = 0xC, + /*! Divide HFCLK by 14 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_14 = 0xD, + /*! Divide HFCLK by 15 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_15 = 0xE, + /*! Divide HFCLK by 16 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_HFCLK_MFPCLK_DIVIDER; + +/** @enum DL_SYSCTL_FCC_TRIG_TYPE */ +typedef enum { + /*! FCC trigger is rising-edge to rising-edge pulse */ + DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE = SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE, + /*! FCC trigger is active-high pulse level */ + DL_SYSCTL_FCC_TRIG_TYPE_LEVEL = SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL, +} DL_SYSCTL_FCC_TRIG_TYPE; + +/** @enum DL_SYSCTL_FCC_TRIG_SOURCE */ +typedef enum { + /*! FCC trigger source is FCC_IN external pin */ + DL_SYSCTL_FCC_TRIG_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN, + /*! FCC trigger source is LFCLK */ + DL_SYSCTL_FCC_TRIG_SOURCE_LFCLK = SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK, +} DL_SYSCTL_FCC_TRIG_SOURCE; + +/** @enum DL_SYSCTL_FCC_CLOCK_SOURCE */ +typedef enum { + /*! FCC clock source to capture is MCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_MCLK = SYSCTL_GENCLKCFG_FCCSELCLK_MCLK, + /*! FCC clock source to capture is SYSOSC */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC, + /*! FCC clock source to capture is HFCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK, + /*! FCC clock source to capture is CLK_OUT */ + DL_SYSCTL_FCC_CLOCK_SOURCE_CLK_OUT = SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK, + /*! FCC clock source to capture is SYSPLLCLK0 */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK0 = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK0, + /*! FCC clock source to capture is SYSPLLCLK1 */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK1 = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK1, + /*! FCC clock source to capture is SYSPLLCLK2X */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK2X = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK2X, + /*! FCC clock source to capture is FCC_IN */ + DL_SYSCTL_FCC_CLOCK_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN, +} DL_SYSCTL_FCC_CLOCK_SOURCE; + +/** @enum DL_SYSCTL_FCC_TRIG_CNT */ +typedef enum { + /*! One monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_01 = + ((uint32_t) 0 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_02 = + ((uint32_t) 1 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_03 = + ((uint32_t) 2 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_04 = + ((uint32_t) 3 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_05 = + ((uint32_t) 4 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_06 = + ((uint32_t) 5 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_07 = + ((uint32_t) 6 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_08 = + ((uint32_t) 7 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_09 = + ((uint32_t) 8 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Ten monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_10 = + ((uint32_t) 9 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eleven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_11 = + ((uint32_t) 10 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twelve monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_12 = + ((uint32_t) 11 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_13 = + ((uint32_t) 12 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fourteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_14 = + ((uint32_t) 13 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fifteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_15 = + ((uint32_t) 14 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Sixteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_16 = + ((uint32_t) 15 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seventeen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_17 = + ((uint32_t) 16 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eighteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_18 = + ((uint32_t) 17 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nineteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_19 = + ((uint32_t) 18 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_20 = + ((uint32_t) 19 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_21 = + ((uint32_t) 20 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_22 = + ((uint32_t) 21 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_23 = + ((uint32_t) 22 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_24 = + ((uint32_t) 23 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_25 = + ((uint32_t) 24 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_26 = + ((uint32_t) 25 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_27 = + ((uint32_t) 26 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_28 = + ((uint32_t) 27 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_29 = + ((uint32_t) 28 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_30 = + ((uint32_t) 29 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_31 = + ((uint32_t) 30 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_32 = + ((uint32_t) 31 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), +} DL_SYSCTL_FCC_TRIG_CNT; + +/** @enum DL_SYSCTL_VBOOST */ +typedef enum { + /*! VBOOST enabled only when COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONDEMAND = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND, + /*! VBOOST enabled in RUN/SLEEP, and in STOP/STANDBY if COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONACTIVE = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE, + /*! VBOOST enabled in all power modes except SHUTDOWN for fastest startup */ + DL_SYSCTL_VBOOST_ONALWAYS = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS, +} DL_SYSCTL_VBOOST; + +/** @enum DL_SYSCTL_FLASH_WAIT_STATE */ +typedef enum { + /*! 0 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_0 = ((uint32_t) 0x00000000U), + /*! 1 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_1 = ((uint32_t) 0x00000100U), + /*! 2 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_2 = ((uint32_t) 0x00000200U), +} DL_SYSCTL_FLASH_WAIT_STATE; + +/** @enum DL_SYSCTL_POWER_POLICY_RUN_SLEEP */ +typedef enum { + /*! RUN/SLEEP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED = 0x0, + /*! Enable RUN0/SLEEP0 power mode policy. */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP0 = 0x1, + /*! Enable the RUN1/SLEEP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP1 = 0x2, + /*! Enable the RUN2/SLEEP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_RUN_SLEEP; + +/** @enum DL_SYSCTL_POWER_POLICY_STOP */ +typedef enum { + /*! STOP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED = 0x0, + /*! Enable the STOP0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP0 = 0x1, + /*! Enable the STOP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP1 = 0x2, + /*! Enable the STOP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_STOP; + +/** @enum DL_SYSCTL_POWER_POLICY_STANDBY */ +typedef enum { + /*! STANDBY power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED = 0x0, + /*! Enable the STANDBY0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY0 = 0x1, + /*! Enable the STANDBY1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY1 = 0x2, +} DL_SYSCTL_POWER_POLICY_STANDBY; + +/** @enum DL_SYSCTL_BOR_THRESHOLD_LEVEL */ +typedef enum { + /*! BOR0 threshold level. This is the minimum allowed threshold. + * A BOR0- violation will force a re-boot. */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_0 = SYSCTL_BORTHRESHOLD_LEVEL_BORMIN, + /*! BOR1 threshold level. A BOR1- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_1 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1, + /*! BOR2 threshold level. A BOR2- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_2 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2, + /*! BOR3 threshold level. A BOR3- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_3 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3, +} DL_SYSCTL_BOR_THRESHOLD_LEVEL; + +/** @enum DL_SYSCTL_SHUTDOWN_STORAGE_BYTE */ +typedef enum { + /*! Shutdown Storage Byte 0 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_0 = 0x0, + /*! Shutdown Storage Byte 1 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_1 = 0x1, + /*! Shutdown Storage Byte 2 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_2 = 0x2, + /*! Shutdown Storage Byte 3 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_3 = 0x3, +} DL_SYSCTL_SHUTDOWN_STORAGE_BYTE; + +/** @enum DL_SYSCTL_RESET_CAUSE */ +typedef enum { + /*! No Reset Since Last Read */ + DL_SYSCTL_RESET_CAUSE_NO_RESET = SYSCTL_RSTCAUSE_ID_NORST, + /*! (VDD < POR- violation) or (PMU trim parity fault) or (SHUTDNSTOREx parity fault) */ + DL_SYSCTL_RESET_CAUSE_POR_HW_FAILURE = SYSCTL_RSTCAUSE_ID_PORHWFAIL, + /*! NRST pin reset (>1s) */ + DL_SYSCTL_RESET_CAUSE_POR_EXTERNAL_NRST = SYSCTL_RSTCAUSE_ID_POREXNRST, + /*! Software-triggered POR */ + DL_SYSCTL_RESET_CAUSE_POR_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_PORSW, + /*! VDD < BOR- violation */ + DL_SYSCTL_RESET_CAUSE_BOR_SUPPLY_FAILURE = SYSCTL_RSTCAUSE_ID_BORSUPPLY, + /*! Wake from SHUTDOWN */ + DL_SYSCTL_RESET_CAUSE_BOR_WAKE_FROM_SHUTDOWN = + SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN, + /*! Non-PMU trim parity fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_NON_PMU_PARITY_FAULT = + SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY, + /*! Fatal clock fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_CLOCK_FAULT = SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL, + /*! Software-triggered BOOTRST */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_BOOTSW, + /*! NRST pin reset (<1s) */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_EXTERNAL_NRST = + SYSCTL_RSTCAUSE_ID_BOOTEXNRST, + /*! BSL exit */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_EXIT = SYSCTL_RSTCAUSE_ID_SYSBSLEXIT, + /*! BSL entry */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_ENTRY = SYSCTL_RSTCAUSE_ID_SYSBSLENTRY, + /*! WWDT0 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT0_VIOLATION = + SYSCTL_RSTCAUSE_ID_BOOTWWDT0, + /*! WWDT1 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT1_VIOLATION = SYSCTL_RSTCAUSE_ID_SYSWWDT1, + /*! Uncorrectable flash ECC error */ + DL_SYSCTL_RESET_CAUSE_SYSRST_FLASH_ECC_ERROR = + SYSCTL_RSTCAUSE_ID_SYSFLASHECC, + /*! CPULOCK violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_CPU_LOCKUP_VIOLATION = + SYSCTL_RSTCAUSE_ID_SYSCPULOCK, + /*! Debug-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSDBG, + /*! Software-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSSW, + /*! Debug-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUDBG, + /*! Software-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUSW, +} DL_SYSCTL_RESET_CAUSE; + +/** @enum DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE */ +typedef enum { + /*! SRAM Bank 1 will be powered ON when in RUN mode */ + DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE_ON = + SYSCTL_SRAMCFG_BANKOFF1_TRUE, + /*! SRAM Bank 1 will be powered OFF when in RUN mode */ + DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE_OFF = + SYSCTL_SRAMCFG_BANKOFF1_FALSE, +} DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE; + +/** @enum DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE */ +typedef enum { + /*! Data contents of SRAM Bank 1 will be retained when in STOP mode */ + DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE_RETAIN = + SYSCTL_SRAMCFG_BANKSTOP1_TRUE, + /*! SRAM Bank 1 will be powered OFF when in STOP mode */ + DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE_OFF = + SYSCTL_SRAMCFG_BANKSTOP1_FALSE, +} DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE; + +/** @enum DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL */ +typedef enum { + /*! DATA Bank Read Write Protect Firewall both RW allowed */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_ENABLED = 0x0, + /*! DATA Bank Read Write Protect Firewall read only */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_R_ONLY = 0x1, + /*! DATA Bank Read Write Protect Firewall both RW disabled */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_DISABLED = 0x2, +} DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL; + +/** + * @brief Enable sleep on exit + * + * Enables sleep on exit when the CPU moves from handler mode to thread mode. + * By enabling, allows an interrupt driven application to avoid returning to + * an empty main application. + */ +__STATIC_INLINE void DL_SYSCTL_enableSleepOnExit(void) +{ + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; +} + +/** + * @brief Disable sleep on exit + * + * Disables sleep on exit when the CPU moves from handler mode to thread mode. + */ +__STATIC_INLINE void DL_SYSCTL_disableSleepOnExit(void) +{ + SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Check if sleep on exit is enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSleepOnExitEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SLEEPONEXIT_Msk) == SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable send event on pending bit + * + * When enabled, any enabled event and all interrupts (including disabled + * interrupts) can wakeup the processor. + */ +__STATIC_INLINE void DL_SYSCTL_enableEventOnPend(void) +{ + SCB->SCR |= SCB_SCR_SEVONPEND_Msk; +} + +/** + * @brief Disable send event on pending bit + * + * When disabled, only enabled interrupts or events can wake up the processor. + * Disabled interrupts are excluded. + */ +__STATIC_INLINE void DL_SYSCTL_disableEventOnPend(void) +{ + SCB->SCR &= ~(SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Check if send event on pending bit is enabled + * + * @return Returns the enabled status of the send event on pending bit + * + * @retval true Send event on pending bit is enabled + * @retval false Send event on pending bit is disabled + */ +__STATIC_INLINE bool DL_SYSCTL_isEventOnPendEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SEVONPEND_Msk) == SCB_SCR_SEVONPEND_Msk); +} + +/*! + * @brief Change MCLK source + * + * To ensure good clocking behavior, these are the recommended steps for transition. + * Valid sources and destinations: LFCLK, SYSOSC, HSCLK + * + * Depending on current MCLK source, steps to switch to next MCLK source can vary. + * This is a macro that redirects to the different possible transitions. + * + * Only valid for RUN modes. In low power modes, MCLK transitions are handled by hardware. + * + * @note Different transition APIs may require different input parameters + * Transitions between LFCLK and HSCLK requires going through SYSOSC. + * + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK + * @sa DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK + * @sa DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC + */ +#define DL_SYSCTL_setMCLKSource(current, next, ...) \ + DL_SYSCTL_switchMCLKfrom##current##to##next(__VA_ARGS__); + +/** + * @brief Change MCLK source from SYSOSC to LFCLK + * + * @pre If disabling SYSOSC, high speed oscillators (SYSPLL, HFXT...) must be disabled beforehand. + * @post MCLK source is switched to LFCLK, function will busy-wait until confirmed. + * + * @param[in] disableSYSOSC Whether to leave SYSOSC running or not + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC); + +/** + * @brief Change MCLK source from LFCLK to SYSOSC + * + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + */ +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void); + +/** + * @brief Change MCLK source from SYSOSC to HSCLK + * + * @pre The desired HSCLK source is enabled beforehand (SYSPLL, HFXT, HFCLK_IN). + * @post MCLK source is switched to HSCLK, function will busy-wait until confirmed. + * + * @param[in] source Desired high-speed clock source + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source); + +/** + * @brief Change MCLK source from HSCLK to SYSOSC + * + * @pre MCLK is sourced from a valid, running HSCLK source (SYSPLL, HFXT, HFCLK_IN) + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + * + * @note No HSCLK sources are disabled by this function + */ +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void); + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN0/SLEEP0 + * + * In RUN0, the MCLK and the CPUCLK run from a fast clock source (SYSOSC, + * HFCLK, or SYSPLL). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN0SLEEP0(void) +{ + DL_SYSCTL_setMCLKSource(LFCLK, SYSOSC); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN1/SLEEP1 + * + * In RUN1, the MCLK and the CPUCLK run from LFCLK (at 32kHz) to reduce active + * power, but SYSOSC is left enabled to service analog modules such as an ADC, + * DAC, OPA, or COMP (in HS mode). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN1SLEEP1(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) false); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN2/SLEEP2 + * + * In RUN2, the MCLK and the CPUCLK run from LFCLK (at 32kHz), and SYSOSC is + * completely disabled to save power. This is the lowest power state with + * the CPU running + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @note Since this turns off SYSOSC, HSCLK sources MUST be disabled before calling + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN2SLEEP2(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) true); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Get the RUN/SLEEP mode power policy + * + * Get which RUN/SLEEP power policy has been set. + * + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. + * + * @return Returns the current RUN/SLEEP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_RUN_SLEEP + + */ +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void); + +/** + * @brief Set the STOP mode power policy to STOP0 + * + * In STOP0, the SYSOSC is left running at the current frequency when entering + * STOP mode (either 32MHz, 24MHz, 16MHz, or 4MHz). ULPCLK is always limited + * to 4MHz automatically by hardware, but SYSOSC is not disturbed to support + * consistent operation of analog peripherals such as the ADC, OPA, or COMP. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~( + SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK | SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP1 + * + * In STOP1, the SYSOSC is gear shifted from its current frequency to 4MHz for + * the lowest power consumption in STOP mode with SYSOSC running. SYSOSC and + * ULPCLK both run at 4MHz. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP2 + * + * In STOP2, the SYSOSC is disabled and the ULPCLK is sourced from LFCLK at + * 32kHz. This is the lowest power state in STOP mode. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP2(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK); + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLESTOP_MASK; +} + +/** + * @brief Get the STOP mode power policy + * + * Get which STOP power policy has been set. + * + * @return Returns the current STOP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STOP if a STOP power policy + */ +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void); + +/** + * @brief Set the STANDBY mode power policy to STANDBY0 + * + * In STANDBY0, all PD0 peripherals receive the ULPCLK and LFCLK, and the RTC + * receives RTCCLK. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_STOPCLKSTBY_MASK); +} + +/** + * @brief Set the STANDBY mode power policy to STANDBY1 + * + * In STANDBY1, only TIMG0 and TIMG1 receive ULPCLK/LFCLK. The RTC continues + * to receive RTCCLK. A TIMG0/1 interrupt, RTC interrupt, or ADC trigger in + * STANDBY1 always triggers an asynchronous fast clock request to wake the + * system. Other PD0 peripherals (such as UART, I2C, GPIO, and COMP) can also + * wake the system upon an external event through an asynchronous fast clock + * request, but they are not actively clocked in STANDBY1. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_STOPCLKSTBY_MASK; +} + +/** + * @brief Get the STANDBY mode power policy + * + * Get which STANDBY power policy has been set. + * + * @return Returns the current STANDBY mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STANDBY + */ +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void); + +/** + * @brief Set power policy to SHUTDOWN mode + * + * In SHUTDOWN mode, no clocks are available. The core regulator is completely + * disabled and all SRAM and register contents are lost, with the exception of + * the 4 bytes of general purpose memory in SYSCTL which may be used to store + * state information. The BOR and bandgap circuit are disabled. The device may + * wake up via a wake-up capable IO, a debug connection, or NRST. SHUTDOWN mode + * has the lowest current consumption of any operating mode. Exiting SHUTDOWN + * mode triggers a BOR. + * + * There is only one SHUTDOWN mode policy option: SHUTDOWN. + * + * @post This API does not actually enter SHUTDOWN mode. After using this API + * to enable SHUTDOWN mode, to enter SHUTDOWN mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySHUTDOWN(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_SHUTDOWN; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Set the brown-out reset (BOR) threshold level + * + * Note that this API does NOT activate the BOR threshold. After setting the + * threshold level with this API, call @ref DL_SYSCTL_activateBORThreshold + * to actually activate the new threshold. + * + * During startup, the BOR threshold defaults to BOR0 (the lowet value) to + * ensure the device always starts at the specified VDD minimum. After boot, + * the BOR threshold level can be configured to a different level. When the + * BOR threshold is BOR0, a BOR0- violation always generates a BOR- violation + * signal to SYSCTL, generating a BOR level reset. When the BOR threshold is + * re-configured to BOR1, BOR2, or BOR3 the BOR circuit will generate a SYSCTL + * interrupt rather than asserting a BOR- violation. This may be used to give + * the application an indication that the supply has dropped below a certain + * level without causing a reset. If the BOR is in interrupt mode (threshold + * level of BOR1-3), and VDD drops below the respective BORx- level, an + * interrupt will be generated and the BOR circuit will automatically switch + * the BOR threshold level to BOR0 to ensure that a BOR- violation is + * asserted if VDD drops below BOR0-. + * + * @param[in] thresholdLevel The BOR threshold level to set. + * One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL. + * + * @post DL_SYSCTL_activateBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_setBORThreshold( + DL_SYSCTL_BOR_THRESHOLD_LEVEL thresholdLevel) +{ + SYSCTL->SOCLOCK.BORTHRESHOLD = (uint32_t) thresholdLevel; +} + +/** + * @brief Get the brown-out reset (BOR) threshold level + * + * @return Returns the current BOR threshold level. + * + * @retval One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL + */ +__STATIC_INLINE DL_SYSCTL_BOR_THRESHOLD_LEVEL DL_SYSCTL_getBORThreshold(void) +{ + return (DL_SYSCTL_BOR_THRESHOLD_LEVEL)(SYSCTL->SOCLOCK.BORTHRESHOLD); +} + +/** + * @brief Activate the BOR threshold level + * + * Attempts to change the active BOR mode to the BOR threshold that was set + * via @ref DL_SYSCTL_setBORThreshold. + * + * Setting this bit also clears any prior BOR violation status indications. + * + * After calling this API, the change can be validated by calling + * @ref DL_SYSCTL_getStatus and checking the return value. + * + * @pre DL_SYSCTL_setBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_activateBORThreshold(void) +{ + SYSCTL->SOCLOCK.BORCLRCMD = + SYSCTL_BORCLRCMD_KEY_VALUE | SYSCTL_BORCLRCMD_GO_TRUE; +} + +/** + * @brief Resets the device + * + * Resets the device using the type of reset selected. This function does not + * return, the reset will happen immediately. + * + * @param[in] resetType Type of reset to perform. One of @ref + * DL_SYSCTL_RESET. + */ +__STATIC_INLINE void DL_SYSCTL_resetDevice(uint32_t resetType) +{ + SYSCTL->SOCLOCK.RESETLEVEL = resetType; + SYSCTL->SOCLOCK.RESETCMD = + SYSCTL_RESETCMD_KEY_VALUE | SYSCTL_RESETCMD_GO_TRUE; +} + +/** + * @brief Enable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_enableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK |= interruptMask; +} + +/** + * @brief Disable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_disableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which SYSCTL interrupts are enabled + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are enabled + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterrupts(uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SYSCTL interrupts + * + * Checks if any of the SYSCTL interrupts that were previously enabled are + * pending. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + * + * @sa DL_SYSCTL_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @return The highest priority pending SYSCTL interrupt + * + * @retval One of @ref DL_SYSCTL_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_IIDX DL_SYSCTL_getPendingInterrupt(void) +{ + return (DL_SYSCTL_IIDX)(SYSCTL->SOCLOCK.IIDX); +} + +/** + * @brief Clear pending SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_clearInterruptStatus(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.ICLR = interruptMask; +} + +/** + * @brief Check interrupt flag of any SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_NMI. + * + * @return Which of the requested SYSCTL non-maskable interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_NMI values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.NMIRIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @return The highest priority pending SYSCTL non-maskable interrupt + * + * @retval One of @ref DL_SYSCTL_NMI_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_NMI_IIDX DL_SYSCTL_getPendingNonMaskableInterrupt( + void) +{ + return (DL_SYSCTL_NMI_IIDX)(SYSCTL->SOCLOCK.NMIIIDX); +} + +/** + * @brief Clear pending SYSCTL non-maskable interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_NMI. + */ +__STATIC_INLINE void DL_SYSCTL_clearNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.NMIICLR = interruptMask; +} + +/** + * @brief Set the behavior when a Flash ECC double error detect (DED) occurs + * + * Configures whether a Flash ECC double error detect (DED) will trigger + * a SYSRST or an NMI (non-maskable interrupt). By default, this error will + * trigger a SYSRST. + * + * @param[in] behavior The behavior when a Flash ECC DED error occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setFlashDEDErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a Flash ECC double error detect (DED) occurs + * + * By default, this error will trigger a SYSRST. + * + * @return The behavior when a Flash ECC DED error occurs + * + * 3@retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getFlashDEDErrorBehavior( + void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the behavior when a WWDT0 error occurs + * + * Configures whether a WWDT0 error will trigger a BOOTRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a BOOTRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT0ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT0 error occurs + * + * By default, this error will trigger a BOOTRST. + * + * @return The behavior when a WWDT0 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT0ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the behavior when a WWDT1 error occurs + * + * Configures whether a WWDT1 error will trigger a SYSRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a SYSRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT1ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT1 error occurs + * + * By default, this error will trigger a SYSRST. + * + * @return The behavior when a WWDT1 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT1ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the Main Clock (MCLK) divider (MDIV) + * + * Additionally, can use this function to disable MDIV. MDIV must be disabled + * before changing SYSOSC frequency. + * + * MDIV is not valid if MCLK source is HSCLK. + * MDIV is not used if MCLK source if LFCLK. + * + * @param[in] divider Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is + * HSCLK, a don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE void DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_MDIV_MASK); +} +/** + * @brief Get the Main Clock (MCLK) divider (MDIV) + * + * @return The value of the Main Clock (MCLK) divider (MDIV) + * + * @retval Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is HSCLK, a + * don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE DL_SYSCTL_MCLK_DIVIDER DL_SYSCTL_getMCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_MDIV_MASK; + + return (DL_SYSCTL_MCLK_DIVIDER)(divider); +} + +/** + * @brief Get the source for the Main Clock (MCLK) + * + * @return The source for the Main Clock (MCLK) + * + * @retval One of @ref DL_SYSCTL_MCLK_SOURCE + */ +__STATIC_INLINE DL_SYSCTL_MCLK_SOURCE DL_SYSCTL_getMCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.MCLKCFG & + (SYSCTL_MCLKCFG_USEHSCLK_MASK | SYSCTL_MCLKCFG_USELFCLK_MASK); + + return (DL_SYSCTL_MCLK_SOURCE)(source); +} + +/** + * @brief Set the target frequency of the System Oscillator (SYSOSC) + * + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * + * The System Oscillator (SYSOSC) is an on-chip, accurate, configurable + * oscillator with factory trimmed support for 32MHz (base frequency) and 4MHz + * (low frequency) operation. + * It can also operate at 16MHz or 24MHz by using the + * @ref DL_SYSCTL_configSYSOSCUserTrim function instead. + * + * SYSOSC provides a flexible high-speed clock source for the system in cases + * where the HFXT is either not present or not used. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] freq Target frequency to use for the System Oscillator (SYSOSC). + * @ref DL_SYSCTL_SYSOSC_FREQ_4M or @ref DL_SYSCTL_SYSOSC_FREQ_BASE. + * + * @sa DL_SYSCTL_configSYSOSCUserTrim + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ freq) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, (uint32_t) freq, + SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Trim the System Oscillator (SYSOSC) to 16MHz or 24MHz + * + * The trim values supplied in the config struct must be determined by + * experimentation. Please refer to the "SYSOSC User Trim Procedure" section + * in the CKM Technical Reference Manual. + * Each device must be trimmed individually for accuracy. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] config Pointer to the SYSOSC user trim configuration struct + * @ref DL_SYSCTL_SYSOSCUserTrimConfig. + * + * @sa DL_SYSCTL_setSYSOSCFreq + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_configSYSOSCUserTrim( + const DL_SYSCTL_SYSOSCUserTrimConfig *config) +{ + SYSCTL->SOCLOCK.SYSOSCTRIMUSER = + ((config->rDiv << SYSCTL_SYSOSCTRIMUSER_RDIV_OFS) & + SYSCTL_SYSOSCTRIMUSER_RDIV_MASK) | + ((config->resistorFine << SYSCTL_SYSOSCTRIMUSER_RESFINE_OFS) & + SYSCTL_SYSOSCTRIMUSER_RESFINE_MASK) | + ((config->resistorCoarse << SYSCTL_SYSOSCTRIMUSER_RESCOARSE_OFS) & + SYSCTL_SYSOSCTRIMUSER_RESCOARSE_MASK) | + (config->capacitor << SYSCTL_SYSOSCTRIMUSER_CAP_OFS) | + ((uint32_t) config->freq); + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, + SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER, SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Get the target frequency of the System Oscillator (SYSOSC) + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * This function matches what is input by @ref DL_SYSCTL_setSYSOSCFreq. + * + * @return The target frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getTargetSYSOSCFreq(void) +{ + uint32_t freq = SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_FREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Get the current frequency of the System Oscillator (SYSOSC) + * Current/actual SYSOSC frequency may be different than target/desired SYSOSC + * frequency during gear shift and other operations. + * + * @return The current frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getCurrentSYSOSCFreq(void) +{ + uint32_t freq = + SYSCTL->SOCLOCK.CLKSTATUS & SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Returns status of the different clocks in CKM + * + * @return Full status of all clock selections + * + * @retval Bitwise OR of @ref DL_SYSCTL_CLK_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getClockStatus(void) +{ + return (SYSCTL->SOCLOCK.CLKSTATUS); +} + +/** + * @brief Returns general status of SYSCTL + * + * @return Full status of all general conditions in SYSCTL + * + * @retval Bitwise OR of @ref DL_SYSCTL_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getStatus(void) +{ + return (SYSCTL->SOCLOCK.SYSSTATUS); +} + +/** + * @brief Clear the ECC error bits in SYSSTATUS + * + * The ECC error bits in SYSSTATUS are sticky (they remain set when an ECC + * error occurs even if future reads do not have errors), and can be + * cleared through this API. + */ +__STATIC_INLINE void DL_SYSCTL_clearECCErrorStatus(void) +{ + SYSCTL->SOCLOCK.SYSSTATUSCLR = + (SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR | SYSCTL_SYSSTATUSCLR_KEY_VALUE); +} + +/** + * @brief Configure SYSPLL output frequencies + * + * @pre SYSPLL is disabled (SYSPLLOFF in CLKSTATUS) + * @pre SYSOSC is running at base frequency (32MHz) even if HFCLK is the + * SYSPLL reference + * @post SYSPLL has completed startup and outputs chosen frequencies + * + * @note For practical purposes, it is not required to wait until SYSPLL + * completes startup, but do not go into STOP/STANDBY or use SYSPLL + * until completed. + * + * @param[in] config Pointer to the SYSPLL configuration struct + * @ref DL_SYSCTL_SYSPLLConfig. Elements sysPLLRef, pDiv, and + * inputFreq control desired startup time versus power consumption. + */ +void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config); + +/** + * @brief Set the divider for the Ultra Low Power Clock (ULPCLK) + * + * The Ultra Low Power Clock (ULPCLK) is always sourced from the Main Clock + * (MCLK) but can be divided down to a lower frequency. The ULPCLK should + * always remain under 40MHz. + * + * The ULPCLK can be used to drive some peripherals on the system. + * + * @param[in] divider Clock divider for Ultra Low Power Clock (ULPCLK). One + * of @ref DL_SYSCTL_ULPCLK_DIV. + */ +__STATIC_INLINE void DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_UDIV_MASK); +} + +/** + * @brief Get divider used for the Ultra Low Power Clock (ULPCLK) + * + * @return The divider used for Ultra Low Power Clock (ULPCLK) + * + * @retval One of @ref DL_SYSCTL_ULPCLK_DIV. + */ +__STATIC_INLINE DL_SYSCTL_ULPCLK_DIV DL_SYSCTL_getULPCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_UDIV_MASK; + + return (DL_SYSCTL_ULPCLK_DIV)(divider); +} + +/** + * @brief Change LFCLK source to external crystal LFXT + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFXT is an ultra-low power crystal oscillator which supports driving a + * standard 32.768kHz watch crystal. + * + * To use the LFXT, a watch crystal must be populated between LFXIN and LFXOUT + * pins. Find more info in LFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure LFXT functionality for LFXIN and LFXOUT before + * calling this function. + * + * This basic implementation will busy-wait until LFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the LFXT is + * stabilizing. You can enable LFXTGOOD interrupt, or check CLKSTATUS.LFXTGOOD + * when convenient, as long as you do not switch the source via + * SETUSELFXT until LFXTGOOD is set. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFCLK_IN is disabled (default). + * + * @param[in] config Pointer to the LFCLK configuration struct + * @ref DL_SYSCTL_LFCLKConfig. + */ +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config); + +/** + * @brief Change LFCLK source to external digital LFCLK_IN + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFCLK_IN is a low frequency digital clock input compatible with 32.768kHz + * typical frequency digital square wave CMOS clock inputs (typical duty + * cycle of 50%). + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * LFCLK_IN. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFXT is disabled (default). + */ +__STATIC_INLINE void DL_SYSCTL_setLFCLKSourceEXLF(void) +{ + SYSCTL->SOCLOCK.EXLFCTL = + (SYSCTL_EXLFCTL_KEY_VALUE | SYSCTL_EXLFCTL_SETUSEEXLF_TRUE); +} + +/** + * @brief Change HFCLK source to external crystal HFXT with default parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * The HFXT startup time is set to ~0.512ms based on the TYP datasheet + * recommendation. Additionally, the HFCLK startup monitor is enabled. + * + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * To modify the default HFXT startup time or disable the startup monitor, use + * @ref DL_SYSCTL_setHFCLKSourceHFXTParams instead of this API. + * + * @param[in] range HFXT frequency range + */ +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range); + +/** + * @brief Change HFCLK source to external crystal HFXT with custom parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * If the HFCLK startup monitor is enabled, then the HFXT will be checked after + * the amount of time specified by the startupTime parameter. + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * If the HFCLK startup monitor is disabled, then this implementation will not + * check if the HFXT oscillator is stabilized. + * + * @param[in] range HFXT frequency range + * @param[in] startupTime HFXT startup time + * @param[in] monitorEnable Whether to enable the HFCLK startup monitor + + */ +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable); + +/** + * @brief Disable the SYSPLL + * + * If SYSPLL is already enabled, application software should not disable the + * SYSPLL until the SYSPLLGOOD or SYSPLOFF bit is set in the CLKSTATUS + * register, indicating that the SYSPLL transitioned to a stable active or a + * stable dead state. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableSYSPLL(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_SYSPLLEN_MASK); +} + +/** + * @brief Disable the HFXT + * + * If HFXT is already enabled, application software must verify that either an + * HFCLKGOOD indication or an HFCLKOFF (off/dead) indication in the CLKSTATUS + * register was asserted by hardware before attempting to disable the HFXT + * by clearing HFXTEN. When disabling the HFXT by clearing HFXTEN, the HFXT + * must not be re-enabled again until the HFCLKOFF bit in the CLKSTATUS + * register is set by hardware. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableHFXT(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_HFXTEN_MASK); +} + +/** + * @brief Change HFCLK source to external digital HFCLK_IN + * + * HFCLK_IN can be used to bypass the HFXT circuit and bring 4-48MHz typical + * frequency digital clock into the devce as HFCLK source instead of HFXT. + * + * HFCLK_IN is a digital clock input compatible with digital square wave CMOS + * clock inputs and should have typical duty cycle of 50%. + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * HFCLK_IN. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKSourceHFCLKIN(void) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE; +} + +/** + * @brief Get the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @return The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_HSCLK_SOURCE DL_SYSCTL_getHSCLKSource(void) +{ + uint32_t source = SYSCTL->SOCLOCK.HSCLKCFG & SYSCTL_HSCLKCFG_HSCLKSEL_MASK; + + return (DL_SYSCTL_HSCLK_SOURCE)(source); +} + +/** + * @brief Set the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @param[in] source The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setHSCLKSource(DL_SYSCTL_HSCLK_SOURCE source) +{ + SYSCTL->SOCLOCK.HSCLKCFG = (uint32_t) source; +} + +/** + * @brief Get the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @return The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_MFPCLK_SOURCE DL_SYSCTL_getMFPCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_MFPCLKSRC_MASK; + + return (DL_SYSCTL_MFPCLK_SOURCE)(source); +} + +/** + * @brief Set the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @param[in] source The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE source) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) source, + SYSCTL_GENCLKCFG_MFPCLKSRC_MASK); +} + +/** + * @brief Enable the Medium Frequency Clock (MFCLK) + * + * MFCLK provides a continuous 4MHz clock to drive certain peripherals on the system. + * The 4MHz rate is always derived from SYSOSC, and the divider is automatically + * applied to maintain the 4MHz rate regardless of SYSOSC frequency. + * MCLK is ideal for timers and serial interfaces which require a constant + * clock source in RUN/SLEEP/STOP power modes. + * + * MFCLK can only run if 3 conditions are met: + * + * 1) Power mode must be RUN, SLEEP, or STOP. + * 2) USEMFTICK register bit is set, which this function does + * 3) MDIV must be set to @ref DL_SYSCTL_MCLK_DIVIDER_DISABLE by @ref DL_SYSCTL_setMCLKDivider. + * + * If MCLK source is not SYSOSC, MCLK frequency must be >=32MHz for correct operation of MFCLK. + * + * @sa DL_SYSCTL_setMCLKDivider + * @sa DL_SYSCTL_getMCLKSource + * @sa DL_SYSCTL_getMCLKFreq + */ +__STATIC_INLINE void DL_SYSCTL_enableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEMFTICK_ENABLE; +} + +/** + * @brief Disable the Medium Frequency Clock (MFCLK) + */ +__STATIC_INLINE void DL_SYSCTL_disableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_USEMFTICK_ENABLE); +} + +/** + * @brief Enable the Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK provides a continuous 4MHz clock to the DAC. + * + * MFPCLK can be sources from either SYSOSC or HFCLK (HFXT or HFCLK_IN). + * + * The DAC does not have a clock selection mux. Its clock source is selected + * by configuring MFPCLK. + * + * @sa DL_SYSCTL_disableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_enableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_MFPCLKEN_ENABLE; +} + +/** + * @brief Disable the Middle Frequency Precision Clock (MFPCLK) + * @sa DL_SYSCTL_enableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_disableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_MFPCLKEN_ENABLE); +} + +/** + * @brief Set the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @param[in] divider The divider of HFCLK for MFPCLK + * One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKDividerForMFPCLK( + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + ((uint32_t) divider << SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS), + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK); +} + +/** + * @brief Get the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @return Returns the divider for HFCLK for MFPCLK + * + * @retval One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER + */ +__STATIC_INLINE DL_SYSCTL_HFCLK_MFPCLK_DIVIDER +DL_SYSCTL_getHFCLKDividerForMFPCLK(void) +{ + uint32_t divider = + (SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK) >> + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS; + + return (DL_SYSCTL_HFCLK_MFPCLK_DIVIDER)(divider); +} + +/** + * @brief Enable the External Clock (CLK_OUT) + * + * CLK_OUT is provided for pushing out digital clocks to external circuits, such + * as an external ADC which does not have its own clock source. + * + * IOMUX setting for CLK_OUT must be configured before using this function. + * + * CLK_OUT has a typical duty cycle of 50% if clock source is HFCLK, SYSPLLOUT1, + * SYSOSC, or LFCLK. If source is MCLK, ULPCLK, or MFCLK, duty cycle is not + * guaranteed to be 50%. + * + * This function performs multiple operations: + * 1) Sets the CLK_OUT source + * 2) Sets the CLK_OUT divider value + * 3) Enables the CLK_OUT divider, which can be disabled by @ref DL_SYSCTL_disableExternalClockDivider + * 4) Enables the CLK_OUT, which can be disabled by @ref DL_SYSCTL_disableExternalClock + * + * @param[in] source The source of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_SOURCE. + * @param[in] divider The divider of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_DIVIDE. + * + * @sa DL_SYSCTL_disableExternalClock + * @sa DL_SYSCTL_disableExternalClockDivider + */ +__STATIC_INLINE void DL_SYSCTL_enableExternalClock( + DL_SYSCTL_CLK_OUT_SOURCE source, DL_SYSCTL_CLK_OUT_DIVIDE divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) divider | (uint32_t) source, + SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK | SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK | + SYSCTL_GENCLKCFG_EXCLKSRC_MASK); + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_EXCLKEN_ENABLE; +} + +/** + * @brief Disable the External Clock (CLK_OUT) + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClock(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_EXCLKEN_ENABLE); +} + +/** + * @brief Disable the External Clock (CLK_OUT) Divider + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClockDivider(void) +{ + SYSCTL->SOCLOCK.GENCLKCFG &= ~(SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE); +} + +/** + * @brief Blocks all asynchronous fast clock requests + * + * To block specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C. + */ +__STATIC_INLINE void DL_SYSCTL_blockAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE; +} + +/** + * @brief Allows all asynchronous fast clock requests + * + * Although this allows all async fast clock requests, individual IPs may still + * be blocking theirs. + * + * To allow specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C, GPIO. + */ +__STATIC_INLINE void DL_SYSCTL_allowAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE); +} + +/** + * @brief Generates an asynchronous fast clock request upon any IRQ request to CPU. + * + * Provides lowest latency interrupt handling regardless of system clock speed. + * Blockable by @ref DL_SYSCTL_blockAllAsyncFastClockRequests + * + * @sa DL_SYSCTL_blockAllAsyncFastClockRequests + */ +__STATIC_INLINE void DL_SYSCTL_enableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE; +} + +/** + * @brief Maintains current system clock speed for IRQ request to CPU. + * + * Latency for interrupt handling will be higher at lower system clock speeds. + */ +__STATIC_INLINE void DL_SYSCTL_disableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE); +} + +/** + * @brief Set the lower SRAM boundary address to act as partition for read-execute + * permission + * + * Specify the lower SRAM partition address to protect the code region of SRAM from + * being written to, and prevent the RW ("data") region of SRAM from being + * used for code execution. + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. This is the default + * value. + * + * The address is set with a 32-byte resolution. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @param[in] address Address to act as the SRAM partition address. Value is + * a valid 32-bit SRAM address. Only address bits [19:5] + * i.e. bit 5 to bit 19 are used for the boundary address + */ +__STATIC_INLINE void DL_SYSCTL_setLowerSRAMBoundaryAddress(uint32_t address) +{ + SYSCTL->SOCLOCK.SRAMBOUNDARY = + (((uint32_t) address) & SYSCTL_SRAMBOUNDARY_ADDR_MASK); +} + +/** + * @brief Set the upper SRAM boundary address to act as partition for read-execute + * permission + * + * Specify the upper SRAM partition address to protect the code region of SRAM from + * being written to, and prevent the RW ("data") region of SRAM from being + * used for code execution. + * The upper SRAM partition address creates the upper partition: + * - Lower partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * If the lower SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. This is the default + * value. + * + * The address is set with a 32-byte resolution. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @param[in] address Address to act as the SRAM partition address. Value is + * a valid 32-bit SRAM address. Only address bits [19:5] + * i.e. bit 5 to bit 19 are used for the boundary address + */ +__STATIC_INLINE void DL_SYSCTL_setUpperSRAMBoundaryAddress(uint32_t address) +{ + SYSCTL->SOCLOCK.SRAMBOUNDARYHIGH = + (((uint32_t) address) & SYSCTL_SRAMBOUNDARYHIGH_ADDR_MASK); +} + +/** + * @brief Get the lower SRAM boundary address + * + * Get the lower SRAM partition address + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. + * + * The address is set with a 32-byte granularity. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @return The SRAM partition address offset from the SRAM base address + * + * @retval Value is range in [0x0, 0x000FFFE0] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getLowerSRAMBoundaryAddress(void) +{ + return (SYSCTL->SOCLOCK.SRAMBOUNDARY); +} + +/** + * @brief Get the upper SRAM boundary address + * + * Get the upper SRAM partition address + * The upper SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * If the lower SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. + * + * The address is set with a 32-byte granularity. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @return The SRAM partition address offset from the SRAM base address + * + * @retval Value is range in [0x0, 0x000FFFE0] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getUpperSRAMBoundaryAddress(void) +{ + return (SYSCTL->SOCLOCK.SRAMBOUNDARYHIGH); +} + +/** + * @brief Set flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @param[in] waitState Desired number of flash wait states. One of + * @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE void DL_SYSCTL_setFlashWaitState( + DL_SYSCTL_FLASH_WAIT_STATE waitState) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) waitState, + SYSCTL_MCLKCFG_FLASHWAIT_MASK); +} + +/** + * @brief Get flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @return Number of flash wait states. One of @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE DL_SYSCTL_FLASH_WAIT_STATE DL_SYSCTL_getFlashWaitState(void) +{ + uint32_t waitState = + SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_FLASHWAIT_MASK; + + return (DL_SYSCTL_FLASH_WAIT_STATE)(waitState); +} + +/** + * @brief Read Frequency Clock Counter (FCC) + * @return 22-bit value of Frequency Clock Counter (FCC) + */ +__STATIC_INLINE uint32_t DL_SYSCTL_readFCC(void) +{ + return (SYSCTL->SOCLOCK.FCC); +} + +/** + * @brief Start Frequency Clock Counter (FCC) + * + * If FCC_IN is already logic high, counting starts immediately. + * When using level trigger, FCC_IN should be low when GO is set, and trigger + * pulse should be sent to FCC_IN after starting FCC. + */ +__STATIC_INLINE void DL_SYSCTL_startFCC(void) +{ + SYSCTL->SOCLOCK.FCCCMD = (SYSCTL_FCCCMD_KEY_VALUE | SYSCTL_FCCCMD_GO_TRUE); +} + +/** + * @brief Returns whether FCC is done capturing + * + * When capture completes, FCCDONE is set by hardware. + * FCCDONE is read-only and is automatically cleared by hardware when a new + * capture is started. + * + * @return Whether FCC is done or not + * @retval true or false (boolean) + */ +__STATIC_INLINE bool DL_SYSCTL_isFCCDone(void) +{ + return (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_FCCDONE_DONE) == + SYSCTL_CLKSTATUS_FCCDONE_DONE; +} + +/** + * @brief Configure the Frequency Clock Counter (FCC) + * + * FCC enables flexible in-system testing and calibration of a variety of oscillators + * and clocks on the device. The FCC counts the number of clock periods seen on the + * selected clock source within a known fixed trigger period (derived from a secondary + * reference source) to provide an estimation of the frequency of the source clock. + * + * @param[in] trigLvl Determines if active high level trigger or rising-edge + * to rising-edge. One of @ref DL_SYSCTL_FCC_TRIG_TYPE. + * @sa DL_SYSCTL_setFCCPeriods must be called to configure + * number of rising-edge to rising-edge periods when + * DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE is selected. + * @param[in] trigSrc Determines which clock source to trigger FCC from. One of + * @ref DL_SYSCTL_FCC_TRIG_SOURCE. + * @param[in] clkSrc Which clock source to capture and measure frequency of. One of + * @ref DL_SYSCTL_FCC_CLOCK_SOURCE. + */ +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc); + +/** + * @brief Sets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * Set the number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @param[in] periods One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE void DL_SYSCTL_setFCCPeriods(DL_SYSCTL_FCC_TRIG_CNT periods) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) periods, + SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK); +} + +/** + * @brief Gets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @return One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT DL_SYSCTL_getFCCPeriods(void) +{ + uint32_t periods = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK; + + return (DL_SYSCTL_FCC_TRIG_CNT)(periods); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in Internal Resistor Mode + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in External Resistor Mode + * + * Used to increase SYSOSC accuracy. An ROSC reference resistor which is suitable + * to meet application accuracy reqiurements must be placed between ROSC pin and + * device ground (VSS). + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + * + * Power consumption of SYSOSC will be marginally higher with FCL enabled due to + * reference current which flows through ROSC. + * Settling time from startup to specified accuracy may also be longer. + * See device-specific datasheet for startup times. + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCLExternalResistor(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE | + SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE); +} + +/** + * @brief Enable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_enableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_ENABLE; +} + +/** + * @brief Disable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_disableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_DISABLE; +} + +/** + * @brief Sets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @param[in] setting One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE void DL_SYSCTL_setVBOOSTConfig(DL_SYSCTL_VBOOST setting) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) setting, + SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK); +} + +/** + * @brief Gets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @return One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE DL_SYSCTL_VBOOST DL_SYSCTL_getVBOOSTConfig(void) +{ + uint32_t setting = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK; + + return (DL_SYSCTL_VBOOST)(setting); +} + +/** + * @brief Return byte that was saved through SHUTDOWN + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * + * @return 8-bit value of Shutdown Storage Byte. + */ +__STATIC_INLINE uint8_t DL_SYSCTL_getShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index) +{ + const volatile uint32_t *pReg = &SYSCTL->SOCLOCK.SHUTDNSTORE0; + + return (uint8_t)( + *(pReg + (uint32_t) index) & SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Save a byte to SHUTDOWN memory + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * @param[in] data 8-bit data to save in memory + */ +__STATIC_INLINE void DL_SYSCTL_setShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index, uint8_t data) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SHUTDNSTORE0 + (uint32_t) index, data, + SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Enable SHUTDOWN IO Release + * + * After shutdown, IO is locked in previous state. + * + * @note Release IO after re-configuring IO to their proper state. + */ +__STATIC_INLINE void DL_SYSCTL_releaseShutdownIO(void) +{ + SYSCTL->SOCLOCK.SHDNIOREL = + (SYSCTL_SHDNIOREL_KEY_VALUE | SYSCTL_SHDNIOREL_RELEASE_TRUE); +} + +/** + * @brief Disable the reset functionality of the NRST pin + * + * Disabling the NRST pin allows the pin to be configured as a GPIO. + * Once disabled, the reset functionality can only be re-enabled by a POR. + * + * @note The register is write-only, so the EXRSTPIN register + * will always appear as "Disabled" in the debugger + */ +__STATIC_INLINE void DL_SYSCTL_disableNRSTPin(void) +{ + SYSCTL->SOCLOCK.EXRSTPIN = + (SYSCTL_EXRSTPIN_KEY_VALUE | SYSCTL_EXRSTPIN_DISABLE_TRUE); +} + +/** + * @brief Disable Serial Wire Debug (SWD) functionality + * + * SWD pins are enabled by default after cold start to allow a debug connection. + * It is possible to disable SWD on these pins to use for other functionality. + * + * @post SWD is disabled, but pins must be re-configured separately. + * + * @note Cannot debug the device after disabling SWD. Only re-enabled by POR. + */ +__STATIC_INLINE void DL_SYSCTL_disableSWD(void) +{ + SYSCTL->SOCLOCK.SWDCFG = + (SYSCTL_SWDCFG_KEY_VALUE | SYSCTL_SWDCFG_DISABLE_TRUE); +} + +/** + * @brief Return byte that is stored in RSTCAUSE. + * + * @return The cause of reset. One of @ref DL_SYSCTL_RESET_CAUSE + */ +__STATIC_INLINE DL_SYSCTL_RESET_CAUSE DL_SYSCTL_getResetCause(void) +{ + uint32_t resetCause = SYSCTL->SOCLOCK.RSTCAUSE & SYSCTL_RSTCAUSE_ID_MASK; + + return (DL_SYSCTL_RESET_CAUSE)(resetCause); +} + +/** + * @brief Set the HFXT startup time + * + * Specify the HFXT startup time in 64us resolution. If the HFCLK startup + * monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time + * expires. + * + * @param[in] startupTime The HFXT startup time to set in ~64us steps. + * Value between [0x0 (~0s), 0xFF (~16.32ms)]. + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTStartupTime(uint32_t startupTime) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, startupTime, + SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Get the HFXT startup time + * + * @return Returns the HFXT startup time in ~64us steps + * + * @retval Value between [0x0 (~0s), 0xFF (~16.32ms)] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getHFXTStartupTime(void) +{ + return (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Set the HFXT frequency range + * + * The high frequency crystal oscillator (HFXT) can be used with standard + * crystals and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * @param[in] range One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTFrequencyRange( + DL_SYSCTL_HFXT_RANGE range) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, ((uint32_t) range), + SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK); +} + +/** + * @brief Get the HFXT frequency range + * + * @return Returns the HFXT frequency range + * + * @retval One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE DL_SYSCTL_HFXT_RANGE DL_SYSCTL_getHFXTFrequencyRange(void) +{ + uint32_t range = + (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK) >> + SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS; + + return (DL_SYSCTL_HFXT_RANGE)(range); +} + +/** + * @brief Enable the HFCLK startup monitor + * + * The HFXT takes time to start after being enabled. A startup monitor is + * provided to indicate to the application software if the HFXT has successfully + * started, at which point the HFCLK can be selected to source a variety of + * system functions. The HFCLK startup monitor also supports checking the + * HFCLK_IN digital clock input for a clock stuck fault. + * + */ +__STATIC_INLINE void DL_SYSCTL_enableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG |= SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE; +} + +/** + * @brief Disable the HFCLK startup monitor + */ +__STATIC_INLINE void DL_SYSCTL_disableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG &= ~(SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK); +} + +/** + * @brief Retrieves the calibration constant of the temperature sensor to be + * used in temperature calculation. + * + * @retval Temperature sensor calibration data + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getTempCalibrationConstant(void) +{ + return DL_FactoryRegion_getTemperatureVoltage(); +} + +/** + * @brief Initializes the Read Execute (RX) Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the read execute protect firewall + * @param[in] endAddr The end address of the read execute protect firewall + * + * @return If the Read Execute Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Initializes the IP Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the IP protect firewall + * @param[in] endAddr The end address of the IP protect firewall + * + * @return If the IP Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Set the address range of the Write Protect Firewall + * + * Set Write Protection starting at 0x0 of flash, for the first + * 32KB at 1KB granularity. + * Setting a bit to 1 enables write protection, and setting a bit to 0 + * allows write. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] addrMask The mask to set the address range for the Write Protect + * Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setWriteProtectFirewallAddrRange( + uint32_t addrMask) +{ + SYSCTL->SECCFG.FWEPROTMAIN = addrMask; +} + +/** + * @brief Get the address range of the Write Protect Firewall + * + * @retval The address range for the Write Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getWriteProtectFirewallAddrRange(void) +{ + return (SYSCTL->SECCFG.FWEPROTMAIN); +} + +/** + * @brief Set the Read Write Protect Firewall for the Flash DATA Bank + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] protectionType The type of protection to set for the DATA Bank. + * One of @ref DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL + */ +__STATIC_INLINE void DL_SYSCTL_setDATABankRWProtectFirewallMode( + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL protectionType) +{ + SYSCTL->SECCFG.FWPROTMAINDATA = (uint32_t) protectionType; +} + +/** + * @brief Get the protection type for the Read Write Protect Firewall for the Flash DATA Bank + * + * @return The protection type for the Read Write Protect Firewall for the Flash DATA Bank + * + * @retval One of @ref DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL + */ +__STATIC_INLINE DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL +DL_SYSCTL_getDATABankRWProtectFirewallMode(void) +{ + return (DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL)( + SYSCTL->SECCFG.FWPROTMAINDATA); +} + +/** + * @brief Set the start address of the Read Execute (RX) Protect Firewall + * + * Set the start of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the read execute protect + * firewall. The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINSTART = + (startAddr & SYSCTL_FRXPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The start address of the read execute protect firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINSTART); +} + +/** + * @brief Set the end address of the Read Execute (RX) Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the read execute protect firewall. + * The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd( + uint32_t endAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINEND = + (endAddr & SYSCTL_FRXPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The end address of the Read Execute Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINEND); +} + +/** + * @brief Set the start address of the IP Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the IP Protect Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINSTART = + (startAddr & SYSCTL_FIPPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the IP Protect Firewall + * + * @return The start address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINSTART); +} + +/** + * @brief Set the end address of the IP Protect firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the IP Protect firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINEND = + (endAddr & SYSCTL_FIPPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the IP Protect Firewall + * + * @return The end address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINEND); +} + +/** + * @brief Enable the policy to allow flash bank swapping + * + * The bank swap policy needs to be configured ahead of any bank swapping or + * firewall configurations. In dual/quad-bank devices, this policy can be set + * to either + * - CSC allows bank swapping + * - CSC does not allow bank swapping + * + * By default, bank swapping is enabled to ensure a high security state if the + * system boot execution was glitched. Defaulting the system as allowing bank + * swapping ensures that firewall protections get mirrored to both flash banks. + * Additionally, when bank swapping is enabled, SYSCTL enforces write-excute + * mutual exclusion across the two banks (or bank-pairs). + * + * @note This is a write-once bit. This bit can only be written to before + * INITDONE. At INITDONE, this bit becomes a read-only bit until next + * BOOTRST. + */ +__STATIC_INLINE void DL_SYSCTL_enableFlashBankSwap(void) +{ + SYSCTL->SECCFG.FLBANKSWPPOLICY &= (~(SYSCTL_FLBANKSWPPOLICY_DISABLE_MASK) | + SYSCTL_FLBANKSWPPOLICY_KEY_VALUE); +} + +/** + * @brief Disable the policy to allow flash bank swapping + * + * The bank swap policy needs to be configured ahead of any bank swapping or + * firewall configurations. In dual/quad-bank devices, this policy can be set + * to either + * - CSC allows bank swapping + * - CSC does not allow bank swapping + * + * By default, bank swapping is enabled to ensure a high security state if the + * system boot execution was glitched. Defaulting the system as allowing bank + * swapping ensures that firewall protections get mirrored to both flash banks. + * Additionally, when bank swapping is enabled, SYSCTL enforces write-excute + * mutual exclusion across the two banks (or bank-pairs). + * + * @note This is a write-once bit. This bit can only be written to before + * INITDONE. At INITDONE, this bit becomes a read-only bit until next + * BOOTRST. + */ +__STATIC_INLINE void DL_SYSCTL_disableFlashBankSwap(void) +{ + SYSCTL->SECCFG.FLBANKSWPPOLICY = (SYSCTL_FLBANKSWPPOLICY_DISABLE_TRUE | + SYSCTL_FLBANKSWPPOLICY_KEY_VALUE); +} + +/** + * @brief Perform bank swap and execute from the Upper Flash Bank + * + * The upper physical bank maps to logical 0x0, and gets RX permission. + * The lower physical bank gets RW permission. + * + * @note This bit can only be written to before INITDONE. At INITDONE, this bit + * becomes a read-only bit until next BOOTRST. + * + * @pre DL_SYSCTL_enableFlashBankSwap + */ +__STATIC_INLINE void DL_SYSCTL_executeFromUpperFlashBank(void) +{ + SYSCTL->SECCFG.FLBANKSWP |= + (SYSCTL_FLBANKSWP_USEUPPER_ENABLE | SYSCTL_FLBANKSWP_KEY_VALUE); +} + +/** + * @brief Perform bank swap and execute from the Lower Flash Bank + * + * The lower physical bank maps to logical 0x0, and gets RX permission. + * The upper physical bank gets RW permission. + * + * @note This bit can only be written to before INITDONE. At INITDONE, this bit + * becomes a read-only bit until next BOOTRST. + * + * @pre DL_SYSCTL_enableFlashBankSwap + */ +__STATIC_INLINE void DL_SYSCTL_executeFromLowerFlashBank(void) +{ + SYSCTL->SECCFG.FLBANKSWP &= + (~(SYSCTL_FLBANKSWP_USEUPPER_MASK) | SYSCTL_FLBANKSWP_KEY_VALUE); +} + +/** + * @brief Enable Read Execute (RX) Protect Firewall + * + * Enables the Read Execute Protect Firewall before INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableReadExecuteProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_FLRXPROT_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable IP Protect Firewall + * + * Enables the IP Protect Firewall before INITDONE. After INITDONE, + * this configuration gets locked until the next BOOTRST. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableIPProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_SECSTATUS_FLIPPROT_ENABLED | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable SRAM Boundary Lock + * + * When SRAM Boundary Lock is enabled, the SRAMBOUNDARY register is only + * writeable only until INITDONE. After INITDONE, the SRAMBOUNDARY register + * cannot be written. + * + * When disabled, the SRAMBOUNDARY register is writeable throughout the + * application, even after INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + * + * @sa DL_SYSCTL_setSRAMBoundaryAddress + */ +__STATIC_INLINE void DL_SYSCTL_enableSRAMBoundaryLock(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Checks if INITDONE has been issued by the CSC + * + * @return Whether INITDONE has been issued or not + * + * @retval true If INITDONE has been issued + * @retval false If INITDONE has not been issued + */ +__STATIC_INLINE bool DL_SYSCTL_isINITDONEIssued(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_INITDONE_YES) == + SYSCTL_SECSTATUS_INITDONE_YES); +} + +/** + * @brief Checks if Customer Startup Code (CSC) exists in system + * + * @return Whether CSC exists in system + * + * @retval true If CSC exists in system + * @retval false If CSC does not exist in system + */ +__STATIC_INLINE bool DL_SYSCTL_ifCSCExists(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_CSCEXISTS_YES) == + SYSCTL_SECSTATUS_CSCEXISTS_YES); +} + +/** + * @brief Checks if Read Execute (RX) Protect Firewall is enabled + * + * @return Whether Read Execute Protect Firewall is enabled + * + * @retval true If Read Execute Protect Firewall is enabled + * @retval false If Read Execute Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isReadExecuteProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLRXPROT_ENABLED) == + SYSCTL_SECSTATUS_FLRXPROT_ENABLED); +} + +/** + * @brief Checks if IP Protect Firewall is enabled + * + * @return Whether IP Protect Firewall is enabled + * + * @retval true If IP Protect Firewall is enabled + * @retval false If IP Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isIPProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLIPPROT_ENABLED) == + SYSCTL_SECSTATUS_FLIPPROT_ENABLED); +} + +/** + * @brief Checks if SRAM Boundary Lock is enabled + * + * @return Whether SRAM Boundary Lock is enabled + * + * @retval true If SRAM Boundary Lock is enabled + * @retval false If SRAM Boundary Lock is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSRAMBoundaryLocked(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED) == + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED); +} + +/** + * @brief Checks if Flash Bank swapping is enabled + * + * @return Whether Flash Bank swap is enabled + * + * @retval true If Flash Bank swap is enabled + * @retval false If Flash Bank swap is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isFlashBankSwapEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & + SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED) == + SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED); +} + +/** + * @brief Checks if executing from upper flash bank + * + * @return Whether executing from upper flash bank + * + * @retval true If executing from upper flash bank + * @retval false If not executing from upper flash bank + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromUpperFlashBank(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLBANKSWP_MASK) == + SYSCTL_SECSTATUS_FLBANKSWP_MASK); +} + +/** + * @brief Checks if executing from lower flash bank + * + * @return Whether executing from lower flash bank + * + * @retval true If executing from lower flash bank + * @retval false If not executing from lower flash bank + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromLowerFlashBank(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLBANKSWP_MASK) != + SYSCTL_SECSTATUS_FLBANKSWP_MASK); +} + +/** + * @brief Indicate that INIT is done + * + * After INITDONE is issued, the security configuration is locked and enforced. + * A SYSRST will occur, restarting startup code execution, and the main + * application is launched. + * + * There is no hardware support to enforce a timeout if INITDONE is not issued + * in a reasonable period of time. It is recommended that the CSC use a + * watchdog to ensure that INITDONE is issued in a timely manner. + */ +__STATIC_INLINE void DL_SYSCTL_issueINITDONE(void) +{ + SYSCTL->SECCFG.INITDONE |= + (SYSCTL_INITDONE_PASS_TRUE | SYSCTL_INITDONE_KEY_VALUE); +} + +/** + * @brief Set the power level for SRAM Bank 1 when in RUN mode + * + * @param[in] powerLevel The power level to set SRAM Bank 1 to when in RUN mode. + * One of @ref DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE + * + */ +__STATIC_INLINE void DL_SYSCTL_setSRAMBank1PowerLevelInRUN( + DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE powerLevel) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SRAMCFG, + ((uint32_t) powerLevel | SYSCTL_SRAMCFG_KEY_VALUE), + (SYSCTL_SRAMCFG_BANKOFF1_MASK | SYSCTL_SRAMCFG_KEY_MASK)); +} + +/** + * @brief Get the power level SRAM Bank 1 power when in RUN mode + * + * @return The power level of SRAM Bank 1 when in RUN mode + * + * @retval One of @ref DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE + */ +__STATIC_INLINE DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE +DL_SYSCTL_getSRAMBank1PowerLevelInRUN(void) +{ + uint32_t powerLevel = + SYSCTL->SOCLOCK.SRAMCFG & SYSCTL_SRAMCFG_BANKOFF1_MASK; + return (DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_RUN_MODE)(powerLevel); +} + +/** + * @brief Set the power level for SRAM Bank 1 when in STOP mode + * + * @param[in] powerLevel The power level to set SRAM Bank 1 to when in STOP mode + * One of @ref DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE + * + */ +__STATIC_INLINE void DL_SYSCTL_setSRAMBank1PowerLevelInSTOP( + DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE powerLevel) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SRAMCFG, + (uint32_t)(powerLevel | SYSCTL_SRAMCFG_KEY_VALUE), + (SYSCTL_SRAMCFG_BANKSTOP1_MASK | SYSCTL_SRAMCFG_KEY_MASK)); +} + +/** + * @brief Get the power level SRAM Bank 1 power when in STOP mode + * + * @return The power level of SRAM Bank 1 when in STOP mode + * + * @retval One of @ref DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE + */ +__STATIC_INLINE DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE +DL_SYSCTL_getSRAMBank1PowerLevelInSTOP(void) +{ + uint32_t powerLevel = + SYSCTL->SOCLOCK.SRAMCFG & SYSCTL_SRAMCFG_BANKSTOP1_MASK; + return (DL_SYSCTL_SRAM_BANK1_POWER_LEVEL_STOP_MODE)(powerLevel); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dl_m0p_dl_sysctl_sysctl__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g511x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g511x.c new file mode 100644 index 0000000..d503729 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g511x.c @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G511X) + +#include +#include + +void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config) +{ + /* PLL configurations are retained in lower reset levels. Set default + * behavior of disabling the PLL to keep a consistent behavior regardless + * of reset level. */ + DL_SYSCTL_disableSYSPLL(); + + /* Check that SYSPLL is disabled before configuration */ + while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) != + (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) { + ; + } + + // set SYSPLL reference clock + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, + ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK); + + // set predivider PDIV (divides reference clock) + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv), + SYSCTL_SYSPLLCFG1_PDIV_MASK); + + // save CPUSS CTL state and disable the cache + uint32_t ctlTemp = DL_CORE_getInstructionConfig(); + DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED, + DL_CORE_LITERAL_CACHE_ENABLED); + + // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq + SYSCTL->SOCLOCK.SYSPLLPARAM0 = + *(volatile uint32_t *) ((uint32_t) config->inputFreq); + SYSCTL->SOCLOCK.SYSPLLPARAM1 = + *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4); + + // restore CPUSS CTL state + CPUSS->CTL = ctlTemp; + + // set feedback divider QDIV (multiplies to give output frequency) + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, + ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) & + SYSCTL_SYSPLLCFG1_QDIV_MASK), + SYSCTL_SYSPLLCFG1_QDIV_MASK); + + // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0 + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, + (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) | + ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) | + ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) | + config->enableCLK2x | config->enableCLK1 | config->enableCLK0 | + (uint32_t) config->sysPLLMCLK), + (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK | + SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK | + SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK)); + + // enable SYSPLL + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE; + + // wait until SYSPLL startup is stabilized + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) { + ; + } +} + +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG, + ((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) | + (uint32_t) config->xt1Drive, + (SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK)); + // start the LFXT oscillator + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE); + // wait until LFXT oscillator is stable + // if it does not stabilize, check the hardware/IOMUX settings + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_LFXT_GOOD) { + ; + } + if (config->monitor) { + // set the LFCLK monitor + SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE; + } + + // switch LFCLK source from LFOSC to LFXT + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE); +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) +{ + if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled + DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } else { + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify LFCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void) +{ + // Only one should have been set, but clear both because unknown incoming state + // Clear SYSOSCCFG.DISABLE to get SYSOSC running again + // Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source) +{ + // Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN) + // Selected desired HSCLK source + DL_SYSCTL_setHSCLKSource(source); + + // Verify HSCLK source is valid + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) { + ; + } + + // Switch MCLK to HSCLK + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify HSCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void) +{ + // Switch MCLK to SYSOSC + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + DL_SYSCTL_setHFXTFrequencyRange(range); + /* Set startup time to ~0.512ms based on TYP datasheet recommendation */ + DL_SYSCTL_setHFXTStartupTime(8); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + DL_SYSCTL_setHFXTFrequencyRange(range); + DL_SYSCTL_setHFXTStartupTime(startupTime); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + + if (monitorEnable == true) { + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ( + (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } + } else { + DL_SYSCTL_disableHFCLKStartupMonitor(); + } +} + +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc, + SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK | + SYSCTL_GENCLKCFG_FCCSELCLK_MASK); +} + +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void) +{ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy = + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED; + + // Check if SLEEP is enabled + if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) == + SYSCTL_MCLKCFG_USELFCLK_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void) +{ + DL_SYSCTL_POWER_POLICY_STOP policy = + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) == + SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_STOP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void) +{ + DL_SYSCTL_POWER_POLICY_STANDBY policy = + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) == + SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STANDBY1; + } else { + policy = DL_SYSCTL_POWER_POLICY_STANDBY0; + } + } + return policy; +} + +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableReadExecuteProtectFirewall(); + status = true; + } + return status; +} + +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableIPProtectFirewall(); + status = true; + } + return status; +} + +void DL_SYSCTL_configUSBFLL(DL_SYSCTL_USBFLL_REFERENCE refSource) +{ + /* Disable USBFLL before any configuration is done */ + DL_SYSCTL_disableUSBFLL(); + + /* Check that USBFLL is disabled before configuration */ + while ((SYSCTL->SOCLOCK.USBFLLCTL & SYSCTL_USBFLLCTL_FLLEN_MASK) != + SYSCTL_USBFLLCTL_FLLEN_FALSE) { + ; + } + + /* Configuring USBFLL reference source */ + DL_Common_updateReg(&SYSCTL->SOCLOCK.USBFLLCTL, ((uint32_t) refSource), + SYSCTL_USBFLLCTL_REFSEL_MASK); + + /* Enabling USB oscillator clock */ + SYSCTL->SOCLOCK.USBFLLCTL |= (SYSCTL_USBFLLCTL_CLKEN_TRUE); + + /* Polling for completion of USB oscillator initializiation */ + while ((SYSCTL->SOCLOCK.USBFLLSTAT & SYSCTL_USBFLLSTAT_CLKRDY_MASK) != + SYSCTL_USBFLLSTAT_CLKRDY_TRUE) + ; + + /* Enabling USBFLL */ + SYSCTL->SOCLOCK.USBFLLCTL |= SYSCTL_USBFLLCTL_FLLEN_TRUE; +} + +#endif /* DeviceFamily_PARENT_MSPM0G511X */ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g511x.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g511x.h new file mode 100644 index 0000000..2c65782 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g511x.h @@ -0,0 +1,3327 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_sysctl_mspm0g511x.h + * @brief System Control (SysCtl) + * @defgroup SYSCTL_mspm0g511x mspm0g511x System Control (SYSCTL) + * + * @anchor ti_dl_m0p_mspm0g511x_dl_sysctl_Overview + * # Overview + * + * The System Control (SysCtl) module enables control over system wide + * settings like clocks and power management. + * + *
+ * + ****************************************************************************** + */ +/** @addtogroup SYSCTL_mspm0g511x + * @{ + */ +#ifndef ti_dl_m0p_dl_sysctl_sysctl__include +#define ti_dl_m0p_dl_sysctl_sysctl__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_SYSCTL_RESET + * @{ + */ +/*! + * @brief Perform a SYSRST + * + * This issues a SYSRST (CPU plus peripherals only) + */ + #define DL_SYSCTL_RESET_SYSRST (SYSCTL_RESETLEVEL_LEVEL_CPU) + +/*! + * @deprecated This API is deprecated. Please refer to @ref DL_SYSCTL_RESET_SYSRST. + */ + #define DL_SYSCTL_RESET_CPU (DL_SYSCTL_RESET_SYSRST) + +/*! + * @brief Perform a Boot reset + * + * This triggers execution of the device boot configuration routine and resets + * the majority of the core logic while also power cycling the SRAM + */ + #define DL_SYSCTL_RESET_BOOT (SYSCTL_RESETLEVEL_LEVEL_BOOT) + +/*! + * @brief Perform a POR reset + * + * This performas a POR reset which is a complete device reset + */ + #define DL_SYSCTL_RESET_POR (SYSCTL_RESETLEVEL_LEVEL_POR) + +/*! + * @brief Perform system reset and exit bootloader to the application + */ + #define DL_SYSCTL_RESET_BOOTLOADER_EXIT \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT) + + /*! + * @brief Perform system reset and run bootloader + */ + #define DL_SYSCTL_RESET_BOOTLOADER_ENTRY \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY) + + +/** @addtogroup DL_SYSCTL_NMI + * @{ + */ +/*! @brief Non-maskable interrupt for SRAM Double Error Detect */ +#define DL_SYSCTL_NMI_SRAM_DED (SYSCTL_NMIISET_SRAMDED_SET) +/*! @brief Non-maskable interrupt for Flash Double Error Detect */ +#define DL_SYSCTL_NMI_FLASH_DED (SYSCTL_NMIISET_FLASHDED_SET) +/*! @brief Non-maskable interrupt for LFCLK Monitor Fail */ +#define DL_SYSCTL_NMI_LFCLK_FAIL (SYSCTL_NMIISET_LFCLKFAIL_SET) +/*! @brief Non-maskable interrupt for Watchdog 1 Fault */ +#define DL_SYSCTL_NMI_WWDT1_FAULT (SYSCTL_NMIISET_WWDT1_SET) +/*! @brief Non-maskable interrupt for Watchdog 0 Fault */ +#define DL_SYSCTL_NMI_WWDT0_FAULT (SYSCTL_NMIISET_WWDT0_SET) +/*! @brief Non-maskable interrupt for early BOR */ +#define DL_SYSCTL_NMI_BORLVL (SYSCTL_NMIISET_BORLVL_SET) +/** @}*/ + +/** @addtogroup DL_SYSCTL_INTERRUPT + * @{ + */ +/*! @brief Low Frequency Oscillator is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFOSC_GOOD (SYSCTL_IMASK_LFOSCGOOD_ENABLE) +/*! @brief Analog clocking consistency error */ +#define DL_SYSCTL_INTERRUPT_ANALOG_CLOCK_ERROR (SYSCTL_IMASK_ANACLKERR_ENABLE) +/*! @brief Flash Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_FLASH_SEC (SYSCTL_IMASK_FLASHSEC_ENABLE) + +/*! @brief SRAM Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_SRAM_SEC (SYSCTL_IMASK_SRAMSEC_ENABLE) + +/*! @brief Low Frequency Crystal is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFXT_GOOD (SYSCTL_IMASK_LFXTGOOD_ENABLE) +/*! @brief High Frequency Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HFCLK_GOOD (SYSCTL_IMASK_HFCLKGOOD_ENABLE) +/*! @brief System PLL is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_SYSPLL_GOOD (SYSCTL_IMASK_SYSPLLGOOD_ENABLE) +/*! @brief High Speed Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HSCLK_GOOD (SYSCTL_IMASK_HSCLKGOOD_ENABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_CLK_STATUS + * @{ + */ +/*! @brief Error with Anacomp High Speed CP Clock Generation - SYSOSC must not + * run at 4MHz */ +#define DL_SYSCTL_CLK_STATUS_ANACOMP_ERROR (SYSCTL_CLKSTATUS_ACOMPHSCLKERR_TRUE) +/*! @brief Error with OPAMP Clock Generation */ +#define DL_SYSCTL_CLK_STATUS_OPAMP_ERROR (SYSCTL_CLKSTATUS_OPAMPCLKERR_TRUE) +/*! @brief Writes to SYSPLLCFG0-1, SYSPLLPARAM0-1 are blocked */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_SYSPLLBLKUPD_TRUE) +/*! @brief Writes to HFCLKCLKCFG are blocked */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE) +/*! @brief SYSOSC Frequency Correcting Loop Mode ON */ +#define DL_SYSCTL_CLK_STATUS_FCL_ON (SYSCTL_CLKSTATUS_FCLMODE_ENABLED) +/*! @brief Clock Fail for LFXT or EXLF clock source */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_FAIL (SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE) +/*! @brief High Speed Clock Good */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_GOOD (SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE) +/*! @brief High Speed Clock Stuck Fault */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_FAULT (SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE) +/*! @brief SYSPLL is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_OFF (SYSCTL_CLKSTATUS_SYSPLLOFF_TRUE) +/*! @brief HFCLKs is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_OFF (SYSCTL_CLKSTATUS_HFCLKOFF_TRUE) +/*! @brief All PLLs, HFCLKs are OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_OFF (SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE) +/*! @brief LFOSC is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFOSC_GOOD (SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE) +/*! @brief LFXT is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFXT_GOOD (SYSCTL_CLKSTATUS_LFXTGOOD_TRUE) +/*! @brief SYSTEM PLL ON */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD (SYSCTL_CLKSTATUS_SYSPLLGOOD_TRUE) +/*! @brief High Frequency Clock ON */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_GOOD (SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE) +/*! @brief MCLK now sourced from HSCLK, otherwise SYSOSC */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK (SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK) +/*! @brief MCLK now sourced from LFCLK */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK \ + (SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK) +/*! @brief Analog clocking error */ +#define DL_SYSCTL_CLK_STATUS_ANALOG_CLOCK_ERROR \ + (SYSCTL_CLKSTATUS_ANACLKERR_TRUE) +/*! @brief Frequency Clock Counter (FCC) done */ +#define DL_SYSCTL_CLK_STATUS_FCC_DONE (SYSCTL_CLKSTATUS_FCCDONE_DONE) +/*! @brief = LFCLK sourced from the LFXT (crystal) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_LFXT (SYSCTL_CLKSTATUS_LFCLKMUX_LFXT) +/*! @brief = LFCLK sourced from LFCLK_IN (external digital clock input) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_EXLF (SYSCTL_CLKSTATUS_LFCLKMUX_EXLF) +/*! @brief = SYSOSC is at low frequency (4MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_4MHZ (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M) +/*! @brief = SYSOSC is at the user-trimmed frequency (16 or 24MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_USERTRIM_FREQ \ + (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER) +/*! @brief = HSCLK current sourced from the HFCLK */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_SOURCE_HFCLK \ + (SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK) +/** @}*/ + +/** @addtogroup DL_SYSCTL_STATUS + * @{ + */ + +/*! @brief IO is locked due to SHUTDOWN */ +#define DL_SYSCTL_STATUS_SHUTDOWN_IO_LOCK_TRUE \ + (SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE) +/*! @brief User has disabled external reset pin */ +#define DL_SYSCTL_STATUS_EXT_RESET_PIN_DISABLED \ + (SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE) +/*! @brief User has disabled SWD port */ +#define DL_SYSCTL_STATUS_SWD_DISABLED (SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE) + +/*! @brief PMU IFREF good */ +#define DL_SYSCTL_STATUS_PMU_IFREF_GOOD (SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE) +/*! @brief VBOOST (Analog Charge Pump) started up properly */ +#define DL_SYSCTL_STATUS_VBOOST_GOOD (SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE) +/*! @brief Brown Out Reset event status indicator */ +#define DL_SYSCTL_STATUS_BOR_EVENT (SYSCTL_SYSSTATUS_BORLVL_TRUE) +/*! @brief MCAN0 ready */ +#define DL_SYSCTL_STATUS_MCAN0_READY (SYSCTL_SYSSTATUS_MCAN0READY_TRUE) +/*! @brief Double Error Detect on Flash */ +#define DL_SYSCTL_STATUS_FLASH_DED (SYSCTL_SYSSTATUS_FLASHDED_TRUE) +/*! @brief Single Error Correction on Flash */ +#define DL_SYSCTL_STATUS_FLASH_SEC (SYSCTL_SYSSTATUS_FLASHSEC_TRUE) +/*! @brief Current Brown Out Reset minimum level */ +#define DL_SYSCTL_STATUS_BOR_LEVEL0 \ + (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN) +/*! @brief Current Brown Out Reset level 1 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL1 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1) +/*! @brief Current Brown Out Reset level 2 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL2 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2) +/*! @brief Current Brown Out Reset level 3 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL3 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK2X + * @{ + */ +/*! @brief Enable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_ENABLE) + +/*! @brief Disable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK1 + * @{ + */ +/*! @brief Enable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_ENABLE) + +/*! @brief Disable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK0 + * @{ + */ +/*! @brief Enable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_ENABLE) + +/*! @brief Disable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_DISABLE) +/** @}*/ + +/* clang-format on */ + +/*! @enum DL_SYSCTL_SYSPLL_MCLK */ +typedef enum { + /*! Use PLL CLK2x as source for MCLK */ + DL_SYSCTL_SYSPLL_MCLK_CLK2X = SYSCTL_SYSPLLCFG0_MCLK2XVCO_ENABLE, + /*! Use PLL CLK0 as source for MCLK */ + DL_SYSCTL_SYSPLL_MCLK_CLK0 = SYSCTL_SYSPLLCFG0_MCLK2XVCO_DISABLE, +} DL_SYSCTL_SYSPLL_MCLK; + +/*! @enum DL_SYSCTL_SYSPLL_REF */ +typedef enum { + /*! Use SYSOSC as input source for SYSPLL */ + DL_SYSCTL_SYSPLL_REF_SYSOSC = SYSCTL_SYSPLLCFG0_SYSPLLREF_SYSOSC, + /*! Use HFCLK as input source for SYSPLL */ + DL_SYSCTL_SYSPLL_REF_HFCLK = SYSCTL_SYSPLLCFG0_SYSPLLREF_HFCLK, +} DL_SYSCTL_SYSPLL_REF; + +/*! @enum DL_SYSCTL_SYSPLL_PDIV */ +typedef enum { + /*! Predivide input reference freq to PLL feedback loop by 1 */ + DL_SYSCTL_SYSPLL_PDIV_1 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV1, + /*! Predivide input reference freq to PLL feedback loop by 2 */ + DL_SYSCTL_SYSPLL_PDIV_2 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV2, + /*! Predivide input reference freq to PLL feedback loop by 4 */ + DL_SYSCTL_SYSPLL_PDIV_4 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV4, + /*! Predivide input reference freq to PLL feedback loop by 8 */ + DL_SYSCTL_SYSPLL_PDIV_8 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV8, +} DL_SYSCTL_SYSPLL_PDIV; + +/** @enum DL_SYSCTL_SYSPLL_INPUT_FREQ */ +typedef enum { + /*! PLL feedback loop input clock frequency [4MHz, 8MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_4_8_MHZ = 0x41C4001C, + /*! PLL feedback loop input clock frequency [8MHz, 16MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ = 0x41C40024, + /*! PLL feedback loop input clock frequency [16MHz, 32MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ = 0x41C4002C, + /*! PLL feedback loop input clock frequency [32MHz, 48MHz] */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ = 0x41C40034, +} DL_SYSCTL_SYSPLL_INPUT_FREQ; + +/*! @brief Configuration struct for @ref DL_SYSCTL_configSYSPLL. */ +typedef struct { + /*! Output divider for CLK2x. [0x0,0xF,0x1] => [/1,/16,1] */ + uint32_t rDivClk2x; + /*! Output divider for CLK1. [0x0,0xF,0x1] => [/2,/32,2] */ + uint32_t rDivClk1; + /*! Output divider for CLK0. [0x0,0xF,0x1] => [/2,/32,2] */ + uint32_t rDivClk0; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK2X */ + uint32_t enableCLK2x; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK1 */ + uint32_t enableCLK1; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK0 */ + uint32_t enableCLK0; + /*! Select which PLL output to use as source for MCLK. @ref DL_SYSCTL_SYSPLL_MCLK */ + DL_SYSCTL_SYSPLL_MCLK sysPLLMCLK; + /*! SYSPLL reference clock source. @ref DL_SYSCTL_SYSPLL_REF */ + DL_SYSCTL_SYSPLL_REF sysPLLRef; + /*! PLL feedback clock divider. [0x01,0x7E,1] => [/2,/127,1] */ + uint32_t qDiv; + /*! PLL reference clock divider. @ref DL_SYSCTL_SYSPLL_PDIV */ + DL_SYSCTL_SYSPLL_PDIV pDiv; + /*! PLL feedback loop input clock frequency. Affects startup time and power consumption. @ref DL_SYSCTL_SYSPLL_INPUT_FREQ */ + DL_SYSCTL_SYSPLL_INPUT_FREQ inputFreq; +} DL_SYSCTL_SYSPLLConfig; + +/*! @enum DL_SYSCTL_NMI_IIDX */ +typedef enum { + /*! @brief NMI interrupt index for SRAM Double Error Detect */ + DL_SYSCTL_NMI_IIDX_SRAM_DED = SYSCTL_NMIIIDX_STAT_SRAMDED, + /*! @brief NMI interrupt index for Flash Double Error Detect */ + DL_SYSCTL_NMI_IIDX_FLASH_DED = SYSCTL_NMIIIDX_STAT_FLASHDED, + /*! @brief NMI interrupt index for LFCLK Monitor Fail */ + DL_SYSCTL_NMI_IIDX_LFCLK_FAIL = SYSCTL_NMIIIDX_STAT_LFCLKFAIL, + /*! @brief NMI interrupt index for Watchdog 1 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT1_FAULT = SYSCTL_NMIIIDX_STAT_WWDT1, + /*! @brief NMI interrupt index for Watchdog 0 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT0_FAULT = SYSCTL_NMIIIDX_STAT_WWDT0, + /*! @brief NMI interrupt index for early BOR */ + DL_SYSCTL_NMI_IIDX_BORLVL = SYSCTL_NMIIIDX_STAT_BORLVL, + /*! @brief NMI interrupt index for no interrupt pending */ + DL_SYSCTL_NMI_IIDX_NO_INT = SYSCTL_NMIIIDX_STAT_NO_INTR, +} DL_SYSCTL_NMI_IIDX; + +/** @}*/ + +/*! @enum DL_SYSCTL_IIDX */ +typedef enum { + /*! @brief Low Frequency Oscillator is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFOSC_GOOD = SYSCTL_IIDX_STAT_LFOSCGOOD, + /*! @brief Analog clocking consistency error */ + DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR = SYSCTL_IIDX_STAT_ANACLKERR, + /*! @brief Flash Single Error Correct */ + DL_SYSCTL_IIDX_FLASH_SEC = SYSCTL_IIDX_STAT_FLASHSEC, + + /*! @brief SRAM Single Error Correct */ + DL_SYSCTL_IIDX_SRAM_SEC = SYSCTL_IIDX_STAT_SRAMSEC, + + /*! @brief Low Frequency Crystal is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFXT_GOOD = SYSCTL_IIDX_STAT_LFXTGOOD, + /*! @brief High Frequency Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HFCLK_GOOD = SYSCTL_IIDX_STAT_HFCLKGOOD, + /*! @brief System PLL is stabilized and ready to use */ + DL_SYSCTL_IIDX_SYSPLL_GOOD = SYSCTL_IIDX_STAT_SYSPLLGOOD, + /*! @brief High Speed Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HSCLK_GOOD = SYSCTL_IIDX_STAT_HSCLKGOOD, +} DL_SYSCTL_IIDX; + +/*! @enum DL_SYSCTL_ERROR_BEHAVIOR */ +typedef enum { + /*! @brief The error event will trigger a SYSRST */ + DL_SYSCTL_ERROR_BEHAVIOR_RESET = 0x0, + /*! @brief The error event will trigger an NMI */ + DL_SYSCTL_ERROR_BEHAVIOR_NMI = 0x1, +} DL_SYSCTL_ERROR_BEHAVIOR; + +/*! @enum DL_SYSCTL_SYSOSC_FREQ */ +typedef enum { + /*! Use 4MHz for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_4M = (SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M), + /*! Use BASE (32MHz) for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_BASE = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE), + /*! User will trim the System Oscillator (SYSOSC) to 16MHz or 24MHz */ + DL_SYSCTL_SYSOSC_FREQ_USERTRIM = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER), +} DL_SYSCTL_SYSOSC_FREQ; + +/** @enum DL_SYSCTL_SYSOSC_USERTRIM_FREQ */ +typedef enum { + /*! Set SYSOSC user trim frequency target to 16MHz */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ_16M = + (SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC16M), + /*! Set SYSOSC user trim frequency target to 24MHz */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ_24M = + (SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC24M), +} DL_SYSCTL_SYSOSC_USERTRIM_FREQ; + +/*! @brief Configuration struct for @ref DL_SYSCTL_configSYSOSCUserTrim. */ +typedef struct { + /*! Frequency Correcting Loop resistor divide value [0x0, 0x1FF] */ + uint32_t rDiv; + /*! Resistor fine trim [0x0, 0xF] */ + uint32_t resistorFine; + /*! Resistor coarse trim [0x0, 0x3F] */ + uint32_t resistorCoarse; + /*! Capacitor trim [0x0, 0x7] */ + uint32_t capacitor; + /*! SYSOSC user trim frequency target */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ freq; +} DL_SYSCTL_SYSOSCUserTrimConfig; + +/** @enum DL_SYSCTL_ULPCLK_DIV */ +typedef enum { + /*! ULPCLK is MCLK */ + DL_SYSCTL_ULPCLK_DIV_1 = (SYSCTL_MCLKCFG_UDIV_NODIVIDE), + /*! ULPCLK is MCLK divided by 2 */ + DL_SYSCTL_ULPCLK_DIV_2 = (SYSCTL_MCLKCFG_UDIV_DIVIDE2), +} DL_SYSCTL_ULPCLK_DIV; + +/** @enum DL_SYSCTL_LFXT_DRIVE_STRENGTH */ +typedef enum { + /*! Lowest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV), + /*! Lower Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWER = (SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV), + /*! Higher Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHER = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV), + /*! Highest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV), +} DL_SYSCTL_LFXT_DRIVE_STRENGTH; + +/*! @brief Configuration struct for @ref DL_SYSCTL_LFCLKConfig. */ +typedef struct { + /*! Enable if CAP is less than 3pF to reduce power consumption */ + bool lowCap; + /*! Enable to use monitor for LFXT, EXLF failure */ + bool monitor; + /*! Drive strength and power consumption option */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH xt1Drive; +} DL_SYSCTL_LFCLKConfig; + +/** @enum DL_SYSCTL_HFXT_RANGE */ +typedef enum { + /*! HFXT frequency range between 4 and 8 MHz */ + DL_SYSCTL_HFXT_RANGE_4_8_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8, + /*! HFXT frequency range between 8.01 and 16 MHz */ + DL_SYSCTL_HFXT_RANGE_8_16_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16, + /*! HFXT frequency range between 16.01 and 32 MHz */ + DL_SYSCTL_HFXT_RANGE_16_32_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32, + /*! HFXT frequency range between 32.01 and 48 MHz */ + DL_SYSCTL_HFXT_RANGE_32_48_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48, +} DL_SYSCTL_HFXT_RANGE; + +/*! @enum DL_SYSCTL_HSCLK_SOURCE */ +typedef enum { + /*! Use SYSPLL as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_SYSPLL = SYSCTL_HSCLKCFG_HSCLKSEL_SYSPLL, + /*! Use HFLK as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_HFCLK = SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK, + /*! Use USBFLL as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_USBFLL = SYSCTL_HSCLKCFG_USBFLL4HSCLK_USBFLL, +} DL_SYSCTL_HSCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MCLK source (default after reset) */ + DL_SYSCTL_MCLK_SOURCE_SYSOSC = SYSCTL_MCLKCFG_USEHSCLK_DISABLE, + /*! Use High Speed Clock (HSCLK) as MCLK source (HFCLK, PLL,...) */ + DL_SYSCTL_MCLK_SOURCE_HSCLK = SYSCTL_MCLKCFG_USEHSCLK_ENABLE, + /*! Use the Low Frequency Clock (LFCLK) as the clock source */ + DL_SYSCTL_MCLK_SOURCE_LFCLK = SYSCTL_MCLKCFG_USELFCLK_ENABLE, +} DL_SYSCTL_MCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_DIVIDER */ +typedef enum { + /*! Disable MCLK divider. Change SYSOSC freq only when MDIV is disabled */ + DL_SYSCTL_MCLK_DIVIDER_DISABLE = 0x0, + /*! Divide MCLK frequency by 2 */ + DL_SYSCTL_MCLK_DIVIDER_2 = 0x1, + /*! Divide MCLK frequency by 3 */ + DL_SYSCTL_MCLK_DIVIDER_3 = 0x2, + /*! Divide MCLK frequency by 4 */ + DL_SYSCTL_MCLK_DIVIDER_4 = 0x3, + /*! Divide MCLK frequency by 5 */ + DL_SYSCTL_MCLK_DIVIDER_5 = 0x4, + /*! Divide MCLK frequency by 6 */ + DL_SYSCTL_MCLK_DIVIDER_6 = 0x5, + /*! Divide MCLK frequency by 7 */ + DL_SYSCTL_MCLK_DIVIDER_7 = 0x6, + /*! Divide MCLK frequency by 8 */ + DL_SYSCTL_MCLK_DIVIDER_8 = 0x7, + /*! Divide MCLK frequency by 9 */ + DL_SYSCTL_MCLK_DIVIDER_9 = 0x8, + /*! Divide MCLK frequency by 10 */ + DL_SYSCTL_MCLK_DIVIDER_10 = 0x9, + /*! Divide MCLK frequency by 11 */ + DL_SYSCTL_MCLK_DIVIDER_11 = 0xA, + /*! Divide MCLK frequency by 12 */ + DL_SYSCTL_MCLK_DIVIDER_12 = 0xB, + /*! Divide MCLK frequency by 13 */ + DL_SYSCTL_MCLK_DIVIDER_13 = 0xC, + /*! Divide MCLK frequency by 14 */ + DL_SYSCTL_MCLK_DIVIDER_14 = 0xD, + /*! Divide MCLK frequency by 15 */ + DL_SYSCTL_MCLK_DIVIDER_15 = 0xE, + /*! Divide MCLK frequency by 16 */ + DL_SYSCTL_MCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_MCLK_DIVIDER; + +/** @enum DL_SYSCTL_CLK_OUT_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC, + /*! Use Ultra Low Power Clock (ULPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_ULPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK, + /*! Use Low Frequency Clock (LFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_LFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK, + /*! Use Middle Frequency Precision Clock (MFPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_MFPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK, + /*! Use High Frequency Clock (HFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_HFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK, + /*! Use System PLL Output 1 (SYSPLLOUT1) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSPLLOUT1 = SYSCTL_GENCLKCFG_EXCLKSRC_SYSPLLOUT1, +} DL_SYSCTL_CLK_OUT_SOURCE; + +/** @enum DL_SYSCTL_CLK_OUT_DIVIDE */ +typedef enum { + /*! Disable the External Clock (CLK_OUT) output divider */ + DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE = SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU, + /*! Divide External Clock (CLK_OUT) output by 2 */ + DL_SYSCTL_CLK_OUT_DIVIDE_2 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2, + /*! Divide External Clock (CLK_OUT) output by 4 */ + DL_SYSCTL_CLK_OUT_DIVIDE_4 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4, + /*! Divide External Clock (CLK_OUT) output by 6 */ + DL_SYSCTL_CLK_OUT_DIVIDE_6 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6, + /*! Divide External Clock (CLK_OUT) output by 8 */ + DL_SYSCTL_CLK_OUT_DIVIDE_8 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8, + /*! Divide External Clock (CLK_OUT) output by 10 */ + DL_SYSCTL_CLK_OUT_DIVIDE_10 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10, + /*! Divide External Clock (CLK_OUT) output by 12 */ + DL_SYSCTL_CLK_OUT_DIVIDE_12 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12, + /*! Divide External Clock (CLK_OUT) output by 14 */ + DL_SYSCTL_CLK_OUT_DIVIDE_14 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14, + /*! Divide External Clock (CLK_OUT) output by 16 */ + DL_SYSCTL_CLK_OUT_DIVIDE_16 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16, +} DL_SYSCTL_CLK_OUT_DIVIDE; + +/** @enum DL_SYSCTL_MFPCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC, + /*! Use High Frequency Clock (HFCLK) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK, +} DL_SYSCTL_MFPCLK_SOURCE; + +/** @enum DL_SYSCTL_HFCLK_MFPCLK_DIVIDER */ +typedef enum { + /*! HFCLK is not divided before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_DISABLE = 0x0, + /*! Divide HFCLK by 2 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_2 = 0x1, + /*! Divide HFCLK by 3 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_3 = 0x2, + /*! Divide HFCLK by 4 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_4 = 0x3, + /*! Divide HFCLK by 5 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_5 = 0x4, + /*! Divide HFCLK by 6 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6 = 0x5, + /*! Divide HFCLK by 7 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_7 = 0x6, + /*! Divide HFCLK by 8 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_8 = 0x7, + /*! Divide HFCLK by 9 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_9 = 0x8, + /*! Divide HFCLK by 10 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_10 = 0x9, + /*! Divide HFCLK by 11 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_11 = 0xA, + /*! Divide HFCLK by 12 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_12 = 0xB, + /*! Divide HFCLK by 13 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_13 = 0xC, + /*! Divide HFCLK by 14 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_14 = 0xD, + /*! Divide HFCLK by 15 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_15 = 0xE, + /*! Divide HFCLK by 16 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_HFCLK_MFPCLK_DIVIDER; + +/** @enum DL_SYSCTL_FCC_TRIG_TYPE */ +typedef enum { + /*! FCC trigger is rising-edge to rising-edge pulse */ + DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE = SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE, + /*! FCC trigger is active-high pulse level */ + DL_SYSCTL_FCC_TRIG_TYPE_LEVEL = SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL, +} DL_SYSCTL_FCC_TRIG_TYPE; + +/** @enum DL_SYSCTL_FCC_TRIG_SOURCE */ +typedef enum { + /*! FCC trigger source is FCC_IN external pin */ + DL_SYSCTL_FCC_TRIG_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN, + /*! FCC trigger source is LFCLK */ + DL_SYSCTL_FCC_TRIG_SOURCE_LFCLK = SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK, +} DL_SYSCTL_FCC_TRIG_SOURCE; + +/** @enum DL_SYSCTL_FCC_CLOCK_SOURCE */ +typedef enum { + /*! FCC clock source to capture is MCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_MCLK = SYSCTL_GENCLKCFG_FCCSELCLK_MCLK, + /*! FCC clock source to capture is SYSOSC */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC, + /*! FCC clock source to capture is HFCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK, + /*! FCC clock source to capture is CLK_OUT */ + DL_SYSCTL_FCC_CLOCK_SOURCE_CLK_OUT = SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK, + /*! FCC clock source to capture is SYSPLLCLK0 */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK0 = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK0, + /*! FCC clock source to capture is SYSPLLCLK1 */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK1 = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK1, + /*! FCC clock source to capture is SYSPLLCLK2X */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK2X = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK2X, + /*! FCC clock source to capture is FCC_IN */ + DL_SYSCTL_FCC_CLOCK_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN, + /*! FCC clock source to capture is USBFLL */ + DL_SYSCTL_FCC_CLOCK_SOURCE_USBFLL = SYSCTL_GENCLKCFG_FCCSELCLK_USBFLL, +} DL_SYSCTL_FCC_CLOCK_SOURCE; + +/** @enum DL_SYSCTL_FCC_TRIG_CNT */ +typedef enum { + /*! One monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_01 = + ((uint32_t) 0 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_02 = + ((uint32_t) 1 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_03 = + ((uint32_t) 2 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_04 = + ((uint32_t) 3 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_05 = + ((uint32_t) 4 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_06 = + ((uint32_t) 5 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_07 = + ((uint32_t) 6 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_08 = + ((uint32_t) 7 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_09 = + ((uint32_t) 8 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Ten monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_10 = + ((uint32_t) 9 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eleven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_11 = + ((uint32_t) 10 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twelve monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_12 = + ((uint32_t) 11 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_13 = + ((uint32_t) 12 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fourteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_14 = + ((uint32_t) 13 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fifteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_15 = + ((uint32_t) 14 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Sixteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_16 = + ((uint32_t) 15 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seventeen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_17 = + ((uint32_t) 16 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eighteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_18 = + ((uint32_t) 17 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nineteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_19 = + ((uint32_t) 18 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_20 = + ((uint32_t) 19 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_21 = + ((uint32_t) 20 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_22 = + ((uint32_t) 21 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_23 = + ((uint32_t) 22 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_24 = + ((uint32_t) 23 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_25 = + ((uint32_t) 24 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_26 = + ((uint32_t) 25 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_27 = + ((uint32_t) 26 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_28 = + ((uint32_t) 27 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_29 = + ((uint32_t) 28 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_30 = + ((uint32_t) 29 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_31 = + ((uint32_t) 30 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_32 = + ((uint32_t) 31 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), +} DL_SYSCTL_FCC_TRIG_CNT; + +/** @enum DL_SYSCTL_VBOOST */ +typedef enum { + /*! VBOOST enabled only when COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONDEMAND = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND, + /*! VBOOST enabled in RUN/SLEEP, and in STOP/STANDBY if COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONACTIVE = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE, + /*! VBOOST enabled in all power modes except SHUTDOWN for fastest startup */ + DL_SYSCTL_VBOOST_ONALWAYS = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS, +} DL_SYSCTL_VBOOST; + +/** @enum DL_SYSCTL_FLASH_WAIT_STATE */ +typedef enum { + /*! 0 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_0 = ((uint32_t) 0x00000000U), + /*! 1 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_1 = ((uint32_t) 0x00000100U), + /*! 2 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_2 = ((uint32_t) 0x00000200U), +} DL_SYSCTL_FLASH_WAIT_STATE; + +/** @enum DL_SYSCTL_POWER_POLICY_RUN_SLEEP */ +typedef enum { + /*! RUN/SLEEP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED = 0x0, + /*! Enable RUN0/SLEEP0 power mode policy. */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP0 = 0x1, + /*! Enable the RUN1/SLEEP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP1 = 0x2, + /*! Enable the RUN2/SLEEP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_RUN_SLEEP; + +/** @enum DL_SYSCTL_POWER_POLICY_STOP */ +typedef enum { + /*! STOP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED = 0x0, + /*! Enable the STOP0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP0 = 0x1, + /*! Enable the STOP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP1 = 0x2, + /*! Enable the STOP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_STOP; + +/** @enum DL_SYSCTL_POWER_POLICY_STANDBY */ +typedef enum { + /*! STANDBY power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED = 0x0, + /*! Enable the STANDBY0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY0 = 0x1, + /*! Enable the STANDBY1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY1 = 0x2, +} DL_SYSCTL_POWER_POLICY_STANDBY; + +/** @enum DL_SYSCTL_BOR_THRESHOLD_LEVEL */ +typedef enum { + /*! BOR0 threshold level. This is the minimum allowed threshold. + * A BOR0- violation will force a re-boot. */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_0 = SYSCTL_BORTHRESHOLD_LEVEL_BORMIN, + /*! BOR1 threshold level. A BOR1- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_1 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1, + /*! BOR2 threshold level. A BOR2- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_2 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2, + /*! BOR3 threshold level. A BOR3- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_3 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3, +} DL_SYSCTL_BOR_THRESHOLD_LEVEL; + +/** @enum DL_SYSCTL_SHUTDOWN_STORAGE_BYTE */ +typedef enum { + /*! Shutdown Storage Byte 0 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_0 = 0x0, + /*! Shutdown Storage Byte 1 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_1 = 0x1, + /*! Shutdown Storage Byte 2 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_2 = 0x2, + /*! Shutdown Storage Byte 3 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_3 = 0x3, +} DL_SYSCTL_SHUTDOWN_STORAGE_BYTE; + +/** @enum DL_SYSCTL_RESET_CAUSE */ +typedef enum { + /*! No Reset Since Last Read */ + DL_SYSCTL_RESET_CAUSE_NO_RESET = SYSCTL_RSTCAUSE_ID_NORST, + /*! (VDD < POR- violation) or (PMU trim parity fault) or (SHUTDNSTOREx parity fault) */ + DL_SYSCTL_RESET_CAUSE_POR_HW_FAILURE = SYSCTL_RSTCAUSE_ID_PORHWFAIL, + /*! NRST pin reset (>1s) */ + DL_SYSCTL_RESET_CAUSE_POR_EXTERNAL_NRST = SYSCTL_RSTCAUSE_ID_POREXNRST, + /*! Software-triggered POR */ + DL_SYSCTL_RESET_CAUSE_POR_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_PORSW, + /*! VDD < BOR- violation */ + DL_SYSCTL_RESET_CAUSE_BOR_SUPPLY_FAILURE = SYSCTL_RSTCAUSE_ID_BORSUPPLY, + /*! Wake from SHUTDOWN */ + DL_SYSCTL_RESET_CAUSE_BOR_WAKE_FROM_SHUTDOWN = + SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN, + /*! Non-PMU trim parity fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_NON_PMU_PARITY_FAULT = + SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY, + /*! Fatal clock fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_CLOCK_FAULT = SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL, + /*! Software-triggered BOOTRST */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_BOOTSW, + /*! NRST pin reset (<1s) */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_EXTERNAL_NRST = + SYSCTL_RSTCAUSE_ID_BOOTEXNRST, + /*! BSL exit */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_EXIT = SYSCTL_RSTCAUSE_ID_SYSBSLEXIT, + /*! BSL entry */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_ENTRY = SYSCTL_RSTCAUSE_ID_SYSBSLENTRY, + /*! WWDT0 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT0_VIOLATION = + SYSCTL_RSTCAUSE_ID_BOOTWWDT0, + /*! WWDT1 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT1_VIOLATION = SYSCTL_RSTCAUSE_ID_SYSWWDT1, + /*! Uncorrectable flash ECC error */ + DL_SYSCTL_RESET_CAUSE_SYSRST_FLASH_ECC_ERROR = + SYSCTL_RSTCAUSE_ID_SYSFLASHECC, + /*! CPULOCK violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_CPU_LOCKUP_VIOLATION = + SYSCTL_RSTCAUSE_ID_SYSCPULOCK, + /*! Debug-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSDBG, + /*! Software-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSSW, + /*! Debug-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUDBG, + /*! Software-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUSW, +} DL_SYSCTL_RESET_CAUSE; + +/** @enum DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL */ +typedef enum { + /*! DATA Bank Read Write Protect Firewall both RW allowed */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_ENABLED = 0x0, + /*! DATA Bank Read Write Protect Firewall read only */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_R_ONLY = 0x1, + /*! DATA Bank Read Write Protect Firewall both RW disabled */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_DISABLED = 0x2, +} DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL; + +/** @enum DL_SYSCTL_USBCLK_SOURCE */ +typedef enum { + /*! Use USB Frequency Lock Loop as USBCLK source */ + DL_SYSCTL_USBCLK_SOURCE_USBFLL = SYSCTL_GENCLKCFG_USBCLKSRC_USBFLLCLK, + /*! Use SYSPLL1 as USBCLK source */ + DL_SYSCTL_USBCLK_SOURCE_PLLCLK1 = SYSCTL_GENCLKCFG_USBCLKSRC_SYSPLLOUT1, +} DL_SYSCTL_USBCLK_SOURCE; + +/** @enum DL_SYSCTL_USBFLL_REFERENCE */ +typedef enum { + /*! Use Start-of-Frame package (SOF) as USBFLL reference source */ + DL_SYSCTL_USBFLL_REFERENCE_SOF = ((uint32_t) 0x00000000U), + /*! Use LFXT as USBFLL reference source */ + DL_SYSCTL_USBFLL_REFERENCE_LFXT = SYSCTL_USBFLLCTL_REFSEL_LFCLK, +} DL_SYSCTL_USBFLL_REFERENCE; + +/** + * @brief Enable sleep on exit + * + * Enables sleep on exit when the CPU moves from handler mode to thread mode. + * By enabling, allows an interrupt driven application to avoid returning to + * an empty main application. + */ +__STATIC_INLINE void DL_SYSCTL_enableSleepOnExit(void) +{ + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; +} + +/** + * @brief Disable sleep on exit + * + * Disables sleep on exit when the CPU moves from handler mode to thread mode. + */ +__STATIC_INLINE void DL_SYSCTL_disableSleepOnExit(void) +{ + SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Check if sleep on exit is enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSleepOnExitEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SLEEPONEXIT_Msk) == SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable send event on pending bit + * + * When enabled, any enabled event and all interrupts (including disabled + * interrupts) can wakeup the processor. + */ +__STATIC_INLINE void DL_SYSCTL_enableEventOnPend(void) +{ + SCB->SCR |= SCB_SCR_SEVONPEND_Msk; +} + +/** + * @brief Disable send event on pending bit + * + * When disabled, only enabled interrupts or events can wake up the processor. + * Disabled interrupts are excluded. + */ +__STATIC_INLINE void DL_SYSCTL_disableEventOnPend(void) +{ + SCB->SCR &= ~(SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Check if send event on pending bit is enabled + * + * @return Returns the enabled status of the send event on pending bit + * + * @retval true Send event on pending bit is enabled + * @retval false Send event on pending bit is disabled + */ +__STATIC_INLINE bool DL_SYSCTL_isEventOnPendEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SEVONPEND_Msk) == SCB_SCR_SEVONPEND_Msk); +} + +/*! + * @brief Change MCLK source + * + * To ensure good clocking behavior, these are the recommended steps for transition. + * Valid sources and destinations: LFCLK, SYSOSC, HSCLK + * + * Depending on current MCLK source, steps to switch to next MCLK source can vary. + * This is a macro that redirects to the different possible transitions. + * + * Only valid for RUN modes. In low power modes, MCLK transitions are handled by hardware. + * + * @note Different transition APIs may require different input parameters + * Transitions between LFCLK and HSCLK requires going through SYSOSC. + * + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK + * @sa DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK + * @sa DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC + */ +#define DL_SYSCTL_setMCLKSource(current, next, ...) \ + DL_SYSCTL_switchMCLKfrom##current##to##next(__VA_ARGS__); + +/** + * @brief Change MCLK source from SYSOSC to LFCLK + * + * @pre If disabling SYSOSC, high speed oscillators (SYSPLL, HFXT...) must be disabled beforehand. + * @post MCLK source is switched to LFCLK, function will busy-wait until confirmed. + * + * @param[in] disableSYSOSC Whether to leave SYSOSC running or not + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC); + +/** + * @brief Change MCLK source from LFCLK to SYSOSC + * + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + */ +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void); + +/** + * @brief Change MCLK source from SYSOSC to HSCLK + * + * @pre The desired HSCLK source is enabled beforehand (SYSPLL, HFXT, HFCLK_IN). + * @post MCLK source is switched to HSCLK, function will busy-wait until confirmed. + * + * @param[in] source Desired high-speed clock source + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source); + +/** + * @brief Change MCLK source from HSCLK to SYSOSC + * + * @pre MCLK is sourced from a valid, running HSCLK source (SYSPLL, HFXT, HFCLK_IN) + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + * + * @note No HSCLK sources are disabled by this function + */ +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void); + +/** + * @brief Configures the USBFLL reference source and enables the USBFLL + * + * @param[in] refSource Desired USBFLL reference source, one of +* @ref DL_SYSCTL_USBFLL_REFERENCE. + */ +void DL_SYSCTL_configUSBFLL(DL_SYSCTL_USBFLL_REFERENCE refSource); + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN0/SLEEP0 + * + * In RUN0, the MCLK and the CPUCLK run from a fast clock source (SYSOSC, + * HFCLK, or SYSPLL). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN0SLEEP0(void) +{ + DL_SYSCTL_setMCLKSource(LFCLK, SYSOSC); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN1/SLEEP1 + * + * In RUN1, the MCLK and the CPUCLK run from LFCLK (at 32kHz) to reduce active + * power, but SYSOSC is left enabled to service analog modules such as an ADC, + * DAC, OPA, or COMP (in HS mode). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN1SLEEP1(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) false); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN2/SLEEP2 + * + * In RUN2, the MCLK and the CPUCLK run from LFCLK (at 32kHz), and SYSOSC is + * completely disabled to save power. This is the lowest power state with + * the CPU running + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @note Since this turns off SYSOSC, HSCLK sources MUST be disabled before calling + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN2SLEEP2(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) true); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Get the RUN/SLEEP mode power policy + * + * Get which RUN/SLEEP power policy has been set. + * + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. + * + * @return Returns the current RUN/SLEEP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_RUN_SLEEP + + */ +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void); + +/** + * @brief Set the STOP mode power policy to STOP0 + * + * In STOP0, the SYSOSC is left running at the current frequency when entering + * STOP mode (either 32MHz, 24MHz, 16MHz, or 4MHz). ULPCLK is always limited + * to 4MHz automatically by hardware, but SYSOSC is not disturbed to support + * consistent operation of analog peripherals such as the ADC, OPA, or COMP. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~( + SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK | SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP1 + * + * In STOP1, the SYSOSC is gear shifted from its current frequency to 4MHz for + * the lowest power consumption in STOP mode with SYSOSC running. SYSOSC and + * ULPCLK both run at 4MHz. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP2 + * + * In STOP2, the SYSOSC is disabled and the ULPCLK is sourced from LFCLK at + * 32kHz. This is the lowest power state in STOP mode. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP2(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK); + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLESTOP_MASK; +} + +/** + * @brief Get the STOP mode power policy + * + * Get which STOP power policy has been set. + * + * @return Returns the current STOP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STOP if a STOP power policy + */ +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void); + +/** + * @brief Set the STANDBY mode power policy to STANDBY0 + * + * In STANDBY0, all PD0 peripherals receive the ULPCLK and LFCLK, and the RTC + * receives RTCCLK. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_STOPCLKSTBY_MASK); +} + +/** + * @brief Set the STANDBY mode power policy to STANDBY1 + * + * In STANDBY1, only TIMG0 and TIMG1 receive ULPCLK/LFCLK. The RTC continues + * to receive RTCCLK. A TIMG0/1 interrupt, RTC interrupt, or ADC trigger in + * STANDBY1 always triggers an asynchronous fast clock request to wake the + * system. Other PD0 peripherals (such as UART, I2C, GPIO, and COMP) can also + * wake the system upon an external event through an asynchronous fast clock + * request, but they are not actively clocked in STANDBY1. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_STOPCLKSTBY_MASK; +} + +/** + * @brief Get the STANDBY mode power policy + * + * Get which STANDBY power policy has been set. + * + * @return Returns the current STANDBY mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STANDBY + */ +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void); + +/** + * @brief Set power policy to SHUTDOWN mode + * + * In SHUTDOWN mode, no clocks are available. The core regulator is completely + * disabled and all SRAM and register contents are lost, with the exception of + * the 4 bytes of general purpose memory in SYSCTL which may be used to store + * state information. The BOR and bandgap circuit are disabled. The device may + * wake up via a wake-up capable IO, a debug connection, or NRST. SHUTDOWN mode + * has the lowest current consumption of any operating mode. Exiting SHUTDOWN + * mode triggers a BOR. + * + * There is only one SHUTDOWN mode policy option: SHUTDOWN. + * + * @post This API does not actually enter SHUTDOWN mode. After using this API + * to enable SHUTDOWN mode, to enter SHUTDOWN mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySHUTDOWN(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_SHUTDOWN; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Set the brown-out reset (BOR) threshold level + * + * Note that this API does NOT activate the BOR threshold. After setting the + * threshold level with this API, call @ref DL_SYSCTL_activateBORThreshold + * to actually activate the new threshold. + * + * During startup, the BOR threshold defaults to BOR0 (the lowet value) to + * ensure the device always starts at the specified VDD minimum. After boot, + * the BOR threshold level can be configured to a different level. When the + * BOR threshold is BOR0, a BOR0- violation always generates a BOR- violation + * signal to SYSCTL, generating a BOR level reset. When the BOR threshold is + * re-configured to BOR1, BOR2, or BOR3 the BOR circuit will generate a SYSCTL + * interrupt rather than asserting a BOR- violation. This may be used to give + * the application an indication that the supply has dropped below a certain + * level without causing a reset. If the BOR is in interrupt mode (threshold + * level of BOR1-3), and VDD drops below the respective BORx- level, an + * interrupt will be generated and the BOR circuit will automatically switch + * the BOR threshold level to BOR0 to ensure that a BOR- violation is + * asserted if VDD drops below BOR0-. + * + * @param[in] thresholdLevel The BOR threshold level to set. + * One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL. + * + * @post DL_SYSCTL_activateBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_setBORThreshold( + DL_SYSCTL_BOR_THRESHOLD_LEVEL thresholdLevel) +{ + SYSCTL->SOCLOCK.BORTHRESHOLD = (uint32_t) thresholdLevel; +} + +/** + * @brief Get the brown-out reset (BOR) threshold level + * + * @return Returns the current BOR threshold level. + * + * @retval One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL + */ +__STATIC_INLINE DL_SYSCTL_BOR_THRESHOLD_LEVEL DL_SYSCTL_getBORThreshold(void) +{ + return (DL_SYSCTL_BOR_THRESHOLD_LEVEL)(SYSCTL->SOCLOCK.BORTHRESHOLD); +} + +/** + * @brief Activate the BOR threshold level + * + * Attempts to change the active BOR mode to the BOR threshold that was set + * via @ref DL_SYSCTL_setBORThreshold. + * + * Setting this bit also clears any prior BOR violation status indications. + * + * After calling this API, the change can be validated by calling + * @ref DL_SYSCTL_getStatus and checking the return value. + * + * @pre DL_SYSCTL_setBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_activateBORThreshold(void) +{ + SYSCTL->SOCLOCK.BORCLRCMD = + SYSCTL_BORCLRCMD_KEY_VALUE | SYSCTL_BORCLRCMD_GO_TRUE; +} + +/** + * @brief Resets the device + * + * Resets the device using the type of reset selected. This function does not + * return, the reset will happen immediately. + * + * @param[in] resetType Type of reset to perform. One of @ref + * DL_SYSCTL_RESET. + */ +__STATIC_INLINE void DL_SYSCTL_resetDevice(uint32_t resetType) +{ + SYSCTL->SOCLOCK.RESETLEVEL = resetType; + SYSCTL->SOCLOCK.RESETCMD = + SYSCTL_RESETCMD_KEY_VALUE | SYSCTL_RESETCMD_GO_TRUE; +} + +/** + * @brief Enable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_enableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK |= interruptMask; +} + +/** + * @brief Disable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_disableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which SYSCTL interrupts are enabled + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are enabled + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterrupts(uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SYSCTL interrupts + * + * Checks if any of the SYSCTL interrupts that were previously enabled are + * pending. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + * + * @sa DL_SYSCTL_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @return The highest priority pending SYSCTL interrupt + * + * @retval One of @ref DL_SYSCTL_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_IIDX DL_SYSCTL_getPendingInterrupt(void) +{ + return (DL_SYSCTL_IIDX)(SYSCTL->SOCLOCK.IIDX); +} + +/** + * @brief Clear pending SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_clearInterruptStatus(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.ICLR = interruptMask; +} + +/** + * @brief Check interrupt flag of any SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_NMI. + * + * @return Which of the requested SYSCTL non-maskable interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_NMI values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.NMIRIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @return The highest priority pending SYSCTL non-maskable interrupt + * + * @retval One of @ref DL_SYSCTL_NMI_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_NMI_IIDX DL_SYSCTL_getPendingNonMaskableInterrupt( + void) +{ + return (DL_SYSCTL_NMI_IIDX)(SYSCTL->SOCLOCK.NMIIIDX); +} + +/** + * @brief Clear pending SYSCTL non-maskable interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_NMI. + */ +__STATIC_INLINE void DL_SYSCTL_clearNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.NMIICLR = interruptMask; +} + +/** + * @brief Set the behavior when a Flash ECC double error detect (DED) occurs + * + * Configures whether a Flash ECC double error detect (DED) will trigger + * a SYSRST or an NMI (non-maskable interrupt). By default, this error will + * trigger a SYSRST. + * + * @param[in] behavior The behavior when a Flash ECC DED error occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setFlashDEDErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a Flash ECC double error detect (DED) occurs + * + * By default, this error will trigger a SYSRST. + * + * @return The behavior when a Flash ECC DED error occurs + * + * 3@retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getFlashDEDErrorBehavior( + void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the behavior when a WWDT0 error occurs + * + * Configures whether a WWDT0 error will trigger a BOOTRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a BOOTRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT0ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT0 error occurs + * + * By default, this error will trigger a BOOTRST. + * + * @return The behavior when a WWDT0 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT0ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the behavior when a WWDT1 error occurs + * + * Configures whether a WWDT1 error will trigger a SYSRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a SYSRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT1ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT1 error occurs + * + * By default, this error will trigger a SYSRST. + * + * @return The behavior when a WWDT1 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT1ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the Main Clock (MCLK) divider (MDIV) + * + * Additionally, can use this function to disable MDIV. MDIV must be disabled + * before changing SYSOSC frequency. + * + * MDIV is not valid if MCLK source is HSCLK. + * MDIV is not used if MCLK source if LFCLK. + * + * @param[in] divider Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is + * HSCLK, a don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE void DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_MDIV_MASK); +} +/** + * @brief Get the Main Clock (MCLK) divider (MDIV) + * + * @return The value of the Main Clock (MCLK) divider (MDIV) + * + * @retval Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is HSCLK, a + * don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE DL_SYSCTL_MCLK_DIVIDER DL_SYSCTL_getMCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_MDIV_MASK; + + return (DL_SYSCTL_MCLK_DIVIDER)(divider); +} + +/** + * @brief Get the source for the Main Clock (MCLK) + * + * @return The source for the Main Clock (MCLK) + * + * @retval One of @ref DL_SYSCTL_MCLK_SOURCE + */ +__STATIC_INLINE DL_SYSCTL_MCLK_SOURCE DL_SYSCTL_getMCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.MCLKCFG & + (SYSCTL_MCLKCFG_USEHSCLK_MASK | SYSCTL_MCLKCFG_USELFCLK_MASK); + + return (DL_SYSCTL_MCLK_SOURCE)(source); +} + +/** + * @brief Set the target frequency of the System Oscillator (SYSOSC) + * + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * + * The System Oscillator (SYSOSC) is an on-chip, accurate, configurable + * oscillator with factory trimmed support for 32MHz (base frequency) and 4MHz + * (low frequency) operation. + * It can also operate at 16MHz or 24MHz by using the + * @ref DL_SYSCTL_configSYSOSCUserTrim function instead. + * + * SYSOSC provides a flexible high-speed clock source for the system in cases + * where the HFXT is either not present or not used. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] freq Target frequency to use for the System Oscillator (SYSOSC). + * @ref DL_SYSCTL_SYSOSC_FREQ_4M or @ref DL_SYSCTL_SYSOSC_FREQ_BASE. + * + * @sa DL_SYSCTL_configSYSOSCUserTrim + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ freq) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, (uint32_t) freq, + SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Trim the System Oscillator (SYSOSC) to 16MHz or 24MHz + * + * The trim values supplied in the config struct must be determined by + * experimentation. Please refer to the "SYSOSC User Trim Procedure" section + * in the CKM Technical Reference Manual. + * Each device must be trimmed individually for accuracy. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] config Pointer to the SYSOSC user trim configuration struct + * @ref DL_SYSCTL_SYSOSCUserTrimConfig. + * + * @sa DL_SYSCTL_setSYSOSCFreq + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_configSYSOSCUserTrim( + const DL_SYSCTL_SYSOSCUserTrimConfig *config) +{ + SYSCTL->SOCLOCK.SYSOSCTRIMUSER = + ((config->rDiv << SYSCTL_SYSOSCTRIMUSER_RDIV_OFS) & + SYSCTL_SYSOSCTRIMUSER_RDIV_MASK) | + ((config->resistorFine << SYSCTL_SYSOSCTRIMUSER_RESFINE_OFS) & + SYSCTL_SYSOSCTRIMUSER_RESFINE_MASK) | + ((config->resistorCoarse << SYSCTL_SYSOSCTRIMUSER_RESCOARSE_OFS) & + SYSCTL_SYSOSCTRIMUSER_RESCOARSE_MASK) | + (config->capacitor << SYSCTL_SYSOSCTRIMUSER_CAP_OFS) | + ((uint32_t) config->freq); + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, + SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER, SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Get the target frequency of the System Oscillator (SYSOSC) + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * This function matches what is input by @ref DL_SYSCTL_setSYSOSCFreq. + * + * @return The target frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getTargetSYSOSCFreq(void) +{ + uint32_t freq = SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_FREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Get the current frequency of the System Oscillator (SYSOSC) + * Current/actual SYSOSC frequency may be different than target/desired SYSOSC + * frequency during gear shift and other operations. + * + * @return The current frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getCurrentSYSOSCFreq(void) +{ + uint32_t freq = + SYSCTL->SOCLOCK.CLKSTATUS & SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Returns status of the different clocks in CKM + * + * @return Full status of all clock selections + * + * @retval Bitwise OR of @ref DL_SYSCTL_CLK_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getClockStatus(void) +{ + return (SYSCTL->SOCLOCK.CLKSTATUS); +} + +/** + * @brief Returns general status of SYSCTL + * + * @return Full status of all general conditions in SYSCTL + * + * @retval Bitwise OR of @ref DL_SYSCTL_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getStatus(void) +{ + return (SYSCTL->SOCLOCK.SYSSTATUS); +} + +/** + * @brief Clear the ECC error bits in SYSSTATUS + * + * The ECC error bits in SYSSTATUS are sticky (they remain set when an ECC + * error occurs even if future reads do not have errors), and can be + * cleared through this API. + */ +__STATIC_INLINE void DL_SYSCTL_clearECCErrorStatus(void) +{ + SYSCTL->SOCLOCK.SYSSTATUSCLR = + (SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR | SYSCTL_SYSSTATUSCLR_KEY_VALUE); +} + +/** + * @brief Configure SYSPLL output frequencies + * + * @pre SYSPLL is disabled (SYSPLLOFF in CLKSTATUS) + * @pre SYSOSC is running at base frequency (32MHz) even if HFCLK is the + * SYSPLL reference + * @post SYSPLL has completed startup and outputs chosen frequencies + * + * @note For practical purposes, it is not required to wait until SYSPLL + * completes startup, but do not go into STOP/STANDBY or use SYSPLL + * until completed. + * + * @param[in] config Pointer to the SYSPLL configuration struct + * @ref DL_SYSCTL_SYSPLLConfig. Elements sysPLLRef, pDiv, and + * inputFreq control desired startup time versus power consumption. + */ +void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config); + +/** + * @brief Set the divider for the Ultra Low Power Clock (ULPCLK) + * + * The Ultra Low Power Clock (ULPCLK) is always sourced from the Main Clock + * (MCLK) but can be divided down to a lower frequency. The ULPCLK should + * always remain under 40MHz. + * + * The ULPCLK can be used to drive some peripherals on the system. + * + * @param[in] divider Clock divider for Ultra Low Power Clock (ULPCLK). One + * of @ref DL_SYSCTL_ULPCLK_DIV. + */ +__STATIC_INLINE void DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_UDIV_MASK); +} + +/** + * @brief Get divider used for the Ultra Low Power Clock (ULPCLK) + * + * @return The divider used for Ultra Low Power Clock (ULPCLK) + * + * @retval One of @ref DL_SYSCTL_ULPCLK_DIV. + */ +__STATIC_INLINE DL_SYSCTL_ULPCLK_DIV DL_SYSCTL_getULPCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_UDIV_MASK; + + return (DL_SYSCTL_ULPCLK_DIV)(divider); +} + +/** + * @brief Change LFCLK source to external crystal LFXT + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFXT is an ultra-low power crystal oscillator which supports driving a + * standard 32.768kHz watch crystal. + * + * To use the LFXT, a watch crystal must be populated between LFXIN and LFXOUT + * pins. Find more info in LFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure LFXT functionality for LFXIN and LFXOUT before + * calling this function. + * + * This basic implementation will busy-wait until LFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the LFXT is + * stabilizing. You can enable LFXTGOOD interrupt, or check CLKSTATUS.LFXTGOOD + * when convenient, as long as you do not switch the source via + * SETUSELFXT until LFXTGOOD is set. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFCLK_IN is disabled (default). + * + * @param[in] config Pointer to the LFCLK configuration struct + * @ref DL_SYSCTL_LFCLKConfig. + */ +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config); + +/** + * @brief Change LFCLK source to external digital LFCLK_IN + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFCLK_IN is a low frequency digital clock input compatible with 32.768kHz + * typical frequency digital square wave CMOS clock inputs (typical duty + * cycle of 50%). + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * LFCLK_IN. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFXT is disabled (default). + */ +__STATIC_INLINE void DL_SYSCTL_setLFCLKSourceEXLF(void) +{ + SYSCTL->SOCLOCK.EXLFCTL = + (SYSCTL_EXLFCTL_KEY_VALUE | SYSCTL_EXLFCTL_SETUSEEXLF_TRUE); +} + +/** + * @brief Change HFCLK source to external crystal HFXT with default parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * The HFXT startup time is set to ~0.512ms based on the TYP datasheet + * recommendation. Additionally, the HFCLK startup monitor is enabled. + * + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * To modify the default HFXT startup time or disable the startup monitor, use + * @ref DL_SYSCTL_setHFCLKSourceHFXTParams instead of this API. + * + * @param[in] range HFXT frequency range + */ +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range); + +/** + * @brief Change HFCLK source to external crystal HFXT with custom parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * If the HFCLK startup monitor is enabled, then the HFXT will be checked after + * the amount of time specified by the startupTime parameter. + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * If the HFCLK startup monitor is disabled, then this implementation will not + * check if the HFXT oscillator is stabilized. + * + * @param[in] range HFXT frequency range + * @param[in] startupTime HFXT startup time + * @param[in] monitorEnable Whether to enable the HFCLK startup monitor + + */ +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable); + +/** + * @brief Disable the SYSPLL + * + * If SYSPLL is already enabled, application software should not disable the + * SYSPLL until the SYSPLLGOOD or SYSPLOFF bit is set in the CLKSTATUS + * register, indicating that the SYSPLL transitioned to a stable active or a + * stable dead state. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableSYSPLL(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_SYSPLLEN_MASK); +} + +/** + * @brief Disable the HFXT + * + * If HFXT is already enabled, application software must verify that either an + * HFCLKGOOD indication or an HFCLKOFF (off/dead) indication in the CLKSTATUS + * register was asserted by hardware before attempting to disable the HFXT + * by clearing HFXTEN. When disabling the HFXT by clearing HFXTEN, the HFXT + * must not be re-enabled again until the HFCLKOFF bit in the CLKSTATUS + * register is set by hardware. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableHFXT(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_HFXTEN_MASK); +} + +/** + * @brief Change HFCLK source to external digital HFCLK_IN + * + * HFCLK_IN can be used to bypass the HFXT circuit and bring 4-48MHz typical + * frequency digital clock into the devce as HFCLK source instead of HFXT. + * + * HFCLK_IN is a digital clock input compatible with digital square wave CMOS + * clock inputs and should have typical duty cycle of 50%. + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * HFCLK_IN. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKSourceHFCLKIN(void) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE; +} + +/** + * @brief Get the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @return The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_HSCLK_SOURCE DL_SYSCTL_getHSCLKSource(void) +{ + uint32_t source = SYSCTL->SOCLOCK.HSCLKCFG & SYSCTL_HSCLKCFG_HSCLKSEL_MASK; + + return (DL_SYSCTL_HSCLK_SOURCE)(source); +} + +/** + * @brief Set the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @param[in] source The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setHSCLKSource(DL_SYSCTL_HSCLK_SOURCE source) +{ + SYSCTL->SOCLOCK.HSCLKCFG = (uint32_t) source; +} + +/** + * @brief Get the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @return The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_MFPCLK_SOURCE DL_SYSCTL_getMFPCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_MFPCLKSRC_MASK; + + return (DL_SYSCTL_MFPCLK_SOURCE)(source); +} + +/** + * @brief Set the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @param[in] source The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE source) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) source, + SYSCTL_GENCLKCFG_MFPCLKSRC_MASK); +} + +/** + * @brief Enable the Medium Frequency Clock (MFCLK) + * + * MFCLK provides a continuous 4MHz clock to drive certain peripherals on the system. + * The 4MHz rate is always derived from SYSOSC, and the divider is automatically + * applied to maintain the 4MHz rate regardless of SYSOSC frequency. + * MCLK is ideal for timers and serial interfaces which require a constant + * clock source in RUN/SLEEP/STOP power modes. + * + * MFCLK can only run if 3 conditions are met: + * + * 1) Power mode must be RUN, SLEEP, or STOP. + * 2) USEMFTICK register bit is set, which this function does + * 3) MDIV must be set to @ref DL_SYSCTL_MCLK_DIVIDER_DISABLE by @ref DL_SYSCTL_setMCLKDivider. + * + * If MCLK source is not SYSOSC, MCLK frequency must be >=32MHz for correct operation of MFCLK. + * + * @sa DL_SYSCTL_setMCLKDivider + * @sa DL_SYSCTL_getMCLKSource + * @sa DL_SYSCTL_getMCLKFreq + */ +__STATIC_INLINE void DL_SYSCTL_enableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEMFTICK_ENABLE; +} + +/** + * @brief Disable the Medium Frequency Clock (MFCLK) + */ +__STATIC_INLINE void DL_SYSCTL_disableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_USEMFTICK_ENABLE); +} + +/** + * @brief Enable the Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK provides a continuous 4MHz clock to the DAC. + * + * MFPCLK can be sources from either SYSOSC or HFCLK (HFXT or HFCLK_IN). + * + * The DAC does not have a clock selection mux. Its clock source is selected + * by configuring MFPCLK. + * + * @sa DL_SYSCTL_disableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_enableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_MFPCLKEN_ENABLE; +} + +/** + * @brief Disable the Middle Frequency Precision Clock (MFPCLK) + * @sa DL_SYSCTL_enableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_disableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_MFPCLKEN_ENABLE); +} + +/** + * @brief Set the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @param[in] divider The divider of HFCLK for MFPCLK + * One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKDividerForMFPCLK( + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + ((uint32_t) divider << SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS), + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK); +} + +/** + * @brief Get the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @return Returns the divider for HFCLK for MFPCLK + * + * @retval One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER + */ +__STATIC_INLINE DL_SYSCTL_HFCLK_MFPCLK_DIVIDER +DL_SYSCTL_getHFCLKDividerForMFPCLK(void) +{ + uint32_t divider = + (SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK) >> + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS; + + return (DL_SYSCTL_HFCLK_MFPCLK_DIVIDER)(divider); +} + +/** + * @brief Enable the External Clock (CLK_OUT) + * + * CLK_OUT is provided for pushing out digital clocks to external circuits, such + * as an external ADC which does not have its own clock source. + * + * IOMUX setting for CLK_OUT must be configured before using this function. + * + * CLK_OUT has a typical duty cycle of 50% if clock source is HFCLK, SYSPLLOUT1, + * SYSOSC, or LFCLK. If source is MCLK, ULPCLK, or MFCLK, duty cycle is not + * guaranteed to be 50%. + * + * This function performs multiple operations: + * 1) Sets the CLK_OUT source + * 2) Sets the CLK_OUT divider value + * 3) Enables the CLK_OUT divider, which can be disabled by @ref DL_SYSCTL_disableExternalClockDivider + * 4) Enables the CLK_OUT, which can be disabled by @ref DL_SYSCTL_disableExternalClock + * + * @param[in] source The source of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_SOURCE. + * @param[in] divider The divider of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_DIVIDE. + * + * @sa DL_SYSCTL_disableExternalClock + * @sa DL_SYSCTL_disableExternalClockDivider + */ +__STATIC_INLINE void DL_SYSCTL_enableExternalClock( + DL_SYSCTL_CLK_OUT_SOURCE source, DL_SYSCTL_CLK_OUT_DIVIDE divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) divider | (uint32_t) source, + SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK | SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK | + SYSCTL_GENCLKCFG_EXCLKSRC_MASK); + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_EXCLKEN_ENABLE; +} + +/** + * @brief Disable the External Clock (CLK_OUT) + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClock(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_EXCLKEN_ENABLE); +} + +/** + * @brief Disable the External Clock (CLK_OUT) Divider + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClockDivider(void) +{ + SYSCTL->SOCLOCK.GENCLKCFG &= ~(SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE); +} + +/** + * @brief Blocks all asynchronous fast clock requests + * + * To block specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C. + */ +__STATIC_INLINE void DL_SYSCTL_blockAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE; +} + +/** + * @brief Allows all asynchronous fast clock requests + * + * Although this allows all async fast clock requests, individual IPs may still + * be blocking theirs. + * + * To allow specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C, GPIO. + */ +__STATIC_INLINE void DL_SYSCTL_allowAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE); +} + +/** + * @brief Generates an asynchronous fast clock request upon any IRQ request to CPU. + * + * Provides lowest latency interrupt handling regardless of system clock speed. + * Blockable by @ref DL_SYSCTL_blockAllAsyncFastClockRequests + * + * @sa DL_SYSCTL_blockAllAsyncFastClockRequests + */ +__STATIC_INLINE void DL_SYSCTL_enableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE; +} + +/** + * @brief Maintains current system clock speed for IRQ request to CPU. + * + * Latency for interrupt handling will be higher at lower system clock speeds. + */ +__STATIC_INLINE void DL_SYSCTL_disableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE); +} + +/** + * @brief Set the lower SRAM boundary address to act as partition for read-execute + * permission + * + * Specify the lower SRAM partition address to protect the code region of SRAM from + * being written to, and prevent the RW ("data") region of SRAM from being + * used for code execution. + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. This is the default + * value. + * + * The address is set with a 32-byte resolution. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @param[in] address Address to act as the SRAM partition address. Value is + * a valid 32-bit SRAM address. Only address bits [19:5] + * i.e. bit 5 to bit 19 are used for the boundary address + */ +__STATIC_INLINE void DL_SYSCTL_setLowerSRAMBoundaryAddress(uint32_t address) +{ + SYSCTL->SOCLOCK.SRAMBOUNDARY = + (((uint32_t) address) & SYSCTL_SRAMBOUNDARY_ADDR_MASK); +} + +/** + * @brief Get the lower SRAM boundary address + * + * Get the lower SRAM partition address + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. + * + * The address is set with a 32-byte granularity. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @return The SRAM partition address offset from the SRAM base address + * + * @retval Value is range in [0x0, 0x000FFFE0] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getLowerSRAMBoundaryAddress(void) +{ + return (SYSCTL->SOCLOCK.SRAMBOUNDARY); +} + +/** + * @brief Set flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @param[in] waitState Desired number of flash wait states. One of + * @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE void DL_SYSCTL_setFlashWaitState( + DL_SYSCTL_FLASH_WAIT_STATE waitState) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) waitState, + SYSCTL_MCLKCFG_FLASHWAIT_MASK); +} + +/** + * @brief Get flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @return Number of flash wait states. One of @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE DL_SYSCTL_FLASH_WAIT_STATE DL_SYSCTL_getFlashWaitState(void) +{ + uint32_t waitState = + SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_FLASHWAIT_MASK; + + return (DL_SYSCTL_FLASH_WAIT_STATE)(waitState); +} + +/** + * @brief Read Frequency Clock Counter (FCC) + * @return 22-bit value of Frequency Clock Counter (FCC) + */ +__STATIC_INLINE uint32_t DL_SYSCTL_readFCC(void) +{ + return (SYSCTL->SOCLOCK.FCC); +} + +/** + * @brief Start Frequency Clock Counter (FCC) + * + * If FCC_IN is already logic high, counting starts immediately. + * When using level trigger, FCC_IN should be low when GO is set, and trigger + * pulse should be sent to FCC_IN after starting FCC. + */ +__STATIC_INLINE void DL_SYSCTL_startFCC(void) +{ + SYSCTL->SOCLOCK.FCCCMD = (SYSCTL_FCCCMD_KEY_VALUE | SYSCTL_FCCCMD_GO_TRUE); +} + +/** + * @brief Returns whether FCC is done capturing + * + * When capture completes, FCCDONE is set by hardware. + * FCCDONE is read-only and is automatically cleared by hardware when a new + * capture is started. + * + * @return Whether FCC is done or not + * @retval true or false (boolean) + */ +__STATIC_INLINE bool DL_SYSCTL_isFCCDone(void) +{ + return (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_FCCDONE_DONE) == + SYSCTL_CLKSTATUS_FCCDONE_DONE; +} + +/** + * @brief Configure the Frequency Clock Counter (FCC) + * + * FCC enables flexible in-system testing and calibration of a variety of oscillators + * and clocks on the device. The FCC counts the number of clock periods seen on the + * selected clock source within a known fixed trigger period (derived from a secondary + * reference source) to provide an estimation of the frequency of the source clock. + * + * @param[in] trigLvl Determines if active high level trigger or rising-edge + * to rising-edge. One of @ref DL_SYSCTL_FCC_TRIG_TYPE. + * @sa DL_SYSCTL_setFCCPeriods must be called to configure + * number of rising-edge to rising-edge periods when + * DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE is selected. + * @param[in] trigSrc Determines which clock source to trigger FCC from. One of + * @ref DL_SYSCTL_FCC_TRIG_SOURCE. + * @param[in] clkSrc Which clock source to capture and measure frequency of. One of + * @ref DL_SYSCTL_FCC_CLOCK_SOURCE. + */ +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc); + +/** + * @brief Sets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * Set the number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @param[in] periods One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE void DL_SYSCTL_setFCCPeriods(DL_SYSCTL_FCC_TRIG_CNT periods) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) periods, + SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK); +} + +/** + * @brief Gets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @return One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT DL_SYSCTL_getFCCPeriods(void) +{ + uint32_t periods = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK; + + return (DL_SYSCTL_FCC_TRIG_CNT)(periods); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in Internal Resistor Mode + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in External Resistor Mode + * + * Used to increase SYSOSC accuracy. An ROSC reference resistor which is suitable + * to meet application accuracy reqiurements must be placed between ROSC pin and + * device ground (VSS). + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + * + * Power consumption of SYSOSC will be marginally higher with FCL enabled due to + * reference current which flows through ROSC. + * Settling time from startup to specified accuracy may also be longer. + * See device-specific datasheet for startup times. + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCLExternalResistor(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE | + SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE); +} + +/** + * @brief Enable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_enableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_ENABLE; +} + +/** + * @brief Disable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_disableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_DISABLE; +} + +/** + * @brief Sets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @param[in] setting One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE void DL_SYSCTL_setVBOOSTConfig(DL_SYSCTL_VBOOST setting) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) setting, + SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK); +} + +/** + * @brief Gets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @return One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE DL_SYSCTL_VBOOST DL_SYSCTL_getVBOOSTConfig(void) +{ + uint32_t setting = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK; + + return (DL_SYSCTL_VBOOST)(setting); +} + +/** + * @brief Return byte that was saved through SHUTDOWN + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * + * @return 8-bit value of Shutdown Storage Byte. + */ +__STATIC_INLINE uint8_t DL_SYSCTL_getShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index) +{ + const volatile uint32_t *pReg = &SYSCTL->SOCLOCK.SHUTDNSTORE0; + + return (uint8_t)( + *(pReg + (uint32_t) index) & SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Save a byte to SHUTDOWN memory + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * @param[in] data 8-bit data to save in memory + */ +__STATIC_INLINE void DL_SYSCTL_setShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index, uint8_t data) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SHUTDNSTORE0 + (uint32_t) index, data, + SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Enable SHUTDOWN IO Release + * + * After shutdown, IO is locked in previous state. + * + * @note Release IO after re-configuring IO to their proper state. + */ +__STATIC_INLINE void DL_SYSCTL_releaseShutdownIO(void) +{ + SYSCTL->SOCLOCK.SHDNIOREL = + (SYSCTL_SHDNIOREL_KEY_VALUE | SYSCTL_SHDNIOREL_RELEASE_TRUE); +} + +/** + * @brief Disable the reset functionality of the NRST pin + * + * Disabling the NRST pin allows the pin to be configured as a GPIO. + * Once disabled, the reset functionality can only be re-enabled by a POR. + * + * @note The register is write-only, so the EXRSTPIN register + * will always appear as "Disabled" in the debugger + */ +__STATIC_INLINE void DL_SYSCTL_disableNRSTPin(void) +{ + SYSCTL->SOCLOCK.EXRSTPIN = + (SYSCTL_EXRSTPIN_KEY_VALUE | SYSCTL_EXRSTPIN_DISABLE_TRUE); +} + +/** + * @brief Disable Serial Wire Debug (SWD) functionality + * + * SWD pins are enabled by default after cold start to allow a debug connection. + * It is possible to disable SWD on these pins to use for other functionality. + * + * @post SWD is disabled, but pins must be re-configured separately. + * + * @note Cannot debug the device after disabling SWD. Only re-enabled by POR. + */ +__STATIC_INLINE void DL_SYSCTL_disableSWD(void) +{ + SYSCTL->SOCLOCK.SWDCFG = + (SYSCTL_SWDCFG_KEY_VALUE | SYSCTL_SWDCFG_DISABLE_TRUE); +} + +/** + * @brief Return byte that is stored in RSTCAUSE. + * + * @return The cause of reset. One of @ref DL_SYSCTL_RESET_CAUSE + */ +__STATIC_INLINE DL_SYSCTL_RESET_CAUSE DL_SYSCTL_getResetCause(void) +{ + uint32_t resetCause = SYSCTL->SOCLOCK.RSTCAUSE & SYSCTL_RSTCAUSE_ID_MASK; + + return (DL_SYSCTL_RESET_CAUSE)(resetCause); +} + +/** + * @brief Set the HFXT startup time + * + * Specify the HFXT startup time in 64us resolution. If the HFCLK startup + * monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time + * expires. + * + * @param[in] startupTime The HFXT startup time to set in ~64us steps. + * Value between [0x0 (~0s), 0xFF (~16.32ms)]. + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTStartupTime(uint32_t startupTime) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, startupTime, + SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Get the HFXT startup time + * + * @return Returns the HFXT startup time in ~64us steps + * + * @retval Value between [0x0 (~0s), 0xFF (~16.32ms)] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getHFXTStartupTime(void) +{ + return (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Set the HFXT frequency range + * + * The high frequency crystal oscillator (HFXT) can be used with standard + * crystals and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * @param[in] range One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTFrequencyRange( + DL_SYSCTL_HFXT_RANGE range) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, ((uint32_t) range), + SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK); +} + +/** + * @brief Get the HFXT frequency range + * + * @return Returns the HFXT frequency range + * + * @retval One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE DL_SYSCTL_HFXT_RANGE DL_SYSCTL_getHFXTFrequencyRange(void) +{ + uint32_t range = + (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK) >> + SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS; + + return (DL_SYSCTL_HFXT_RANGE)(range); +} + +/** + * @brief Enable the HFCLK startup monitor + * + * The HFXT takes time to start after being enabled. A startup monitor is + * provided to indicate to the application software if the HFXT has successfully + * started, at which point the HFCLK can be selected to source a variety of + * system functions. The HFCLK startup monitor also supports checking the + * HFCLK_IN digital clock input for a clock stuck fault. + * + */ +__STATIC_INLINE void DL_SYSCTL_enableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG |= SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE; +} + +/** + * @brief Disable the HFCLK startup monitor + */ +__STATIC_INLINE void DL_SYSCTL_disableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG &= ~(SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK); +} + +/** + * @brief Retrieves the calibration constant of the temperature sensor to be + * used in temperature calculation. + * + * @retval Temperature sensor calibration data + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getTempCalibrationConstant(void) +{ + return DL_FactoryRegion_getTemperatureVoltage(); +} + +/** + * @brief Initializes the Read Execute (RX) Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the read execute protect firewall + * @param[in] endAddr The end address of the read execute protect firewall + * + * @return If the Read Execute Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Initializes the IP Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the IP protect firewall + * @param[in] endAddr The end address of the IP protect firewall + * + * @return If the IP Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Set the address range of the Write Protect Firewall + * + * Set Write Protection starting at 0x0 of flash, for the first + * 32KB at 1KB granularity. + * Setting a bit to 1 enables write protection, and setting a bit to 0 + * allows write. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] addrMask The mask to set the address range for the Write Protect + * Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setWriteProtectFirewallAddrRange( + uint32_t addrMask) +{ + SYSCTL->SECCFG.FWEPROTMAIN = addrMask; +} + +/** + * @brief Get the address range of the Write Protect Firewall + * + * @retval The address range for the Write Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getWriteProtectFirewallAddrRange(void) +{ + return (SYSCTL->SECCFG.FWEPROTMAIN); +} + +/** + * @brief Set the Read Write Protect Firewall for the Flash DATA Bank + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] protectionType The type of protection to set for the DATA Bank. + * One of @ref DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL + */ +__STATIC_INLINE void DL_SYSCTL_setDATABankRWProtectFirewallMode( + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL protectionType) +{ + SYSCTL->SECCFG.FWPROTMAINDATA = (uint32_t) protectionType; +} + +/** + * @brief Get the protection type for the Read Write Protect Firewall for the Flash DATA Bank + * + * @return The protection type for the Read Write Protect Firewall for the Flash DATA Bank + * + * @retval One of @ref DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL + */ +__STATIC_INLINE DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL +DL_SYSCTL_getDATABankRWProtectFirewallMode(void) +{ + return (DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL)( + SYSCTL->SECCFG.FWPROTMAINDATA); +} + +/** + * @brief Set the start address of the Read Execute (RX) Protect Firewall + * + * Set the start of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the read execute protect + * firewall. The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINSTART = + (startAddr & SYSCTL_FRXPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The start address of the read execute protect firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINSTART); +} + +/** + * @brief Set the end address of the Read Execute (RX) Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the read execute protect firewall. + * The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd( + uint32_t endAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINEND = + (endAddr & SYSCTL_FRXPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The end address of the Read Execute Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINEND); +} + +/** + * @brief Set the start address of the IP Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the IP Protect Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINSTART = + (startAddr & SYSCTL_FIPPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the IP Protect Firewall + * + * @return The start address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINSTART); +} + +/** + * @brief Set the end address of the IP Protect firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the IP Protect firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINEND = + (endAddr & SYSCTL_FIPPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the IP Protect Firewall + * + * @return The end address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINEND); +} + +/** + * @brief Enable the policy to allow flash bank swapping + * + * The bank swap policy needs to be configured ahead of any bank swapping or + * firewall configurations. In dual/quad-bank devices, this policy can be set + * to either + * - CSC allows bank swapping + * - CSC does not allow bank swapping + * + * By default, bank swapping is enabled to ensure a high security state if the + * system boot execution was glitched. Defaulting the system as allowing bank + * swapping ensures that firewall protections get mirrored to both flash banks. + * Additionally, when bank swapping is enabled, SYSCTL enforces write-excute + * mutual exclusion across the two banks (or bank-pairs). + * + * @note This is a write-once bit. This bit can only be written to before + * INITDONE. At INITDONE, this bit becomes a read-only bit until next + * BOOTRST. + */ +__STATIC_INLINE void DL_SYSCTL_enableFlashBankSwap(void) +{ + SYSCTL->SECCFG.FLBANKSWPPOLICY &= (~(SYSCTL_FLBANKSWPPOLICY_DISABLE_MASK) | + SYSCTL_FLBANKSWPPOLICY_KEY_VALUE); +} + +/** + * @brief Disable the policy to allow flash bank swapping + * + * The bank swap policy needs to be configured ahead of any bank swapping or + * firewall configurations. In dual/quad-bank devices, this policy can be set + * to either + * - CSC allows bank swapping + * - CSC does not allow bank swapping + * + * By default, bank swapping is enabled to ensure a high security state if the + * system boot execution was glitched. Defaulting the system as allowing bank + * swapping ensures that firewall protections get mirrored to both flash banks. + * Additionally, when bank swapping is enabled, SYSCTL enforces write-excute + * mutual exclusion across the two banks (or bank-pairs). + * + * @note This is a write-once bit. This bit can only be written to before + * INITDONE. At INITDONE, this bit becomes a read-only bit until next + * BOOTRST. + */ +__STATIC_INLINE void DL_SYSCTL_disableFlashBankSwap(void) +{ + SYSCTL->SECCFG.FLBANKSWPPOLICY = (SYSCTL_FLBANKSWPPOLICY_DISABLE_TRUE | + SYSCTL_FLBANKSWPPOLICY_KEY_VALUE); +} + +/** + * @brief Perform bank swap and execute from the Upper Flash Bank + * + * The upper physical bank maps to logical 0x0, and gets RX permission. + * The lower physical bank gets RW permission. + * + * @note This bit can only be written to before INITDONE. At INITDONE, this bit + * becomes a read-only bit until next BOOTRST. + * + * @pre DL_SYSCTL_enableFlashBankSwap + */ +__STATIC_INLINE void DL_SYSCTL_executeFromUpperFlashBank(void) +{ + SYSCTL->SECCFG.FLBANKSWP |= + (SYSCTL_FLBANKSWP_USEUPPER_ENABLE | SYSCTL_FLBANKSWP_KEY_VALUE); +} + +/** + * @brief Perform bank swap and execute from the Lower Flash Bank + * + * The lower physical bank maps to logical 0x0, and gets RX permission. + * The upper physical bank gets RW permission. + * + * @note This bit can only be written to before INITDONE. At INITDONE, this bit + * becomes a read-only bit until next BOOTRST. + * + * @pre DL_SYSCTL_enableFlashBankSwap + */ +__STATIC_INLINE void DL_SYSCTL_executeFromLowerFlashBank(void) +{ + SYSCTL->SECCFG.FLBANKSWP &= + (~(SYSCTL_FLBANKSWP_USEUPPER_MASK) | SYSCTL_FLBANKSWP_KEY_VALUE); +} + +/** + * @brief Enable Read Execute (RX) Protect Firewall + * + * Enables the Read Execute Protect Firewall before INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableReadExecuteProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_FLRXPROT_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable IP Protect Firewall + * + * Enables the IP Protect Firewall before INITDONE. After INITDONE, + * this configuration gets locked until the next BOOTRST. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableIPProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_SECSTATUS_FLIPPROT_ENABLED | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable SRAM Boundary Lock + * + * When SRAM Boundary Lock is enabled, the SRAMBOUNDARY register is only + * writeable only until INITDONE. After INITDONE, the SRAMBOUNDARY register + * cannot be written. + * + * When disabled, the SRAMBOUNDARY register is writeable throughout the + * application, even after INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + * + * @sa DL_SYSCTL_setSRAMBoundaryAddress + */ +__STATIC_INLINE void DL_SYSCTL_enableSRAMBoundaryLock(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Checks if INITDONE has been issued by the CSC + * + * @return Whether INITDONE has been issued or not + * + * @retval true If INITDONE has been issued + * @retval false If INITDONE has not been issued + */ +__STATIC_INLINE bool DL_SYSCTL_isINITDONEIssued(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_INITDONE_YES) == + SYSCTL_SECSTATUS_INITDONE_YES); +} + +/** + * @brief Checks if Customer Startup Code (CSC) exists in system + * + * @return Whether CSC exists in system + * + * @retval true If CSC exists in system + * @retval false If CSC does not exist in system + */ +__STATIC_INLINE bool DL_SYSCTL_ifCSCExists(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_CSCEXISTS_YES) == + SYSCTL_SECSTATUS_CSCEXISTS_YES); +} + +/** + * @brief Checks if Read Execute (RX) Protect Firewall is enabled + * + * @return Whether Read Execute Protect Firewall is enabled + * + * @retval true If Read Execute Protect Firewall is enabled + * @retval false If Read Execute Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isReadExecuteProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLRXPROT_ENABLED) == + SYSCTL_SECSTATUS_FLRXPROT_ENABLED); +} + +/** + * @brief Checks if IP Protect Firewall is enabled + * + * @return Whether IP Protect Firewall is enabled + * + * @retval true If IP Protect Firewall is enabled + * @retval false If IP Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isIPProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLIPPROT_ENABLED) == + SYSCTL_SECSTATUS_FLIPPROT_ENABLED); +} + +/** + * @brief Checks if SRAM Boundary Lock is enabled + * + * @return Whether SRAM Boundary Lock is enabled + * + * @retval true If SRAM Boundary Lock is enabled + * @retval false If SRAM Boundary Lock is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSRAMBoundaryLocked(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED) == + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED); +} + +/** + * @brief Checks if Flash Bank swapping is enabled + * + * @return Whether Flash Bank swap is enabled + * + * @retval true If Flash Bank swap is enabled + * @retval false If Flash Bank swap is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isFlashBankSwapEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & + SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED) == + SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED); +} + +/** + * @brief Checks if executing from upper flash bank + * + * @return Whether executing from upper flash bank + * + * @retval true If executing from upper flash bank + * @retval false If not executing from upper flash bank + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromUpperFlashBank(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLBANKSWP_MASK) == + SYSCTL_SECSTATUS_FLBANKSWP_MASK); +} + +/** + * @brief Checks if executing from lower flash bank + * + * @return Whether executing from lower flash bank + * + * @retval true If executing from lower flash bank + * @retval false If not executing from lower flash bank + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromLowerFlashBank(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLBANKSWP_MASK) != + SYSCTL_SECSTATUS_FLBANKSWP_MASK); +} + +/** + * @brief Indicate that INIT is done + * + * After INITDONE is issued, the security configuration is locked and enforced. + * A SYSRST will occur, restarting startup code execution, and the main + * application is launched. + * + * There is no hardware support to enforce a timeout if INITDONE is not issued + * in a reasonable period of time. It is recommended that the CSC use a + * watchdog to ensure that INITDONE is issued in a timely manner. + */ +__STATIC_INLINE void DL_SYSCTL_issueINITDONE(void) +{ + SYSCTL->SECCFG.INITDONE |= + (SYSCTL_INITDONE_PASS_TRUE | SYSCTL_INITDONE_KEY_VALUE); +} + +/** + * @brief Set USBCLK source + * + * Configures USBCLK to source from either PLLCLK1 or USBFLL. + * + * @param[in] source The clock that USBCLK will source from, + * one of @ref DL_SYSCTL_USBCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setUSBCLKSource(DL_SYSCTL_USBCLK_SOURCE source) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) source, + SYSCTL_GENCLKCFG_USBCLKSRC_MASK); +} + +/** + * @brief Get the source for the USB Clock (USBCLK) + * + * @return The source for the USB Clock (USBCLK) + * + * @retval One of @ref DL_SYSCTL_USBCLK_SOURCE + */ +__STATIC_INLINE DL_SYSCTL_USBCLK_SOURCE DL_SYSCTL_getUSBCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_USBCLKSRC_MASK; + + return (DL_SYSCTL_USBCLK_SOURCE)(source); +} + +/** + * @brief Disable USBFLL + * + * Updates the USBFLLCTL register to disable the USB Frequency Lock Loop + */ +__STATIC_INLINE void DL_SYSCTL_disableUSBFLL(void) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.USBFLLCTL, + SYSCTL_USBFLLCTL_FLLEN_FALSE, SYSCTL_USBFLLCTL_FLLEN_MASK); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dl_m0p_dl_sysctl_sysctl__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g518x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g518x.c new file mode 100644 index 0000000..372b6eb --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g518x.c @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G518X) + +#include +#include + +void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config) +{ + /* PLL configurations are retained in lower reset levels. Set default + * behavior of disabling the PLL to keep a consistent behavior regardless + * of reset level. */ + DL_SYSCTL_disableSYSPLL(); + + /* Check that SYSPLL is disabled before configuration */ + while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) != + (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) { + ; + } + + // set SYSPLL reference clock + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, + ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK); + + // set predivider PDIV (divides reference clock) + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv), + SYSCTL_SYSPLLCFG1_PDIV_MASK); + + // save CPUSS CTL state and disable the cache + uint32_t ctlTemp = DL_CORE_getInstructionConfig(); + DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED, + DL_CORE_LITERAL_CACHE_ENABLED); + + // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq + SYSCTL->SOCLOCK.SYSPLLPARAM0 = + *(volatile uint32_t *) ((uint32_t) config->inputFreq); + SYSCTL->SOCLOCK.SYSPLLPARAM1 = + *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4); + + // restore CPUSS CTL state + CPUSS->CTL = ctlTemp; + + // set feedback divider QDIV (multiplies to give output frequency) + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, + ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) & + SYSCTL_SYSPLLCFG1_QDIV_MASK), + SYSCTL_SYSPLLCFG1_QDIV_MASK); + + // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0 + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, + (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) | + ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) | + ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) & + SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) | + config->enableCLK2x | config->enableCLK1 | config->enableCLK0 | + (uint32_t) config->sysPLLMCLK), + (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK | + SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK | + SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK | + SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK)); + + // enable SYSPLL + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE; + + // wait until SYSPLL startup is stabilized + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) { + ; + } +} + +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG, + ((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) | + (uint32_t) config->xt1Drive, + (SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK)); + // start the LFXT oscillator + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE); + // wait until LFXT oscillator is stable + // if it does not stabilize, check the hardware/IOMUX settings + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_LFXT_GOOD) { + ; + } + if (config->monitor) { + // set the LFCLK monitor + SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE; + } + + // switch LFCLK source from LFOSC to LFXT + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE); +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) +{ + if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled + DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } else { + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify LFCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void) +{ + // Only one should have been set, but clear both because unknown incoming state + // Clear SYSOSCCFG.DISABLE to get SYSOSC running again + // Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source) +{ + // Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN) + // Selected desired HSCLK source + DL_SYSCTL_setHSCLKSource(source); + + // Verify HSCLK source is valid + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) { + ; + } + + // Switch MCLK to HSCLK + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify HSCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void) +{ + // Switch MCLK to SYSOSC + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + DL_SYSCTL_setHFXTFrequencyRange(range); + /* Set startup time to ~0.512ms based on TYP datasheet recommendation */ + DL_SYSCTL_setHFXTStartupTime(8); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + DL_SYSCTL_setHFXTFrequencyRange(range); + DL_SYSCTL_setHFXTStartupTime(startupTime); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + + if (monitorEnable == true) { + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ( + (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } + } else { + DL_SYSCTL_disableHFCLKStartupMonitor(); + } +} + +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc, + SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK | + SYSCTL_GENCLKCFG_FCCSELCLK_MASK); +} + +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void) +{ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy = + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED; + + // Check if SLEEP is enabled + if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) == + SYSCTL_MCLKCFG_USELFCLK_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void) +{ + DL_SYSCTL_POWER_POLICY_STOP policy = + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) == + SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_STOP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void) +{ + DL_SYSCTL_POWER_POLICY_STANDBY policy = + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) == + SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STANDBY1; + } else { + policy = DL_SYSCTL_POWER_POLICY_STANDBY0; + } + } + return policy; +} + +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableReadExecuteProtectFirewall(); + status = true; + } + return status; +} + +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableIPProtectFirewall(); + status = true; + } + return status; +} + +void DL_SYSCTL_configUSBFLL(DL_SYSCTL_USBFLL_REFERENCE refSource) +{ + /* Disable USBFLL before any configuration is done */ + DL_SYSCTL_disableUSBFLL(); + + /* Check that USBFLL is disabled before configuration */ + while ((SYSCTL->SOCLOCK.USBFLLCTL & SYSCTL_USBFLLCTL_FLLEN_MASK) != + SYSCTL_USBFLLCTL_FLLEN_FALSE) { + ; + } + + /* Configuring USBFLL reference source */ + DL_Common_updateReg(&SYSCTL->SOCLOCK.USBFLLCTL, ((uint32_t) refSource), + SYSCTL_USBFLLCTL_REFSEL_MASK); + + /* Enabling USB oscillator clock */ + SYSCTL->SOCLOCK.USBFLLCTL |= (SYSCTL_USBFLLCTL_CLKEN_TRUE); + + /* Polling for completion of USB oscillator initializiation */ + while ((SYSCTL->SOCLOCK.USBFLLSTAT & SYSCTL_USBFLLSTAT_CLKRDY_MASK) != + SYSCTL_USBFLLSTAT_CLKRDY_TRUE) + ; + + /* Enabling USBFLL */ + SYSCTL->SOCLOCK.USBFLLCTL |= SYSCTL_USBFLLCTL_FLLEN_TRUE; +} + +#endif /* DeviceFamily_PARENT_MSPM0G518X */ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g518x.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g518x.h new file mode 100644 index 0000000..65f78a6 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g518x.h @@ -0,0 +1,3314 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_sysctl_mspm0g518x.h + * @brief System Control (SysCtl) + * @defgroup SYSCTL_mspm0g518x mspm0g518x System Control (SYSCTL) + * + * @anchor ti_dl_m0p_mspm0g518x_dl_sysctl_Overview + * # Overview + * + * The System Control (SysCtl) module enables control over system wide + * settings like clocks and power management. + * + *
+ * + ****************************************************************************** + */ +/** @addtogroup SYSCTL_mspm0g518x + * @{ + */ +#ifndef ti_dl_m0p_dl_sysctl_sysctl__include +#define ti_dl_m0p_dl_sysctl_sysctl__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_SYSCTL_RESET + * @{ + */ +/*! + * @brief Perform a SYSRST + * + * This issues a SYSRST (CPU plus peripherals only) + */ + #define DL_SYSCTL_RESET_SYSRST (SYSCTL_RESETLEVEL_LEVEL_CPU) + +/*! + * @deprecated This API is deprecated. Please refer to @ref DL_SYSCTL_RESET_SYSRST. + */ + #define DL_SYSCTL_RESET_CPU (DL_SYSCTL_RESET_SYSRST) + +/*! + * @brief Perform a Boot reset + * + * This triggers execution of the device boot configuration routine and resets + * the majority of the core logic while also power cycling the SRAM + */ + #define DL_SYSCTL_RESET_BOOT (SYSCTL_RESETLEVEL_LEVEL_BOOT) + +/*! + * @brief Perform a POR reset + * + * This performas a POR reset which is a complete device reset + */ + #define DL_SYSCTL_RESET_POR (SYSCTL_RESETLEVEL_LEVEL_POR) + +/*! + * @brief Perform system reset and exit bootloader to the application + */ + #define DL_SYSCTL_RESET_BOOTLOADER_EXIT \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT) + + /*! + * @brief Perform system reset and run bootloader + */ + #define DL_SYSCTL_RESET_BOOTLOADER_ENTRY \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY) + + +/** @addtogroup DL_SYSCTL_NMI + * @{ + */ +/*! @brief Non-maskable interrupt for SRAM Double Error Detect */ +#define DL_SYSCTL_NMI_SRAM_DED (SYSCTL_NMIISET_SRAMDED_SET) +/*! @brief Non-maskable interrupt for Flash Double Error Detect */ +#define DL_SYSCTL_NMI_FLASH_DED (SYSCTL_NMIISET_FLASHDED_SET) +/*! @brief Non-maskable interrupt for LFCLK Monitor Fail */ +#define DL_SYSCTL_NMI_LFCLK_FAIL (SYSCTL_NMIISET_LFCLKFAIL_SET) +/*! @brief Non-maskable interrupt for Watchdog 1 Fault */ +#define DL_SYSCTL_NMI_WWDT1_FAULT (SYSCTL_NMIISET_WWDT1_SET) +/*! @brief Non-maskable interrupt for Watchdog 0 Fault */ +#define DL_SYSCTL_NMI_WWDT0_FAULT (SYSCTL_NMIISET_WWDT0_SET) +/*! @brief Non-maskable interrupt for early BOR */ +#define DL_SYSCTL_NMI_BORLVL (SYSCTL_NMIISET_BORLVL_SET) +/** @}*/ + +/** @addtogroup DL_SYSCTL_INTERRUPT + * @{ + */ +/*! @brief Low Frequency Oscillator is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFOSC_GOOD (SYSCTL_IMASK_LFOSCGOOD_ENABLE) +/*! @brief Analog clocking consistency error */ +#define DL_SYSCTL_INTERRUPT_ANALOG_CLOCK_ERROR (SYSCTL_IMASK_ANACLKERR_ENABLE) +/*! @brief Flash Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_FLASH_SEC (SYSCTL_IMASK_FLASHSEC_ENABLE) + +/*! @brief SRAM Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_SRAM_SEC (SYSCTL_IMASK_SRAMSEC_ENABLE) + +/*! @brief Low Frequency Crystal is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFXT_GOOD (SYSCTL_IMASK_LFXTGOOD_ENABLE) +/*! @brief High Frequency Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HFCLK_GOOD (SYSCTL_IMASK_HFCLKGOOD_ENABLE) +/*! @brief System PLL is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_SYSPLL_GOOD (SYSCTL_IMASK_SYSPLLGOOD_ENABLE) +/*! @brief High Speed Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HSCLK_GOOD (SYSCTL_IMASK_HSCLKGOOD_ENABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_CLK_STATUS + * @{ + */ +/*! @brief Error with Anacomp High Speed CP Clock Generation - SYSOSC must not + * run at 4MHz */ +#define DL_SYSCTL_CLK_STATUS_ANACOMP_ERROR (SYSCTL_CLKSTATUS_ACOMPHSCLKERR_TRUE) +/*! @brief Error with OPAMP Clock Generation */ +#define DL_SYSCTL_CLK_STATUS_OPAMP_ERROR (SYSCTL_CLKSTATUS_OPAMPCLKERR_TRUE) +/*! @brief Writes to SYSPLLCFG0-1, SYSPLLPARAM0-1 are blocked */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_SYSPLLBLKUPD_TRUE) +/*! @brief Writes to HFCLKCLKCFG are blocked */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE) +/*! @brief SYSOSC Frequency Correcting Loop Mode ON */ +#define DL_SYSCTL_CLK_STATUS_FCL_ON (SYSCTL_CLKSTATUS_FCLMODE_ENABLED) +/*! @brief Clock Fail for LFXT or EXLF clock source */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_FAIL (SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE) +/*! @brief High Speed Clock Good */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_GOOD (SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE) +/*! @brief High Speed Clock Stuck Fault */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_FAULT (SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE) +/*! @brief SYSPLL is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_OFF (SYSCTL_CLKSTATUS_SYSPLLOFF_TRUE) +/*! @brief HFCLKs is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_OFF (SYSCTL_CLKSTATUS_HFCLKOFF_TRUE) +/*! @brief All PLLs, HFCLKs are OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_OFF (SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE) +/*! @brief LFOSC is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFOSC_GOOD (SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE) +/*! @brief LFXT is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFXT_GOOD (SYSCTL_CLKSTATUS_LFXTGOOD_TRUE) +/*! @brief SYSTEM PLL ON */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD (SYSCTL_CLKSTATUS_SYSPLLGOOD_TRUE) +/*! @brief High Frequency Clock ON */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_GOOD (SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE) +/*! @brief MCLK now sourced from HSCLK, otherwise SYSOSC */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK (SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK) +/*! @brief MCLK now sourced from LFCLK */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK \ + (SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK) +/*! @brief Analog clocking error */ +#define DL_SYSCTL_CLK_STATUS_ANALOG_CLOCK_ERROR \ + (SYSCTL_CLKSTATUS_ANACLKERR_TRUE) +/*! @brief Frequency Clock Counter (FCC) done */ +#define DL_SYSCTL_CLK_STATUS_FCC_DONE (SYSCTL_CLKSTATUS_FCCDONE_DONE) +/*! @brief = LFCLK sourced from the LFXT (crystal) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_LFXT (SYSCTL_CLKSTATUS_LFCLKMUX_LFXT) +/*! @brief = LFCLK sourced from LFCLK_IN (external digital clock input) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_EXLF (SYSCTL_CLKSTATUS_LFCLKMUX_EXLF) +/*! @brief = SYSOSC is at low frequency (4MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_4MHZ (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M) +/*! @brief = SYSOSC is at the user-trimmed frequency (16 or 24MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_USERTRIM_FREQ \ + (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER) +/*! @brief = HSCLK current sourced from the HFCLK */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_SOURCE_HFCLK \ + (SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK) +/*! @brief NPU peripheral is ready */ +#define DL_SYSCTL_STATUS_NPU_READY (SYSCTL_SYSSTATUS_NPUREADY_TRUE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_STATUS + * @{ + */ + +/*! @brief IO is locked due to SHUTDOWN */ +#define DL_SYSCTL_STATUS_SHUTDOWN_IO_LOCK_TRUE \ + (SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE) +/*! @brief User has disabled external reset pin */ +#define DL_SYSCTL_STATUS_EXT_RESET_PIN_DISABLED \ + (SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE) +/*! @brief User has disabled SWD port */ +#define DL_SYSCTL_STATUS_SWD_DISABLED (SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE) + +/*! @brief PMU IFREF good */ +#define DL_SYSCTL_STATUS_PMU_IFREF_GOOD (SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE) +/*! @brief VBOOST (Analog Charge Pump) started up properly */ +#define DL_SYSCTL_STATUS_VBOOST_GOOD (SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE) +/*! @brief Brown Out Reset event status indicator */ +#define DL_SYSCTL_STATUS_BOR_EVENT (SYSCTL_SYSSTATUS_BORLVL_TRUE) +/*! @brief MCAN0 ready */ +#define DL_SYSCTL_STATUS_MCAN0_READY (SYSCTL_SYSSTATUS_MCAN0READY_TRUE) +/*! @brief Double Error Detect on Flash */ +#define DL_SYSCTL_STATUS_FLASH_DED (SYSCTL_SYSSTATUS_FLASHDED_TRUE) +/*! @brief Single Error Correction on Flash */ +#define DL_SYSCTL_STATUS_FLASH_SEC (SYSCTL_SYSSTATUS_FLASHSEC_TRUE) +/*! @brief Current Brown Out Reset minimum level */ +#define DL_SYSCTL_STATUS_BOR_LEVEL0 \ + (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN) +/*! @brief Current Brown Out Reset level 1 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL1 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1) +/*! @brief Current Brown Out Reset level 2 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL2 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2) +/*! @brief Current Brown Out Reset level 3 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL3 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK2X + * @{ + */ +/*! @brief Enable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_ENABLE) + +/*! @brief Disable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK1 + * @{ + */ +/*! @brief Enable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_ENABLE) + +/*! @brief Disable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK0 + * @{ + */ +/*! @brief Enable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_ENABLE) + +/*! @brief Disable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_DISABLE) +/** @}*/ + +/* clang-format on */ + +/*! @enum DL_SYSCTL_SYSPLL_MCLK */ +typedef enum { + /*! Use PLL CLK2x as source for MCLK */ + DL_SYSCTL_SYSPLL_MCLK_CLK2X = SYSCTL_SYSPLLCFG0_MCLK2XVCO_ENABLE, + /*! Use PLL CLK0 as source for MCLK */ + DL_SYSCTL_SYSPLL_MCLK_CLK0 = SYSCTL_SYSPLLCFG0_MCLK2XVCO_DISABLE, +} DL_SYSCTL_SYSPLL_MCLK; + +/*! @enum DL_SYSCTL_SYSPLL_REF */ +typedef enum { + /*! Use SYSOSC as input source for SYSPLL */ + DL_SYSCTL_SYSPLL_REF_SYSOSC = SYSCTL_SYSPLLCFG0_SYSPLLREF_SYSOSC, + /*! Use HFCLK as input source for SYSPLL */ + DL_SYSCTL_SYSPLL_REF_HFCLK = SYSCTL_SYSPLLCFG0_SYSPLLREF_HFCLK, +} DL_SYSCTL_SYSPLL_REF; + +/*! @enum DL_SYSCTL_SYSPLL_PDIV */ +typedef enum { + /*! Predivide input reference freq to PLL feedback loop by 1 */ + DL_SYSCTL_SYSPLL_PDIV_1 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV1, + /*! Predivide input reference freq to PLL feedback loop by 2 */ + DL_SYSCTL_SYSPLL_PDIV_2 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV2, + /*! Predivide input reference freq to PLL feedback loop by 4 */ + DL_SYSCTL_SYSPLL_PDIV_4 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV4, + /*! Predivide input reference freq to PLL feedback loop by 8 */ + DL_SYSCTL_SYSPLL_PDIV_8 = SYSCTL_SYSPLLCFG1_PDIV_REFDIV8, +} DL_SYSCTL_SYSPLL_PDIV; + +/** @enum DL_SYSCTL_SYSPLL_INPUT_FREQ */ +typedef enum { + /*! PLL feedback loop input clock frequency [4MHz, 8MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_4_8_MHZ = 0x41C4001C, + /*! PLL feedback loop input clock frequency [8MHz, 16MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ = 0x41C40024, + /*! PLL feedback loop input clock frequency [16MHz, 32MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ = 0x41C4002C, + /*! PLL feedback loop input clock frequency [32MHz, 48MHz] */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ = 0x41C40034, +} DL_SYSCTL_SYSPLL_INPUT_FREQ; + +/*! @brief Configuration struct for @ref DL_SYSCTL_configSYSPLL. */ +typedef struct { + /*! Output divider for CLK2x. [0x0,0xF,0x1] => [/1,/16,1] */ + uint32_t rDivClk2x; + /*! Output divider for CLK1. [0x0,0xF,0x1] => [/2,/32,2] */ + uint32_t rDivClk1; + /*! Output divider for CLK0. [0x0,0xF,0x1] => [/2,/32,2] */ + uint32_t rDivClk0; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK2X */ + uint32_t enableCLK2x; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK1 */ + uint32_t enableCLK1; + /*! PLL CLK2x output enabled or not. @ref DL_SYSCTL_SYSPLL_CLK0 */ + uint32_t enableCLK0; + /*! Select which PLL output to use as source for MCLK. @ref DL_SYSCTL_SYSPLL_MCLK */ + DL_SYSCTL_SYSPLL_MCLK sysPLLMCLK; + /*! SYSPLL reference clock source. @ref DL_SYSCTL_SYSPLL_REF */ + DL_SYSCTL_SYSPLL_REF sysPLLRef; + /*! PLL feedback clock divider. [0x01,0x7E,1] => [/2,/127,1] */ + uint32_t qDiv; + /*! PLL reference clock divider. @ref DL_SYSCTL_SYSPLL_PDIV */ + DL_SYSCTL_SYSPLL_PDIV pDiv; + /*! PLL feedback loop input clock frequency. Affects startup time and power consumption. @ref DL_SYSCTL_SYSPLL_INPUT_FREQ */ + DL_SYSCTL_SYSPLL_INPUT_FREQ inputFreq; +} DL_SYSCTL_SYSPLLConfig; + +/*! @enum DL_SYSCTL_NMI_IIDX */ +typedef enum { + /*! @brief NMI interrupt index for SRAM Double Error Detect */ + DL_SYSCTL_NMI_IIDX_SRAM_DED = SYSCTL_NMIIIDX_STAT_SRAMDED, + /*! @brief NMI interrupt index for Flash Double Error Detect */ + DL_SYSCTL_NMI_IIDX_FLASH_DED = SYSCTL_NMIIIDX_STAT_FLASHDED, + /*! @brief NMI interrupt index for LFCLK Monitor Fail */ + DL_SYSCTL_NMI_IIDX_LFCLK_FAIL = SYSCTL_NMIIIDX_STAT_LFCLKFAIL, + /*! @brief NMI interrupt index for Watchdog 1 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT1_FAULT = SYSCTL_NMIIIDX_STAT_WWDT1, + /*! @brief NMI interrupt index for Watchdog 0 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT0_FAULT = SYSCTL_NMIIIDX_STAT_WWDT0, + /*! @brief NMI interrupt index for early BOR */ + DL_SYSCTL_NMI_IIDX_BORLVL = SYSCTL_NMIIIDX_STAT_BORLVL, + /*! @brief NMI interrupt index for no interrupt pending */ + DL_SYSCTL_NMI_IIDX_NO_INT = SYSCTL_NMIIIDX_STAT_NO_INTR, +} DL_SYSCTL_NMI_IIDX; + +/** @}*/ + +/*! @enum DL_SYSCTL_IIDX */ +typedef enum { + /*! @brief Low Frequency Oscillator is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFOSC_GOOD = SYSCTL_IIDX_STAT_LFOSCGOOD, + /*! @brief Analog clocking consistency error */ + DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR = SYSCTL_IIDX_STAT_ANACLKERR, + /*! @brief Flash Single Error Correct */ + DL_SYSCTL_IIDX_FLASH_SEC = SYSCTL_IIDX_STAT_FLASHSEC, + + /*! @brief SRAM Single Error Correct */ + DL_SYSCTL_IIDX_SRAM_SEC = SYSCTL_IIDX_STAT_SRAMSEC, + + /*! @brief Low Frequency Crystal is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFXT_GOOD = SYSCTL_IIDX_STAT_LFXTGOOD, + /*! @brief High Frequency Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HFCLK_GOOD = SYSCTL_IIDX_STAT_HFCLKGOOD, + /*! @brief System PLL is stabilized and ready to use */ + DL_SYSCTL_IIDX_SYSPLL_GOOD = SYSCTL_IIDX_STAT_SYSPLLGOOD, + /*! @brief High Speed Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HSCLK_GOOD = SYSCTL_IIDX_STAT_HSCLKGOOD, +} DL_SYSCTL_IIDX; + +/*! @enum DL_SYSCTL_ERROR_BEHAVIOR */ +typedef enum { + /*! @brief The error event will trigger a SYSRST */ + DL_SYSCTL_ERROR_BEHAVIOR_RESET = 0x0, + /*! @brief The error event will trigger an NMI */ + DL_SYSCTL_ERROR_BEHAVIOR_NMI = 0x1, +} DL_SYSCTL_ERROR_BEHAVIOR; + +/*! @enum DL_SYSCTL_SYSOSC_FREQ */ +typedef enum { + /*! Use 4MHz for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_4M = (SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M), + /*! Use BASE (32MHz) for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_BASE = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE), + /*! User will trim the System Oscillator (SYSOSC) to 16MHz or 24MHz */ + DL_SYSCTL_SYSOSC_FREQ_USERTRIM = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER), +} DL_SYSCTL_SYSOSC_FREQ; + +/** @enum DL_SYSCTL_SYSOSC_USERTRIM_FREQ */ +typedef enum { + /*! Set SYSOSC user trim frequency target to 16MHz */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ_16M = + (SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC16M), + /*! Set SYSOSC user trim frequency target to 24MHz */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ_24M = + (SYSCTL_SYSOSCTRIMUSER_FREQ_SYSOSC24M), +} DL_SYSCTL_SYSOSC_USERTRIM_FREQ; + +/*! @brief Configuration struct for @ref DL_SYSCTL_configSYSOSCUserTrim. */ +typedef struct { + /*! Frequency Correcting Loop resistor divide value [0x0, 0x1FF] */ + uint32_t rDiv; + /*! Resistor fine trim [0x0, 0xF] */ + uint32_t resistorFine; + /*! Resistor coarse trim [0x0, 0x3F] */ + uint32_t resistorCoarse; + /*! Capacitor trim [0x0, 0x7] */ + uint32_t capacitor; + /*! SYSOSC user trim frequency target */ + DL_SYSCTL_SYSOSC_USERTRIM_FREQ freq; +} DL_SYSCTL_SYSOSCUserTrimConfig; + +/** @enum DL_SYSCTL_ULPCLK_DIV */ +typedef enum { + /*! ULPCLK is MCLK */ + DL_SYSCTL_ULPCLK_DIV_1 = (SYSCTL_MCLKCFG_UDIV_NODIVIDE), + /*! ULPCLK is MCLK divided by 2 */ + DL_SYSCTL_ULPCLK_DIV_2 = (SYSCTL_MCLKCFG_UDIV_DIVIDE2), +} DL_SYSCTL_ULPCLK_DIV; + +/** @enum DL_SYSCTL_LFXT_DRIVE_STRENGTH */ +typedef enum { + /*! Lowest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV), + /*! Lower Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWER = (SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV), + /*! Higher Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHER = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV), + /*! Highest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV), +} DL_SYSCTL_LFXT_DRIVE_STRENGTH; + +/*! @brief Configuration struct for @ref DL_SYSCTL_LFCLKConfig. */ +typedef struct { + /*! Enable if CAP is less than 3pF to reduce power consumption */ + bool lowCap; + /*! Enable to use monitor for LFXT, EXLF failure */ + bool monitor; + /*! Drive strength and power consumption option */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH xt1Drive; +} DL_SYSCTL_LFCLKConfig; + +/** @enum DL_SYSCTL_HFXT_RANGE */ +typedef enum { + /*! HFXT frequency range between 4 and 8 MHz */ + DL_SYSCTL_HFXT_RANGE_4_8_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8, + /*! HFXT frequency range between 8.01 and 16 MHz */ + DL_SYSCTL_HFXT_RANGE_8_16_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16, + /*! HFXT frequency range between 16.01 and 32 MHz */ + DL_SYSCTL_HFXT_RANGE_16_32_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32, + /*! HFXT frequency range between 32.01 and 48 MHz */ + DL_SYSCTL_HFXT_RANGE_32_48_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48, +} DL_SYSCTL_HFXT_RANGE; + +/*! @enum DL_SYSCTL_HSCLK_SOURCE */ +typedef enum { + /*! Use SYSPLL as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_SYSPLL = SYSCTL_HSCLKCFG_HSCLKSEL_SYSPLL, + /*! Use HFLK as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_HFCLK = SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK, + /*! Use USBFLL as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_USBFLL = SYSCTL_HSCLKCFG_USBFLL4HSCLK_USBFLL, +} DL_SYSCTL_HSCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MCLK source (default after reset) */ + DL_SYSCTL_MCLK_SOURCE_SYSOSC = SYSCTL_MCLKCFG_USEHSCLK_DISABLE, + /*! Use High Speed Clock (HSCLK) as MCLK source (HFCLK, PLL,...) */ + DL_SYSCTL_MCLK_SOURCE_HSCLK = SYSCTL_MCLKCFG_USEHSCLK_ENABLE, + /*! Use the Low Frequency Clock (LFCLK) as the clock source */ + DL_SYSCTL_MCLK_SOURCE_LFCLK = SYSCTL_MCLKCFG_USELFCLK_ENABLE, +} DL_SYSCTL_MCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_DIVIDER */ +typedef enum { + /*! Disable MCLK divider. Change SYSOSC freq only when MDIV is disabled */ + DL_SYSCTL_MCLK_DIVIDER_DISABLE = 0x0, + /*! Divide MCLK frequency by 2 */ + DL_SYSCTL_MCLK_DIVIDER_2 = 0x1, + /*! Divide MCLK frequency by 3 */ + DL_SYSCTL_MCLK_DIVIDER_3 = 0x2, + /*! Divide MCLK frequency by 4 */ + DL_SYSCTL_MCLK_DIVIDER_4 = 0x3, + /*! Divide MCLK frequency by 5 */ + DL_SYSCTL_MCLK_DIVIDER_5 = 0x4, + /*! Divide MCLK frequency by 6 */ + DL_SYSCTL_MCLK_DIVIDER_6 = 0x5, + /*! Divide MCLK frequency by 7 */ + DL_SYSCTL_MCLK_DIVIDER_7 = 0x6, + /*! Divide MCLK frequency by 8 */ + DL_SYSCTL_MCLK_DIVIDER_8 = 0x7, + /*! Divide MCLK frequency by 9 */ + DL_SYSCTL_MCLK_DIVIDER_9 = 0x8, + /*! Divide MCLK frequency by 10 */ + DL_SYSCTL_MCLK_DIVIDER_10 = 0x9, + /*! Divide MCLK frequency by 11 */ + DL_SYSCTL_MCLK_DIVIDER_11 = 0xA, + /*! Divide MCLK frequency by 12 */ + DL_SYSCTL_MCLK_DIVIDER_12 = 0xB, + /*! Divide MCLK frequency by 13 */ + DL_SYSCTL_MCLK_DIVIDER_13 = 0xC, + /*! Divide MCLK frequency by 14 */ + DL_SYSCTL_MCLK_DIVIDER_14 = 0xD, + /*! Divide MCLK frequency by 15 */ + DL_SYSCTL_MCLK_DIVIDER_15 = 0xE, + /*! Divide MCLK frequency by 16 */ + DL_SYSCTL_MCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_MCLK_DIVIDER; + +/** @enum DL_SYSCTL_CLK_OUT_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC, + /*! Use Ultra Low Power Clock (ULPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_ULPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK, + /*! Use Low Frequency Clock (LFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_LFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK, + /*! Use Middle Frequency Precision Clock (MFPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_MFPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK, + /*! Use High Frequency Clock (HFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_HFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK, + /*! Use System PLL Output 1 (SYSPLLOUT1) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSPLLOUT1 = SYSCTL_GENCLKCFG_EXCLKSRC_SYSPLLOUT1, +} DL_SYSCTL_CLK_OUT_SOURCE; + +/** @enum DL_SYSCTL_CLK_OUT_DIVIDE */ +typedef enum { + /*! Disable the External Clock (CLK_OUT) output divider */ + DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE = SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU, + /*! Divide External Clock (CLK_OUT) output by 2 */ + DL_SYSCTL_CLK_OUT_DIVIDE_2 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2, + /*! Divide External Clock (CLK_OUT) output by 4 */ + DL_SYSCTL_CLK_OUT_DIVIDE_4 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4, + /*! Divide External Clock (CLK_OUT) output by 6 */ + DL_SYSCTL_CLK_OUT_DIVIDE_6 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6, + /*! Divide External Clock (CLK_OUT) output by 8 */ + DL_SYSCTL_CLK_OUT_DIVIDE_8 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8, + /*! Divide External Clock (CLK_OUT) output by 10 */ + DL_SYSCTL_CLK_OUT_DIVIDE_10 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10, + /*! Divide External Clock (CLK_OUT) output by 12 */ + DL_SYSCTL_CLK_OUT_DIVIDE_12 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12, + /*! Divide External Clock (CLK_OUT) output by 14 */ + DL_SYSCTL_CLK_OUT_DIVIDE_14 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14, + /*! Divide External Clock (CLK_OUT) output by 16 */ + DL_SYSCTL_CLK_OUT_DIVIDE_16 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16, +} DL_SYSCTL_CLK_OUT_DIVIDE; + +/** @enum DL_SYSCTL_MFPCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC, + /*! Use High Frequency Clock (HFCLK) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK, +} DL_SYSCTL_MFPCLK_SOURCE; + +/** @enum DL_SYSCTL_HFCLK_MFPCLK_DIVIDER */ +typedef enum { + /*! HFCLK is not divided before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_DISABLE = 0x0, + /*! Divide HFCLK by 2 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_2 = 0x1, + /*! Divide HFCLK by 3 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_3 = 0x2, + /*! Divide HFCLK by 4 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_4 = 0x3, + /*! Divide HFCLK by 5 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_5 = 0x4, + /*! Divide HFCLK by 6 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6 = 0x5, + /*! Divide HFCLK by 7 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_7 = 0x6, + /*! Divide HFCLK by 8 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_8 = 0x7, + /*! Divide HFCLK by 9 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_9 = 0x8, + /*! Divide HFCLK by 10 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_10 = 0x9, + /*! Divide HFCLK by 11 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_11 = 0xA, + /*! Divide HFCLK by 12 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_12 = 0xB, + /*! Divide HFCLK by 13 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_13 = 0xC, + /*! Divide HFCLK by 14 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_14 = 0xD, + /*! Divide HFCLK by 15 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_15 = 0xE, + /*! Divide HFCLK by 16 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_HFCLK_MFPCLK_DIVIDER; + +/** @enum DL_SYSCTL_FCC_TRIG_TYPE */ +typedef enum { + /*! FCC trigger is rising-edge to rising-edge pulse */ + DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE = SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE, + /*! FCC trigger is active-high pulse level */ + DL_SYSCTL_FCC_TRIG_TYPE_LEVEL = SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL, +} DL_SYSCTL_FCC_TRIG_TYPE; + +/** @enum DL_SYSCTL_FCC_TRIG_SOURCE */ +typedef enum { + /*! FCC trigger source is FCC_IN external pin */ + DL_SYSCTL_FCC_TRIG_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN, + /*! FCC trigger source is LFCLK */ + DL_SYSCTL_FCC_TRIG_SOURCE_LFCLK = SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK, +} DL_SYSCTL_FCC_TRIG_SOURCE; + +/** @enum DL_SYSCTL_FCC_CLOCK_SOURCE */ +typedef enum { + /*! FCC clock source to capture is MCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_MCLK = SYSCTL_GENCLKCFG_FCCSELCLK_MCLK, + /*! FCC clock source to capture is SYSOSC */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC, + /*! FCC clock source to capture is HFCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK, + /*! FCC clock source to capture is CLK_OUT */ + DL_SYSCTL_FCC_CLOCK_SOURCE_CLK_OUT = SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK, + /*! FCC clock source to capture is SYSPLLCLK0 */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK0 = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK0, + /*! FCC clock source to capture is SYSPLLCLK1 */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK1 = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK1, + /*! FCC clock source to capture is SYSPLLCLK2X */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSPLLCLK2X = + SYSCTL_GENCLKCFG_FCCSELCLK_SYSPLLCLK2X, + /*! FCC clock source to capture is FCC_IN */ + DL_SYSCTL_FCC_CLOCK_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN, + /*! FCC clock source to capture is USBFLL */ + DL_SYSCTL_FCC_CLOCK_SOURCE_USBFLL = SYSCTL_GENCLKCFG_FCCSELCLK_USBFLL, +} DL_SYSCTL_FCC_CLOCK_SOURCE; + +/** @enum DL_SYSCTL_FCC_TRIG_CNT */ +typedef enum { + /*! One monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_01 = + ((uint32_t) 0 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_02 = + ((uint32_t) 1 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_03 = + ((uint32_t) 2 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_04 = + ((uint32_t) 3 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_05 = + ((uint32_t) 4 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_06 = + ((uint32_t) 5 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_07 = + ((uint32_t) 6 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_08 = + ((uint32_t) 7 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_09 = + ((uint32_t) 8 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Ten monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_10 = + ((uint32_t) 9 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eleven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_11 = + ((uint32_t) 10 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twelve monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_12 = + ((uint32_t) 11 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_13 = + ((uint32_t) 12 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fourteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_14 = + ((uint32_t) 13 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fifteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_15 = + ((uint32_t) 14 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Sixteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_16 = + ((uint32_t) 15 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seventeen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_17 = + ((uint32_t) 16 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eighteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_18 = + ((uint32_t) 17 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nineteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_19 = + ((uint32_t) 18 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_20 = + ((uint32_t) 19 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_21 = + ((uint32_t) 20 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_22 = + ((uint32_t) 21 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_23 = + ((uint32_t) 22 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_24 = + ((uint32_t) 23 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_25 = + ((uint32_t) 24 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_26 = + ((uint32_t) 25 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_27 = + ((uint32_t) 26 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_28 = + ((uint32_t) 27 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_29 = + ((uint32_t) 28 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_30 = + ((uint32_t) 29 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_31 = + ((uint32_t) 30 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_32 = + ((uint32_t) 31 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), +} DL_SYSCTL_FCC_TRIG_CNT; + +/** @enum DL_SYSCTL_VBOOST */ +typedef enum { + /*! VBOOST enabled only when COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONDEMAND = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND, + /*! VBOOST enabled in RUN/SLEEP, and in STOP/STANDBY if COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONACTIVE = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE, + /*! VBOOST enabled in all power modes except SHUTDOWN for fastest startup */ + DL_SYSCTL_VBOOST_ONALWAYS = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS, +} DL_SYSCTL_VBOOST; + +/** @enum DL_SYSCTL_FLASH_WAIT_STATE */ +typedef enum { + /*! 0 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_0 = ((uint32_t) 0x00000000U), + /*! 1 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_1 = ((uint32_t) 0x00000100U), + /*! 2 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_2 = ((uint32_t) 0x00000200U), +} DL_SYSCTL_FLASH_WAIT_STATE; + +/** @enum DL_SYSCTL_POWER_POLICY_RUN_SLEEP */ +typedef enum { + /*! RUN/SLEEP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED = 0x0, + /*! Enable RUN0/SLEEP0 power mode policy. */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP0 = 0x1, + /*! Enable the RUN1/SLEEP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP1 = 0x2, + /*! Enable the RUN2/SLEEP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_RUN_SLEEP; + +/** @enum DL_SYSCTL_POWER_POLICY_STOP */ +typedef enum { + /*! STOP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED = 0x0, + /*! Enable the STOP0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP0 = 0x1, + /*! Enable the STOP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP1 = 0x2, + /*! Enable the STOP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_STOP; + +/** @enum DL_SYSCTL_POWER_POLICY_STANDBY */ +typedef enum { + /*! STANDBY power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED = 0x0, + /*! Enable the STANDBY0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY0 = 0x1, + /*! Enable the STANDBY1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY1 = 0x2, +} DL_SYSCTL_POWER_POLICY_STANDBY; + +/** @enum DL_SYSCTL_BOR_THRESHOLD_LEVEL */ +typedef enum { + /*! BOR0 threshold level. This is the minimum allowed threshold. + * A BOR0- violation will force a re-boot. */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_0 = SYSCTL_BORTHRESHOLD_LEVEL_BORMIN, + /*! BOR1 threshold level. A BOR1- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_1 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1, + /*! BOR2 threshold level. A BOR2- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_2 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2, + /*! BOR3 threshold level. A BOR3- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_3 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3, +} DL_SYSCTL_BOR_THRESHOLD_LEVEL; + +/** @enum DL_SYSCTL_SHUTDOWN_STORAGE_BYTE */ +typedef enum { + /*! Shutdown Storage Byte 0 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_0 = 0x0, + /*! Shutdown Storage Byte 1 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_1 = 0x1, + /*! Shutdown Storage Byte 2 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_2 = 0x2, + /*! Shutdown Storage Byte 3 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_3 = 0x3, +} DL_SYSCTL_SHUTDOWN_STORAGE_BYTE; + +/** @enum DL_SYSCTL_RESET_CAUSE */ +typedef enum { + /*! No Reset Since Last Read */ + DL_SYSCTL_RESET_CAUSE_NO_RESET = SYSCTL_RSTCAUSE_ID_NORST, + /*! (VDD < POR- violation) or (PMU trim parity fault) or (SHUTDNSTOREx parity fault) */ + DL_SYSCTL_RESET_CAUSE_POR_HW_FAILURE = SYSCTL_RSTCAUSE_ID_PORHWFAIL, + /*! NRST pin reset (>1s) */ + DL_SYSCTL_RESET_CAUSE_POR_EXTERNAL_NRST = SYSCTL_RSTCAUSE_ID_POREXNRST, + /*! Software-triggered POR */ + DL_SYSCTL_RESET_CAUSE_POR_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_PORSW, + /*! VDD < BOR- violation */ + DL_SYSCTL_RESET_CAUSE_BOR_SUPPLY_FAILURE = SYSCTL_RSTCAUSE_ID_BORSUPPLY, + /*! Wake from SHUTDOWN */ + DL_SYSCTL_RESET_CAUSE_BOR_WAKE_FROM_SHUTDOWN = + SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN, + /*! Non-PMU trim parity fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_NON_PMU_PARITY_FAULT = + SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY, + /*! Fatal clock fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_CLOCK_FAULT = SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL, + /*! Software-triggered BOOTRST */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_BOOTSW, + /*! NRST pin reset (<1s) */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_EXTERNAL_NRST = + SYSCTL_RSTCAUSE_ID_BOOTEXNRST, + /*! BSL exit */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_EXIT = SYSCTL_RSTCAUSE_ID_SYSBSLEXIT, + /*! BSL entry */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_ENTRY = SYSCTL_RSTCAUSE_ID_SYSBSLENTRY, + /*! WWDT0 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT0_VIOLATION = + SYSCTL_RSTCAUSE_ID_BOOTWWDT0, + /*! WWDT1 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT1_VIOLATION = SYSCTL_RSTCAUSE_ID_SYSWWDT1, + /*! Uncorrectable flash ECC error */ + DL_SYSCTL_RESET_CAUSE_SYSRST_FLASH_ECC_ERROR = + SYSCTL_RSTCAUSE_ID_SYSFLASHECC, + /*! CPULOCK violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_CPU_LOCKUP_VIOLATION = + SYSCTL_RSTCAUSE_ID_SYSCPULOCK, + /*! Debug-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSDBG, + /*! Software-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSSW, + /*! Debug-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUDBG, + /*! Software-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUSW, +} DL_SYSCTL_RESET_CAUSE; + +/** @enum DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL */ +typedef enum { + /*! DATA Bank Read Write Protect Firewall both RW allowed */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_ENABLED = 0x0, + /*! DATA Bank Read Write Protect Firewall read only */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_R_ONLY = 0x1, + /*! DATA Bank Read Write Protect Firewall both RW disabled */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_DISABLED = 0x2, +} DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL; + +/** @enum DL_SYSCTL_USBCLK_SOURCE */ +typedef enum { + /*! Use USB Frequency Lock Loop as USBCLK source */ + DL_SYSCTL_USBCLK_SOURCE_USBFLL = SYSCTL_GENCLKCFG_USBCLKSRC_USBFLLCLK, + /*! Use SYSPLL1 as USBCLK source */ + DL_SYSCTL_USBCLK_SOURCE_PLLCLK1 = SYSCTL_GENCLKCFG_USBCLKSRC_SYSPLLOUT1, +} DL_SYSCTL_USBCLK_SOURCE; + +/** @enum DL_SYSCTL_USBFLL_REFERENCE */ +typedef enum { + /*! Use Start-of-Frame package (SOF) as USBFLL reference source */ + DL_SYSCTL_USBFLL_REFERENCE_SOF = ((uint32_t) 0x00000000U), + /*! Use LFXT as USBFLL reference source */ + DL_SYSCTL_USBFLL_REFERENCE_LFXT = SYSCTL_USBFLLCTL_REFSEL_LFCLK, +} DL_SYSCTL_USBFLL_REFERENCE; + +/** + * @brief Enable sleep on exit + * + * Enables sleep on exit when the CPU moves from handler mode to thread mode. + * By enabling, allows an interrupt driven application to avoid returning to + * an empty main application. + */ +__STATIC_INLINE void DL_SYSCTL_enableSleepOnExit(void) +{ + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; +} + +/** + * @brief Disable sleep on exit + * + * Disables sleep on exit when the CPU moves from handler mode to thread mode. + */ +__STATIC_INLINE void DL_SYSCTL_disableSleepOnExit(void) +{ + SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Check if sleep on exit is enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSleepOnExitEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SLEEPONEXIT_Msk) == SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable send event on pending bit + * + * When enabled, any enabled event and all interrupts (including disabled + * interrupts) can wakeup the processor. + */ +__STATIC_INLINE void DL_SYSCTL_enableEventOnPend(void) +{ + SCB->SCR |= SCB_SCR_SEVONPEND_Msk; +} + +/** + * @brief Disable send event on pending bit + * + * When disabled, only enabled interrupts or events can wake up the processor. + * Disabled interrupts are excluded. + */ +__STATIC_INLINE void DL_SYSCTL_disableEventOnPend(void) +{ + SCB->SCR &= ~(SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Check if send event on pending bit is enabled + * + * @return Returns the enabled status of the send event on pending bit + * + * @retval true Send event on pending bit is enabled + * @retval false Send event on pending bit is disabled + */ +__STATIC_INLINE bool DL_SYSCTL_isEventOnPendEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SEVONPEND_Msk) == SCB_SCR_SEVONPEND_Msk); +} + +/*! + * @brief Change MCLK source + * + * To ensure good clocking behavior, these are the recommended steps for transition. + * Valid sources and destinations: LFCLK, SYSOSC, HSCLK + * + * Depending on current MCLK source, steps to switch to next MCLK source can vary. + * This is a macro that redirects to the different possible transitions. + * + * Only valid for RUN modes. In low power modes, MCLK transitions are handled by hardware. + * + * @note Different transition APIs may require different input parameters + * Transitions between LFCLK and HSCLK requires going through SYSOSC. + * + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK + * @sa DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK + * @sa DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC + */ +#define DL_SYSCTL_setMCLKSource(current, next, ...) \ + DL_SYSCTL_switchMCLKfrom##current##to##next(__VA_ARGS__); + +/** + * @brief Change MCLK source from SYSOSC to LFCLK + * + * @pre If disabling SYSOSC, high speed oscillators (SYSPLL, HFXT...) must be disabled beforehand. + * @post MCLK source is switched to LFCLK, function will busy-wait until confirmed. + * + * @param[in] disableSYSOSC Whether to leave SYSOSC running or not + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC); + +/** + * @brief Change MCLK source from LFCLK to SYSOSC + * + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + */ +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void); + +/** + * @brief Change MCLK source from SYSOSC to HSCLK + * + * @pre The desired HSCLK source is enabled beforehand (SYSPLL, HFXT, HFCLK_IN). + * @post MCLK source is switched to HSCLK, function will busy-wait until confirmed. + * + * @param[in] source Desired high-speed clock source + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source); + +/** + * @brief Change MCLK source from HSCLK to SYSOSC + * + * @pre MCLK is sourced from a valid, running HSCLK source (SYSPLL, HFXT, HFCLK_IN) + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + * + * @note No HSCLK sources are disabled by this function + */ +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void); + +/** + * @brief Configures the USBFLL reference source and enables the USBFLL + * + * @param[in] refSource Desired USBFLL reference source, one of +* @ref DL_SYSCTL_USBFLL_REFERENCE. + */ +void DL_SYSCTL_configUSBFLL(DL_SYSCTL_USBFLL_REFERENCE refSource); + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN0/SLEEP0 + * + * In RUN0, the MCLK and the CPUCLK run from a fast clock source (SYSOSC, + * HFCLK, or SYSPLL). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN0SLEEP0(void) +{ + DL_SYSCTL_setMCLKSource(LFCLK, SYSOSC); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN1/SLEEP1 + * + * In RUN1, the MCLK and the CPUCLK run from LFCLK (at 32kHz) to reduce active + * power, but SYSOSC is left enabled to service analog modules such as an ADC, + * DAC, OPA, or COMP (in HS mode). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN1SLEEP1(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) false); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN2/SLEEP2 + * + * In RUN2, the MCLK and the CPUCLK run from LFCLK (at 32kHz), and SYSOSC is + * completely disabled to save power. This is the lowest power state with + * the CPU running + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @note Since this turns off SYSOSC, HSCLK sources MUST be disabled before calling + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN2SLEEP2(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) true); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Get the RUN/SLEEP mode power policy + * + * Get which RUN/SLEEP power policy has been set. + * + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. + * + * @return Returns the current RUN/SLEEP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_RUN_SLEEP + + */ +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void); + +/** + * @brief Set the STOP mode power policy to STOP0 + * + * In STOP0, the SYSOSC is left running at the current frequency when entering + * STOP mode (either 32MHz, 24MHz, 16MHz, or 4MHz). ULPCLK is always limited + * to 4MHz automatically by hardware, but SYSOSC is not disturbed to support + * consistent operation of analog peripherals such as the ADC, OPA, or COMP. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~( + SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK | SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP1 + * + * In STOP1, the SYSOSC is gear shifted from its current frequency to 4MHz for + * the lowest power consumption in STOP mode with SYSOSC running. SYSOSC and + * ULPCLK both run at 4MHz. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP2 + * + * In STOP2, the SYSOSC is disabled and the ULPCLK is sourced from LFCLK at + * 32kHz. This is the lowest power state in STOP mode. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP2(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK); + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLESTOP_MASK; +} + +/** + * @brief Get the STOP mode power policy + * + * Get which STOP power policy has been set. + * + * @return Returns the current STOP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STOP if a STOP power policy + */ +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void); + +/** + * @brief Set the STANDBY mode power policy to STANDBY0 + * + * In STANDBY0, all PD0 peripherals receive the ULPCLK and LFCLK, and the RTC + * receives RTCCLK. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_STOPCLKSTBY_MASK); +} + +/** + * @brief Set the STANDBY mode power policy to STANDBY1 + * + * In STANDBY1, only TIMG0 and TIMG1 receive ULPCLK/LFCLK. The RTC continues + * to receive RTCCLK. A TIMG0/1 interrupt, RTC interrupt, or ADC trigger in + * STANDBY1 always triggers an asynchronous fast clock request to wake the + * system. Other PD0 peripherals (such as UART, I2C, GPIO, and COMP) can also + * wake the system upon an external event through an asynchronous fast clock + * request, but they are not actively clocked in STANDBY1. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_STOPCLKSTBY_MASK; +} + +/** + * @brief Get the STANDBY mode power policy + * + * Get which STANDBY power policy has been set. + * + * @return Returns the current STANDBY mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STANDBY + */ +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void); + +/** + * @brief Set power policy to SHUTDOWN mode + * + * In SHUTDOWN mode, no clocks are available. The core regulator is completely + * disabled and all SRAM and register contents are lost, with the exception of + * the 4 bytes of general purpose memory in SYSCTL which may be used to store + * state information. The BOR and bandgap circuit are disabled. The device may + * wake up via a wake-up capable IO, a debug connection, or NRST. SHUTDOWN mode + * has the lowest current consumption of any operating mode. Exiting SHUTDOWN + * mode triggers a BOR. + * + * There is only one SHUTDOWN mode policy option: SHUTDOWN. + * + * @post This API does not actually enter SHUTDOWN mode. After using this API + * to enable SHUTDOWN mode, to enter SHUTDOWN mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySHUTDOWN(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_SHUTDOWN; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Set the brown-out reset (BOR) threshold level + * + * Note that this API does NOT activate the BOR threshold. After setting the + * threshold level with this API, call @ref DL_SYSCTL_activateBORThreshold + * to actually activate the new threshold. + * + * During startup, the BOR threshold defaults to BOR0 (the lowet value) to + * ensure the device always starts at the specified VDD minimum. After boot, + * the BOR threshold level can be configured to a different level. When the + * BOR threshold is BOR0, a BOR0- violation always generates a BOR- violation + * signal to SYSCTL, generating a BOR level reset. When the BOR threshold is + * re-configured to BOR1, BOR2, or BOR3 the BOR circuit will generate a SYSCTL + * interrupt rather than asserting a BOR- violation. This may be used to give + * the application an indication that the supply has dropped below a certain + * level without causing a reset. If the BOR is in interrupt mode (threshold + * level of BOR1-3), and VDD drops below the respective BORx- level, an + * interrupt will be generated and the BOR circuit will automatically switch + * the BOR threshold level to BOR0 to ensure that a BOR- violation is + * asserted if VDD drops below BOR0-. + * + * @param[in] thresholdLevel The BOR threshold level to set. + * One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL. + * + * @post DL_SYSCTL_activateBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_setBORThreshold( + DL_SYSCTL_BOR_THRESHOLD_LEVEL thresholdLevel) +{ + SYSCTL->SOCLOCK.BORTHRESHOLD = (uint32_t) thresholdLevel; +} + +/** + * @brief Get the brown-out reset (BOR) threshold level + * + * @return Returns the current BOR threshold level. + * + * @retval One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL + */ +__STATIC_INLINE DL_SYSCTL_BOR_THRESHOLD_LEVEL DL_SYSCTL_getBORThreshold(void) +{ + return (DL_SYSCTL_BOR_THRESHOLD_LEVEL)(SYSCTL->SOCLOCK.BORTHRESHOLD); +} + +/** + * @brief Activate the BOR threshold level + * + * Attempts to change the active BOR mode to the BOR threshold that was set + * via @ref DL_SYSCTL_setBORThreshold. + * + * Setting this bit also clears any prior BOR violation status indications. + * + * After calling this API, the change can be validated by calling + * @ref DL_SYSCTL_getStatus and checking the return value. + * + * @pre DL_SYSCTL_setBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_activateBORThreshold(void) +{ + SYSCTL->SOCLOCK.BORCLRCMD = + SYSCTL_BORCLRCMD_KEY_VALUE | SYSCTL_BORCLRCMD_GO_TRUE; +} + +/** + * @brief Resets the device + * + * Resets the device using the type of reset selected. This function does not + * return, the reset will happen immediately. + * + * @param[in] resetType Type of reset to perform. One of @ref + * DL_SYSCTL_RESET. + */ +__STATIC_INLINE void DL_SYSCTL_resetDevice(uint32_t resetType) +{ + SYSCTL->SOCLOCK.RESETLEVEL = resetType; + SYSCTL->SOCLOCK.RESETCMD = + SYSCTL_RESETCMD_KEY_VALUE | SYSCTL_RESETCMD_GO_TRUE; +} + +/** + * @brief Enable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_enableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK |= interruptMask; +} + +/** + * @brief Disable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_disableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which SYSCTL interrupts are enabled + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are enabled + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterrupts(uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SYSCTL interrupts + * + * Checks if any of the SYSCTL interrupts that were previously enabled are + * pending. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + * + * @sa DL_SYSCTL_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @return The highest priority pending SYSCTL interrupt + * + * @retval One of @ref DL_SYSCTL_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_IIDX DL_SYSCTL_getPendingInterrupt(void) +{ + return (DL_SYSCTL_IIDX)(SYSCTL->SOCLOCK.IIDX); +} + +/** + * @brief Clear pending SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_clearInterruptStatus(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.ICLR = interruptMask; +} + +/** + * @brief Check interrupt flag of any SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_NMI. + * + * @return Which of the requested SYSCTL non-maskable interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_NMI values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.NMIRIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @return The highest priority pending SYSCTL non-maskable interrupt + * + * @retval One of @ref DL_SYSCTL_NMI_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_NMI_IIDX DL_SYSCTL_getPendingNonMaskableInterrupt( + void) +{ + return (DL_SYSCTL_NMI_IIDX)(SYSCTL->SOCLOCK.NMIIIDX); +} + +/** + * @brief Clear pending SYSCTL non-maskable interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_NMI. + */ +__STATIC_INLINE void DL_SYSCTL_clearNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.NMIICLR = interruptMask; +} + +/** + * @brief Set the behavior when a Flash ECC double error detect (DED) occurs + * + * Configures whether a Flash ECC double error detect (DED) will trigger + * a SYSRST or an NMI (non-maskable interrupt). By default, this error will + * trigger a SYSRST. + * + * @param[in] behavior The behavior when a Flash ECC DED error occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setFlashDEDErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a Flash ECC double error detect (DED) occurs + * + * By default, this error will trigger a SYSRST. + * + * @return The behavior when a Flash ECC DED error occurs + * + * 3@retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getFlashDEDErrorBehavior( + void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the behavior when a WWDT0 error occurs + * + * Configures whether a WWDT0 error will trigger a BOOTRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a BOOTRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT0ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT0 error occurs + * + * By default, this error will trigger a BOOTRST. + * + * @return The behavior when a WWDT0 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT0ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the behavior when a WWDT1 error occurs + * + * Configures whether a WWDT1 error will trigger a SYSRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a SYSRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT1ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT1 error occurs + * + * By default, this error will trigger a SYSRST. + * + * @return The behavior when a WWDT1 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT1ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP1RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the Main Clock (MCLK) divider (MDIV) + * + * Additionally, can use this function to disable MDIV. MDIV must be disabled + * before changing SYSOSC frequency. + * + * MDIV is not valid if MCLK source is HSCLK. + * MDIV is not used if MCLK source if LFCLK. + * + * @param[in] divider Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is + * HSCLK, a don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE void DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_MDIV_MASK); +} +/** + * @brief Get the Main Clock (MCLK) divider (MDIV) + * + * @return The value of the Main Clock (MCLK) divider (MDIV) + * + * @retval Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is HSCLK, a + * don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE DL_SYSCTL_MCLK_DIVIDER DL_SYSCTL_getMCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_MDIV_MASK; + + return (DL_SYSCTL_MCLK_DIVIDER)(divider); +} + +/** + * @brief Get the source for the Main Clock (MCLK) + * + * @return The source for the Main Clock (MCLK) + * + * @retval One of @ref DL_SYSCTL_MCLK_SOURCE + */ +__STATIC_INLINE DL_SYSCTL_MCLK_SOURCE DL_SYSCTL_getMCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.MCLKCFG & + (SYSCTL_MCLKCFG_USEHSCLK_MASK | SYSCTL_MCLKCFG_USELFCLK_MASK); + + return (DL_SYSCTL_MCLK_SOURCE)(source); +} + +/** + * @brief Set the target frequency of the System Oscillator (SYSOSC) + * + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * + * The System Oscillator (SYSOSC) is an on-chip, accurate, configurable + * oscillator with factory trimmed support for 32MHz (base frequency) and 4MHz + * (low frequency) operation. + * It can also operate at 16MHz or 24MHz by using the + * @ref DL_SYSCTL_configSYSOSCUserTrim function instead. + * + * SYSOSC provides a flexible high-speed clock source for the system in cases + * where the HFXT is either not present or not used. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] freq Target frequency to use for the System Oscillator (SYSOSC). + * @ref DL_SYSCTL_SYSOSC_FREQ_4M or @ref DL_SYSCTL_SYSOSC_FREQ_BASE. + * + * @sa DL_SYSCTL_configSYSOSCUserTrim + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ freq) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, (uint32_t) freq, + SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Trim the System Oscillator (SYSOSC) to 16MHz or 24MHz + * + * The trim values supplied in the config struct must be determined by + * experimentation. Please refer to the "SYSOSC User Trim Procedure" section + * in the CKM Technical Reference Manual. + * Each device must be trimmed individually for accuracy. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] config Pointer to the SYSOSC user trim configuration struct + * @ref DL_SYSCTL_SYSOSCUserTrimConfig. + * + * @sa DL_SYSCTL_setSYSOSCFreq + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_configSYSOSCUserTrim( + const DL_SYSCTL_SYSOSCUserTrimConfig *config) +{ + SYSCTL->SOCLOCK.SYSOSCTRIMUSER = + ((config->rDiv << SYSCTL_SYSOSCTRIMUSER_RDIV_OFS) & + SYSCTL_SYSOSCTRIMUSER_RDIV_MASK) | + ((config->resistorFine << SYSCTL_SYSOSCTRIMUSER_RESFINE_OFS) & + SYSCTL_SYSOSCTRIMUSER_RESFINE_MASK) | + ((config->resistorCoarse << SYSCTL_SYSOSCTRIMUSER_RESCOARSE_OFS) & + SYSCTL_SYSOSCTRIMUSER_RESCOARSE_MASK) | + (config->capacitor << SYSCTL_SYSOSCTRIMUSER_CAP_OFS) | + ((uint32_t) config->freq); + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, + SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER, SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Get the target frequency of the System Oscillator (SYSOSC) + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * This function matches what is input by @ref DL_SYSCTL_setSYSOSCFreq. + * + * @return The target frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getTargetSYSOSCFreq(void) +{ + uint32_t freq = SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_FREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Get the current frequency of the System Oscillator (SYSOSC) + * Current/actual SYSOSC frequency may be different than target/desired SYSOSC + * frequency during gear shift and other operations. + * + * @return The current frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getCurrentSYSOSCFreq(void) +{ + uint32_t freq = + SYSCTL->SOCLOCK.CLKSTATUS & SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Returns status of the different clocks in CKM + * + * @return Full status of all clock selections + * + * @retval Bitwise OR of @ref DL_SYSCTL_CLK_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getClockStatus(void) +{ + return (SYSCTL->SOCLOCK.CLKSTATUS); +} + +/** + * @brief Returns general status of SYSCTL + * + * @return Full status of all general conditions in SYSCTL + * + * @retval Bitwise OR of @ref DL_SYSCTL_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getStatus(void) +{ + return (SYSCTL->SOCLOCK.SYSSTATUS); +} + +/** + * @brief Clear the ECC error bits in SYSSTATUS + * + * The ECC error bits in SYSSTATUS are sticky (they remain set when an ECC + * error occurs even if future reads do not have errors), and can be + * cleared through this API. + */ +__STATIC_INLINE void DL_SYSCTL_clearECCErrorStatus(void) +{ + SYSCTL->SOCLOCK.SYSSTATUSCLR = + (SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR | SYSCTL_SYSSTATUSCLR_KEY_VALUE); +} + +/** + * @brief Configure SYSPLL output frequencies + * + * @pre SYSPLL is disabled (SYSPLLOFF in CLKSTATUS) + * @pre SYSOSC is running at base frequency (32MHz) even if HFCLK is the + * SYSPLL reference + * @post SYSPLL has completed startup and outputs chosen frequencies + * + * @note For practical purposes, it is not required to wait until SYSPLL + * completes startup, but do not go into STOP/STANDBY or use SYSPLL + * until completed. + * + * @param[in] config Pointer to the SYSPLL configuration struct + * @ref DL_SYSCTL_SYSPLLConfig. Elements sysPLLRef, pDiv, and + * inputFreq control desired startup time versus power consumption. + */ +void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config); + +/** + * @brief Set the divider for the Ultra Low Power Clock (ULPCLK) + * + * The Ultra Low Power Clock (ULPCLK) is always sourced from the Main Clock + * (MCLK) but can be divided down to a lower frequency. The ULPCLK should + * always remain under 40MHz. + * + * The ULPCLK can be used to drive some peripherals on the system. + * + * @param[in] divider Clock divider for Ultra Low Power Clock (ULPCLK). One + * of @ref DL_SYSCTL_ULPCLK_DIV. + */ +__STATIC_INLINE void DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_UDIV_MASK); +} + +/** + * @brief Get divider used for the Ultra Low Power Clock (ULPCLK) + * + * @return The divider used for Ultra Low Power Clock (ULPCLK) + * + * @retval One of @ref DL_SYSCTL_ULPCLK_DIV. + */ +__STATIC_INLINE DL_SYSCTL_ULPCLK_DIV DL_SYSCTL_getULPCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_UDIV_MASK; + + return (DL_SYSCTL_ULPCLK_DIV)(divider); +} + +/** + * @brief Change LFCLK source to external crystal LFXT + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFXT is an ultra-low power crystal oscillator which supports driving a + * standard 32.768kHz watch crystal. + * + * To use the LFXT, a watch crystal must be populated between LFXIN and LFXOUT + * pins. Find more info in LFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure LFXT functionality for LFXIN and LFXOUT before + * calling this function. + * + * This basic implementation will busy-wait until LFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the LFXT is + * stabilizing. You can enable LFXTGOOD interrupt, or check CLKSTATUS.LFXTGOOD + * when convenient, as long as you do not switch the source via + * SETUSELFXT until LFXTGOOD is set. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFCLK_IN is disabled (default). + * + * @param[in] config Pointer to the LFCLK configuration struct + * @ref DL_SYSCTL_LFCLKConfig. + */ +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config); + +/** + * @brief Change LFCLK source to external digital LFCLK_IN + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFCLK_IN is a low frequency digital clock input compatible with 32.768kHz + * typical frequency digital square wave CMOS clock inputs (typical duty + * cycle of 50%). + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * LFCLK_IN. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFXT is disabled (default). + */ +__STATIC_INLINE void DL_SYSCTL_setLFCLKSourceEXLF(void) +{ + SYSCTL->SOCLOCK.EXLFCTL = + (SYSCTL_EXLFCTL_KEY_VALUE | SYSCTL_EXLFCTL_SETUSEEXLF_TRUE); +} + +/** + * @brief Change HFCLK source to external crystal HFXT with default parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * The HFXT startup time is set to ~0.512ms based on the TYP datasheet + * recommendation. Additionally, the HFCLK startup monitor is enabled. + * + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * To modify the default HFXT startup time or disable the startup monitor, use + * @ref DL_SYSCTL_setHFCLKSourceHFXTParams instead of this API. + * + * @param[in] range HFXT frequency range + */ +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range); + +/** + * @brief Change HFCLK source to external crystal HFXT with custom parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * If the HFCLK startup monitor is enabled, then the HFXT will be checked after + * the amount of time specified by the startupTime parameter. + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * If the HFCLK startup monitor is disabled, then this implementation will not + * check if the HFXT oscillator is stabilized. + * + * @param[in] range HFXT frequency range + * @param[in] startupTime HFXT startup time + * @param[in] monitorEnable Whether to enable the HFCLK startup monitor + + */ +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable); + +/** + * @brief Disable the SYSPLL + * + * If SYSPLL is already enabled, application software should not disable the + * SYSPLL until the SYSPLLGOOD or SYSPLOFF bit is set in the CLKSTATUS + * register, indicating that the SYSPLL transitioned to a stable active or a + * stable dead state. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableSYSPLL(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_SYSPLLEN_MASK); +} + +/** + * @brief Disable the HFXT + * + * If HFXT is already enabled, application software must verify that either an + * HFCLKGOOD indication or an HFCLKOFF (off/dead) indication in the CLKSTATUS + * register was asserted by hardware before attempting to disable the HFXT + * by clearing HFXTEN. When disabling the HFXT by clearing HFXTEN, the HFXT + * must not be re-enabled again until the HFCLKOFF bit in the CLKSTATUS + * register is set by hardware. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableHFXT(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_HFXTEN_MASK); +} + +/** + * @brief Change HFCLK source to external digital HFCLK_IN + * + * HFCLK_IN can be used to bypass the HFXT circuit and bring 4-48MHz typical + * frequency digital clock into the devce as HFCLK source instead of HFXT. + * + * HFCLK_IN is a digital clock input compatible with digital square wave CMOS + * clock inputs and should have typical duty cycle of 50%. + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * HFCLK_IN. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKSourceHFCLKIN(void) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE; +} + +/** + * @brief Get the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @return The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_HSCLK_SOURCE DL_SYSCTL_getHSCLKSource(void) +{ + uint32_t source = SYSCTL->SOCLOCK.HSCLKCFG & SYSCTL_HSCLKCFG_HSCLKSEL_MASK; + + return (DL_SYSCTL_HSCLK_SOURCE)(source); +} + +/** + * @brief Set the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @param[in] source The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setHSCLKSource(DL_SYSCTL_HSCLK_SOURCE source) +{ + SYSCTL->SOCLOCK.HSCLKCFG = (uint32_t) source; +} + +/** + * @brief Get the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @return The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_MFPCLK_SOURCE DL_SYSCTL_getMFPCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_MFPCLKSRC_MASK; + + return (DL_SYSCTL_MFPCLK_SOURCE)(source); +} + +/** + * @brief Set the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @param[in] source The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE source) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) source, + SYSCTL_GENCLKCFG_MFPCLKSRC_MASK); +} + +/** + * @brief Enable the Medium Frequency Clock (MFCLK) + * + * MFCLK provides a continuous 4MHz clock to drive certain peripherals on the system. + * The 4MHz rate is always derived from SYSOSC, and the divider is automatically + * applied to maintain the 4MHz rate regardless of SYSOSC frequency. + * MCLK is ideal for timers and serial interfaces which require a constant + * clock source in RUN/SLEEP/STOP power modes. + * + * MFCLK can only run if 3 conditions are met: + * + * 1) Power mode must be RUN, SLEEP, or STOP. + * 2) USEMFTICK register bit is set, which this function does + * 3) MDIV must be set to @ref DL_SYSCTL_MCLK_DIVIDER_DISABLE by @ref DL_SYSCTL_setMCLKDivider. + * + * If MCLK source is not SYSOSC, MCLK frequency must be >=32MHz for correct operation of MFCLK. + * + * @sa DL_SYSCTL_setMCLKDivider + * @sa DL_SYSCTL_getMCLKSource + * @sa DL_SYSCTL_getMCLKFreq + */ +__STATIC_INLINE void DL_SYSCTL_enableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEMFTICK_ENABLE; +} + +/** + * @brief Disable the Medium Frequency Clock (MFCLK) + */ +__STATIC_INLINE void DL_SYSCTL_disableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_USEMFTICK_ENABLE); +} + +/** + * @brief Enable the Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK provides a continuous 4MHz clock to the DAC. + * + * MFPCLK can be sources from either SYSOSC or HFCLK (HFXT or HFCLK_IN). + * + * The DAC does not have a clock selection mux. Its clock source is selected + * by configuring MFPCLK. + * + * @sa DL_SYSCTL_disableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_enableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_MFPCLKEN_ENABLE; +} + +/** + * @brief Disable the Middle Frequency Precision Clock (MFPCLK) + * @sa DL_SYSCTL_enableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_disableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_MFPCLKEN_ENABLE); +} + +/** + * @brief Set the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @param[in] divider The divider of HFCLK for MFPCLK + * One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKDividerForMFPCLK( + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + ((uint32_t) divider << SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS), + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK); +} + +/** + * @brief Get the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @return Returns the divider for HFCLK for MFPCLK + * + * @retval One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER + */ +__STATIC_INLINE DL_SYSCTL_HFCLK_MFPCLK_DIVIDER +DL_SYSCTL_getHFCLKDividerForMFPCLK(void) +{ + uint32_t divider = + (SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK) >> + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS; + + return (DL_SYSCTL_HFCLK_MFPCLK_DIVIDER)(divider); +} + +/** + * @brief Enable the External Clock (CLK_OUT) + * + * CLK_OUT is provided for pushing out digital clocks to external circuits, such + * as an external ADC which does not have its own clock source. + * + * IOMUX setting for CLK_OUT must be configured before using this function. + * + * CLK_OUT has a typical duty cycle of 50% if clock source is HFCLK, SYSPLLOUT1, + * SYSOSC, or LFCLK. If source is MCLK, ULPCLK, or MFCLK, duty cycle is not + * guaranteed to be 50%. + * + * This function performs multiple operations: + * 1) Sets the CLK_OUT source + * 2) Sets the CLK_OUT divider value + * 3) Enables the CLK_OUT divider, which can be disabled by @ref DL_SYSCTL_disableExternalClockDivider + * 4) Enables the CLK_OUT, which can be disabled by @ref DL_SYSCTL_disableExternalClock + * + * @param[in] source The source of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_SOURCE. + * @param[in] divider The divider of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_DIVIDE. + * + * @sa DL_SYSCTL_disableExternalClock + * @sa DL_SYSCTL_disableExternalClockDivider + */ +__STATIC_INLINE void DL_SYSCTL_enableExternalClock( + DL_SYSCTL_CLK_OUT_SOURCE source, DL_SYSCTL_CLK_OUT_DIVIDE divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) divider | (uint32_t) source, + SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK | SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK | + SYSCTL_GENCLKCFG_EXCLKSRC_MASK); + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_EXCLKEN_ENABLE; +} + +/** + * @brief Disable the External Clock (CLK_OUT) + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClock(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_EXCLKEN_ENABLE); +} + +/** + * @brief Disable the External Clock (CLK_OUT) Divider + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClockDivider(void) +{ + SYSCTL->SOCLOCK.GENCLKCFG &= ~(SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE); +} + +/** + * @brief Blocks all asynchronous fast clock requests + * + * To block specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C. + */ +__STATIC_INLINE void DL_SYSCTL_blockAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE; +} + +/** + * @brief Allows all asynchronous fast clock requests + * + * Although this allows all async fast clock requests, individual IPs may still + * be blocking theirs. + * + * To allow specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C, GPIO. + */ +__STATIC_INLINE void DL_SYSCTL_allowAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE); +} + +/** + * @brief Generates an asynchronous fast clock request upon any IRQ request to CPU. + * + * Provides lowest latency interrupt handling regardless of system clock speed. + * Blockable by @ref DL_SYSCTL_blockAllAsyncFastClockRequests + * + * @sa DL_SYSCTL_blockAllAsyncFastClockRequests + */ +__STATIC_INLINE void DL_SYSCTL_enableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE; +} + +/** + * @brief Maintains current system clock speed for IRQ request to CPU. + * + * Latency for interrupt handling will be higher at lower system clock speeds. + */ +__STATIC_INLINE void DL_SYSCTL_disableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE); +} + +/** + * @brief Set the lower SRAM boundary address to act as partition for read-execute + * permission + * + * Specify the lower SRAM partition address to protect the code region of SRAM from + * being written to, and prevent the RW ("data") region of SRAM from being + * used for code execution. + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. This is the default + * value. + * + * The address is set with a 32-byte resolution. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @param[in] address Address to act as the SRAM partition address. Value is + * a valid 32-bit SRAM address. Only address bits [19:5] + * i.e. bit 5 to bit 19 are used for the boundary address + */ +__STATIC_INLINE void DL_SYSCTL_setLowerSRAMBoundaryAddress(uint32_t address) +{ + SYSCTL->SOCLOCK.SRAMBOUNDARY = + (((uint32_t) address) & SYSCTL_SRAMBOUNDARY_ADDR_MASK); +} + +/** + * @brief Get the lower SRAM boundary address + * + * Get the lower SRAM partition address + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. + * + * The address is set with a 32-byte granularity. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @return The SRAM partition address offset from the SRAM base address + * + * @retval Value is range in [0x0, 0x000FFFE0] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getLowerSRAMBoundaryAddress(void) +{ + return (SYSCTL->SOCLOCK.SRAMBOUNDARY); +} + +/** + * @brief Set flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @param[in] waitState Desired number of flash wait states. One of + * @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE void DL_SYSCTL_setFlashWaitState( + DL_SYSCTL_FLASH_WAIT_STATE waitState) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) waitState, + SYSCTL_MCLKCFG_FLASHWAIT_MASK); +} + +/** + * @brief Get flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @return Number of flash wait states. One of @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE DL_SYSCTL_FLASH_WAIT_STATE DL_SYSCTL_getFlashWaitState(void) +{ + uint32_t waitState = + SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_FLASHWAIT_MASK; + + return (DL_SYSCTL_FLASH_WAIT_STATE)(waitState); +} + +/** + * @brief Read Frequency Clock Counter (FCC) + * @return 22-bit value of Frequency Clock Counter (FCC) + */ +__STATIC_INLINE uint32_t DL_SYSCTL_readFCC(void) +{ + return (SYSCTL->SOCLOCK.FCC); +} + +/** + * @brief Start Frequency Clock Counter (FCC) + * + * If FCC_IN is already logic high, counting starts immediately. + * When using level trigger, FCC_IN should be low when GO is set, and trigger + * pulse should be sent to FCC_IN after starting FCC. + */ +__STATIC_INLINE void DL_SYSCTL_startFCC(void) +{ + SYSCTL->SOCLOCK.FCCCMD = (SYSCTL_FCCCMD_KEY_VALUE | SYSCTL_FCCCMD_GO_TRUE); +} + +/** + * @brief Returns whether FCC is done capturing + * + * When capture completes, FCCDONE is set by hardware. + * FCCDONE is read-only and is automatically cleared by hardware when a new + * capture is started. + * + * @return Whether FCC is done or not + * @retval true or false (boolean) + */ +__STATIC_INLINE bool DL_SYSCTL_isFCCDone(void) +{ + return (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_FCCDONE_DONE) == + SYSCTL_CLKSTATUS_FCCDONE_DONE; +} + +/** + * @brief Configure the Frequency Clock Counter (FCC) + * + * FCC enables flexible in-system testing and calibration of a variety of oscillators + * and clocks on the device. The FCC counts the number of clock periods seen on the + * selected clock source within a known fixed trigger period (derived from a secondary + * reference source) to provide an estimation of the frequency of the source clock. + * + * @param[in] trigLvl Determines if active high level trigger or rising-edge + * to rising-edge. One of @ref DL_SYSCTL_FCC_TRIG_TYPE. + * @sa DL_SYSCTL_setFCCPeriods must be called to configure + * number of rising-edge to rising-edge periods when + * DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE is selected. + * @param[in] trigSrc Determines which clock source to trigger FCC from. One of + * @ref DL_SYSCTL_FCC_TRIG_SOURCE. + * @param[in] clkSrc Which clock source to capture and measure frequency of. One of + * @ref DL_SYSCTL_FCC_CLOCK_SOURCE. + */ +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc); + +/** + * @brief Sets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * Set the number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @param[in] periods One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE void DL_SYSCTL_setFCCPeriods(DL_SYSCTL_FCC_TRIG_CNT periods) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) periods, + SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK); +} + +/** + * @brief Gets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @return One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT DL_SYSCTL_getFCCPeriods(void) +{ + uint32_t periods = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK; + + return (DL_SYSCTL_FCC_TRIG_CNT)(periods); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in Internal Resistor Mode + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in External Resistor Mode + * + * Used to increase SYSOSC accuracy. An ROSC reference resistor which is suitable + * to meet application accuracy reqiurements must be placed between ROSC pin and + * device ground (VSS). + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + * + * Power consumption of SYSOSC will be marginally higher with FCL enabled due to + * reference current which flows through ROSC. + * Settling time from startup to specified accuracy may also be longer. + * See device-specific datasheet for startup times. + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCLExternalResistor(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE | + SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE); +} + +/** + * @brief Enable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_enableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_ENABLE; +} + +/** + * @brief Disable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_disableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_DISABLE; +} + +/** + * @brief Sets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @param[in] setting One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE void DL_SYSCTL_setVBOOSTConfig(DL_SYSCTL_VBOOST setting) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) setting, + SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK); +} + +/** + * @brief Gets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @return One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE DL_SYSCTL_VBOOST DL_SYSCTL_getVBOOSTConfig(void) +{ + uint32_t setting = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK; + + return (DL_SYSCTL_VBOOST)(setting); +} + +/** + * @brief Return byte that was saved through SHUTDOWN + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * + * @return 8-bit value of Shutdown Storage Byte. + */ +__STATIC_INLINE uint8_t DL_SYSCTL_getShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index) +{ + const volatile uint32_t *pReg = &SYSCTL->SOCLOCK.SHUTDNSTORE0; + + return (uint8_t)( + *(pReg + (uint32_t) index) & SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Save a byte to SHUTDOWN memory + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * @param[in] data 8-bit data to save in memory + */ +__STATIC_INLINE void DL_SYSCTL_setShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index, uint8_t data) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SHUTDNSTORE0 + (uint32_t) index, data, + SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Enable SHUTDOWN IO Release + * + * After shutdown, IO is locked in previous state. + * + * @note Release IO after re-configuring IO to their proper state. + */ +__STATIC_INLINE void DL_SYSCTL_releaseShutdownIO(void) +{ + SYSCTL->SOCLOCK.SHDNIOREL = + (SYSCTL_SHDNIOREL_KEY_VALUE | SYSCTL_SHDNIOREL_RELEASE_TRUE); +} + +/** + * @brief Disable the reset functionality of the NRST pin + * + * Disabling the NRST pin allows the pin to be configured as a GPIO. + * Once disabled, the reset functionality can only be re-enabled by a POR. + * + * @note The register is write-only, so the EXRSTPIN register + * will always appear as "Disabled" in the debugger + */ +__STATIC_INLINE void DL_SYSCTL_disableNRSTPin(void) +{ + SYSCTL->SOCLOCK.EXRSTPIN = + (SYSCTL_EXRSTPIN_KEY_VALUE | SYSCTL_EXRSTPIN_DISABLE_TRUE); +} + +/** + * @brief Disable Serial Wire Debug (SWD) functionality + * + * SWD pins are enabled by default after cold start to allow a debug connection. + * It is possible to disable SWD on these pins to use for other functionality. + * + * @post SWD is disabled, but pins must be re-configured separately. + * + * @note Cannot debug the device after disabling SWD. Only re-enabled by POR. + */ +__STATIC_INLINE void DL_SYSCTL_disableSWD(void) +{ + SYSCTL->SOCLOCK.SWDCFG = + (SYSCTL_SWDCFG_KEY_VALUE | SYSCTL_SWDCFG_DISABLE_TRUE); +} + +/** + * @brief Return byte that is stored in RSTCAUSE. + * + * @return The cause of reset. One of @ref DL_SYSCTL_RESET_CAUSE + */ +__STATIC_INLINE DL_SYSCTL_RESET_CAUSE DL_SYSCTL_getResetCause(void) +{ + uint32_t resetCause = SYSCTL->SOCLOCK.RSTCAUSE & SYSCTL_RSTCAUSE_ID_MASK; + + return (DL_SYSCTL_RESET_CAUSE)(resetCause); +} + +/** + * @brief Set the HFXT startup time + * + * Specify the HFXT startup time in 64us resolution. If the HFCLK startup + * monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time + * expires. + * + * @param[in] startupTime The HFXT startup time to set in ~64us steps. + * Value between [0x0 (~0s), 0xFF (~16.32ms)]. + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTStartupTime(uint32_t startupTime) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, startupTime, + SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Get the HFXT startup time + * + * @return Returns the HFXT startup time in ~64us steps + * + * @retval Value between [0x0 (~0s), 0xFF (~16.32ms)] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getHFXTStartupTime(void) +{ + return (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Set the HFXT frequency range + * + * The high frequency crystal oscillator (HFXT) can be used with standard + * crystals and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * @param[in] range One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTFrequencyRange( + DL_SYSCTL_HFXT_RANGE range) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, ((uint32_t) range), + SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK); +} + +/** + * @brief Get the HFXT frequency range + * + * @return Returns the HFXT frequency range + * + * @retval One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE DL_SYSCTL_HFXT_RANGE DL_SYSCTL_getHFXTFrequencyRange(void) +{ + uint32_t range = + (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK) >> + SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS; + + return (DL_SYSCTL_HFXT_RANGE)(range); +} + +/** + * @brief Enable the HFCLK startup monitor + * + * The HFXT takes time to start after being enabled. A startup monitor is + * provided to indicate to the application software if the HFXT has successfully + * started, at which point the HFCLK can be selected to source a variety of + * system functions. The HFCLK startup monitor also supports checking the + * HFCLK_IN digital clock input for a clock stuck fault. + * + */ +__STATIC_INLINE void DL_SYSCTL_enableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG |= SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE; +} + +/** + * @brief Disable the HFCLK startup monitor + */ +__STATIC_INLINE void DL_SYSCTL_disableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG &= ~(SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK); +} + +/** + * @brief Retrieves the calibration constant of the temperature sensor to be + * used in temperature calculation. + * + * @retval Temperature sensor calibration data + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getTempCalibrationConstant(void) +{ + return DL_FactoryRegion_getTemperatureVoltage(); +} + +/** + * @brief Initializes the Read Execute (RX) Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the read execute protect firewall + * @param[in] endAddr The end address of the read execute protect firewall + * + * @return If the Read Execute Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Initializes the IP Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the IP protect firewall + * @param[in] endAddr The end address of the IP protect firewall + * + * @return If the IP Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Set the address range of the Write Protect Firewall + * + * Set Write Protection starting at 0x0 of flash, for the first + * 32KB at 1KB granularity. + * Setting a bit to 1 enables write protection, and setting a bit to 0 + * allows write. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] addrMask The mask to set the address range for the Write Protect + * Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setWriteProtectFirewallAddrRange( + uint32_t addrMask) +{ + SYSCTL->SECCFG.FWEPROTMAIN = addrMask; +} + +/** + * @brief Get the address range of the Write Protect Firewall + * + * @retval The address range for the Write Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getWriteProtectFirewallAddrRange(void) +{ + return (SYSCTL->SECCFG.FWEPROTMAIN); +} + +/** + * @brief Set the Read Write Protect Firewall for the Flash DATA Bank + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] protectionType The type of protection to set for the DATA Bank. + * One of @ref DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL + */ +__STATIC_INLINE void DL_SYSCTL_setDATABankRWProtectFirewallMode( + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL protectionType) +{ + SYSCTL->SECCFG.FWPROTMAINDATA = (uint32_t) protectionType; +} + +/** + * @brief Get the protection type for the Read Write Protect Firewall for the Flash DATA Bank + * + * @return The protection type for the Read Write Protect Firewall for the Flash DATA Bank + * + * @retval One of @ref DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL + */ +__STATIC_INLINE DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL +DL_SYSCTL_getDATABankRWProtectFirewallMode(void) +{ + return (DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL)( + SYSCTL->SECCFG.FWPROTMAINDATA); +} + +/** + * @brief Set the start address of the Read Execute (RX) Protect Firewall + * + * Set the start of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the read execute protect + * firewall. The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINSTART = + (startAddr & SYSCTL_FRXPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The start address of the read execute protect firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINSTART); +} + +/** + * @brief Set the end address of the Read Execute (RX) Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the read execute protect firewall. + * The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd( + uint32_t endAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINEND = + (endAddr & SYSCTL_FRXPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The end address of the Read Execute Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINEND); +} + +/** + * @brief Set the start address of the IP Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the IP Protect Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINSTART = + (startAddr & SYSCTL_FIPPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the IP Protect Firewall + * + * @return The start address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINSTART); +} + +/** + * @brief Set the end address of the IP Protect firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the IP Protect firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINEND = + (endAddr & SYSCTL_FIPPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the IP Protect Firewall + * + * @return The end address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINEND); +} + +/** + * @brief Enable the policy to allow flash bank swapping + * + * The bank swap policy needs to be configured ahead of any bank swapping or + * firewall configurations. In dual/quad-bank devices, this policy can be set + * to either + * - CSC allows bank swapping + * - CSC does not allow bank swapping + * + * By default, bank swapping is enabled to ensure a high security state if the + * system boot execution was glitched. Defaulting the system as allowing bank + * swapping ensures that firewall protections get mirrored to both flash banks. + * Additionally, when bank swapping is enabled, SYSCTL enforces write-excute + * mutual exclusion across the two banks (or bank-pairs). + * + * @note This is a write-once bit. This bit can only be written to before + * INITDONE. At INITDONE, this bit becomes a read-only bit until next + * BOOTRST. + */ +__STATIC_INLINE void DL_SYSCTL_enableFlashBankSwap(void) +{ + SYSCTL->SECCFG.FLBANKSWPPOLICY &= (~(SYSCTL_FLBANKSWPPOLICY_DISABLE_MASK) | + SYSCTL_FLBANKSWPPOLICY_KEY_VALUE); +} + +/** + * @brief Disable the policy to allow flash bank swapping + * + * The bank swap policy needs to be configured ahead of any bank swapping or + * firewall configurations. In dual/quad-bank devices, this policy can be set + * to either + * - CSC allows bank swapping + * - CSC does not allow bank swapping + * + * By default, bank swapping is enabled to ensure a high security state if the + * system boot execution was glitched. Defaulting the system as allowing bank + * swapping ensures that firewall protections get mirrored to both flash banks. + * Additionally, when bank swapping is enabled, SYSCTL enforces write-excute + * mutual exclusion across the two banks (or bank-pairs). + * + * @note This is a write-once bit. This bit can only be written to before + * INITDONE. At INITDONE, this bit becomes a read-only bit until next + * BOOTRST. + */ +__STATIC_INLINE void DL_SYSCTL_disableFlashBankSwap(void) +{ + SYSCTL->SECCFG.FLBANKSWPPOLICY = (SYSCTL_FLBANKSWPPOLICY_DISABLE_TRUE | + SYSCTL_FLBANKSWPPOLICY_KEY_VALUE); +} + +/** + * @brief Perform bank swap and execute from the Upper Flash Bank + * + * The upper physical bank maps to logical 0x0, and gets RX permission. + * The lower physical bank gets RW permission. + * + * @note This bit can only be written to before INITDONE. At INITDONE, this bit + * becomes a read-only bit until next BOOTRST. + * + * @pre DL_SYSCTL_enableFlashBankSwap + */ +__STATIC_INLINE void DL_SYSCTL_executeFromUpperFlashBank(void) +{ + SYSCTL->SECCFG.FLBANKSWP |= + (SYSCTL_FLBANKSWP_USEUPPER_ENABLE | SYSCTL_FLBANKSWP_KEY_VALUE); +} + +/** + * @brief Perform bank swap and execute from the Lower Flash Bank + * + * The lower physical bank maps to logical 0x0, and gets RX permission. + * The upper physical bank gets RW permission. + * + * @note This bit can only be written to before INITDONE. At INITDONE, this bit + * becomes a read-only bit until next BOOTRST. + * + * @pre DL_SYSCTL_enableFlashBankSwap + */ +__STATIC_INLINE void DL_SYSCTL_executeFromLowerFlashBank(void) +{ + SYSCTL->SECCFG.FLBANKSWP &= + (~(SYSCTL_FLBANKSWP_USEUPPER_MASK) | SYSCTL_FLBANKSWP_KEY_VALUE); +} + +/** + * @brief Enable Read Execute (RX) Protect Firewall + * + * Enables the Read Execute Protect Firewall before INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableReadExecuteProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_FLRXPROT_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable IP Protect Firewall + * + * Enables the IP Protect Firewall before INITDONE. After INITDONE, + * this configuration gets locked until the next BOOTRST. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableIPProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_SECSTATUS_FLIPPROT_ENABLED | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable SRAM Boundary Lock + * + * When SRAM Boundary Lock is enabled, the SRAMBOUNDARY register is only + * writeable only until INITDONE. After INITDONE, the SRAMBOUNDARY register + * cannot be written. + * + * When disabled, the SRAMBOUNDARY register is writeable throughout the + * application, even after INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + * + * @sa DL_SYSCTL_setSRAMBoundaryAddress + */ +__STATIC_INLINE void DL_SYSCTL_enableSRAMBoundaryLock(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Checks if INITDONE has been issued by the CSC + * + * @return Whether INITDONE has been issued or not + * + * @retval true If INITDONE has been issued + * @retval false If INITDONE has not been issued + */ +__STATIC_INLINE bool DL_SYSCTL_isINITDONEIssued(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_INITDONE_YES) == + SYSCTL_SECSTATUS_INITDONE_YES); +} + +/** + * @brief Checks if Customer Startup Code (CSC) exists in system + * + * @return Whether CSC exists in system + * + * @retval true If CSC exists in system + * @retval false If CSC does not exist in system + */ +__STATIC_INLINE bool DL_SYSCTL_ifCSCExists(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_CSCEXISTS_YES) == + SYSCTL_SECSTATUS_CSCEXISTS_YES); +} + +/** + * @brief Checks if Read Execute (RX) Protect Firewall is enabled + * + * @return Whether Read Execute Protect Firewall is enabled + * + * @retval true If Read Execute Protect Firewall is enabled + * @retval false If Read Execute Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isReadExecuteProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLRXPROT_ENABLED) == + SYSCTL_SECSTATUS_FLRXPROT_ENABLED); +} + +/** + * @brief Checks if IP Protect Firewall is enabled + * + * @return Whether IP Protect Firewall is enabled + * + * @retval true If IP Protect Firewall is enabled + * @retval false If IP Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isIPProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLIPPROT_ENABLED) == + SYSCTL_SECSTATUS_FLIPPROT_ENABLED); +} + +/** + * @brief Checks if SRAM Boundary Lock is enabled + * + * @return Whether SRAM Boundary Lock is enabled + * + * @retval true If SRAM Boundary Lock is enabled + * @retval false If SRAM Boundary Lock is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSRAMBoundaryLocked(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED) == + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED); +} + +/** + * @brief Checks if Flash Bank swapping is enabled + * + * @return Whether Flash Bank swap is enabled + * + * @retval true If Flash Bank swap is enabled + * @retval false If Flash Bank swap is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isFlashBankSwapEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & + SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED) == + SYSCTL_SECSTATUS_FLBANKSWPPOLICY_ENABLED); +} + +/** + * @brief Checks if executing from upper flash bank + * + * @return Whether executing from upper flash bank + * + * @retval true If executing from upper flash bank + * @retval false If not executing from upper flash bank + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromUpperFlashBank(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLBANKSWP_MASK) == + SYSCTL_SECSTATUS_FLBANKSWP_MASK); +} + +/** + * @brief Checks if executing from lower flash bank + * + * @return Whether executing from lower flash bank + * + * @retval true If executing from lower flash bank + * @retval false If not executing from lower flash bank + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromLowerFlashBank(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLBANKSWP_MASK) != + SYSCTL_SECSTATUS_FLBANKSWP_MASK); +} + +/** + * @brief Indicate that INIT is done + * + * After INITDONE is issued, the security configuration is locked and enforced. + * A SYSRST will occur, restarting startup code execution, and the main + * application is launched. + * + * There is no hardware support to enforce a timeout if INITDONE is not issued + * in a reasonable period of time. It is recommended that the CSC use a + * watchdog to ensure that INITDONE is issued in a timely manner. + */ +__STATIC_INLINE void DL_SYSCTL_issueINITDONE(void) +{ + SYSCTL->SECCFG.INITDONE |= + (SYSCTL_INITDONE_PASS_TRUE | SYSCTL_INITDONE_KEY_VALUE); +} + +/** + * @brief Set USBCLK source + * + * Configures USBCLK to source from either PLLCLK1 or USBFLL. + * + * @param[in] source The clock that USBCLK will source from, + * one of @ref DL_SYSCTL_USBCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setUSBCLKSource(DL_SYSCTL_USBCLK_SOURCE source) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) source, + SYSCTL_GENCLKCFG_USBCLKSRC_MASK); +} + +/** + * @brief Disable USBFLL + * + * Updates the USBFLLCTL register to disable the USB Frequency Lock Loop + */ +__STATIC_INLINE void DL_SYSCTL_disableUSBFLL(void) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.USBFLLCTL, + SYSCTL_USBFLLCTL_FLLEN_FALSE, SYSCTL_USBFLLCTL_FLLEN_MASK); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dl_m0p_dl_sysctl_sysctl__include */ +/** @}*/ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h index 451bc48..11c9d02 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h @@ -2557,7 +2557,8 @@ __STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) __STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCLExternalResistor(void) { SYSCTL->SOCLOCK.SYSOSCFCLCTL = - (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE | + SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE); } /** @@ -3048,7 +3049,7 @@ __STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrStart(void) */ __STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) { - SYSCTL->SECCFG.FIPPROTMAINSTART = + SYSCTL->SECCFG.FIPPROTMAINEND = (endAddr & SYSCTL_FIPPROTMAINEND_ADDR_MASK); } @@ -3059,7 +3060,7 @@ __STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) */ __STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrEnd(void) { - return (SYSCTL->SECCFG.FIPPROTMAINSTART); + return (SYSCTL->SECCFG.FIPPROTMAINEND); } /** diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.c index 4f5023e..be08642 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.c +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.c @@ -64,17 +64,14 @@ void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config) void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) { - // Set SYSOSC back to base frequency if left enabled if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); - // Do not set both bits SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; - SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; } else { - // Do not set both bits - SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; // Verify LFCLK -> MCLK while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.c index cf1d4e9..33d2667 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.c +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.c @@ -89,17 +89,14 @@ void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config) void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) { - // Set SYSOSC back to base frequency if left enabled if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); - // Do not set both bits SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; - SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; } else { - // Do not set both bits - SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; // Verify LFCLK -> MCLK while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h index e9e3003..d1ceab9 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h @@ -114,15 +114,26 @@ extern "C" { #define DL_SYSCTL_INTERRUPT_LFOSC_GOOD (SYSCTL_IMASK_LFOSCGOOD_ENABLE) /*! @brief Analog clocking consistency error */ #define DL_SYSCTL_INTERRUPT_ANALOG_CLOCK_ERROR (SYSCTL_IMASK_ANACLKERR_ENABLE) +/*! @brief Flash Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_FLASH_SEC (SYSCTL_IMASK_FLASHSEC_ENABLE) +/*! @brief Low Frequency Crystal is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFXT_GOOD (SYSCTL_IMASK_LFXTGOOD_ENABLE) /** @}*/ /*! @enum DL_SYSCTL_IIDX */ typedef enum { + /*! @brief Interrupt index if no interrupt is pending */ + DL_SYSCTL_IIDX_NO_INT = SYSCTL_IIDX_STAT_NO_INTR, /*! @brief Low Frequency Oscillator is stabilized and ready to use */ DL_SYSCTL_IIDX_LFOSC_GOOD = SYSCTL_IIDX_STAT_LFOSCGOOD, /*! @brief Analog clocking consistency error */ DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR = SYSCTL_IIDX_STAT_ANACLKERR, + /*! @brief Flash Single Error Correct */ + DL_SYSCTL_IIDX_FLASH_SEC = SYSCTL_IIDX_STAT_FLASHSEC, + /*! @brief Low Frequency Crystal is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFXT_GOOD = SYSCTL_IIDX_STAT_LFXTGOOD, + } DL_SYSCTL_IIDX; @@ -2028,7 +2039,8 @@ __STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) __STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCLExternalResistor(void) { SYSCTL->SOCLOCK.SYSOSCFCLCTL = - (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE | + SYSCTL_SYSOSCFCLCTL_SETUSEEXRES_TRUE); } /** @@ -2407,7 +2419,7 @@ __STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrStart(void) */ __STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) { - SYSCTL->SECCFG.FIPPROTMAINSTART = + SYSCTL->SECCFG.FIPPROTMAINEND = (endAddr & SYSCTL_FIPPROTMAINEND_ADDR_MASK); } @@ -2418,7 +2430,7 @@ __STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) */ __STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrEnd(void) { - return (SYSCTL->SECCFG.FIPPROTMAINSTART); + return (SYSCTL->SECCFG.FIPPROTMAINEND); } /** diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h index 41db072..6172ca0 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h @@ -1724,19 +1724,6 @@ __STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT DL_SYSCTL_getFCCPeriods(void) return (DL_SYSCTL_FCC_TRIG_CNT)(periods); } -/** - * @brief Enable Frequency Correction Loop (FCL) - * - * FCL for this device is using the external resistor by default. - * - * This API calls @ref DL_SYSCTL_enableSYSOSCFCLExternalResistor - */ -__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) -{ - SYSCTL->SOCLOCK.SYSOSCFCLCTL = - (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); -} - /** * @brief Enable Frequency Correction Loop (FCL) in External Resistor Mode * @@ -1753,7 +1740,20 @@ __STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) */ __STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCLExternalResistor(void) { - DL_SYSCTL_enableSYSOSCFCL(); + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) + * + * FCL for this device is using the external resistor by default. + * + * This API calls @ref DL_SYSCTL_enableSYSOSCFCLExternalResistor + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) +{ + DL_SYSCTL_enableSYSOSCFCLExternalResistor(); } /** diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.c index 5b95e8e..26e32ed 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.c +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.c @@ -89,17 +89,14 @@ void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config) void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) { - // Set SYSOSC back to base frequency if left enabled if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); - // Do not set both bits SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; - SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; } else { - // Do not set both bits - SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; // Verify LFCLK -> MCLK while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h index bc15cff..7403cf4 100644 --- a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h @@ -2635,7 +2635,7 @@ __STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrStart(void) */ __STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) { - SYSCTL->SECCFG.FIPPROTMAINSTART = + SYSCTL->SECCFG.FIPPROTMAINEND = (endAddr & SYSCTL_FIPPROTMAINEND_ADDR_MASK); } @@ -2646,7 +2646,7 @@ __STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) */ __STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrEnd(void) { - return (SYSCTL->SECCFG.FIPPROTMAINSTART); + return (SYSCTL->SECCFG.FIPPROTMAINEND); } /** @@ -2932,8 +2932,9 @@ __STATIC_INLINE void DL_SYSCTL_enableSuperCapacitor(void) */ __STATIC_INLINE void DL_SYSCTL_disableSuperCapacitor(void) { - SYSCTL->SOCLOCK.SYSTEMCFG &= - (~(SYSCTL_SYSTEMCFG_SUPERCAPEN_TRUE) | SYSCTL_SYSTEMCFG_KEY_VALUE); + SYSCTL->SOCLOCK.SYSTEMCFG = + (SYSCTL->SOCLOCK.SYSTEMCFG & (~SYSCTL_SYSTEMCFG_SUPERCAPEN_TRUE)) | + SYSCTL_SYSTEMCFG_KEY_VALUE; } /** diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l211x_l112x.c b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l211x_l112x.c new file mode 100644 index 0000000..9f2d787 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l211x_l112x.c @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L211X_L112X) + +#include +#include + +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG, + ((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) | + (uint32_t) config->xt1Drive, + (SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK)); + // start the LFXT oscillator + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE); + // wait until LFXT oscillator is stable + // if it does not stabilize, check the hardware/IOMUX settings + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_LFXT_GOOD) { + ; + } + if (config->monitor) { + // set the LFCLK monitor + SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE; + } + + // switch LFCLK source from LFOSC to LFXT + SYSCTL->SOCLOCK.LFXTCTL = + (SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE); +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC) +{ + if (disableSYSOSC == false) { + // Set SYSOSC back to base frequency if left enabled + DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } else { + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + } + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify LFCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void) +{ + // Only one should have been set, but clear both because unknown incoming state + // Clear SYSOSCCFG.DISABLE to get SYSOSC running again + // Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC + SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE; + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source) +{ + // Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN) + // Selected desired HSCLK source + DL_SYSCTL_setHSCLKSource(source); + + // Verify HSCLK source is valid + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) { + ; + } + + // Switch MCLK to HSCLK + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify HSCLK -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) != + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void) +{ + // Switch MCLK to SYSOSC + SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE; + + // Verify SYSOSC -> MCLK + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) == + DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + DL_SYSCTL_setHFXTFrequencyRange(range); + /* Set startup time to ~0.512ms based on TYP datasheet recommendation */ + DL_SYSCTL_setHFXTStartupTime(8); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } +} + +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + DL_SYSCTL_setHFXTFrequencyRange(range); + DL_SYSCTL_setHFXTStartupTime(startupTime); + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; + + if (monitorEnable == true) { + DL_SYSCTL_enableHFCLKStartupMonitor(); + /* Wait until HFXT oscillator is stable. If it does not stabilize, check the + hardware/IOMUX settings */ + while ( + (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) != + DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) { + ; + } + } else { + DL_SYSCTL_disableHFCLKStartupMonitor(); + } +} + +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc, + SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK | + SYSCTL_GENCLKCFG_FCCSELCLK_MASK); +} + +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void) +{ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy = + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED; + + // Check if SLEEP is enabled + if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) == + SYSCTL_MCLKCFG_USELFCLK_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1; + } else if ((SYSCTL->SOCLOCK.SYSOSCCFG & + SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void) +{ + DL_SYSCTL_POWER_POLICY_STOP policy = + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) == + SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STOP2; + } else { + policy = DL_SYSCTL_POWER_POLICY_STOP0; + } + } + return policy; +} + +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void) +{ + DL_SYSCTL_POWER_POLICY_STANDBY policy = + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED; + + // Check if STOP is enabled + if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) && + (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) { + // Check which policy is enabled + if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) == + SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) { + policy = DL_SYSCTL_POWER_POLICY_STANDBY1; + } else { + policy = DL_SYSCTL_POWER_POLICY_STANDBY0; + } + } + return policy; +} + +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableReadExecuteProtectFirewall(); + status = true; + } + return status; +} + +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr) +{ + bool status = false; + if (!DL_SYSCTL_isINITDONEIssued()) { + DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr); + DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr); + DL_SYSCTL_enableIPProtectFirewall(); + status = true; + } + return status; +} + +#endif /* DeviceFamily_PARENT_MSPM0G511X */ diff --git a/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l211x_l112x.h b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l211x_l112x.h new file mode 100644 index 0000000..17c32f2 --- /dev/null +++ b/mspm0/source/ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l211x_l112x.h @@ -0,0 +1,2863 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file dl_sysctl_mspm0l211x_l112x.h + * @brief System Control (SysCtl) + * @defgroup SYSCTL_mspm0l211x_l112x mspm0l211x_l112x System Control (SYSCTL) + * + * @anchor ti_dl_m0p_mspm0l211x_l112x_dl_sysctl_Overview + * # Overview + * + * The System Control (SysCtl) module enables control over system wide + * settings like clocks and power management. + * + *
+ * + ****************************************************************************** + */ +/** @addtogroup SYSCTL_mspm0l211x_l112x + * @{ + */ +#ifndef ti_dl_m0p_dl_sysctl_sysctl__include +#define ti_dl_m0p_dl_sysctl_sysctl__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* clang-format off */ + +/** @addtogroup DL_SYSCTL_RESET + * @{ + */ +/*! + * @brief Perform a SYSRST + * + * This issues a SYSRST (CPU plus peripherals only) + */ + #define DL_SYSCTL_RESET_SYSRST (SYSCTL_RESETLEVEL_LEVEL_CPU) + +/*! + * @deprecated This API is deprecated. Please refer to @ref DL_SYSCTL_RESET_SYSRST. + */ + #define DL_SYSCTL_RESET_CPU (DL_SYSCTL_RESET_SYSRST) + +/*! + * @brief Perform a Boot reset + * + * This triggers execution of the device boot configuration routine and resets + * the majority of the core logic while also power cycling the SRAM + */ + #define DL_SYSCTL_RESET_BOOT (SYSCTL_RESETLEVEL_LEVEL_BOOT) + +/*! + * @brief Perform a POR reset + * + * This performas a POR reset which is a complete device reset + */ + #define DL_SYSCTL_RESET_POR (SYSCTL_RESETLEVEL_LEVEL_POR) + +/*! + * @brief Perform system reset and exit bootloader to the application + */ + #define DL_SYSCTL_RESET_BOOTLOADER_EXIT \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT) + + /*! + * @brief Perform system reset and run bootloader + */ + #define DL_SYSCTL_RESET_BOOTLOADER_ENTRY \ + (SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY) + + +/** @addtogroup DL_SYSCTL_NMI + * @{ + */ +/*! @brief Non-maskable interrupt for SRAM Double Error Detect */ +#define DL_SYSCTL_NMI_SRAM_DED (SYSCTL_NMIISET_SRAMDED_SET) +/*! @brief Non-maskable interrupt for Flash Double Error Detect */ +#define DL_SYSCTL_NMI_FLASH_DED (SYSCTL_NMIISET_FLASHDED_SET) +/*! @brief Non-maskable interrupt for LFCLK Monitor Fail */ +#define DL_SYSCTL_NMI_LFCLK_FAIL (SYSCTL_NMIISET_LFCLKFAIL_SET) +/*! @brief Non-maskable interrupt for Watchdog 1 Fault */ +#define DL_SYSCTL_NMI_WWDT1_FAULT (SYSCTL_NMIISET_WWDT1_SET) +/*! @brief Non-maskable interrupt for Watchdog 0 Fault */ +#define DL_SYSCTL_NMI_WWDT0_FAULT (SYSCTL_NMIISET_WWDT0_SET) +/*! @brief Non-maskable interrupt for early BOR */ +#define DL_SYSCTL_NMI_BORLVL (SYSCTL_NMIISET_BORLVL_SET) +/** @}*/ + +/** @addtogroup DL_SYSCTL_INTERRUPT + * @{ + */ +/*! @brief Low Frequency Oscillator is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFOSC_GOOD (SYSCTL_IMASK_LFOSCGOOD_ENABLE) +/*! @brief Analog clocking consistency error */ +#define DL_SYSCTL_INTERRUPT_ANALOG_CLOCK_ERROR (SYSCTL_IMASK_ANACLKERR_ENABLE) +/*! @brief Flash Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_FLASH_SEC (SYSCTL_IMASK_FLASHSEC_ENABLE) + +/*! @brief SRAM Single Error Correct */ +#define DL_SYSCTL_INTERRUPT_SRAM_SEC (SYSCTL_IMASK_SRAMSEC_ENABLE) + +/*! @brief Low Frequency Crystal is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_LFXT_GOOD (SYSCTL_IMASK_LFXTGOOD_ENABLE) +/*! @brief High Frequency Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HFCLK_GOOD (SYSCTL_IMASK_HFCLKGOOD_ENABLE) +/*! @brief System PLL is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_SYSPLL_GOOD (SYSCTL_IMASK_SYSPLLGOOD_ENABLE) +/*! @brief High Speed Clock is stabilized and ready to use */ +#define DL_SYSCTL_INTERRUPT_HSCLK_GOOD (SYSCTL_IMASK_HSCLKGOOD_ENABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_CLK_STATUS + * @{ + */ +/*! @brief Error with Anacomp High Speed CP Clock Generation - SYSOSC must not + * run at 4MHz */ +#define DL_SYSCTL_CLK_STATUS_ANACOMP_ERROR (SYSCTL_CLKSTATUS_ACOMPHSCLKERR_TRUE) +/*! @brief Error with OPAMP Clock Generation */ +#define DL_SYSCTL_CLK_STATUS_OPAMP_ERROR (SYSCTL_CLKSTATUS_OPAMPCLKERR_TRUE) +/*! @brief Writes to SYSPLLCFG0-1, SYSPLLPARAM0-1 are blocked */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_SYSPLLBLKUPD_TRUE) +/*! @brief Writes to HFCLKCLKCFG are blocked */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_CONFIG_BLOCKED \ + (SYSCTL_CLKSTATUS_HFCLKBLKUPD_TRUE) +/*! @brief SYSOSC Frequency Correcting Loop Mode ON */ +#define DL_SYSCTL_CLK_STATUS_FCL_ON (SYSCTL_CLKSTATUS_FCLMODE_ENABLED) +/*! @brief Clock Fail for LFXT or EXLF clock source */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_FAIL (SYSCTL_CLKSTATUS_LFCLKFAIL_TRUE) +/*! @brief High Speed Clock Good */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_GOOD (SYSCTL_CLKSTATUS_HSCLKGOOD_TRUE) +/*! @brief High Speed Clock Stuck Fault */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_FAULT (SYSCTL_CLKSTATUS_HSCLKDEAD_TRUE) +/*! @brief SYSPLL is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_OFF (SYSCTL_CLKSTATUS_SYSPLLOFF_TRUE) +/*! @brief HFCLKs is OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_OFF (SYSCTL_CLKSTATUS_HFCLKOFF_TRUE) +/*! @brief All PLLs, HFCLKs are OFF or DEAD */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_OFF (SYSCTL_CLKSTATUS_HSCLKSOFF_TRUE) +/*! @brief LFOSC is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFOSC_GOOD (SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE) +/*! @brief LFXT is Valid */ +#define DL_SYSCTL_CLK_STATUS_LFXT_GOOD (SYSCTL_CLKSTATUS_LFXTGOOD_TRUE) +/*! @brief SYSTEM PLL ON */ +#define DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD (SYSCTL_CLKSTATUS_SYSPLLGOOD_TRUE) +/*! @brief High Frequency Clock ON */ +#define DL_SYSCTL_CLK_STATUS_HFCLK_GOOD (SYSCTL_CLKSTATUS_HFCLKGOOD_TRUE) +/*! @brief MCLK now sourced from HSCLK, otherwise SYSOSC */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK (SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK) +/*! @brief MCLK now sourced from LFCLK */ +#define DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK \ + (SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK) +/*! @brief Analog clocking error */ +#define DL_SYSCTL_CLK_STATUS_ANALOG_CLOCK_ERROR \ + (SYSCTL_CLKSTATUS_ANACLKERR_TRUE) +/*! @brief Frequency Clock Counter (FCC) done */ +#define DL_SYSCTL_CLK_STATUS_FCC_DONE (SYSCTL_CLKSTATUS_FCCDONE_DONE) +/*! @brief = LFCLK sourced from the LFXT (crystal) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_LFXT (SYSCTL_CLKSTATUS_LFCLKMUX_LFXT) +/*! @brief = LFCLK sourced from LFCLK_IN (external digital clock input) */ +#define DL_SYSCTL_CLK_STATUS_LFCLK_SOURCE_EXLF (SYSCTL_CLKSTATUS_LFCLKMUX_EXLF) +/*! @brief = SYSOSC is at low frequency (4MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_4MHZ (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M) +/*! @brief = SYSOSC is at the user-trimmed frequency (16 or 24MHz) */ +#define DL_SYSCTL_CLK_STATUS_SYSOSC_USERTRIM_FREQ \ + (SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER) +/*! @brief = HSCLK current sourced from the HFCLK */ +#define DL_SYSCTL_CLK_STATUS_HSCLK_SOURCE_HFCLK \ + (SYSCTL_CLKSTATUS_CURHSCLKSEL_HFCLK) +/** @}*/ + +/** @addtogroup DL_SYSCTL_STATUS + * @{ + */ + +/*! @brief IO is locked due to SHUTDOWN */ +#define DL_SYSCTL_STATUS_SHUTDOWN_IO_LOCK_TRUE \ + (SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE) +/*! @brief User has disabled external reset pin */ +#define DL_SYSCTL_STATUS_EXT_RESET_PIN_DISABLED \ + (SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE) +/*! @brief User has disabled SWD port */ +#define DL_SYSCTL_STATUS_SWD_DISABLED (SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE) + +/*! @brief PMU IFREF good */ +#define DL_SYSCTL_STATUS_PMU_IFREF_GOOD (SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE) +/*! @brief VBOOST (Analog Charge Pump) started up properly */ +#define DL_SYSCTL_STATUS_VBOOST_GOOD (SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE) +/*! @brief Brown Out Reset event status indicator */ +#define DL_SYSCTL_STATUS_BOR_EVENT (SYSCTL_SYSSTATUS_BORLVL_TRUE) +/*! @brief MCAN0 ready */ +#define DL_SYSCTL_STATUS_MCAN0_READY (SYSCTL_SYSSTATUS_MCAN0READY_TRUE) +/*! @brief Double Error Detect on Flash */ +#define DL_SYSCTL_STATUS_FLASH_DED (SYSCTL_SYSSTATUS_FLASHDED_TRUE) +/*! @brief Single Error Correction on Flash */ +#define DL_SYSCTL_STATUS_FLASH_SEC (SYSCTL_SYSSTATUS_FLASHSEC_TRUE) +/*! @brief Current Brown Out Reset minimum level */ +#define DL_SYSCTL_STATUS_BOR_LEVEL0 \ + (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN) +/*! @brief Current Brown Out Reset level 1 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL1 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1) +/*! @brief Current Brown Out Reset level 2 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL2 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2) +/*! @brief Current Brown Out Reset level 3 */ +#define DL_SYSCTL_STATUS_BOR_LEVEL3 (SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK2X + * @{ + */ +/*! @brief Enable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_ENABLE) + +/*! @brief Disable CLK2x output */ +#define DL_SYSCTL_SYSPLL_CLK2X_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK2X_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK1 + * @{ + */ +/*! @brief Enable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_ENABLE) + +/*! @brief Disable CLK1 output */ +#define DL_SYSCTL_SYSPLL_CLK1_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK1_DISABLE) +/** @}*/ + +/** @addtogroup DL_SYSCTL_SYSPLL_CLK0 + * @{ + */ +/*! @brief Enable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_ENABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_ENABLE) + +/*! @brief Disable CLK0 output */ +#define DL_SYSCTL_SYSPLL_CLK0_DISABLE (SYSCTL_SYSPLLCFG0_ENABLECLK0_DISABLE) +/** @}*/ + +/* clang-format on */ + +/** @enum DL_SYSCTL_SYSPLL_INPUT_FREQ */ +typedef enum { + /*! PLL feedback loop input clock frequency [4MHz, 8MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_4_8_MHZ = 0x41C4001C, + /*! PLL feedback loop input clock frequency [8MHz, 16MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ = 0x41C40024, + /*! PLL feedback loop input clock frequency [16MHz, 32MHz) */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ = 0x41C4002C, + /*! PLL feedback loop input clock frequency [32MHz, 48MHz] */ + DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ = 0x41C40034, +} DL_SYSCTL_SYSPLL_INPUT_FREQ; + +/*! @enum DL_SYSCTL_NMI_IIDX */ +typedef enum { + /*! @brief NMI interrupt index for SRAM Double Error Detect */ + DL_SYSCTL_NMI_IIDX_SRAM_DED = SYSCTL_NMIIIDX_STAT_SRAMDED, + /*! @brief NMI interrupt index for Flash Double Error Detect */ + DL_SYSCTL_NMI_IIDX_FLASH_DED = SYSCTL_NMIIIDX_STAT_FLASHDED, + /*! @brief NMI interrupt index for LFCLK Monitor Fail */ + DL_SYSCTL_NMI_IIDX_LFCLK_FAIL = SYSCTL_NMIIIDX_STAT_LFCLKFAIL, + /*! @brief NMI interrupt index for Watchdog 0 Fault */ + DL_SYSCTL_NMI_IIDX_WWDT0_FAULT = SYSCTL_NMIIIDX_STAT_WWDT0, + /*! @brief NMI interrupt index for early BOR */ + DL_SYSCTL_NMI_IIDX_BORLVL = SYSCTL_NMIIIDX_STAT_BORLVL, + /*! @brief NMI interrupt index for no interrupt pending */ + DL_SYSCTL_NMI_IIDX_NO_INT = SYSCTL_NMIIIDX_STAT_NO_INTR, +} DL_SYSCTL_NMI_IIDX; + +/** @}*/ + +/*! @enum DL_SYSCTL_IIDX */ +typedef enum { + /*! @brief Low Frequency Oscillator is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFOSC_GOOD = SYSCTL_IIDX_STAT_LFOSCGOOD, + /*! @brief Analog clocking consistency error */ + DL_SYSCTL_IIDX_ANALOG_CLOCK_ERROR = SYSCTL_IIDX_STAT_ANACLKERR, + /*! @brief Flash Single Error Correct */ + DL_SYSCTL_IIDX_FLASH_SEC = SYSCTL_IIDX_STAT_FLASHSEC, + + /*! @brief SRAM Single Error Correct */ + DL_SYSCTL_IIDX_SRAM_SEC = SYSCTL_IIDX_STAT_SRAMSEC, + + /*! @brief Low Frequency Crystal is stabilized and ready to use */ + DL_SYSCTL_IIDX_LFXT_GOOD = SYSCTL_IIDX_STAT_LFXTGOOD, + /*! @brief High Frequency Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HFCLK_GOOD = SYSCTL_IIDX_STAT_HFCLKGOOD, + /*! @brief High Speed Clock is stabilized and ready to use */ + DL_SYSCTL_IIDX_HSCLK_GOOD = SYSCTL_IIDX_STAT_HSCLKGOOD, +} DL_SYSCTL_IIDX; + +/*! @enum DL_SYSCTL_ERROR_BEHAVIOR */ +typedef enum { + /*! @brief The error event will trigger a SYSRST */ + DL_SYSCTL_ERROR_BEHAVIOR_RESET = 0x0, + /*! @brief The error event will trigger an NMI */ + DL_SYSCTL_ERROR_BEHAVIOR_NMI = 0x1, +} DL_SYSCTL_ERROR_BEHAVIOR; + +/*! @enum DL_SYSCTL_SYSOSC_FREQ */ +typedef enum { + /*! Use 4MHz for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_4M = (SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M), + /*! Use BASE (32MHz) for System Oscillator (SYSOSC) */ + DL_SYSCTL_SYSOSC_FREQ_BASE = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE), + /*! User will trim the System Oscillator (SYSOSC) to 16MHz or 24MHz */ + DL_SYSCTL_SYSOSC_FREQ_USERTRIM = (SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER), +} DL_SYSCTL_SYSOSC_FREQ; + +/** @enum DL_SYSCTL_LFXT_DRIVE_STRENGTH */ +typedef enum { + /*! Lowest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_LOWESTDRV), + /*! Lower Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_LOWER = (SYSCTL_LFCLKCFG_XT1DRIVE_LOWERDRV), + /*! Higher Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHER = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHERDRV), + /*! Highest Drive and Current */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHEST = + (SYSCTL_LFCLKCFG_XT1DRIVE_HIGHESTDRV), +} DL_SYSCTL_LFXT_DRIVE_STRENGTH; + +/*! @brief Configuration struct for @ref DL_SYSCTL_LFCLKConfig. */ +typedef struct { + /*! Enable if CAP is less than 3pF to reduce power consumption */ + bool lowCap; + /*! Enable to use monitor for LFXT, EXLF failure */ + bool monitor; + /*! Drive strength and power consumption option */ + DL_SYSCTL_LFXT_DRIVE_STRENGTH xt1Drive; +} DL_SYSCTL_LFCLKConfig; + +/** @enum DL_SYSCTL_HFXT_RANGE */ +typedef enum { + /*! HFXT frequency range between 4 and 8 MHz */ + DL_SYSCTL_HFXT_RANGE_4_8_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8, + /*! HFXT frequency range between 8.01 and 16 MHz */ + DL_SYSCTL_HFXT_RANGE_8_16_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16, + /*! HFXT frequency range between 16.01 and 32 MHz */ + DL_SYSCTL_HFXT_RANGE_16_32_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32, + /*! HFXT frequency range between 32.01 and 48 MHz */ + DL_SYSCTL_HFXT_RANGE_32_48_MHZ = SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48, +} DL_SYSCTL_HFXT_RANGE; + +/*! @enum DL_SYSCTL_HSCLK_SOURCE */ +typedef enum { + /*! Use HFLK as input source for HSCLK */ + DL_SYSCTL_HSCLK_SOURCE_HFCLK = SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK, +} DL_SYSCTL_HSCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MCLK source (default after reset) */ + DL_SYSCTL_MCLK_SOURCE_SYSOSC = SYSCTL_MCLKCFG_USEHSCLK_DISABLE, + /*! Use High Speed Clock (HSCLK) as MCLK source (HFCLK, PLL,...) */ + DL_SYSCTL_MCLK_SOURCE_HSCLK = SYSCTL_MCLKCFG_USEHSCLK_ENABLE, + /*! Use the Low Frequency Clock (LFCLK) as the clock source */ + DL_SYSCTL_MCLK_SOURCE_LFCLK = SYSCTL_MCLKCFG_USELFCLK_ENABLE, +} DL_SYSCTL_MCLK_SOURCE; + +/** @enum DL_SYSCTL_MCLK_DIVIDER */ +typedef enum { + /*! Disable MCLK divider. Change SYSOSC freq only when MDIV is disabled */ + DL_SYSCTL_MCLK_DIVIDER_DISABLE = 0x0, + /*! Divide MCLK frequency by 2 */ + DL_SYSCTL_MCLK_DIVIDER_2 = 0x1, + /*! Divide MCLK frequency by 3 */ + DL_SYSCTL_MCLK_DIVIDER_3 = 0x2, + /*! Divide MCLK frequency by 4 */ + DL_SYSCTL_MCLK_DIVIDER_4 = 0x3, + /*! Divide MCLK frequency by 5 */ + DL_SYSCTL_MCLK_DIVIDER_5 = 0x4, + /*! Divide MCLK frequency by 6 */ + DL_SYSCTL_MCLK_DIVIDER_6 = 0x5, + /*! Divide MCLK frequency by 7 */ + DL_SYSCTL_MCLK_DIVIDER_7 = 0x6, + /*! Divide MCLK frequency by 8 */ + DL_SYSCTL_MCLK_DIVIDER_8 = 0x7, + /*! Divide MCLK frequency by 9 */ + DL_SYSCTL_MCLK_DIVIDER_9 = 0x8, + /*! Divide MCLK frequency by 10 */ + DL_SYSCTL_MCLK_DIVIDER_10 = 0x9, + /*! Divide MCLK frequency by 11 */ + DL_SYSCTL_MCLK_DIVIDER_11 = 0xA, + /*! Divide MCLK frequency by 12 */ + DL_SYSCTL_MCLK_DIVIDER_12 = 0xB, + /*! Divide MCLK frequency by 13 */ + DL_SYSCTL_MCLK_DIVIDER_13 = 0xC, + /*! Divide MCLK frequency by 14 */ + DL_SYSCTL_MCLK_DIVIDER_14 = 0xD, + /*! Divide MCLK frequency by 15 */ + DL_SYSCTL_MCLK_DIVIDER_15 = 0xE, + /*! Divide MCLK frequency by 16 */ + DL_SYSCTL_MCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_MCLK_DIVIDER; + +/** @enum DL_SYSCTL_CLK_OUT_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC, + /*! Use Ultra Low Power Clock (ULPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_ULPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK, + /*! Use Low Frequency Clock (LFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_LFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK, + /*! Use Middle Frequency Precision Clock (MFPCLK) as CLK_OUT source. + * @ref DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE must not be selected for this + * configuration. */ + DL_SYSCTL_CLK_OUT_SOURCE_MFPCLK = SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK, + /*! Use High Frequency Clock (HFCLK) as CLK_OUT source */ + DL_SYSCTL_CLK_OUT_SOURCE_HFCLK = SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK, +} DL_SYSCTL_CLK_OUT_SOURCE; + +/** @enum DL_SYSCTL_CLK_OUT_DIVIDE */ +typedef enum { + /*! Disable the External Clock (CLK_OUT) output divider */ + DL_SYSCTL_CLK_OUT_DIVIDE_DISABLE = SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU, + /*! Divide External Clock (CLK_OUT) output by 2 */ + DL_SYSCTL_CLK_OUT_DIVIDE_2 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2, + /*! Divide External Clock (CLK_OUT) output by 4 */ + DL_SYSCTL_CLK_OUT_DIVIDE_4 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4, + /*! Divide External Clock (CLK_OUT) output by 6 */ + DL_SYSCTL_CLK_OUT_DIVIDE_6 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6, + /*! Divide External Clock (CLK_OUT) output by 8 */ + DL_SYSCTL_CLK_OUT_DIVIDE_8 = + SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8, + /*! Divide External Clock (CLK_OUT) output by 10 */ + DL_SYSCTL_CLK_OUT_DIVIDE_10 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10, + /*! Divide External Clock (CLK_OUT) output by 12 */ + DL_SYSCTL_CLK_OUT_DIVIDE_12 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12, + /*! Divide External Clock (CLK_OUT) output by 14 */ + DL_SYSCTL_CLK_OUT_DIVIDE_14 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14, + /*! Divide External Clock (CLK_OUT) output by 16 */ + DL_SYSCTL_CLK_OUT_DIVIDE_16 = SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE | + SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16, +} DL_SYSCTL_CLK_OUT_DIVIDE; + +/** @enum DL_SYSCTL_MFPCLK_SOURCE */ +typedef enum { + /*! Use System Oscillator (SYSOSC) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC, + /*! Use High Frequency Clock (HFCLK) as MFPCLK source */ + DL_SYSCTL_MFPCLK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK, +} DL_SYSCTL_MFPCLK_SOURCE; + +/** @enum DL_SYSCTL_HFCLK_MFPCLK_DIVIDER */ +typedef enum { + /*! HFCLK is not divided before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_DISABLE = 0x0, + /*! Divide HFCLK by 2 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_2 = 0x1, + /*! Divide HFCLK by 3 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_3 = 0x2, + /*! Divide HFCLK by 4 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_4 = 0x3, + /*! Divide HFCLK by 5 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_5 = 0x4, + /*! Divide HFCLK by 6 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6 = 0x5, + /*! Divide HFCLK by 7 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_7 = 0x6, + /*! Divide HFCLK by 8 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_8 = 0x7, + /*! Divide HFCLK by 9 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_9 = 0x8, + /*! Divide HFCLK by 10 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_10 = 0x9, + /*! Divide HFCLK by 11 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_11 = 0xA, + /*! Divide HFCLK by 12 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_12 = 0xB, + /*! Divide HFCLK by 13 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_13 = 0xC, + /*! Divide HFCLK by 14 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_14 = 0xD, + /*! Divide HFCLK by 15 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_15 = 0xE, + /*! Divide HFCLK by 16 before being used for MFPCLK */ + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_16 = 0xF, +} DL_SYSCTL_HFCLK_MFPCLK_DIVIDER; + +/** @enum DL_SYSCTL_FCC_TRIG_TYPE */ +typedef enum { + /*! FCC trigger is rising-edge to rising-edge pulse */ + DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE = SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE, + /*! FCC trigger is active-high pulse level */ + DL_SYSCTL_FCC_TRIG_TYPE_LEVEL = SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL, +} DL_SYSCTL_FCC_TRIG_TYPE; + +/** @enum DL_SYSCTL_FCC_TRIG_SOURCE */ +typedef enum { + /*! FCC trigger source is FCC_IN external pin */ + DL_SYSCTL_FCC_TRIG_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN, + /*! FCC trigger source is LFCLK */ + DL_SYSCTL_FCC_TRIG_SOURCE_LFCLK = SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK, +} DL_SYSCTL_FCC_TRIG_SOURCE; + +/** @enum DL_SYSCTL_FCC_CLOCK_SOURCE */ +typedef enum { + /*! FCC clock source to capture is MCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_MCLK = SYSCTL_GENCLKCFG_FCCSELCLK_MCLK, + /*! FCC clock source to capture is SYSOSC */ + DL_SYSCTL_FCC_CLOCK_SOURCE_SYSOSC = SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC, + /*! FCC clock source to capture is HFCLK */ + DL_SYSCTL_FCC_CLOCK_SOURCE_HFCLK = SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK, + /*! FCC clock source to capture is CLK_OUT */ + DL_SYSCTL_FCC_CLOCK_SOURCE_CLK_OUT = SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK, + /*! FCC clock source to capture is FCC_IN */ + DL_SYSCTL_FCC_CLOCK_SOURCE_FCC_IN = SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN, +} DL_SYSCTL_FCC_CLOCK_SOURCE; + +/** @enum DL_SYSCTL_FCC_TRIG_CNT */ +typedef enum { + /*! One monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_01 = + ((uint32_t) 0 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_02 = + ((uint32_t) 1 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_03 = + ((uint32_t) 2 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_04 = + ((uint32_t) 3 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_05 = + ((uint32_t) 4 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_06 = + ((uint32_t) 5 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_07 = + ((uint32_t) 6 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_08 = + ((uint32_t) 7 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_09 = + ((uint32_t) 8 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Ten monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_10 = + ((uint32_t) 9 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eleven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_11 = + ((uint32_t) 10 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twelve monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_12 = + ((uint32_t) 11 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_13 = + ((uint32_t) 12 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fourteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_14 = + ((uint32_t) 13 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Fifteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_15 = + ((uint32_t) 14 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Sixteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_16 = + ((uint32_t) 15 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Seventeen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_17 = + ((uint32_t) 16 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Eighteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_18 = + ((uint32_t) 17 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Nineteen monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_19 = + ((uint32_t) 18 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_20 = + ((uint32_t) 19 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_21 = + ((uint32_t) 20 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_22 = + ((uint32_t) 21 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-three monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_23 = + ((uint32_t) 22 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-four monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_24 = + ((uint32_t) 23 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-five monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_25 = + ((uint32_t) 24 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-six monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_26 = + ((uint32_t) 25 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-seven monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_27 = + ((uint32_t) 26 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-eight monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_28 = + ((uint32_t) 27 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Twenty-nine monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_29 = + ((uint32_t) 28 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_30 = + ((uint32_t) 29 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-one monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_31 = + ((uint32_t) 30 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), + /*! Thirty-two monitoring period */ + DL_SYSCTL_FCC_TRIG_CNT_32 = + ((uint32_t) 31 << SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS), +} DL_SYSCTL_FCC_TRIG_CNT; + +/** @enum DL_SYSCTL_VBOOST */ +typedef enum { + /*! VBOOST enabled only when COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONDEMAND = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND, + /*! VBOOST enabled in RUN/SLEEP, and in STOP/STANDBY if COMP/OPA/GPAMP is enabled */ + DL_SYSCTL_VBOOST_ONACTIVE = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE, + /*! VBOOST enabled in all power modes except SHUTDOWN for fastest startup */ + DL_SYSCTL_VBOOST_ONALWAYS = SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS, +} DL_SYSCTL_VBOOST; + +/** @enum DL_SYSCTL_FLASH_WAIT_STATE */ +typedef enum { + /*! 0 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_0 = ((uint32_t) 0x00000000U), + /*! 1 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_1 = ((uint32_t) 0x00000100U), + /*! 2 flash wait states */ + DL_SYSCTL_FLASH_WAIT_STATE_2 = ((uint32_t) 0x00000200U), +} DL_SYSCTL_FLASH_WAIT_STATE; + +/** @enum DL_SYSCTL_POWER_POLICY_RUN_SLEEP */ +typedef enum { + /*! RUN/SLEEP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED = 0x0, + /*! Enable RUN0/SLEEP0 power mode policy. */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP0 = 0x1, + /*! Enable the RUN1/SLEEP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP1 = 0x2, + /*! Enable the RUN2/SLEEP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_RUN_SLEEP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_RUN_SLEEP; + +/** @enum DL_SYSCTL_POWER_POLICY_STOP */ +typedef enum { + /*! STOP power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED = 0x0, + /*! Enable the STOP0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP0 = 0x1, + /*! Enable the STOP1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP1 = 0x2, + /*! Enable the STOP2 power mode policy */ + DL_SYSCTL_POWER_POLICY_STOP2 = 0x3, +} DL_SYSCTL_POWER_POLICY_STOP; + +/** @enum DL_SYSCTL_POWER_POLICY_STANDBY */ +typedef enum { + /*! STANDBY power policy is not enabled */ + DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED = 0x0, + /*! Enable the STANDBY0 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY0 = 0x1, + /*! Enable the STANDBY1 power mode policy */ + DL_SYSCTL_POWER_POLICY_STANDBY1 = 0x2, +} DL_SYSCTL_POWER_POLICY_STANDBY; + +/** @enum DL_SYSCTL_BOR_THRESHOLD_LEVEL */ +typedef enum { + /*! BOR0 threshold level. This is the minimum allowed threshold. + * A BOR0- violation will force a re-boot. */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_0 = SYSCTL_BORTHRESHOLD_LEVEL_BORMIN, + /*! BOR1 threshold level. A BOR1- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_1 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1, + /*! BOR2 threshold level. A BOR2- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_2 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2, + /*! BOR3 threshold level. A BOR3- violation generates an interrupt */ + DL_SYSCTL_BOR_THRESHOLD_LEVEL_3 = SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3, +} DL_SYSCTL_BOR_THRESHOLD_LEVEL; + +/** @enum DL_SYSCTL_SHUTDOWN_STORAGE_BYTE */ +typedef enum { + /*! Shutdown Storage Byte 0 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_0 = 0x0, + /*! Shutdown Storage Byte 1 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_1 = 0x1, + /*! Shutdown Storage Byte 2 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_2 = 0x2, + /*! Shutdown Storage Byte 3 */ + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE_3 = 0x3, +} DL_SYSCTL_SHUTDOWN_STORAGE_BYTE; + +/** @enum DL_SYSCTL_RESET_CAUSE */ +typedef enum { + /*! No Reset Since Last Read */ + DL_SYSCTL_RESET_CAUSE_NO_RESET = SYSCTL_RSTCAUSE_ID_NORST, + /*! (VDD < POR- violation) or (PMU trim parity fault) or (SHUTDNSTOREx parity fault) */ + DL_SYSCTL_RESET_CAUSE_POR_HW_FAILURE = SYSCTL_RSTCAUSE_ID_PORHWFAIL, + /*! NRST pin reset (>1s) */ + DL_SYSCTL_RESET_CAUSE_POR_EXTERNAL_NRST = SYSCTL_RSTCAUSE_ID_POREXNRST, + /*! Software-triggered POR */ + DL_SYSCTL_RESET_CAUSE_POR_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_PORSW, + /*! VDD < BOR- violation */ + DL_SYSCTL_RESET_CAUSE_BOR_SUPPLY_FAILURE = SYSCTL_RSTCAUSE_ID_BORSUPPLY, + /*! Wake from SHUTDOWN */ + DL_SYSCTL_RESET_CAUSE_BOR_WAKE_FROM_SHUTDOWN = + SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN, + /*! Non-PMU trim parity fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_NON_PMU_PARITY_FAULT = + SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY, + /*! Fatal clock fault */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_CLOCK_FAULT = SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL, + /*! Software-triggered BOOTRST */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_BOOTSW, + /*! NRST pin reset (<1s) */ + DL_SYSCTL_RESET_CAUSE_BOOTRST_EXTERNAL_NRST = + SYSCTL_RSTCAUSE_ID_BOOTEXNRST, + /*! BSL exit */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_EXIT = SYSCTL_RSTCAUSE_ID_SYSBSLEXIT, + /*! BSL entry */ + DL_SYSCTL_RESET_CAUSE_SYSRST_BSL_ENTRY = SYSCTL_RSTCAUSE_ID_SYSBSLENTRY, + /*! WWDT0 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT0_VIOLATION = + SYSCTL_RSTCAUSE_ID_BOOTWWDT0, + /*! WWDT1 violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_WWDT1_VIOLATION = SYSCTL_RSTCAUSE_ID_SYSWWDT1, + /*! Uncorrectable flash ECC error */ + DL_SYSCTL_RESET_CAUSE_SYSRST_FLASH_ECC_ERROR = + SYSCTL_RSTCAUSE_ID_SYSFLASHECC, + /*! CPULOCK violation */ + DL_SYSCTL_RESET_CAUSE_SYSRST_CPU_LOCKUP_VIOLATION = + SYSCTL_RSTCAUSE_ID_SYSCPULOCK, + /*! Debug-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSDBG, + /*! Software-triggered SYSRST */ + DL_SYSCTL_RESET_CAUSE_SYSRST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_SYSSW, + /*! Debug-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_DEBUG_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUDBG, + /*! Software-triggered CPURST */ + DL_SYSCTL_RESET_CAUSE_CPURST_SW_TRIGGERED = SYSCTL_RSTCAUSE_ID_CPUSW, +} DL_SYSCTL_RESET_CAUSE; + +/** @enum DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL */ +typedef enum { + /*! DATA Bank Read Write Protect Firewall both RW allowed */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_ENABLED = 0x0, + /*! DATA Bank Read Write Protect Firewall read only */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_R_ONLY = 0x1, + /*! DATA Bank Read Write Protect Firewall both RW disabled */ + DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL_RW_DISABLED = 0x2, +} DL_SYSCTL_DATA_BANK_READ_WRITE_PROTECT_FIREWALL; + +/** + * @brief Enable sleep on exit + * + * Enables sleep on exit when the CPU moves from handler mode to thread mode. + * By enabling, allows an interrupt driven application to avoid returning to + * an empty main application. + */ +__STATIC_INLINE void DL_SYSCTL_enableSleepOnExit(void) +{ + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; +} + +/** + * @brief Disable sleep on exit + * + * Disables sleep on exit when the CPU moves from handler mode to thread mode. + */ +__STATIC_INLINE void DL_SYSCTL_disableSleepOnExit(void) +{ + SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Check if sleep on exit is enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSleepOnExitEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SLEEPONEXIT_Msk) == SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable send event on pending bit + * + * When enabled, any enabled event and all interrupts (including disabled + * interrupts) can wakeup the processor. + */ +__STATIC_INLINE void DL_SYSCTL_enableEventOnPend(void) +{ + SCB->SCR |= SCB_SCR_SEVONPEND_Msk; +} + +/** + * @brief Disable send event on pending bit + * + * When disabled, only enabled interrupts or events can wake up the processor. + * Disabled interrupts are excluded. + */ +__STATIC_INLINE void DL_SYSCTL_disableEventOnPend(void) +{ + SCB->SCR &= ~(SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Check if send event on pending bit is enabled + * + * @return Returns the enabled status of the send event on pending bit + * + * @retval true Send event on pending bit is enabled + * @retval false Send event on pending bit is disabled + */ +__STATIC_INLINE bool DL_SYSCTL_isEventOnPendEnabled(void) +{ + return ((SCB->SCR & SCB_SCR_SEVONPEND_Msk) == SCB_SCR_SEVONPEND_Msk); +} + +/*! + * @brief Change MCLK source + * + * To ensure good clocking behavior, these are the recommended steps for transition. + * Valid sources and destinations: LFCLK, SYSOSC, HSCLK + * + * Depending on current MCLK source, steps to switch to next MCLK source can vary. + * This is a macro that redirects to the different possible transitions. + * + * Only valid for RUN modes. In low power modes, MCLK transitions are handled by hardware. + * + * @note Different transition APIs may require different input parameters + * Transitions between LFCLK and HSCLK requires going through SYSOSC. + * + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK + * @sa DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC + * @sa DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK + * @sa DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC + */ +#define DL_SYSCTL_setMCLKSource(current, next, ...) \ + DL_SYSCTL_switchMCLKfrom##current##to##next(__VA_ARGS__); + +/** + * @brief Change MCLK source from SYSOSC to LFCLK + * + * @pre If disabling SYSOSC, high speed oscillators (SYSPLL, HFXT...) must be disabled beforehand. + * @post MCLK source is switched to LFCLK, function will busy-wait until confirmed. + * + * @param[in] disableSYSOSC Whether to leave SYSOSC running or not + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC); + +/** + * @brief Change MCLK source from LFCLK to SYSOSC + * + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + */ +void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void); + +/** + * @brief Change MCLK source from SYSOSC to HSCLK + * + * @pre The desired HSCLK source is enabled beforehand (SYSPLL, HFXT, HFCLK_IN). + * @post MCLK source is switched to HSCLK, function will busy-wait until confirmed. + * + * @param[in] source Desired high-speed clock source + */ +void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source); + +/** + * @brief Change MCLK source from HSCLK to SYSOSC + * + * @pre MCLK is sourced from a valid, running HSCLK source (SYSPLL, HFXT, HFCLK_IN) + * @post MCLK source is switched to SYSOSC, function will busy-wait until confirmed. + * + * @note No HSCLK sources are disabled by this function + */ +void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void); + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN0/SLEEP0 + * + * In RUN0, the MCLK and the CPUCLK run from a fast clock source (SYSOSC, + * HFCLK, or SYSPLL). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN0SLEEP0(void) +{ + DL_SYSCTL_setMCLKSource(LFCLK, SYSOSC); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN1/SLEEP1 + * + * In RUN1, the MCLK and the CPUCLK run from LFCLK (at 32kHz) to reduce active + * power, but SYSOSC is left enabled to service analog modules such as an ADC, + * DAC, OPA, or COMP (in HS mode). + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN1SLEEP1(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) false); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Set the RUN/SLEEP mode power policy to RUN2/SLEEP2 + * + * In RUN2, the MCLK and the CPUCLK run from LFCLK (at 32kHz), and SYSOSC is + * completely disabled to save power. This is the lowest power state with + * the CPU running + * + * Setting the RUN power policy will also set the SLEEP power policy. + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. To actually enter SLEEP mode, you must call + * `__WFI()` to wait for interrupts or `__WFE()` to wait for ARM events. + * `__WFI()` is used in interrupt-driven applications, and `__WFE()` is used + * for interactions between the interrupt handler and main application. + * + * There are three RUN/SLEEP mode policy options: RUN0/SLEEP0, RUN1/SLEEP1, + * and RUN2/SLEEP2. Refer to the device TRM for more information on each policy + * + * @note Since this turns off SYSOSC, HSCLK sources MUST be disabled before calling + * + * @sa DL_SYSCTL_setMCLKSource + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicyRUN2SLEEP2(void) +{ + DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, (bool) true); + SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Get the RUN/SLEEP mode power policy + * + * Get which RUN/SLEEP power policy has been set. + * + * The SLEEP mode behavior is always identical to RUN mode, just with the + * CPUCLK disabled. As such, the SLEEP behavior is determined by the + * configuration of the RUN mode. + * + * @return Returns the current RUN/SLEEP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_RUN_SLEEP + + */ +DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void); + +/** + * @brief Set the STOP mode power policy to STOP0 + * + * In STOP0, the SYSOSC is left running at the current frequency when entering + * STOP mode (either 32MHz, 24MHz, 16MHz, or 4MHz). ULPCLK is always limited + * to 4MHz automatically by hardware, but SYSOSC is not disturbed to support + * consistent operation of analog peripherals such as the ADC, OPA, or COMP. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP1 + * + * In STOP1, the SYSOSC is gear shifted from its current frequency to 4MHz for + * the lowest power consumption in STOP mode with SYSOSC running. SYSOSC and + * ULPCLK both run at 4MHz. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_DISABLESTOP_MASK); +} + +/** + * @brief Set the STOP mode power policy to STOP2 + * + * In STOP2, the SYSOSC is disabled and the ULPCLK is sourced from LFCLK at + * 32kHz. This is the lowest power state in STOP mode. + * + * There are three STOP mode policy options: STOP0, STOP1, and STOP2. + * Refer to the device TRM for more information on each policy. + * + * @post This API does not actually enter STOP mode. After using this API to + * set the power policy, to enter STOP mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTOP2(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STOP; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLESTOP_MASK; +} + +/** + * @brief Get the STOP mode power policy + * + * Get which STOP power policy has been set. + * + * @return Returns the current STOP mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STOP if a STOP power policy + */ +DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void); + +/** + * @brief Set the STANDBY mode power policy to STANDBY0 + * + * In STANDBY0, all PD0 peripherals receive the ULPCLK and LFCLK, and the RTC + * receives RTCCLK. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY0(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_STOPCLKSTBY_MASK); +} + +/** + * @brief Set the STANDBY mode power policy to STANDBY1 + * + * In STANDBY1, only TIMG0 and TIMG1 receive ULPCLK/LFCLK. The RTC continues + * to receive RTCCLK. A TIMG0/1 interrupt, RTC interrupt, or ADC trigger in + * STANDBY1 always triggers an asynchronous fast clock request to wake the + * system. Other PD0 peripherals (such as UART, I2C, GPIO, and COMP) can also + * wake the system upon an external event through an asynchronous fast clock + * request, but they are not actively clocked in STANDBY1. + * + * There are two STANDBY mode policy options: STANDBY0 and STANDBY1. + * + * @post This API does not actually enter STANDBY mode. After using this API to + * set the power policy, to enter STANDBY mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySTANDBY1(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_STANDBY; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_STOPCLKSTBY_MASK; +} + +/** + * @brief Get the STANDBY mode power policy + * + * Get which STANDBY power policy has been set. + * + * @return Returns the current STANDBY mode power policy + * + * @retval One of @ref DL_SYSCTL_POWER_POLICY_STANDBY + */ +DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void); + +/** + * @brief Set power policy to SHUTDOWN mode + * + * In SHUTDOWN mode, no clocks are available. The core regulator is completely + * disabled and all SRAM and register contents are lost, with the exception of + * the 4 bytes of general purpose memory in SYSCTL which may be used to store + * state information. The BOR and bandgap circuit are disabled. The device may + * wake up via a wake-up capable IO, a debug connection, or NRST. SHUTDOWN mode + * has the lowest current consumption of any operating mode. Exiting SHUTDOWN + * mode triggers a BOR. + * + * There is only one SHUTDOWN mode policy option: SHUTDOWN. + * + * @post This API does not actually enter SHUTDOWN mode. After using this API + * to enable SHUTDOWN mode, to enter SHUTDOWN mode you must call `__WFI()` to + * wait for interrupts or `__WFE()` to wait for ARM events. `__WFI()` is used + * in interrupt-driven applications, and `__WFE()` is used for interactions + * between the interrupt handler and main application. + */ +__STATIC_INLINE void DL_SYSCTL_setPowerPolicySHUTDOWN(void) +{ + SYSCTL->SOCLOCK.PMODECFG = SYSCTL_PMODECFG_DSLEEP_SHUTDOWN; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Set the brown-out reset (BOR) threshold level + * + * Note that this API does NOT activate the BOR threshold. After setting the + * threshold level with this API, call @ref DL_SYSCTL_activateBORThreshold + * to actually activate the new threshold. + * + * During startup, the BOR threshold defaults to BOR0 (the lowet value) to + * ensure the device always starts at the specified VDD minimum. After boot, + * the BOR threshold level can be configured to a different level. When the + * BOR threshold is BOR0, a BOR0- violation always generates a BOR- violation + * signal to SYSCTL, generating a BOR level reset. When the BOR threshold is + * re-configured to BOR1, BOR2, or BOR3 the BOR circuit will generate a SYSCTL + * interrupt rather than asserting a BOR- violation. This may be used to give + * the application an indication that the supply has dropped below a certain + * level without causing a reset. If the BOR is in interrupt mode (threshold + * level of BOR1-3), and VDD drops below the respective BORx- level, an + * interrupt will be generated and the BOR circuit will automatically switch + * the BOR threshold level to BOR0 to ensure that a BOR- violation is + * asserted if VDD drops below BOR0-. + * + * @param[in] thresholdLevel The BOR threshold level to set. + * One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL. + * + * @post DL_SYSCTL_activateBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_setBORThreshold( + DL_SYSCTL_BOR_THRESHOLD_LEVEL thresholdLevel) +{ + SYSCTL->SOCLOCK.BORTHRESHOLD = (uint32_t) thresholdLevel; +} + +/** + * @brief Get the brown-out reset (BOR) threshold level + * + * @return Returns the current BOR threshold level. + * + * @retval One of @ref DL_SYSCTL_BOR_THRESHOLD_LEVEL + */ +__STATIC_INLINE DL_SYSCTL_BOR_THRESHOLD_LEVEL DL_SYSCTL_getBORThreshold(void) +{ + return (DL_SYSCTL_BOR_THRESHOLD_LEVEL)(SYSCTL->SOCLOCK.BORTHRESHOLD); +} + +/** + * @brief Activate the BOR threshold level + * + * Attempts to change the active BOR mode to the BOR threshold that was set + * via @ref DL_SYSCTL_setBORThreshold. + * + * Setting this bit also clears any prior BOR violation status indications. + * + * After calling this API, the change can be validated by calling + * @ref DL_SYSCTL_getStatus and checking the return value. + * + * @pre DL_SYSCTL_setBORThreshold + */ +__STATIC_INLINE void DL_SYSCTL_activateBORThreshold(void) +{ + SYSCTL->SOCLOCK.BORCLRCMD = + SYSCTL_BORCLRCMD_KEY_VALUE | SYSCTL_BORCLRCMD_GO_TRUE; +} + +/** + * @brief Resets the device + * + * Resets the device using the type of reset selected. This function does not + * return, the reset will happen immediately. + * + * @param[in] resetType Type of reset to perform. One of @ref + * DL_SYSCTL_RESET. + */ +__STATIC_INLINE void DL_SYSCTL_resetDevice(uint32_t resetType) +{ + SYSCTL->SOCLOCK.RESETLEVEL = resetType; + SYSCTL->SOCLOCK.RESETCMD = + SYSCTL_RESETCMD_KEY_VALUE | SYSCTL_RESETCMD_GO_TRUE; +} + +/** + * @brief Enable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_enableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK |= interruptMask; +} + +/** + * @brief Disable SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to enable. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_disableInterrupt(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.IMASK &= ~(interruptMask); +} + +/** + * @brief Check which SYSCTL interrupts are enabled + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are enabled + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterrupts(uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.IMASK & interruptMask); +} + +/** + * @brief Check interrupt flag of enabled SYSCTL interrupts + * + * Checks if any of the SYSCTL interrupts that were previously enabled are + * pending. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + * + * @sa DL_SYSCTL_enableInterrupt + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getEnabledInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.MIS & interruptMask); +} + +/** + * @brief Check interrupt flag of any SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + * + * @return Which of the requested SYSCTL interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_INTERRUPT values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.RIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL interrupt + * + * Checks if any of the SYSCTL interrupts are pending. Interrupts do not have to + * be previously enabled. + * + * @return The highest priority pending SYSCTL interrupt + * + * @retval One of @ref DL_SYSCTL_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_IIDX DL_SYSCTL_getPendingInterrupt(void) +{ + return (DL_SYSCTL_IIDX)(SYSCTL->SOCLOCK.IIDX); +} + +/** + * @brief Clear pending SYSCTL interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_INTERRUPT. + */ +__STATIC_INLINE void DL_SYSCTL_clearInterruptStatus(uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.ICLR = interruptMask; +} + +/** + * @brief Check interrupt flag of any SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of + * @ref DL_SYSCTL_NMI. + * + * @return Which of the requested SYSCTL non-maskable interrupts are pending + * + * @retval Bitwise OR of @ref DL_SYSCTL_NMI values + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getRawNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + return (SYSCTL->SOCLOCK.NMIRIS & interruptMask); +} + +/** + * @brief Get highest priority pending SYSCTL non-maskable interrupt + * + * Checks if any of the SYSCTL non-maskable interrupts are pending. Interrupts + * do not have to be previously enabled. + * + * @return The highest priority pending SYSCTL non-maskable interrupt + * + * @retval One of @ref DL_SYSCTL_NMI_IIDX values + */ +__STATIC_INLINE DL_SYSCTL_NMI_IIDX DL_SYSCTL_getPendingNonMaskableInterrupt( + void) +{ + return (DL_SYSCTL_NMI_IIDX)(SYSCTL->SOCLOCK.NMIIIDX); +} + +/** + * @brief Clear pending SYSCTL non-maskable interrupts + * + * @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of + * @ref DL_SYSCTL_NMI. + */ +__STATIC_INLINE void DL_SYSCTL_clearNonMaskableInterruptStatus( + uint32_t interruptMask) +{ + SYSCTL->SOCLOCK.NMIICLR = interruptMask; +} + +/** + * @brief Set the behavior when a Flash ECC double error detect (DED) occurs + * + * Configures whether a Flash ECC double error detect (DED) will trigger + * a SYSRST or an NMI (non-maskable interrupt). By default, this error will + * trigger a SYSRST. + * + * @param[in] behavior The behavior when a Flash ECC DED error occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setFlashDEDErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a Flash ECC double error detect (DED) occurs + * + * By default, this error will trigger a SYSRST. + * + * @return The behavior when a Flash ECC DED error occurs + * + * 3@retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getFlashDEDErrorBehavior( + void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_FLASHECCRSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the behavior when a WWDT0 error occurs + * + * Configures whether a WWDT0 error will trigger a BOOTRST or an NMI + * (non-maskable interrupt). By default, this error will trigger a BOOTRST. + * + * @param[in] behavior The behavior when a Flash ECC DED occurrs + * + * @sa DL_SYSCTL_enableNonMaskableInterrupt + */ +__STATIC_INLINE void DL_SYSCTL_setWWDT0ErrorBehavior( + DL_SYSCTL_ERROR_BEHAVIOR behavior) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSTEMCFG, + (((uint32_t) behavior << SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS)) | + SYSCTL_SYSTEMCFG_KEY_VALUE, + (SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK | SYSCTL_SYSTEMCFG_KEY_MASK)); +} + +/** + * @brief Get the behavior when a WWDT0 error occurs + * + * By default, this error will trigger a BOOTRST. + * + * @return The behavior when a WWDT0 error occurs + * + * @retval One of @ref DL_SYSCTL_ERROR_BEHAVIOR + */ +__STATIC_INLINE DL_SYSCTL_ERROR_BEHAVIOR DL_SYSCTL_getWWDT0ErrorBehavior(void) +{ + uint32_t behavior = + (SYSCTL->SOCLOCK.SYSTEMCFG & SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK) >> + SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS; + + return (DL_SYSCTL_ERROR_BEHAVIOR)(behavior); +} + +/** + * @brief Set the Main Clock (MCLK) divider (MDIV) + * + * Additionally, can use this function to disable MDIV. MDIV must be disabled + * before changing SYSOSC frequency. + * + * MDIV is not valid if MCLK source is HSCLK. + * MDIV is not used if MCLK source if LFCLK. + * + * @param[in] divider Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is + * HSCLK, a don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE void DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) divider, + SYSCTL_MCLKCFG_MDIV_MASK); +} +/** + * @brief Get the Main Clock (MCLK) divider (MDIV) + * + * @return The value of the Main Clock (MCLK) divider (MDIV) + * + * @retval Should be DL_SYSCTL_MCLK_DIVIDER_DISABLE if source is HSCLK, a + * don't care if LFCLK, and one of DL_SYSCTL_MCLK_DIVIDER if SYSOSC. + */ +__STATIC_INLINE DL_SYSCTL_MCLK_DIVIDER DL_SYSCTL_getMCLKDivider(void) +{ + uint32_t divider = SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_MDIV_MASK; + + return (DL_SYSCTL_MCLK_DIVIDER)(divider); +} + +/** + * @brief Get the source for the Main Clock (MCLK) + * + * @return The source for the Main Clock (MCLK) + * + * @retval One of @ref DL_SYSCTL_MCLK_SOURCE + */ +__STATIC_INLINE DL_SYSCTL_MCLK_SOURCE DL_SYSCTL_getMCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.MCLKCFG & + (SYSCTL_MCLKCFG_USEHSCLK_MASK | SYSCTL_MCLKCFG_USELFCLK_MASK); + + return (DL_SYSCTL_MCLK_SOURCE)(source); +} + +/** + * @brief Set the target frequency of the System Oscillator (SYSOSC) + * + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * + * The System Oscillator (SYSOSC) is an on-chip, accurate, configurable + * oscillator with factory trimmed support for 32MHz (base frequency) and 4MHz + * (low frequency) operation. + * + * SYSOSC provides a flexible high-speed clock source for the system in cases + * where the HFXT is either not present or not used. + * + * MDIV must be disabled before changing SYSOSC freq. See @ref DL_SYSCTL_setMCLKDivider. + * + * @param[in] freq Target frequency to use for the System Oscillator (SYSOSC). + * @ref DL_SYSCTL_SYSOSC_FREQ_4M or @ref DL_SYSCTL_SYSOSC_FREQ_BASE. + * + * @sa DL_SYSCTL_setMCLKDivider + */ +__STATIC_INLINE void DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ freq) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSOSCCFG, (uint32_t) freq, + SYSCTL_SYSOSCCFG_FREQ_MASK); +} + +/** + * @brief Get the target frequency of the System Oscillator (SYSOSC) + * Target/desired SYSOSC frequency may be different than current/actual SYSOSC + * frequency during gear shift and other operations. + * This function matches what is input by @ref DL_SYSCTL_setSYSOSCFreq. + * + * @return The target frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getTargetSYSOSCFreq(void) +{ + uint32_t freq = SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_FREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Get the current frequency of the System Oscillator (SYSOSC) + * Current/actual SYSOSC frequency may be different than target/desired SYSOSC + * frequency during gear shift and other operations. + * + * @return The current frequency of System Oscillator (SYSOSC). One of + * @ref DL_SYSCTL_SYSOSC_FREQ. + */ +__STATIC_INLINE DL_SYSCTL_SYSOSC_FREQ DL_SYSCTL_getCurrentSYSOSCFreq(void) +{ + uint32_t freq = + SYSCTL->SOCLOCK.CLKSTATUS & SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK; + + return (DL_SYSCTL_SYSOSC_FREQ)(freq); +} + +/** + * @brief Returns status of the different clocks in CKM + * + * @return Full status of all clock selections + * + * @retval Bitwise OR of @ref DL_SYSCTL_CLK_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getClockStatus(void) +{ + return (SYSCTL->SOCLOCK.CLKSTATUS); +} + +/** + * @brief Returns general status of SYSCTL + * + * @return Full status of all general conditions in SYSCTL + * + * @retval Bitwise OR of @ref DL_SYSCTL_STATUS. + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getStatus(void) +{ + return (SYSCTL->SOCLOCK.SYSSTATUS); +} + +/** + * @brief Clear the ECC error bits in SYSSTATUS + * + * The ECC error bits in SYSSTATUS are sticky (they remain set when an ECC + * error occurs even if future reads do not have errors), and can be + * cleared through this API. + */ +__STATIC_INLINE void DL_SYSCTL_clearECCErrorStatus(void) +{ + SYSCTL->SOCLOCK.SYSSTATUSCLR = + (SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR | SYSCTL_SYSSTATUSCLR_KEY_VALUE); +} + +/** + * @brief Change LFCLK source to external crystal LFXT + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFXT is an ultra-low power crystal oscillator which supports driving a + * standard 32.768kHz watch crystal. + * + * To use the LFXT, a watch crystal must be populated between LFXIN and LFXOUT + * pins. Find more info in LFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure LFXT functionality for LFXIN and LFXOUT before + * calling this function. + * + * This basic implementation will busy-wait until LFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the LFXT is + * stabilizing. You can enable LFXTGOOD interrupt, or check CLKSTATUS.LFXTGOOD + * when convenient, as long as you do not switch the source via + * SETUSELFXT until LFXTGOOD is set. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFCLK_IN is disabled (default). + * + * @param[in] config Pointer to the LFCLK configuration struct + * @ref DL_SYSCTL_LFCLKConfig. + */ +void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config); + +/** + * @brief Change LFCLK source to external digital LFCLK_IN + * + * LFOSC is the internal 32kHz oscillator and default LFCLK source after a BOR. + * Once LFCLK source is changed, the change is locked, LFOSC is disabled to + * save power, and LFCLK source cannot be selected again without BOR. + * + * LFCLK_IN is a low frequency digital clock input compatible with 32.768kHz + * typical frequency digital square wave CMOS clock inputs (typical duty + * cycle of 50%). + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * LFCLK_IN. + * + * LFCLK_IN and LFXT are mutually exclusive. + * This function assumes LFXT is disabled (default). + */ +__STATIC_INLINE void DL_SYSCTL_setLFCLKSourceEXLF(void) +{ + SYSCTL->SOCLOCK.EXLFCTL = + (SYSCTL_EXLFCTL_KEY_VALUE | SYSCTL_EXLFCTL_SETUSEEXLF_TRUE); +} + +/** + * @brief Change HFCLK source to external crystal HFXT with default parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * The HFXT startup time is set to ~0.512ms based on the TYP datasheet + * recommendation. Additionally, the HFCLK startup monitor is enabled. + * + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * To modify the default HFXT startup time or disable the startup monitor, use + * @ref DL_SYSCTL_setHFCLKSourceHFXTParams instead of this API. + * + * @param[in] range HFXT frequency range + */ +void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range); + +/** + * @brief Change HFCLK source to external crystal HFXT with custom parameters + * + * HFXT is a high frequency crystal oscillator which supports standard crystals + * and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * To use the HFXT, a crystal or resonator must be populated between HFXIN and HFXOUT + * pins. Find more info in HFXT section of CKM Technical Reference Manual. + * + * GPIO/IOMUX must be configure HFXT functionality for HFXIN and HFXOUT before + * calling this function. + * + * If the HFCLK startup monitor is enabled, then the HFXT will be checked after + * the amount of time specified by the startupTime parameter. + * This basic implementation will busy-wait until HFXT oscillator is stabilized. + * But a more advanced implementation can do other things while the HFXT is + * stabilizing. You can enable HFCLKGOOD interrupt, or check CLKSTATUS.HFCLKGOOD + * when convenient, as long as you do not switch the source before HFCLKGOOD is set. + * + * If the HFCLK startup monitor is disabled, then this implementation will not + * check if the HFXT oscillator is stabilized. + * + * @param[in] range HFXT frequency range + * @param[in] startupTime HFXT startup time + * @param[in] monitorEnable Whether to enable the HFCLK startup monitor + + */ +void DL_SYSCTL_setHFCLKSourceHFXTParams( + DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable); + +/** + * @brief Disable the HFXT + * + * If HFXT is already enabled, application software must verify that either an + * HFCLKGOOD indication or an HFCLKOFF (off/dead) indication in the CLKSTATUS + * register was asserted by hardware before attempting to disable the HFXT + * by clearing HFXTEN. When disabling the HFXT by clearing HFXTEN, the HFXT + * must not be re-enabled again until the HFCLKOFF bit in the CLKSTATUS + * register is set by hardware. + * + * @sa DL_SYSCTL_getClockStatus + */ +__STATIC_INLINE void DL_SYSCTL_disableHFXT(void) +{ + SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_HFXTEN_MASK); +} + +/** + * @brief Change HFCLK source to external digital HFCLK_IN + * + * HFCLK_IN can be used to bypass the HFXT circuit and bring 4-48MHz typical + * frequency digital clock into the devce as HFCLK source instead of HFXT. + * + * HFCLK_IN is a digital clock input compatible with digital square wave CMOS + * clock inputs and should have typical duty cycle of 50%. + * + * Digital clock input must be valid and GPIO/IOMUX must be configured + * separately on the appropriate pin before calling this function to enable + * HFCLK_IN. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKSourceHFCLKIN(void) +{ + /* Some crystal configurations are retained in lower reset levels. Set + * default behavior of HFXT to keep a consistent behavior regardless of + * reset level. */ + DL_SYSCTL_disableHFXT(); + + SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE; +} + +/** + * @brief Get the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @return The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_HSCLK_SOURCE DL_SYSCTL_getHSCLKSource(void) +{ + uint32_t source = SYSCTL->SOCLOCK.HSCLKCFG & SYSCTL_HSCLKCFG_HSCLKSEL_MASK; + + return (DL_SYSCTL_HSCLK_SOURCE)(source); +} + +/** + * @brief Set the source of High Speed Clock (HSCLK) + * + * HSCLK can be sourced by SYSPLL or HFCLK. + * HSCLK is an optional source for MCLK alongside SYSOSC or LFCLK. + * + * @param[in] source The source of HSCLK. One of @ref DL_SYSCTL_HSCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setHSCLKSource(DL_SYSCTL_HSCLK_SOURCE source) +{ + SYSCTL->SOCLOCK.HSCLKCFG = (uint32_t) source; +} + +/** + * @brief Get the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @return The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE DL_SYSCTL_MFPCLK_SOURCE DL_SYSCTL_getMFPCLKSource(void) +{ + uint32_t source = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_MFPCLKSRC_MASK; + + return (DL_SYSCTL_MFPCLK_SOURCE)(source); +} + +/** + * @brief Set the source of Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK is a continuous 4MHz to DAC module in RUN/SLEEP/STOP mode. + * Unlike MFCLK, MFPCLK is async to MCLK/ULPCLK, providing higher DAC precision and performance. + * MFPCLK is the only clock source for DAC. + * + * @param[in] source The source of MFPCLK. One of @ref DL_SYSCTL_MFPCLK_SOURCE. + */ +__STATIC_INLINE void DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE source) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) source, + SYSCTL_GENCLKCFG_MFPCLKSRC_MASK); +} + +/** + * @brief Enable the Medium Frequency Clock (MFCLK) + * + * MFCLK provides a continuous 4MHz clock to drive certain peripherals on the system. + * The 4MHz rate is always derived from SYSOSC, and the divider is automatically + * applied to maintain the 4MHz rate regardless of SYSOSC frequency. + * MCLK is ideal for timers and serial interfaces which require a constant + * clock source in RUN/SLEEP/STOP power modes. + * + * MFCLK can only run if 3 conditions are met: + * + * 1) Power mode must be RUN, SLEEP, or STOP. + * 2) USEMFTICK register bit is set, which this function does + * 3) MDIV must be set to @ref DL_SYSCTL_MCLK_DIVIDER_DISABLE by @ref DL_SYSCTL_setMCLKDivider. + * + * If MCLK source is not SYSOSC, MCLK frequency must be >=32MHz for correct operation of MFCLK. + * + * @sa DL_SYSCTL_setMCLKDivider + * @sa DL_SYSCTL_getMCLKSource + * @sa DL_SYSCTL_getMCLKFreq + */ +__STATIC_INLINE void DL_SYSCTL_enableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEMFTICK_ENABLE; +} + +/** + * @brief Disable the Medium Frequency Clock (MFCLK) + */ +__STATIC_INLINE void DL_SYSCTL_disableMFCLK(void) +{ + SYSCTL->SOCLOCK.MCLKCFG &= ~(SYSCTL_MCLKCFG_USEMFTICK_ENABLE); +} + +/** + * @brief Enable the Middle Frequency Precision Clock (MFPCLK) + * + * MFPCLK provides a continuous 4MHz clock to the DAC. + * + * MFPCLK can be sources from either SYSOSC or HFCLK (HFXT or HFCLK_IN). + * + * The DAC does not have a clock selection mux. Its clock source is selected + * by configuring MFPCLK. + * + * @sa DL_SYSCTL_disableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_enableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_MFPCLKEN_ENABLE; +} + +/** + * @brief Disable the Middle Frequency Precision Clock (MFPCLK) + * @sa DL_SYSCTL_enableMFPCLK + */ +__STATIC_INLINE void DL_SYSCTL_disableMFPCLK(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_MFPCLKEN_ENABLE); +} + +/** + * @brief Set the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @param[in] divider The divider of HFCLK for MFPCLK + * One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER. + */ +__STATIC_INLINE void DL_SYSCTL_setHFCLKDividerForMFPCLK( + DL_SYSCTL_HFCLK_MFPCLK_DIVIDER divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + ((uint32_t) divider << SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS), + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK); +} + +/** + * @brief Get the divider for HFCLK when HFCLK is used as the MFPCLK source + * + * @return Returns the divider for HFCLK for MFPCLK + * + * @retval One of @ref DL_SYSCTL_HFCLK_MFPCLK_DIVIDER + */ +__STATIC_INLINE DL_SYSCTL_HFCLK_MFPCLK_DIVIDER +DL_SYSCTL_getHFCLKDividerForMFPCLK(void) +{ + uint32_t divider = + (SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK) >> + SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS; + + return (DL_SYSCTL_HFCLK_MFPCLK_DIVIDER)(divider); +} + +/** + * @brief Enable the External Clock (CLK_OUT) + * + * CLK_OUT is provided for pushing out digital clocks to external circuits, such + * as an external ADC which does not have its own clock source. + * + * IOMUX setting for CLK_OUT must be configured before using this function. + * + * CLK_OUT has a typical duty cycle of 50% if clock source is HFCLK, SYSPLLOUT1, + * SYSOSC, or LFCLK. If source is MCLK, ULPCLK, or MFCLK, duty cycle is not + * guaranteed to be 50%. + * + * This function performs multiple operations: + * 1) Sets the CLK_OUT source + * 2) Sets the CLK_OUT divider value + * 3) Enables the CLK_OUT divider, which can be disabled by @ref DL_SYSCTL_disableExternalClockDivider + * 4) Enables the CLK_OUT, which can be disabled by @ref DL_SYSCTL_disableExternalClock + * + * @param[in] source The source of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_SOURCE. + * @param[in] divider The divider of CLK_OUT. One of @ref DL_SYSCTL_CLK_OUT_DIVIDE. + * + * @sa DL_SYSCTL_disableExternalClock + * @sa DL_SYSCTL_disableExternalClockDivider + */ +__STATIC_INLINE void DL_SYSCTL_enableExternalClock( + DL_SYSCTL_CLK_OUT_SOURCE source, DL_SYSCTL_CLK_OUT_DIVIDE divider) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, + (uint32_t) divider | (uint32_t) source, + SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK | SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK | + SYSCTL_GENCLKCFG_EXCLKSRC_MASK); + SYSCTL->SOCLOCK.GENCLKEN |= SYSCTL_GENCLKEN_EXCLKEN_ENABLE; +} + +/** + * @brief Disable the External Clock (CLK_OUT) + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClock(void) +{ + SYSCTL->SOCLOCK.GENCLKEN &= ~(SYSCTL_GENCLKEN_EXCLKEN_ENABLE); +} + +/** + * @brief Disable the External Clock (CLK_OUT) Divider + * @sa DL_SYSCTL_enableExternalClock + */ +__STATIC_INLINE void DL_SYSCTL_disableExternalClockDivider(void) +{ + SYSCTL->SOCLOCK.GENCLKCFG &= ~(SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE); +} + +/** + * @brief Blocks all asynchronous fast clock requests + * + * To block specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C. + */ +__STATIC_INLINE void DL_SYSCTL_blockAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE; +} + +/** + * @brief Allows all asynchronous fast clock requests + * + * Although this allows all async fast clock requests, individual IPs may still + * be blocking theirs. + * + * To allow specific async fast clock requests on certain IP, refer to their + * individual driverlib. Examples include: RTC, UART, SPI, I2C, GPIO. + */ +__STATIC_INLINE void DL_SYSCTL_allowAllAsyncFastClockRequests(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE); +} + +/** + * @brief Generates an asynchronous fast clock request upon any IRQ request to CPU. + * + * Provides lowest latency interrupt handling regardless of system clock speed. + * Blockable by @ref DL_SYSCTL_blockAllAsyncFastClockRequests + * + * @sa DL_SYSCTL_blockAllAsyncFastClockRequests + */ +__STATIC_INLINE void DL_SYSCTL_enableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE; +} + +/** + * @brief Maintains current system clock speed for IRQ request to CPU. + * + * Latency for interrupt handling will be higher at lower system clock speeds. + */ +__STATIC_INLINE void DL_SYSCTL_disableFastCPUEventHandling(void) +{ + SYSCTL->SOCLOCK.SYSOSCCFG &= ~(SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE); +} + +/** + * @brief Set the lower SRAM boundary address to act as partition for read-execute + * permission + * + * Specify the lower SRAM partition address to protect the code region of SRAM from + * being written to, and prevent the RW ("data") region of SRAM from being + * used for code execution. + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. This is the default + * value. + * + * The address is set with a 32-byte resolution. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @param[in] address Address to act as the SRAM partition address. Value is + * a valid 32-bit SRAM address. Only address bits [19:5] + * i.e. bit 5 to bit 19 are used for the boundary address + */ +__STATIC_INLINE void DL_SYSCTL_setLowerSRAMBoundaryAddress(uint32_t address) +{ + SYSCTL->SOCLOCK.SRAMBOUNDARY = + (((uint32_t) address) & SYSCTL_SRAMBOUNDARY_ADDR_MASK); +} + +/** + * @brief Get the lower SRAM boundary address + * + * Get the lower SRAM partition address + * The lower SRAM partition address creates lower and higher partitions: + * - Lower partition is Read-Write only, no execute + * - Upper partition is Read-Execute only, no write + * If the upper SRAM partition is also set it creates a middle partition: + * - Lower partition is Read-Write only, no execute + * - Middle partition is Read-Execute only, no write + * - Upper partition is Read-Write only, no execute + * A partition address of 0x0 is a special case and indicates that all SRAM is + * configured with RWX (read-write-execute) permissions. + * + * The address is set with a 32-byte granularity. The address written is the + * system memory map address of the partition (0x200X_XXXX). + * + * @return The SRAM partition address offset from the SRAM base address + * + * @retval Value is range in [0x0, 0x000FFFE0] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getLowerSRAMBoundaryAddress(void) +{ + return (SYSCTL->SOCLOCK.SRAMBOUNDARY); +} + +/** + * @brief Set flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @param[in] waitState Desired number of flash wait states. One of + * @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE void DL_SYSCTL_setFlashWaitState( + DL_SYSCTL_FLASH_WAIT_STATE waitState) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.MCLKCFG, (uint32_t) waitState, + SYSCTL_MCLKCFG_FLASHWAIT_MASK); +} + +/** + * @brief Get flash wait state + * + * @note Flash wait states are managed automatically by SYSCTL when MCLK is + * running from SYSOSC or LFCLK. + * @note This wait state is only applied if MCLK running from SYSPLL, HFXT, + * or HFCLK_IN. + * + * Consult device specific datasheet for proper values. + * + * @return Number of flash wait states. One of @ref DL_SYSCTL_FLASH_WAIT_STATE. + */ +__STATIC_INLINE DL_SYSCTL_FLASH_WAIT_STATE DL_SYSCTL_getFlashWaitState(void) +{ + uint32_t waitState = + SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_FLASHWAIT_MASK; + + return (DL_SYSCTL_FLASH_WAIT_STATE)(waitState); +} + +/** + * @brief Read Frequency Clock Counter (FCC) + * @return 22-bit value of Frequency Clock Counter (FCC) + */ +__STATIC_INLINE uint32_t DL_SYSCTL_readFCC(void) +{ + return (SYSCTL->SOCLOCK.FCC); +} + +/** + * @brief Start Frequency Clock Counter (FCC) + * + * If FCC_IN is already logic high, counting starts immediately. + * When using level trigger, FCC_IN should be low when GO is set, and trigger + * pulse should be sent to FCC_IN after starting FCC. + */ +__STATIC_INLINE void DL_SYSCTL_startFCC(void) +{ + SYSCTL->SOCLOCK.FCCCMD = (SYSCTL_FCCCMD_KEY_VALUE | SYSCTL_FCCCMD_GO_TRUE); +} + +/** + * @brief Returns whether FCC is done capturing + * + * When capture completes, FCCDONE is set by hardware. + * FCCDONE is read-only and is automatically cleared by hardware when a new + * capture is started. + * + * @return Whether FCC is done or not + * @retval true or false (boolean) + */ +__STATIC_INLINE bool DL_SYSCTL_isFCCDone(void) +{ + return (DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_FCCDONE_DONE) == + SYSCTL_CLKSTATUS_FCCDONE_DONE; +} + +/** + * @brief Configure the Frequency Clock Counter (FCC) + * + * FCC enables flexible in-system testing and calibration of a variety of oscillators + * and clocks on the device. The FCC counts the number of clock periods seen on the + * selected clock source within a known fixed trigger period (derived from a secondary + * reference source) to provide an estimation of the frequency of the source clock. + * + * @param[in] trigLvl Determines if active high level trigger or rising-edge + * to rising-edge. One of @ref DL_SYSCTL_FCC_TRIG_TYPE. + * @sa DL_SYSCTL_setFCCPeriods must be called to configure + * number of rising-edge to rising-edge periods when + * DL_SYSCTL_FCC_TRIG_TYPE_RISE_RISE is selected. + * @param[in] trigSrc Determines which clock source to trigger FCC from. One of + * @ref DL_SYSCTL_FCC_TRIG_SOURCE. + * @param[in] clkSrc Which clock source to capture and measure frequency of. One of + * @ref DL_SYSCTL_FCC_CLOCK_SOURCE. + */ +void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl, + DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc); + +/** + * @brief Sets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * Set the number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @param[in] periods One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE void DL_SYSCTL_setFCCPeriods(DL_SYSCTL_FCC_TRIG_CNT periods) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) periods, + SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK); +} + +/** + * @brief Gets number of rising-edge to rising-edge period for Frequency + * Clock Counter (FCC) + * + * @return One of @ref DL_SYSCTL_FCC_TRIG_CNT + */ +__STATIC_INLINE DL_SYSCTL_FCC_TRIG_CNT DL_SYSCTL_getFCCPeriods(void) +{ + uint32_t periods = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK; + + return (DL_SYSCTL_FCC_TRIG_CNT)(periods); +} + +/** + * @brief Enable Frequency Correction Loop (FCL) in Internal Resistor Mode + * + * Once FCL is enable, it cannot be disabled by software. A BOOTRST is required. + */ +__STATIC_INLINE void DL_SYSCTL_enableSYSOSCFCL(void) +{ + SYSCTL->SOCLOCK.SYSOSCFCLCTL = + (SYSCTL_SYSOSCFCLCTL_KEY_VALUE | SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE); +} + +/** + * @brief Enable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_enableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_ENABLE; +} + +/** + * @brief Disable write protection of selected SYSCTL registers + * + * Protecting writes to configuration registers in SYSCTL can add a layer of + * robustness against unintended changes during runtime. + * + * @note Does not protect all SYSCTL registers, see TRM for more detail. + */ +__STATIC_INLINE void DL_SYSCTL_disableWriteLock(void) +{ + SYSCTL->SOCLOCK.WRITELOCK = SYSCTL_WRITELOCK_ACTIVE_DISABLE; +} + +/** + * @brief Sets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @param[in] setting One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE void DL_SYSCTL_setVBOOSTConfig(DL_SYSCTL_VBOOST setting) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG, (uint32_t) setting, + SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK); +} + +/** + * @brief Gets operating mode of VBOOST (analog charge pump) + * + * Active VBOOST circuitry is needed for COMP/OPA/GPAMP (if present on device). + * VBOOST has a startup time, so consider power consumption versus desired startup time. + * + * @note Although VBOOST clock source is automatically managed, it is up to + * application software to ensure certain cases, or else ANACLKERR occurs. + * See VBOOST section of TRM for more details. + * @return One of @ref DL_SYSCTL_VBOOST. + */ +__STATIC_INLINE DL_SYSCTL_VBOOST DL_SYSCTL_getVBOOSTConfig(void) +{ + uint32_t setting = + SYSCTL->SOCLOCK.GENCLKCFG & SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK; + + return (DL_SYSCTL_VBOOST)(setting); +} + +/** + * @brief Return byte that was saved through SHUTDOWN + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * + * @return 8-bit value of Shutdown Storage Byte. + */ +__STATIC_INLINE uint8_t DL_SYSCTL_getShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index) +{ + const volatile uint32_t *pReg = &SYSCTL->SOCLOCK.SHUTDNSTORE0; + + return (uint8_t)( + *(pReg + (uint32_t) index) & SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Save a byte to SHUTDOWN memory + * + * Shutdown memory persists beyond BOR, BOOTRST, and SYSRST. + * + * @note Parity bits and parity fault checking is done by hardware. + * + * @param[in] index One of @ref DL_SYSCTL_SHUTDOWN_STORAGE_BYTE. + * @param[in] data 8-bit data to save in memory + */ +__STATIC_INLINE void DL_SYSCTL_setShutdownStorageByte( + DL_SYSCTL_SHUTDOWN_STORAGE_BYTE index, uint8_t data) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.SHUTDNSTORE0 + (uint32_t) index, data, + SYSCTL_SHUTDNSTORE0_DATA_MASK); +} + +/** + * @brief Enable SHUTDOWN IO Release + * + * After shutdown, IO is locked in previous state. + * + * @note Release IO after re-configuring IO to their proper state. + */ +__STATIC_INLINE void DL_SYSCTL_releaseShutdownIO(void) +{ + SYSCTL->SOCLOCK.SHDNIOREL = + (SYSCTL_SHDNIOREL_KEY_VALUE | SYSCTL_SHDNIOREL_RELEASE_TRUE); +} + +/** + * @brief Disable the reset functionality of the NRST pin + * + * Disabling the NRST pin allows the pin to be configured as a GPIO. + * Once disabled, the reset functionality can only be re-enabled by a POR. + * + * @note The register is write-only, so the EXRSTPIN register + * will always appear as "Disabled" in the debugger + */ +__STATIC_INLINE void DL_SYSCTL_disableNRSTPin(void) +{ + SYSCTL->SOCLOCK.EXRSTPIN = + (SYSCTL_EXRSTPIN_KEY_VALUE | SYSCTL_EXRSTPIN_DISABLE_TRUE); +} + +/** + * @brief Disable Serial Wire Debug (SWD) functionality + * + * SWD pins are enabled by default after cold start to allow a debug connection. + * It is possible to disable SWD on these pins to use for other functionality. + * + * @post SWD is disabled, but pins must be re-configured separately. + * + * @note Cannot debug the device after disabling SWD. Only re-enabled by POR. + */ +__STATIC_INLINE void DL_SYSCTL_disableSWD(void) +{ + SYSCTL->SOCLOCK.SWDCFG = + (SYSCTL_SWDCFG_KEY_VALUE | SYSCTL_SWDCFG_DISABLE_TRUE); +} + +/** + * @brief Return byte that is stored in RSTCAUSE. + * + * @return The cause of reset. One of @ref DL_SYSCTL_RESET_CAUSE + */ +__STATIC_INLINE DL_SYSCTL_RESET_CAUSE DL_SYSCTL_getResetCause(void) +{ + uint32_t resetCause = SYSCTL->SOCLOCK.RSTCAUSE & SYSCTL_RSTCAUSE_ID_MASK; + + return (DL_SYSCTL_RESET_CAUSE)(resetCause); +} + +/** + * @brief Set the HFXT startup time + * + * Specify the HFXT startup time in 64us resolution. If the HFCLK startup + * monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time + * expires. + * + * @param[in] startupTime The HFXT startup time to set in ~64us steps. + * Value between [0x0 (~0s), 0xFF (~16.32ms)]. + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTStartupTime(uint32_t startupTime) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, startupTime, + SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Get the HFXT startup time + * + * @return Returns the HFXT startup time in ~64us steps + * + * @retval Value between [0x0 (~0s), 0xFF (~16.32ms)] + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getHFXTStartupTime(void) +{ + return (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTTIME_MASK); +} + +/** + * @brief Set the HFXT frequency range + * + * The high frequency crystal oscillator (HFXT) can be used with standard + * crystals and resonators in the 4-48MHz range to generate a stable high-speed + * reference clock for the system. + * + * @param[in] range One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE void DL_SYSCTL_setHFXTFrequencyRange( + DL_SYSCTL_HFXT_RANGE range) +{ + DL_Common_updateReg(&SYSCTL->SOCLOCK.HFCLKCLKCFG, ((uint32_t) range), + SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK); +} + +/** + * @brief Get the HFXT frequency range + * + * @return Returns the HFXT frequency range + * + * @retval One of @ref DL_SYSCTL_HFXT_RANGE + */ +__STATIC_INLINE DL_SYSCTL_HFXT_RANGE DL_SYSCTL_getHFXTFrequencyRange(void) +{ + uint32_t range = + (SYSCTL->SOCLOCK.HFCLKCLKCFG & SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK) >> + SYSCTL_HFCLKCLKCFG_HFXTRSEL_OFS; + + return (DL_SYSCTL_HFXT_RANGE)(range); +} + +/** + * @brief Enable the HFCLK startup monitor + * + * The HFXT takes time to start after being enabled. A startup monitor is + * provided to indicate to the application software if the HFXT has successfully + * started, at which point the HFCLK can be selected to source a variety of + * system functions. The HFCLK startup monitor also supports checking the + * HFCLK_IN digital clock input for a clock stuck fault. + * + */ +__STATIC_INLINE void DL_SYSCTL_enableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG |= SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE; +} + +/** + * @brief Disable the HFCLK startup monitor + */ +__STATIC_INLINE void DL_SYSCTL_disableHFCLKStartupMonitor(void) +{ + SYSCTL->SOCLOCK.HFCLKCLKCFG &= ~(SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK); +} + +/** + * @brief Retrieves the calibration constant of the temperature sensor to be + * used in temperature calculation. + * + * @retval Temperature sensor calibration data + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getTempCalibrationConstant(void) +{ + return DL_FactoryRegion_getTemperatureVoltage(); +} + +/** + * @brief Initializes the Read Execute (RX) Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the read execute protect firewall + * @param[in] endAddr The end address of the read execute protect firewall + * + * @return If the Read Execute Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initReadExecuteProtectFirewall( + uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Initializes the IP Protect Firewall + * + * The firewall security configuration can only be configured if INITDONE has + * not been issued by the CSC. + * This API checks if INITDONE has been issued. If it has not been issued, + * then the start and end addresses are set, and then it enables the firewall. + * If INITDONE has been issused, then the API immediately returns. + * + * @param[in] startAddr The start address of the IP protect firewall + * @param[in] endAddr The end address of the IP protect firewall + * + * @return If the IP Protect Firewall was configured + * + * @retval true If INITDONE was not issued and the firewall was configured + * @retval false If INITDONE was issued and the firewall was not configured + */ +bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr); + +/** + * @brief Set the address range of the Write Protect Firewall + * + * Set Write Protection starting at 0x0 of flash, for the first + * 32KB at 1KB granularity. + * Setting a bit to 1 enables write protection, and setting a bit to 0 + * allows write. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] addrMask The mask to set the address range for the Write Protect + * Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setWriteProtectFirewallAddrRange( + uint32_t addrMask) +{ + SYSCTL->SECCFG.FWEPROTMAIN = addrMask; +} + +/** + * @brief Get the address range of the Write Protect Firewall + * + * @retval The address range for the Write Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getWriteProtectFirewallAddrRange(void) +{ + return (SYSCTL->SECCFG.FWEPROTMAIN); +} + +/** + * @brief Set the start address of the Read Execute (RX) Protect Firewall + * + * Set the start of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the read execute protect + * firewall. The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINSTART = + (startAddr & SYSCTL_FRXPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The start address of the read execute protect firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINSTART); +} + +/** + * @brief Set the end address of the Read Execute (RX) Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from both read and execute accesses. The firewall is configured as an + * address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is RX + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are RX protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the read execute protect firewall. + * The 6 LSBs are don't cares. + */ +__STATIC_INLINE void DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd( + uint32_t endAddr) +{ + SYSCTL->SECCFG.FRXPROTMAINEND = + (endAddr & SYSCTL_FRXPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the Read Execute (RX) Protect Firewall + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * + * @return The end address of the Read Execute Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getReadExecuteProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FRXPROTMAINEND); +} + +/** + * @brief Set the start address of the IP Protect Firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] startAddr The start address of the IP Protect Firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrStart( + uint32_t startAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINSTART = + (startAddr & SYSCTL_FIPPROTMAINSTART_ADDR_MASK); +} + +/** + * @brief Get the start address of the IP Protect Firewall + * + * @return The start address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrStart(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINSTART); +} + +/** + * @brief Set the end address of the IP Protect firewall + * + * Set the end of the range of Flash MAIN memory that needs to be guarded + * from read access, allowing only execute accesses. The firewall is configured + * as an address range. + * + * The start and end addresses are specified at 64B sector granularity, so + * the 6 LSBs are don't cares. + * If the start address is equal to the end address, then one sector is IP + * protected. If the end address is equal to the start address + 1, then two + * sectors are protected, and so on. If the end address is less than the start + * address, the no sectors are IP protected. The hardware does not perform any + * checks on the addresses. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST. + * + * @param[in] endAddr The end address of the IP Protect firewall + */ +__STATIC_INLINE void DL_SYSCTL_setIPProtectFirewallAddrEnd(uint32_t endAddr) +{ + SYSCTL->SECCFG.FIPPROTMAINEND = + (endAddr & SYSCTL_FIPPROTMAINEND_ADDR_MASK); +} + +/** + * @brief Get the end address of the IP Protect Firewall + * + * @return The end address of the IP Protect Firewall + */ +__STATIC_INLINE uint32_t DL_SYSCTL_getIPProtectFirewallAddrEnd(void) +{ + return (SYSCTL->SECCFG.FIPPROTMAINEND); +} + +/** + * @brief Enable Read Execute (RX) Protect Firewall + * + * Enables the Read Execute Protect Firewall before INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableReadExecuteProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_FLRXPROT_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable IP Protect Firewall + * + * Enables the IP Protect Firewall before INITDONE. After INITDONE, + * this configuration gets locked until the next BOOTRST. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + */ +__STATIC_INLINE void DL_SYSCTL_enableIPProtectFirewall(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_SECSTATUS_FLIPPROT_ENABLED | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Enable SRAM Boundary Lock + * + * When SRAM Boundary Lock is enabled, the SRAMBOUNDARY register is only + * writeable only until INITDONE. After INITDONE, the SRAMBOUNDARY register + * cannot be written. + * + * When disabled, the SRAMBOUNDARY register is writeable throughout the + * application, even after INITDONE. + * + * @note This bit can be written only before INITDONE. At INITDONE, this + * configuration gets locked and stays locked until the next BOOTRST + * + * @sa DL_SYSCTL_setSRAMBoundaryAddress + */ +__STATIC_INLINE void DL_SYSCTL_enableSRAMBoundaryLock(void) +{ + SYSCTL->SECCFG.FWENABLE |= + (SYSCTL_FWENABLE_SRAMBOUNDARYLOCK_ENABLE | SYSCTL_FWENABLE_KEY_VALUE); +} + +/** + * @brief Checks if INITDONE has been issued by the CSC + * + * @return Whether INITDONE has been issued or not + * + * @retval true If INITDONE has been issued + * @retval false If INITDONE has not been issued + */ +__STATIC_INLINE bool DL_SYSCTL_isINITDONEIssued(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_INITDONE_YES) == + SYSCTL_SECSTATUS_INITDONE_YES); +} + +/** + * @brief Checks if Customer Startup Code (CSC) exists in system + * + * @return Whether CSC exists in system + * + * @retval true If CSC exists in system + * @retval false If CSC does not exist in system + */ +__STATIC_INLINE bool DL_SYSCTL_ifCSCExists(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_CSCEXISTS_YES) == + SYSCTL_SECSTATUS_CSCEXISTS_YES); +} + +/** + * @brief Checks if Read Execute (RX) Protect Firewall is enabled + * + * @return Whether Read Execute Protect Firewall is enabled + * + * @retval true If Read Execute Protect Firewall is enabled + * @retval false If Read Execute Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isReadExecuteProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLRXPROT_ENABLED) == + SYSCTL_SECSTATUS_FLRXPROT_ENABLED); +} + +/** + * @brief Checks if IP Protect Firewall is enabled + * + * @return Whether IP Protect Firewall is enabled + * + * @retval true If IP Protect Firewall is enabled + * @retval false If IP Protect Firewall is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isIPProtectFirewallEnabled(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & SYSCTL_SECSTATUS_FLIPPROT_ENABLED) == + SYSCTL_SECSTATUS_FLIPPROT_ENABLED); +} + +/** + * @brief Checks if SRAM Boundary Lock is enabled + * + * @return Whether SRAM Boundary Lock is enabled + * + * @retval true If SRAM Boundary Lock is enabled + * @retval false If SRAM Boundary Lock is not enabled + */ +__STATIC_INLINE bool DL_SYSCTL_isSRAMBoundaryLocked(void) +{ + return ((SYSCTL->SECCFG.SECSTATUS & + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED) == + SYSCTL_SECSTATUS_SRAMBOUNDARYLOCK_ENABLED); +} + +/** + * @brief Indicate that INIT is done + * + * After INITDONE is issued, the security configuration is locked and enforced. + * A SYSRST will occur, restarting startup code execution, and the main + * application is launched. + * + * There is no hardware support to enforce a timeout if INITDONE is not issued + * in a reasonable period of time. It is recommended that the CSC use a + * watchdog to ensure that INITDONE is issued in a timely manner. + */ +__STATIC_INLINE void DL_SYSCTL_issueINITDONE(void) +{ + SYSCTL->SECCFG.INITDONE |= + (SYSCTL_INITDONE_PASS_TRUE | SYSCTL_INITDONE_KEY_VALUE); +} + +/** + * @brief Checks if Flash Bank swapping is enabled + * + * @return Whether Flash Bank swap is enabled + * + * @retval false This is not a multi-bank device + */ +__STATIC_INLINE bool DL_SYSCTL_isFlashBankSwapEnabled(void) +{ + return false; +} + +/** + * @brief Checks if executing from upper flash bank + * + * @return Whether executing from upper flash bank + * + * @retval false This is not a multi-bank device. + */ +__STATIC_INLINE bool DL_SYSCTL_isExecuteFromUpperFlashBank(void) +{ + return false; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dl_m0p_dl_sysctl_sysctl__include */ +/** @}*/