xtensa: add config Intel_bdw_adsp

This adds the config ti build the toolchain for
the Audio DSP on the Intel Broadwell platform.

The overlay is taken from the sof-gcc9x branch,
commit f16cbc7dd794d0292be3613d6eeac986841f5492

The config has the selections of tools and their versions
from the Sound Open Firmware project.

Signed-off-by: Liam Girdwood <[email protected]>

Author: lrgirdwo

.shippable.yml

@@ -15,6 +15,7 @@ env:
       - TARGET=x86_64-zephyr-elf
       - TARGET=xtensa_sample_controller
       - TARGET=xtensa_intel_apl_adsp
+      - TARGET=xtensa_intel_bdw_adsp
       - TARGET=xtensa_intel_s1000
       - TARGET="tools"
 

README.md

@@ -14,7 +14,7 @@ Currently we build the following toolchains:
 - arm64
 - riscv64
 - sparc
-- xtensa (sample_controller, intel_apl_adsp, intel_s1000)
+- xtensa (sample_controller, intel_apl_adsp, intel_s1000, intel_bdw_adsp)
 
 To build for any of the above, run:
 

configs/xtensa_intel_bdw_adsp.config

@@ -0,0 +1,48 @@
+CT_CONFIG_VERSION="3"
+CT_OBSOLETE=y
+CT_EXPERIMENTAL=y
+CT_LOCAL_TARBALLS_DIR="${OUTPUT_DIR:-${HOME}/x-tools}/sources"
+# CT_PREFIX_DIR_RO is not set
+CT_PATCH_BUNDLED_LOCAL=y
+CT_LOCAL_PATCH_DIR="${CT_TOP_DIR}/../../patches"
+# CT_LOG_PROGRESS_BAR is not set
+CT_ARCH_XTENSA=y
+CT_XTENSA_CUSTOM=y
+# CT_ARCH_USE_MMU is not set
+CT_OVERLAY_NAME="intel_bdw_adsp"
+CT_OVERLAY_LOCATION="./overlays"
+CT_TARGET_VENDOR="zephyr"
+CT_NEWLIB_SRC_DEVEL=y
+CT_NEWLIB_DEVEL_URL="https://github.com/jcmvbkbc/newlib-xtensa.git"
+CT_NEWLIB_DEVEL_BRANCH="xtensa"
+CT_LIBC_NEWLIB_IO_LL=y
+CT_LIBC_NEWLIB_IO_FLOAT=y
+# CT_LIBC_NEWLIB_FSEEK_OPTIMIZATION is not set
+CT_LIBC_NEWLIB_DISABLE_SUPPLIED_SYSCALLS=y
+CT_LIBC_NEWLIB_GLOBAL_ATEXIT=y
+CT_LIBC_NEWLIB_LITE_EXIT=y
+# CT_LIBC_NEWLIB_MULTITHREAD is not set
+CT_LIBC_NEWLIB_RETARGETABLE_LOCKING=y
+# CT_LIBC_NEWLIB_WIDE_ORIENT is not set
+# CT_LIBC_NEWLIB_NANO_MALLOC is not set
+# CT_LIBC_NEWLIB_NANO_FORMATTED_IO is not set
+CT_LIBC_NEWLIB_EXTRA_SECTIONS=y
+CT_LIBC_NANO_NEWLIB=y
+CT_LIBC_NANO_NEWLIB_IO_FLOAT=y
+# CT_LIBC_NANO_NEWLIB_FSEEK_OPTIMIZATION is not set
+CT_LIBC_NANO_NEWLIB_DISABLE_SUPPLIED_SYSCALLS=y
+CT_LIBC_NANO_NEWLIB_GLOBAL_ATEXIT=y
+CT_LIBC_NANO_NEWLIB_LITE_EXIT=y
+# CT_LIBC_NANO_NEWLIB_MULTITHREAD is not set
+CT_LIBC_NANO_NEWLIB_RETARGETABLE_LOCKING=y
+# CT_LIBC_NANO_NEWLIB_WIDE_ORIENT is not set
+CT_LIBC_NANO_NEWLIB_NANO_MALLOC=y
+CT_LIBC_NANO_NEWLIB_NANO_FORMATTED_IO=y
+CT_LIBC_NANO_NEWLIB_EXTRA_SECTIONS=y
+CT_CC_GCC_EXTRA_CONFIG_ARRAY="--with-gnu-ld --with-gnu-as --enable-initfini-array"
+CT_CC_LANG_CXX=y
+CT_CC_GCC_LIBSTDCXX_NANO=y
+CT_DEBUG_GDB=y
+CT_GDB_V_8_3=y
+CT_ISL_V_0_18=y
+CT_LIBICONV_NEEDED=y

go.sh

@@ -123,6 +123,9 @@ for t in ${TARGETS}; do
 			xtensa_intel_apl_adsp)
 				patch -p1 -N < ${GITDIR}/patches/xtensa/hal/intel_apl_adsp/0001-Adding-APL-DSP-config-files.patch
 				;;
+			xtensa_intel_bdw_adsp)
+				patch -p1 -N < ${GITDIR}/patches/xtensa/hal/intel_bdw_adsp/0001-Adding-BDW-DSP-config-files.patch
+				;;
 			xtensa_intel_s1000)
 				patch -p1 -N < ${GITDIR}/patches/xtensa/hal/intel_s1000/0001-Add-Sue-Creek-config-files.patch
 				;;