Update RISC-V GCC 8.3

Pull in fixes from https://github.com/riscv/riscv-gcc/commits/riscv-gcc-8.3.0

Signed-off-by: Kumar Gala <[email protected]>

Author: galak

patches/gcc/8.3.0/0023-RISC-V-Fix-epilogue-unwind-info-with-fp-and-single-s.patch

@@ -0,0 +1,94 @@
+From 1660664ab806bad90af096cd74717bdb18407f70 Mon Sep 17 00:00:00 2001
+From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Sat, 17 Nov 2018 23:31:01 +0000
+Subject: [PATCH 23/42] RISC-V: Fix epilogue unwind info with fp and single sp
+ adjust.
+
+	gcc/
+	* config/riscv/riscv.c (epilogue_cfa_sp_offset): New.
+	(riscv_restore_reg): If restoring HARD_FRAME_POINTER_REGNUM, and
+	epilogue_cfa_sp_offset set, then add REG_CFA_DEF_CFA regnote.
+	(riscv_expand_epilogue): Initialize epilogue_cfa_sp_offset.  Set it
+	to step2 if frame_pointer_needed and step1 is 0.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@266241 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/ChangeLog            |  8 ++++++++
+ gcc/config/riscv/riscv.c | 23 ++++++++++++++++++++++-
+ 2 files changed, 30 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index ee9a790fa47..5b61aee9b1b 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1,3 +1,11 @@
++2018-11-17  Jim Wilson  <[email protected]>
++
++	* config/riscv/riscv.c (epilogue_cfa_sp_offset): New.
++	(riscv_restore_reg): If restoring HARD_FRAME_POINTER_REGNUM, and
++	epilogue_cfa_sp_offset set, then add REG_CFA_DEF_CFA regnote.
++	(riscv_expand_epilogue): Initialize epilogue_cfa_sp_offset.  Set it
++	to step2 if frame_pointer_needed and step1 is 0.
++
+ 2018-10-05  Andrew Waterman  <[email protected]>
+ 	    Jim Wilson  <[email protected]>
+ 
+diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
+index 76bb74fb2d4..c0a9557638e 100644
+--- a/gcc/config/riscv/riscv.c
++++ b/gcc/config/riscv/riscv.c
+@@ -237,6 +237,11 @@ bool riscv_slow_unaligned_access_p;
+ /* Stack alignment to assume/maintain.  */
+ unsigned riscv_stack_boundary;
+ 
++/* If non-zero, this is an offset to be added to SP to redefine the CFA
++   when restoring the FP register from the stack.  Only valid when generating
++   the epilogue.  */
++static int epilogue_cfa_sp_offset;
++
+ /* Which tuning parameters to use.  */
+ static const struct riscv_tune_info *tune_info;
+ 
+@@ -3621,8 +3626,15 @@ riscv_restore_reg (rtx reg, rtx mem)
+   rtx insn = riscv_emit_move (reg, mem);
+   rtx dwarf = NULL_RTX;
+   dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
+-  REG_NOTES (insn) = dwarf;
+ 
++  if (epilogue_cfa_sp_offset && REGNO (reg) == HARD_FRAME_POINTER_REGNUM)
++    {
++      rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
++					 GEN_INT (epilogue_cfa_sp_offset));
++      dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
++    }
++
++  REG_NOTES (insn) = dwarf;
+   RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ 
+@@ -3871,6 +3883,9 @@ riscv_expand_epilogue (int style)
+       return;
+     }
+ 
++  /* Reset the epilogue cfa info before starting to emit the epilogue.  */
++  epilogue_cfa_sp_offset = 0;
++
+   /* Move past any dynamic stack allocations.  */
+   if (cfun->calls_alloca)
+     {
+@@ -3935,6 +3950,12 @@ riscv_expand_epilogue (int style)
+ 
+       REG_NOTES (insn) = dwarf;
+     }
++  else if (frame_pointer_needed)
++    {
++      /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
++	 old value of FP.  */
++      epilogue_cfa_sp_offset = step2;
++    }
+ 
+   if (use_restore_libcall)
+     frame->mask = 0; /* Temporarily fib that we need not save GPRs.  */
+-- 
+2.20.1
+