qemu: Pull in fixes for ARM MPS2/3 platform

galak · galak · commit aaa5f956759a · 2021-05-11T13:45:31.000-05:00
Pull patch series from upstream QEMU for: hw/arm: Fix modelling of SSE-300 TCMs and SRAM https://patchwork.kernel.org/project/qemu-devel/list/?series=479755 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-hw-misc-mps2-scc-Add-QEMU-interface-comment.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-hw-misc-mps2-scc-Add-QEMU-interface-comment.patch
@@ -1,7 +1,7 @@
-From e7e98396465486ba1dba055c54fb9ee258a159d1 Mon Sep 17 00:00:00 2001
+From 4455b24e9b396bcf3bcf90ccf7453af28aff5a82 Mon Sep 17 00:00:00 2001
 From: Peter Maydell <peter.maydell@linaro.org>
 Date: Mon, 12 Apr 2021 14:43:15 +0100
-Subject: [PATCH 01/10] hw/misc/mps2-scc: Add "QEMU interface" comment
+Subject: [PATCH 01/16] hw/misc/mps2-scc: Add "QEMU interface" comment
 
 The MPS2 SCC device doesn't have any documentation of its properties;
 add a "QEMU interface" format comment describing them.
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-hw-misc-mps2-scc-Support-using-CFG0-bit-0-for-remapp.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-hw-misc-mps2-scc-Support-using-CFG0-bit-0-for-remapp.patch
@@ -1,8 +1,11 @@
-From 91b5b1545419eb1954421b9c25e90f6475a8f521 Mon Sep 17 00:00:00 2001
+From 6c88579eb30dc6e81bca150ba6be00547cc37185 Mon Sep 17 00:00:00 2001
 From: Peter Maydell <peter.maydell@linaro.org>
-Date: Mon, 12 Apr 2021 14:43:16 +0100
-Subject: [PATCH 02/10] hw/misc/mps2-scc: Support using CFG0 bit 0 for
+Date: Tue, 4 May 2021 13:09:11 +0100
+Subject: [PATCH 02/16] hw/misc/mps2-scc: Support using CFG0 bit 0 for
  remapping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
 
 On some boards, SCC config register CFG0 bit 0 controls whether
 parts of the board memory map are remapped. Support this with:
@@ -13,6 +16,8 @@ parts of the board memory map are remapped. Support this with:
 
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
 ---
  hw/misc/mps2-scc.c         | 13 ++++++++++---
  include/hw/misc/mps2-scc.h |  9 +++++++++
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-hw-arm-mps2-tz-Implement-AN524-memory-remapping-via-.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-hw-arm-mps2-tz-Implement-AN524-memory-remapping-via-.patch
@@ -1,18 +1,25 @@
-From 6c3dcb888a263dec0d0e47faf82f095204c1d32c Mon Sep 17 00:00:00 2001
+From aefcd8789c4046d9612629060a6c8b0b98af753a Mon Sep 17 00:00:00 2001
 From: Peter Maydell <peter.maydell@linaro.org>
-Date: Mon, 12 Apr 2021 14:43:17 +0100
-Subject: [PATCH 03/10] hw/arm/mps2-tz: Implement AN524 memory remapping via
+Date: Tue, 4 May 2021 13:09:12 +0100
+Subject: [PATCH 03/16] hw/arm/mps2-tz: Implement AN524 memory remapping via
  machine property
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
 
-The AN524 FPGA image supports two memory maps, which differ
-in where the QSPI and BRAM are. In the default map, the BRAM
-is at 0x0000_0000, and the QSPI at 0x2800_0000. In the second
-map, they are the other way around.
+The AN524 FPGA image supports two memory maps, which differ in where
+the QSPI and BRAM are.  In the default map, the BRAM is at
+0x0000_0000, and the QSPI at 0x2800_0000.  In the second map, they
+are the other way around.
 
-In hardware, the initial mapping can be selected by the user
-by writing either "REMAP: BRAM" (the default) or "REMAP: QSPI"
-in the board configuration file. The guest can also dynamically
-change the mapping via the SCC CFG_REG0 register.
+In hardware, the initial mapping can be selected by the user by
+writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the
+board configuration file.  The board config file is acted on by the
+"Motherboard Configuration Controller", which is an entirely separate
+microcontroller on the dev board but outside the FPGA.
+
+The guest can also dynamically change the mapping via the SCC
+CFG_REG0 register.
 
 Implement this functionality for QEMU, using a machine property
 "remap" with valid values "BRAM" and "QSPI" to allow the user to set
@@ -21,10 +28,12 @@ wiring up the bit from the SCC register to also switch the mapping.
 
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20210504120912.23094-4-peter.maydell@linaro.org
 ---
  docs/system/arm/mps2.rst |  10 ++++
- hw/arm/mps2-tz.c         | 106 ++++++++++++++++++++++++++++++++++++++-
- 2 files changed, 115 insertions(+), 1 deletion(-)
+ hw/arm/mps2-tz.c         | 108 ++++++++++++++++++++++++++++++++++++++-
+ 2 files changed, 117 insertions(+), 1 deletion(-)
 
 diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
 index f83b151787..8a75beb3a0 100644
@@ -45,7 +54,7 @@ index f83b151787..8a75beb3a0 100644
 +  Set ``BRAM``/``QSPI`` to select the initial memory mapping. The
 +  default is ``BRAM``.
 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
-index 25016e464d..e980677932 100644
+index 25016e464d..70aa31a7f6 100644
 --- a/hw/arm/mps2-tz.c
 +++ b/hw/arm/mps2-tz.c
 @@ -55,6 +55,7 @@
@@ -69,7 +78,7 @@ index 25016e464d..e980677932 100644
      Clock *sysclk;
      Clock *s32kclk;
 +
-+    int remap;
++    bool remap;
 +    qemu_irq remap_irq;
  };
  
@@ -89,11 +98,11 @@ index 25016e464d..e980677932 100644
  
      object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
      sccdev = DEVICE(scc);
-+    qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap);
++    qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0);
      qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
      qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
      qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
-@@ -573,6 +583,50 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
+@@ -573,6 +583,52 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
      return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
  }
  
@@ -125,13 +134,15 @@ index 25016e464d..e980677932 100644
 +        return;
 +    }
 +
++    memory_region_transaction_begin();
 +    for (i = 0; i < 2; i++) {
 +        TZMPC *mpc = &mms->mpc[i];
 +        MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
 +        hwaddr addr = (i ^ map) ? 0x28000000 : 0;
 +
 +        memory_region_set_address(upstream, addr);
 +    }
++    memory_region_transaction_commit();
 +}
 +
 +static void remap_irq_fn(void *opaque, int n, int level)
@@ -144,7 +155,7 @@ index 25016e464d..e980677932 100644
  static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
                                const char *name, hwaddr size,
                                const int *irqs)
-@@ -711,7 +765,7 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms)
+@@ -711,7 +767,7 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms)
      MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
  
      for (p = mmc->raminfo; p->name; p++) {
@@ -153,7 +164,7 @@ index 25016e464d..e980677932 100644
              return p->size;
          }
      }
-@@ -1095,6 +1149,16 @@ static void mps2tz_common_init(MachineState *machine)
+@@ -1095,6 +1151,16 @@ static void mps2tz_common_init(MachineState *machine)
  
      create_non_mpc_ram(mms);
  
@@ -170,7 +181,7 @@ index 25016e464d..e980677932 100644
      armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
                         boot_ram_size(mms));
  }
-@@ -1117,12 +1181,47 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
+@@ -1117,12 +1183,47 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
      *iregion = region;
  }
  
@@ -186,9 +197,9 @@ index 25016e464d..e980677932 100644
 +    MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj);
 +
 +    if (!strcmp(value, "BRAM")) {
-+        mms->remap = 0;
++        mms->remap = false;
 +    } else if (!strcmp(value, "QSPI")) {
-+        mms->remap = 1;
++        mms->remap = true;
 +    } else {
 +        error_setg(errp, "Invalid remap value");
 +        error_append_hint(errp, "Valid values are BRAM and QSPI.\n");
@@ -218,7 +229,7 @@ index 25016e464d..e980677932 100644
      iic->check = mps2_tz_idau_check;
  }
  
-@@ -1225,6 +1324,11 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
+@@ -1225,6 +1326,11 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
      mmc->raminfo = an524_raminfo;
      mmc->armsse_type = TYPE_SSE200;
      mps2tz_set_default_ram_info(mmc);
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-nios2-Add-Altera-MAX-10-board-support-for-Zephy.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-nios2-Add-Altera-MAX-10-board-support-for-Zephy.patch
@@ -1,7 +1,7 @@
-From 6f6b4209a4912f968685cddc19cc4906e2f61095 Mon Sep 17 00:00:00 2001
+From 28b2a8f91060dcf14bcfb9d60caa5caf399623a9 Mon Sep 17 00:00:00 2001
 From: Kumar Gala <kumar.gala@linaro.org>
 Date: Thu, 25 Mar 2021 18:24:50 -0500
-Subject: [PATCH 04/10] qemu/nios2: Add Altera MAX 10 board support for Zephyr
+Subject: [PATCH 04/16] qemu/nios2: Add Altera MAX 10 board support for Zephyr
  OS
 
 Exisitng 10m50_devboard is not supporting qemu-niso2 on Zephyr OS
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-hw-sparc-Add-leon-at697-machine.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-hw-sparc-Add-leon-at697-machine.patch
@@ -1,7 +1,7 @@
-From 5f4dc79eaffbf7acb14a72443e81ee42b683a923 Mon Sep 17 00:00:00 2001
+From d7e0be4e797c79198728a4b4d2dd6e7e7160bebf Mon Sep 17 00:00:00 2001
 From: Yasushi SHOJI <y-shoji@ispace-inc.com>
 Date: Wed, 9 Mar 2016 12:22:16 +0100
-Subject: [PATCH 05/10] hw/sparc: Add leon (at697) machine
+Subject: [PATCH 05/16] hw/sparc: Add leon (at697) machine
 
 This commit add LEON2 support.  It is taken from AdaCore Qemu
 repository at https://github.com/adacore/qemu.
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0006-hw-sparc-leon-Fix-compilation-errors.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0006-hw-sparc-leon-Fix-compilation-errors.patch
@@ -1,7 +1,7 @@
-From fb227dfc09dbaf347c982072203f625dde24c1d1 Mon Sep 17 00:00:00 2001
+From d6f7f09579a55c28fc29e57dc28ea03d3b2211ac Mon Sep 17 00:00:00 2001
 From: Yasushi SHOJI <y-shoji@ispace-inc.com>
 Date: Thu, 5 Sep 2019 11:06:56 +0900
-Subject: [PATCH 06/10] hw/sparc/leon: Fix compilation errors
+Subject: [PATCH 06/16] hw/sparc/leon: Fix compilation errors
 
 The previous commit, taken from AdaCore repository as is for future
 reference, depends on other commit in the AdaCore repository and fails
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-hw-sparc-leon-timer-Call-leon_timer_io_read-for-TIME.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-hw-sparc-leon-timer-Call-leon_timer_io_read-for-TIME.patch
@@ -1,7 +1,7 @@
-From 5d266778f1d36d200cf07e15d82a885d398ce1a9 Mon Sep 17 00:00:00 2001
+From bdd73723d04fa722c56659e0bd2ed44a1ce4c108 Mon Sep 17 00:00:00 2001
 From: Yasushi SHOJI <y-shoji@ispace-inc.com>
 Date: Fri, 17 May 2019 21:42:30 +0900
-Subject: [PATCH 07/10] hw/sparc/leon: timer: Call leon_timer_io_read() for
+Subject: [PATCH 07/16] hw/sparc/leon: timer: Call leon_timer_io_read() for
  TIMER_1_COUNTER_REGISTER
 
 Accessing timer1 counter register (offset 0x40) always returned 0
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-hw-sparc-leon-Switch-to-transaction-based-ptimer-API.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-hw-sparc-leon-Switch-to-transaction-based-ptimer-API.patch
@@ -1,7 +1,7 @@
-From b1143ad203d22cbe2ab1af20b7f2ee3ae7451dbb Mon Sep 17 00:00:00 2001
+From a64a2a59b1637d1d06b1286802f756241f6e5546 Mon Sep 17 00:00:00 2001
 From: Yasushi SHOJI <y-shoji@ispace-inc.com>
 Date: Mon, 9 Dec 2019 11:56:20 +0900
-Subject: [PATCH 08/10] hw/sparc/leon: Switch to transaction-based ptimer API
+Subject: [PATCH 08/16] hw/sparc/leon: Switch to transaction-based ptimer API
 
 Switch the leon code away from old ptimers to the new
 transaction-based ptimer API.  This requires adding begin/commit calls
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0009-hw-sparc-leon-Fix-compilation-errors-with-qemu-6-cha.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0009-hw-sparc-leon-Fix-compilation-errors-with-qemu-6-cha.patch
@@ -1,7 +1,7 @@
-From e955eabb3289dd3584a997a0671dda44f0a5ecb0 Mon Sep 17 00:00:00 2001
+From fb9a3921040b1115db534f88a74997bffe3204be Mon Sep 17 00:00:00 2001
 From: Kumar Gala <kumar.gala@linaro.org>
 Date: Thu, 25 Mar 2021 18:59:10 -0500
-Subject: [PATCH 09/10] hw/sparc/leon: Fix compilation errors with qemu 6
+Subject: [PATCH 09/16] hw/sparc/leon: Fix compilation errors with qemu 6
  changes
 
 Make updates to build due to upstream changes in qemu 6.0.0
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-Add-ARC-support.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-Add-ARC-support.patch
@@ -1,7 +1,7 @@
-From 4970a86a1fce6420903f3b9dfdeb4bd0c8be5e8e Mon Sep 17 00:00:00 2001
+From c42894f665c808526bbec2659883e303ae15ef9b Mon Sep 17 00:00:00 2001
 From: Alexey Brodkin <abrodkin@synopsys.com>
 Date: Fri, 16 Apr 2021 20:15:42 +0300
-Subject: [PATCH 10/10] Add ARC support
+Subject: [PATCH 10/16] Add ARC support
 
 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
 ---
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-hw-arm-mps2-tz-Don-t-duplicate-modelling-of-SRAM-in-.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-hw-arm-mps2-tz-Don-t-duplicate-modelling-of-SRAM-in-.patch
@@ -0,0 +1,49 @@
+From 78ec7edffef0c0265c80d47b7716a11cf4376b32 Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Mon, 10 May 2021 20:08:39 +0100
+Subject: [PATCH 11/16] hw/arm/mps2-tz: Don't duplicate modelling of SRAM in
+ AN524
+
+The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model
+it that way in hw/arm/armsse.c (along with the associated MPCs).  We
+incorrectly also added an entry to the RAMInfo array for the AN524 in
+hw/arm/mps2-tz.c, which was pointless because the CPU would never see
+it.  Delete it.
+
+The bug had no guest-visible effect because devices in the SSE-200
+take priority over those in the board model (armsse.c maps
+s->board_memory at priority -2).
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/mps2-tz.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
+index 70aa31a7f6..77ff83acb0 100644
+--- a/hw/arm/mps2-tz.c
++++ b/hw/arm/mps2-tz.c
+@@ -243,19 +243,13 @@ static const RAMInfo an524_raminfo[] = { {
+         .size = 512 * KiB,
+         .mpc = 0,
+         .mrindex = 0,
+-    }, {
+-        .name = "sram",
+-        .base = 0x20000000,
+-        .size = 32 * 4 * KiB,
+-        .mpc = -1,
+-        .mrindex = 1,
+     }, {
+         /* We don't model QSPI flash yet; for now expose it as simple ROM */
+         .name = "QSPI",
+         .base = 0x28000000,
+         .size = 8 * MiB,
+         .mpc = 1,
+-        .mrindex = 2,
++        .mrindex = 1,
+         .flags = IS_ROM,
+     }, {
+         .name = "DDR",
+-- 
+2.30.2
+
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0012-hw-arm-mps2-tz-Make-SRAM_ADDR_WIDTH-board-specific.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0012-hw-arm-mps2-tz-Make-SRAM_ADDR_WIDTH-board-specific.patch
@@ -0,0 +1,70 @@
+From d18f61482ab637263731f3296e47ad5ea8256447 Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Mon, 10 May 2021 20:08:40 +0100
+Subject: [PATCH 12/16] hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific
+
+The AN547 sets the SRAM_ADDR_WIDTH for the SSE-300 to 21;
+since this is not the default value for the SSE-300, model this
+in mps2-tz.c as a per-board value.
+
+Reported-by: Devaraj Ranganna <devaraj.ranganna@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/mps2-tz.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
+index 77ff83acb0..f2595b1c7f 100644
+--- a/hw/arm/mps2-tz.c
++++ b/hw/arm/mps2-tz.c
+@@ -123,6 +123,7 @@ struct MPS2TZMachineClass {
+     int numirq; /* Number of external interrupts */
+     int uart_overflow_irq; /* number of the combined UART overflow IRQ */
+     uint32_t init_svtor; /* init-svtor setting for SSE */
++    uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
+     const RAMInfo *raminfo;
+     const char *armsse_type;
+ };
+@@ -806,6 +807,7 @@ static void mps2tz_common_init(MachineState *machine)
+                              OBJECT(system_memory), &error_abort);
+     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
+     qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
++    qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
+     qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
+     qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
+     sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
+@@ -1263,6 +1265,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
+     mmc->numirq = 92;
+     mmc->uart_overflow_irq = 47;
+     mmc->init_svtor = 0x10000000;
++    mmc->sram_addr_width = 15;
+     mmc->raminfo = an505_raminfo;
+     mmc->armsse_type = TYPE_IOTKIT;
+     mps2tz_set_default_ram_info(mmc);
+@@ -1290,6 +1293,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
+     mmc->numirq = 92;
+     mmc->uart_overflow_irq = 47;
+     mmc->init_svtor = 0x10000000;
++    mmc->sram_addr_width = 15;
+     mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */
+     mmc->armsse_type = TYPE_SSE200;
+     mps2tz_set_default_ram_info(mmc);
+@@ -1317,6 +1321,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
+     mmc->numirq = 95;
+     mmc->uart_overflow_irq = 47;
+     mmc->init_svtor = 0x10000000;
++    mmc->sram_addr_width = 15;
+     mmc->raminfo = an524_raminfo;
+     mmc->armsse_type = TYPE_SSE200;
+     mps2tz_set_default_ram_info(mmc);
+@@ -1349,6 +1354,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
+     mmc->numirq = 96;
+     mmc->uart_overflow_irq = 48;
+     mmc->init_svtor = 0x00000000;
++    mmc->sram_addr_width = 21;
+     mmc->raminfo = an547_raminfo;
+     mmc->armsse_type = TYPE_SSE300;
+     mps2tz_set_default_ram_info(mmc);
+-- 
+2.30.2
+
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0013-hw-arm-armsse.c-Correct-modelling-of-SSE-300-interna.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0013-hw-arm-armsse.c-Correct-modelling-of-SSE-300-interna.patch
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0014-hw-arm-armsse-Convert-armsse_realize-to-use-ERRP_GUA.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0014-hw-arm-armsse-Convert-armsse_realize-to-use-ERRP_GUA.patch
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0015-hw-arm-mps2-tz-Allow-board-to-specify-a-boot-RAM-siz.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0015-hw-arm-mps2-tz-Allow-board-to-specify-a-boot-RAM-siz.patch
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0016-hw-arm-Model-TCMs-in-the-SSE-300-not-the-AN547.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0016-hw-arm-Model-TCMs-in-the-SSE-300-not-the-AN547.patch
diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb b/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb
diff --git a/release-notes.md b/release-notes.md
