Re-gen RISC-V GCC patches for gcc 8.3.0

Update the RISC-V gcc patches so they apply against gcc 8.3.0

Signed-off-by: Kumar Gala <[email protected]>

Author: galak

patches/gcc/8.3.0/0001-Backport-of-RISC-V-support-for-libffi.patch

@@ -1,4 +1,4 @@
-From e0f10f22f9dd52a0abf02068176d1720159fc1da Mon Sep 17 00:00:00 2001
+From dc11802c62f9e829ec57f6fd6ada01d7c97e7edf Mon Sep 17 00:00:00 2001
 From: schwab <schwab@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Tue, 8 May 2018 10:29:16 +0000
 Subject: [PATCH 01/22] Backport of RISC-V support for libffi
@@ -24,7 +24,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260033 138bc75d-0d04-0410-961f-8
  create mode 100644 libffi/src/riscv/sysv.S
 
 diff --git a/libffi/ChangeLog b/libffi/ChangeLog
-index fc8a4f82a4c..c1cb542c7ca 100644
+index 97bdfd02bae..5963137eabb 100644
 --- a/libffi/ChangeLog
 +++ b/libffi/ChangeLog
 @@ -1,3 +1,12 @@
@@ -37,9 +37,9 @@ index fc8a4f82a4c..c1cb542c7ca 100644
 +	* src/riscv/ffi.c, src/riscv/ffitarget.h, src/riscv/sysv.S: New
 +	files.
 +
- 2018-07-26  Release Manager
+ 2019-02-22  Release Manager
 
- 	* GCC 8.2.0 released.
+ 	* GCC 8.3.0 released.
 diff --git a/libffi/Makefile.am b/libffi/Makefile.am
 index dc433285362..37f5ecaf3c3 100644
 --- a/libffi/Makefile.am

patches/gcc/8.3.0/0002-PATCH-RISC-V-Use-new-linker-emulations-for-glibc-ABI.patch

@@ -1,4 +1,4 @@
-From 0b345eb3a1ec62baa9d9c82671e0842a194cb8a8 Mon Sep 17 00:00:00 2001
+From 6e300c7b778e19bfe4a84455815dab0f35a7c33c Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Tue, 8 May 2018 21:27:04 +0000
 Subject: [PATCH 02/22] [PATCH] RISC-V: Use new linker emulations for glibc
@@ -16,7 +16,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260056 138bc75d-0d04-0410-961f-8
  2 files changed, 16 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index b93dae5dfb0..1083f9ee4e8 100644
+index d1fd9f6a7b9..2b609c2dd0a 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,9 @@
@@ -26,9 +26,9 @@ index b93dae5dfb0..1083f9ee4e8 100644
 +	(LD_EMUL_SUFFIX): New.
 +	(LINK_SPEC): Use it.
 +
- 2018-07-26  Release Manager
+ 2019-02-22  Release Manager
 
- 	* GCC 8.2.0 released.
+ 	* GCC 8.3.0 released.
 diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
 index aa8a28d5d31..85561846dad 100644
 --- a/gcc/config/riscv/linux.h

patches/gcc/8.3.0/0003-RISC-V-Add-with-multilib-list-support.patch

@@ -1,4 +1,4 @@
-From eb64d6b593a51f2cf2a6e8b043b90e555c8f6c62 Mon Sep 17 00:00:00 2001
+From fb9b78859bafc910d982bfae25340698590d83d5 Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Wed, 9 May 2018 21:17:14 +0000
 Subject: [PATCH 03/22] RISC-V: Add with-multilib-list support.
@@ -22,7 +22,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260096 138bc75d-0d04-0410-961f-8
  create mode 100644 gcc/config/riscv/withmultilib.h
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index 1083f9ee4e8..98bd7ce0e07 100644
+index 2b609c2dd0a..f0f6dcfe75b 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,11 @@
@@ -38,10 +38,10 @@ index 1083f9ee4e8..98bd7ce0e07 100644
 
  	* config/riscv/linux.h (MUSL_ABI_SUFFIX): Delete unnecessary backslash.
 diff --git a/gcc/config.gcc b/gcc/config.gcc
-index 532c33f4c2b..fd5d154e8f6 100644
+index 7af8e028104..822b0d034c5 100644
 --- a/gcc/config.gcc
 +++ b/gcc/config.gcc
-@@ -4131,6 +4131,58 @@ case "${target}" in
+@@ -4134,6 +4134,58 @@ case "${target}" in
  			exit 1
  			;;
  		esac
@@ -170,21 +170,21 @@ index 00000000000..d703147fa64
 +# error "unsupported TARGET_MLIB_ARCH value"
 +#endif
 diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
-index ec20fd26685..7c5cdc762d3 100644
+index 1cc427249a4..0e161d0e61a 100644
 --- a/gcc/doc/install.texi
 +++ b/gcc/doc/install.texi
 @@ -1072,8 +1072,8 @@ sysv, aix.
  @itemx --without-multilib-list
  Specify what multilibs to build.  @var{list} is a comma separated list of
  values, possibly consisting of a single value.  Currently only implemented
--for arm*-*-*, sh*-*-* and x86-64-*-linux*.  The accepted values and meaning
--for each target is given below.
-+for arm*-*-*, riscv*-*-*, sh*-*-* and x86-64-*-linux*.  The accepted
-+values and meaning for each target is given below.
+-for aarch64*-*-*, arm*-*-*, sh*-*-* and x86-64-*-linux*.  The accepted
+-alues and meaning for each target is given below.
++for aarch64*-*-*, arm*-*-*, riscv*-*-*, sh*-*-* and x86-64-*-linux*.  The
++accepted values and meaning for each target is given below.
 
  @table @code
- @item arm*-*-*
-@@ -1128,6 +1128,13 @@ and @code{rmprofile}.
+ @item aarch64*-*-*
+@@ -1137,6 +1137,13 @@ and @code{rmprofile}.
  @code{-mfloat-abi=hard}
  @end multitable
 

patches/gcc/8.3.0/0004-RISC-V-Minor-pattern-name-cleanup.patch

@@ -1,4 +1,4 @@
-From 2d9231f25f3f9cfd03bc4969b95597f8c3e9d3c7 Mon Sep 17 00:00:00 2001
+From 8caf0c1992357a70201e7eaa913bafe36c38308b Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Wed, 16 May 2018 18:37:52 +0000
 Subject: [PATCH 04/22] RISC-V: Minor pattern name cleanup.
@@ -15,7 +15,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260299 138bc75d-0d04-0410-961f-8
  2 files changed, 10 insertions(+), 4 deletions(-)
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index 98bd7ce0e07..aa2af8043f3 100644
+index f0f6dcfe75b..321d78fca38 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,9 @@

patches/gcc/8.3.0/0005-RISC-V-Optimize-switch-with-sign-extended-index.patch

@@ -1,4 +1,4 @@
-From e89f9f869fa27a75d290920784e45ad8b3c644ad Mon Sep 17 00:00:00 2001
+From 493132f79766fd27908aec95358d56fa29311058 Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Thu, 17 May 2018 22:37:38 +0000
 Subject: [PATCH 05/22] RISC-V: Optimize switch with sign-extended index.
@@ -29,7 +29,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260340 138bc75d-0d04-0410-961f-8
  create mode 100644 gcc/testsuite/gcc.target/riscv/switch-si.c
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index aa2af8043f3..4cbec373314 100644
+index 321d78fca38..b657d3e5303 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,13 @@
@@ -72,10 +72,10 @@ index 2a8f87d1e94..b4975888bbb 100644
  	  *op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0);
  	  if (CONST_INT_P (*op1))
 diff --git a/gcc/expr.c b/gcc/expr.c
-index 9ca466144be..b14577f780f 100644
+index bac0c787e4f..61321ab6e29 100644
 --- a/gcc/expr.c
 +++ b/gcc/expr.c
-@@ -11779,11 +11779,26 @@ do_tablejump (rtx index, machine_mode mode, rtx range, rtx table_label,
+@@ -11819,11 +11819,26 @@ do_tablejump (rtx index, machine_mode mode, rtx range, rtx table_label,
      emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, mode, 1,
  			     default_label, default_probability);
 
@@ -105,7 +105,7 @@ index 9ca466144be..b14577f780f 100644
    /* Don't let a MEM slip through, because then INDEX that comes
       out of PIC_CASE_VECTOR_ADDRESS won't be a valid address,
 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
-index b80ff889f15..ff95cde01ed 100644
+index 7d5e65b1a74..4f4cdb8b486 100644
 --- a/gcc/testsuite/ChangeLog
 +++ b/gcc/testsuite/ChangeLog
 @@ -1,3 +1,8 @@
@@ -114,9 +114,9 @@ index b80ff889f15..ff95cde01ed 100644
 +	* gcc.target/riscv/switch-qi.c: New.
 +	* gcc.target/riscv/switch-si.c: New.
 +
- 2018-07-26  Release Manager
+ 2019-02-22  Release Manager
 
- 	* GCC 8.2.0 released.
+ 	* GCC 8.3.0 released.
 diff --git a/gcc/testsuite/gcc.target/riscv/switch-qi.c b/gcc/testsuite/gcc.target/riscv/switch-qi.c
 new file mode 100644
 index 00000000000..973d09aaaf1

patches/gcc/8.3.0/0006-RISC-V-Add-RV32E-support.patch

@@ -1,4 +1,4 @@
-From d2f7c2e7ddac5d2b2fe9d0a0daa4de6dfaad6255 Mon Sep 17 00:00:00 2001
+From 06ab742f982d23488ec2d8c0266cb720fe775f7c Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Fri, 18 May 2018 22:53:55 +0000
 Subject: [PATCH 06/22] RISC-V: Add RV32E support.
@@ -50,7 +50,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260384 138bc75d-0d04-0410-961f-8
  13 files changed, 166 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index 4cbec373314..77a06d49fbc 100644
+index b657d3e5303..2072ac7a8e0 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,26 @@
@@ -142,10 +142,10 @@ index 9db83015aed..8a78aebc320 100644
      {
        error_at (loc, "-march=%s: invalid ISA string", isa);
 diff --git a/gcc/config.gcc b/gcc/config.gcc
-index fd5d154e8f6..1d6f34b46e1 100644
+index 822b0d034c5..a845800d6a6 100644
 --- a/gcc/config.gcc
 +++ b/gcc/config.gcc
-@@ -4080,19 +4080,20 @@ case "${target}" in
+@@ -4083,19 +4083,20 @@ case "${target}" in
 
  		# Infer arch from --with-arch, --target, and --with-abi.
  		case "${with_arch}" in
@@ -168,7 +168,7 @@ index fd5d154e8f6..1d6f34b46e1 100644
  			exit 1
  			;;
  		esac
-@@ -4101,11 +4102,12 @@ case "${target}" in
+@@ -4104,11 +4105,12 @@ case "${target}" in
  		# pick a default based on the ISA, preferring soft-float
  		# unless the D extension is present.
  		case "${with_abi}" in
@@ -182,7 +182,7 @@ index fd5d154e8f6..1d6f34b46e1 100644
  			rv32*) with_abi=ilp32 ;;
  			rv64*d* | rv64g*) with_abi=lp64d ;;
  			rv64*) with_abi=lp64 ;;
-@@ -4119,7 +4121,7 @@ case "${target}" in
+@@ -4122,7 +4124,7 @@ case "${target}" in
 
  		# Make sure ABI and ISA are compatible.
  		case "${with_abi},${with_arch}" in
@@ -354,10 +354,10 @@ index b37ac75d9bb..13693221d26 100644
 +
 +Mask(RVE)
 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
-index bde6b7cbaaf..4477b6d400c 100644
+index e5c4e8125aa..0f88569984c 100644
 --- a/gcc/doc/invoke.texi
 +++ b/gcc/doc/invoke.texi
-@@ -23054,7 +23054,9 @@ conventions are: @samp{ilp32}, @samp{ilp32f}, @samp{ilp32d}, @samp{lp64},
+@@ -23079,7 +23079,9 @@ conventions are: @samp{ilp32}, @samp{ilp32f}, @samp{ilp32d}, @samp{lp64},
  @samp{lp64f}, and @samp{lp64d}.  Some calling conventions are impossible to
  implement on some ISAs: for example, @samp{-march=rv32if -mabi=ilp32d} is
  invalid because the ABI requires 64-bit values be passed in F registers, but F
@@ -368,7 +368,7 @@ index bde6b7cbaaf..4477b6d400c 100644
 
  @item -mfdiv
  @itemx -mno-fdiv
-@@ -23073,7 +23075,8 @@ these instructions.
+@@ -23098,7 +23100,8 @@ these instructions.
  @item -march=@var{ISA-string}
  @opindex march
  Generate code for given RISC-V ISA (e.g.@ @samp{rv64im}).  ISA strings must be
@@ -379,7 +379,7 @@ index bde6b7cbaaf..4477b6d400c 100644
  @item -mtune=@var{processor-string}
  @opindex mtune
 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
-index ff95cde01ed..4c86e7bd3fe 100644
+index 4f4cdb8b486..36311c6893d 100644
 --- a/gcc/testsuite/ChangeLog
 +++ b/gcc/testsuite/ChangeLog
 @@ -1,3 +1,7 @@
@@ -408,7 +408,7 @@ index 45d2c7b6aae..038bd4ec05c 100644
  #if defined (__AVR_3_BYTE_PC__ )
  #  define SIZE 251 /* 256 - 2 bytes for Y - 3 bytes for return address */
 diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
-index 1726ac15f53..050e41dd247 100644
+index 99d410137a5..d44cfdc18da 100644
 --- a/libgcc/ChangeLog
 +++ b/libgcc/ChangeLog
 @@ -1,3 +1,9 @@
@@ -418,9 +418,9 @@ index 1726ac15f53..050e41dd247 100644
 +
 +	* config/riscv/save-restore.S: Add support for rv32e.
 +
- 2018-07-26  Release Manager
+ 2019-02-22  Release Manager
 
- 	* GCC 8.2.0 released.
+ 	* GCC 8.3.0 released.
 diff --git a/libgcc/config/riscv/save-restore.S b/libgcc/config/riscv/save-restore.S
 index 9a6d0c9fcfc..a76c9780902 100644
 --- a/libgcc/config/riscv/save-restore.S

patches/gcc/8.3.0/0007-RISC-V-Add-interrupt-attribute-support.patch

@@ -1,4 +1,4 @@
-From ae581c86a9848c323b60d7f5e4900ed4e473f279 Mon Sep 17 00:00:00 2001
+From 242a6ef793a572e4b49c8e7d72a87fdd4ed3df55 Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Fri, 25 May 2018 22:29:17 +0000
 Subject: [PATCH 07/22] RISC-V: Add interrupt attribute support.
@@ -57,7 +57,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260785 138bc75d-0d04-0410-961f-8
  create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-5.c
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index 77a06d49fbc..8fff651a1a1 100644
+index 2072ac7a8e0..73cb98f285f 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,29 @@
@@ -392,7 +392,7 @@ index 56fe516dbcf..fa681971c4c 100644
  (define_insn "stack_tie<mode>"
    [(set (mem:BLK (scratch))
 diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
-index bfd5ff2b713..bc1a344f71c 100644
+index 11e926e9d47..e651efb4074 100644
 --- a/gcc/doc/extend.texi
 +++ b/gcc/doc/extend.texi
 @@ -5138,6 +5138,12 @@ prologue/epilogue sequences generated by the compiler. Only basic
@@ -409,7 +409,7 @@ index bfd5ff2b713..bc1a344f71c 100644
 
  @node RL78 Function Attributes
 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
-index 4c86e7bd3fe..d2b820342cb 100644
+index 36311c6893d..62690ff9ecd 100644
 --- a/gcc/testsuite/ChangeLog
 +++ b/gcc/testsuite/ChangeLog
 @@ -1,3 +1,11 @@

patches/gcc/8.3.0/0008-RISC-V-Fix-a-comment-typo.patch

@@ -1,4 +1,4 @@
-From fc0da4364e70c2a8874fa71f369f433a9f43dd05 Mon Sep 17 00:00:00 2001
+From 450bc7c0876837dbbde78a75137a9a7d90369226 Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Tue, 29 May 2018 22:31:17 +0000
 Subject: [PATCH 08/22] RISC-V: Fix a comment typo.
@@ -12,7 +12,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260907 138bc75d-0d04-0410-961f-8
  2 files changed, 5 insertions(+), 1 deletion(-)
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index 8fff651a1a1..c889efbea19 100644
+index 73cb98f285f..e595a4e72b2 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,7 @@

patches/gcc/8.3.0/0009-RISC-V-Don-t-clobber-retval-when-__builtin_eh_return.patch

@@ -1,4 +1,4 @@
-From 85a1cb0dcff819ec5cfe2d51be0ed791b9d2dc8d Mon Sep 17 00:00:00 2001
+From 1f9501d1322337c455602e57baf182e5c08e3c0b Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Mon, 4 Jun 2018 23:44:43 +0000
 Subject: [PATCH 09/22] RISC-V: Don't clobber retval when __builtin_eh_return
@@ -30,7 +30,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@261176 138bc75d-0d04-0410-961f-8
  4 files changed, 74 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index c889efbea19..6ce5a7e1447 100644
+index e595a4e72b2..cd86119701f 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,21 @@

patches/gcc/8.3.0/0010-RISC-V-Add-interrupt-attribute-modes.patch

@@ -1,4 +1,4 @@
-From 04ea1da7f5dc017624ba3f6e3084d4c3378291b5 Mon Sep 17 00:00:00 2001
+From 5f7e9359194cf4ea9bff65d4ab1dbc777a13852d Mon Sep 17 00:00:00 2001
 From: wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
 Date: Wed, 6 Jun 2018 19:08:36 +0000
 Subject: [PATCH 10/22] RISC-V: Add interrupt attribute modes.
@@ -39,7 +39,7 @@ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@261244 138bc75d-0d04-0410-961f-8
  create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-umode.c
 
 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
-index 6ce5a7e1447..ef462110cd7 100644
+index cd86119701f..4ba08d2b23a 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,17 @@
@@ -233,7 +233,7 @@ index b9faf00d076..a5940dcc425 100644
    [(set (mem:BLK (scratch))
  	(unspec:BLK [(match_operand:X 0 "register_operand" "r")
 diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
-index bc1a344f71c..50084c114f6 100644
+index e651efb4074..4ad67404724 100644
 --- a/gcc/doc/extend.texi
 +++ b/gcc/doc/extend.texi
 @@ -5144,6 +5144,17 @@ depended upon to work reliably and are not supported.
@@ -255,7 +255,7 @@ index bc1a344f71c..50084c114f6 100644
 
  @node RL78 Function Attributes
 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
-index d2b820342cb..7170c68f261 100644
+index 62690ff9ecd..a28ddc0ff86 100644
 --- a/gcc/testsuite/ChangeLog
 +++ b/gcc/testsuite/ChangeLog
 @@ -1,3 +1,10 @@