diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 92903196..61a68e07 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -849,6 +849,8 @@ jobs: group: ${{ matrix.host.runner }} container: ${{ matrix.host.container }} + env: + TAR_OPTIONS: --no-same-owner defaults: run: shell: bash diff --git a/meta-zephyr-sdk/conf/distro/include/zephyr-sdk.inc b/meta-zephyr-sdk/conf/distro/include/zephyr-sdk.inc index 673d178e..c701c946 100644 --- a/meta-zephyr-sdk/conf/distro/include/zephyr-sdk.inc +++ b/meta-zephyr-sdk/conf/distro/include/zephyr-sdk.inc @@ -14,9 +14,12 @@ DISTRO_FEATURES_NATIVE = "" DISTRO_FEATURES_BACKFILL = "" DISTRO_FEATURES_NATIVESDK = "" -MAINTAINER = "Intel Yocto team" +MAINTAINER = "Zephyr developers / devops team" SSTATE_DIR ?= "${TOPDIR}/../zephyr-cache/sstate-cache" CACHE_forcevariable = "${TOPDIR}/../zephyr-cache/cache" PERSISTENT_DIR = "${TOPDIR}/../zephyr-cache/persistent" DL_DIR ?= "${TOPDIR}/../zephyr-downloads" + +PREFERRED_VERSION_meson:forcevariable = "1.7.%" +PREFERRED_VERSION_nativesdk-meson:forcevariable = "1.7.%" diff --git a/meta-zephyr-sdk/conf/distro/zephyr-sdk.conf b/meta-zephyr-sdk/conf/distro/zephyr-sdk.conf index ca9ea289..b8b270cb 100644 --- a/meta-zephyr-sdk/conf/distro/zephyr-sdk.conf +++ b/meta-zephyr-sdk/conf/distro/zephyr-sdk.conf @@ -1,6 +1,6 @@ require conf/distro/poky.conf require include/zephyr-sdk.inc -DISTRO_VERSION = "0.9" +DISTRO_VERSION = "0.10" PACKAGE_CLASSES = "package_ipk" TARGET_VENDOR = "-zephyr" diff --git a/meta-zephyr-sdk/conf/layer.conf b/meta-zephyr-sdk/conf/layer.conf index b458a754..828fb76c 100644 --- a/meta-zephyr-sdk/conf/layer.conf +++ b/meta-zephyr-sdk/conf/layer.conf @@ -9,4 +9,4 @@ LICENSE_PATH += "${LAYERDIR}/files/additional-licenses" BBFILE_COLLECTIONS += "zephyr-sdk" BBFILE_PATTERN_zephyr-sdk := "^${LAYERDIR}/" BBFILE_PRIORITY_zephyr-sdk = "8" - +LAYERSERIES_COMPAT_zephyr_sdk = "Scarthgap" diff --git a/meta-zephyr-sdk/recipes-core/expat/expat_%.bbappend b/meta-zephyr-sdk/recipes-core/expat/expat_%.bbappend deleted file mode 100644 index d6dbd453..00000000 --- a/meta-zephyr-sdk/recipes-core/expat/expat_%.bbappend +++ /dev/null @@ -1,6 +0,0 @@ -# Override the source URL for expat since the old mirror specified in the meta -# layer is no longer available. - -VERSION_TAG = "${@d.getVar('PV').replace('.', '_')}" - -SRC_URI_prepend = "https://github.com/libexpat/libexpat/releases/download/R_${VERSION_TAG}/expat-${PV}.tar.bz2 " diff --git a/meta-zephyr-sdk/recipes-devtools/arc_qemu/files/cross.patch b/meta-zephyr-sdk/recipes-devtools/arc_qemu/files/cross.patch deleted file mode 100644 index 618a6036..00000000 --- a/meta-zephyr-sdk/recipes-devtools/arc_qemu/files/cross.patch +++ /dev/null @@ -1,30 +0,0 @@ -We need to be able to trigger configure's cross code but we don't want -to set cross_prefix as it does other things we don't want. Patch things -so we can do what we need in the target config case. - -Upstream-Status: Inappropriate [may be rewritten in a way upstream may accept?] -Signed-off-by: Richard Purdie - - -Index: qemu/configure -=================================================================== ---- a/configure -+++ b/configure -@@ -3934,7 +3934,6 @@ if test "$skip_meson" = no; then - fi - echo "strip = [$(meson_quote $strip)]" >> $cross - echo "windres = [$(meson_quote $windres)]" >> $cross -- if test "$cross_compile" = "yes"; then - cross_arg="--cross-file config-meson.cross" - echo "[host_machine]" >> $cross - if test "$mingw32" = "yes" ; then -@@ -3966,9 +3965,6 @@ if test "$skip_meson" = no; then - else - echo "endian = 'little'" >> $cross - fi -- else -- cross_arg="--native-file config-meson.cross" -- fi - mv $cross config-meson.cross - - rm -rf meson-private meson-info meson-logs diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson.inc b/meta-zephyr-sdk/recipes-devtools/meson/meson.inc deleted file mode 100644 index 17a61e0e..00000000 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson.inc +++ /dev/null @@ -1,37 +0,0 @@ -HOMEPAGE = "http://mesonbuild.com" -SUMMARY = "A high performance build system" -DESCRIPTION = "Meson is a build system designed to increase programmer \ -productivity. It does this by providing a fast, simple and easy to use \ -interface for modern software development tools and practices." - -LICENSE = "Apache-2.0" -LIC_FILES_CHKSUM = "file://COPYING;md5=3b83ef96387f14655fc854ddc3c6bd57" - -SRC_URI = "https://github.com/mesonbuild/meson/releases/download/${PV}/meson-${PV}.tar.gz \ - file://0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch \ - file://0001-python-module-do-not-manipulate-the-environment-when.patch \ - file://disable-rpath-handling.patch \ - file://0001-Make-CPU-family-warnings-fatal.patch \ - file://0002-Support-building-allarch-recipes-again.patch \ - file://0001-is_debianlike-always-return-False.patch \ - " -SRC_URI[sha256sum] = "0a35cfd4cb779a6a415ad3ccbf2d4143334e96139125585ce49915bec494da02" - -UPSTREAM_CHECK_URI = "https://github.com/mesonbuild/meson/releases" -UPSTREAM_CHECK_REGEX = "meson-(?P\d+(\.\d+)+)\.tar" - -inherit setuptools3 - -RDEPENDS_${PN} = "ninja python3-modules python3-pkg-resources" - -FILES_${PN} += "${datadir}/polkit-1" - -do_install_append () { - # As per the same issue in the python recipe itself: - # Unfortunately the following pyc files are non-deterministic due to 'frozenset' - # being written without strict ordering, even with PYTHONHASHSEED = 0 - # Upstream is discussing ways to solve the issue properly, until then let's - # just not install the problematic files. - # More info: http://benno.id.au/blog/2013/01/15/python-determinism - rm ${D}${libdir}/python*/site-packages/mesonbuild/dependencies/__pycache__/mpi.cpython* -} diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-Make-CPU-family-warnings-fatal.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-Make-CPU-family-warnings-fatal.patch index c5be526b..dcc8209c 100644 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-Make-CPU-family-warnings-fatal.patch +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-Make-CPU-family-warnings-fatal.patch @@ -1,40 +1,43 @@ -From 6c4eef1d92e9e42fdbc888365cab3c95fb33c605 Mon Sep 17 00:00:00 2001 +From 32c4ccfbdc8649f595a79e7fd1bd39d6f8325340 Mon Sep 17 00:00:00 2001 From: Ross Burton Date: Tue, 3 Jul 2018 13:59:09 +0100 Subject: [PATCH] Make CPU family warnings fatal Upstream-Status: Inappropriate [OE specific] Signed-off-by: Ross Burton - --- - mesonbuild/envconfig.py | 2 +- - mesonbuild/environment.py | 4 +--- - 2 files changed, 2 insertions(+), 4 deletions(-) + mesonbuild/envconfig.py | 4 ++-- + mesonbuild/environment.py | 6 ++---- + 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/mesonbuild/envconfig.py b/mesonbuild/envconfig.py -index 307aac3..66fb7ec 100644 +index 86bad9b..9703315 100644 --- a/mesonbuild/envconfig.py +++ b/mesonbuild/envconfig.py -@@ -267,7 +267,7 @@ class MachineInfo(HoldableObject): +@@ -277,8 +277,8 @@ class MachineInfo(HoldableObject): + 'but is missing {}.'.format(minimum_literal - set(literal))) cpu_family = literal['cpu_family'] - if cpu_family not in known_cpu_families: +- if cpu_family not in known_cpu_families: - mlog.warning(f'Unknown CPU family {cpu_family}, please report this at https://github.com/mesonbuild/meson/issues/new') ++ if cpu_family not in known_cpu_families and cpu_family != "riscv": + raise EnvironmentException('Unknown CPU family {}, see https://wiki.yoctoproject.org/wiki/Meson/UnknownCPU for directions.'.format(cpu_family)) endian = literal['endian'] if endian not in ('little', 'big'): diff --git a/mesonbuild/environment.py b/mesonbuild/environment.py -index 71286a5..179917e 100644 +index 71a2f3a..4cbeabe 100644 --- a/mesonbuild/environment.py +++ b/mesonbuild/environment.py -@@ -352,9 +352,7 @@ def detect_cpu_family(compilers: CompilersDict) -> str: - trial = 'ppc64' +@@ -416,10 +416,8 @@ def detect_cpu_family(compilers: CompilersDict) -> str: + if compilers and not any_compiler_has_define(compilers, '__mips64'): + trial = 'mips' - if trial not in known_cpu_families: +- if trial not in known_cpu_families: - mlog.warning(f'Unknown CPU family {trial!r}, please report this at ' - 'https://github.com/mesonbuild/meson/issues/new with the ' - 'output of `uname -a` and `cat /proc/cpuinfo`') ++ if trial not in known_cpu_families and trail != "riscv": + raise EnvironmentException('Unknown CPU family %s, see https://wiki.yoctoproject.org/wiki/Meson/UnknownCPU for directions.' % trial) return trial diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-dependencies-dev-prepend-sysroot-when-searching-for-.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-dependencies-dev-prepend-sysroot-when-searching-for-.patch new file mode 100644 index 00000000..e4700bc9 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-dependencies-dev-prepend-sysroot-when-searching-for-.patch @@ -0,0 +1,36 @@ +From 6f33fb67097beeb17e2345aaec3bda4a57b0b138 Mon Sep 17 00:00:00 2001 +From: Ross Burton +Date: Wed, 20 Nov 2024 13:09:38 +0000 +Subject: [PATCH] dependencies/dev: prepend sysroot when searching for GTest + sources + +Don't hardcode paths in /usr when looking for the GTest sources, as in +cross-compile or other builds with a sysroot this will find the host +sources, not ones that we want to use in the sysroot. + +Closes #12690. + +Upstream-Status: Submitted [https://github.com/mesonbuild/meson/pull/13934] +Signed-off-by: Ross Burton +--- + mesonbuild/dependencies/dev.py | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/mesonbuild/dependencies/dev.py b/mesonbuild/dependencies/dev.py +index 94f51ff69..cceb1756c 100644 +--- a/mesonbuild/dependencies/dev.py ++++ b/mesonbuild/dependencies/dev.py +@@ -56,7 +56,9 @@ class GTestDependencySystem(SystemDependency): + def __init__(self, name: str, environment: 'Environment', kwargs: T.Dict[str, T.Any]) -> None: + super().__init__(name, environment, kwargs, language='cpp') + self.main = kwargs.get('main', False) +- self.src_dirs = ['/usr/src/gtest/src', '/usr/src/googletest/googletest/src'] ++ ++ sysroot = environment.properties[self.for_machine].get_sys_root() or "" ++ self.src_dirs = [sysroot + '/usr/src/gtest/src', sysroot + '/usr/src/googletest/googletest/src'] + if not self._add_sub_dependency(threads_factory(environment, self.for_machine, {})): + self.is_found = False + return +-- +2.34.1 + diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch deleted file mode 100644 index ce90e515..00000000 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-gtkdoc-fix-issues-that-arise-when-cross-compiling.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 2f9c59e0489e569c5382404667c10f5c200a72ad Mon Sep 17 00:00:00 2001 -From: Alexander Kanavin -Date: Fri, 4 Aug 2017 16:16:41 +0300 -Subject: [PATCH] gtkdoc: fix issues that arise when cross-compiling - -Specifically: -1) Make it possible to specify a wrapper for executing binaries -(usually, some kind of target hardware emulator, such as qemu) -2) Explicitly provide CC and LD via command line, as otherwise gtk-doc will -try to guess them, incorrectly. -3) If things break down, print the full command with arguments, -not just the binary name. -4) Correctly determine the compiler/linker executables and cross-options when cross-compiling - -Upstream-Status: Pending -Signed-off-by: Alexander Kanavin - ---- - mesonbuild/modules/gnome.py | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/mesonbuild/modules/gnome.py b/mesonbuild/modules/gnome.py -index dc2979e..c9ff9bd 100644 ---- a/mesonbuild/modules/gnome.py -+++ b/mesonbuild/modules/gnome.py -@@ -1053,6 +1053,10 @@ class GnomeModule(ExtensionModule): - args.append(f'--{program_name}={path}') - if namespace: - args.append('--namespace=' + namespace) -+ gtkdoc_exe_wrapper = state.environment.properties.host.get('gtkdoc_exe_wrapper', None) -+ if gtkdoc_exe_wrapper is not None: -+ args.append('--run=' + gtkdoc_exe_wrapper) -+ - args += self._unpack_args('--htmlargs=', 'html_args', kwargs) - args += self._unpack_args('--scanargs=', 'scan_args', kwargs) - args += self._unpack_args('--scanobjsargs=', 'scanobjs_args', kwargs) diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-is_debianlike-always-return-False.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-is_debianlike-always-return-False.patch deleted file mode 100644 index 83c4782a..00000000 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-is_debianlike-always-return-False.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 667b9ede638677fb37911306937ea62f05897581 Mon Sep 17 00:00:00 2001 -From: Alexander Kanavin -Date: Mon, 18 Oct 2021 15:55:59 +0200 -Subject: [PATCH] is_debianlike(): always return False - -Otherwise, host contamination happens. - -Upstream-Status: Inappropriate [oe-core specific] -Signed-off-by: Alexander Kanavin ---- - mesonbuild/mesonlib/universal.py | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/mesonbuild/mesonlib/universal.py b/mesonbuild/mesonlib/universal.py -index d670d04..47d1b52 100644 ---- a/mesonbuild/mesonlib/universal.py -+++ b/mesonbuild/mesonlib/universal.py -@@ -651,7 +651,7 @@ def is_cygwin() -> bool: - - - def is_debianlike() -> bool: -- return os.path.isfile('/etc/debian_version') -+ return False - - - def is_dragonflybsd() -> bool: diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-python-module-do-not-manipulate-the-environment-when.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-python-module-do-not-manipulate-the-environment-when.patch index fdadc686..84a9c18c 100644 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-python-module-do-not-manipulate-the-environment-when.patch +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0001-python-module-do-not-manipulate-the-environment-when.patch @@ -1,4 +1,4 @@ -From 2264e67d7c2c22ca634fd26ea8ada6f0344ab280 Mon Sep 17 00:00:00 2001 +From f264b7fd2c86edfd5db77da264e8bf05f5e2bfeb Mon Sep 17 00:00:00 2001 From: Alexander Kanavin Date: Mon, 19 Nov 2018 14:24:26 +0100 Subject: [PATCH] python module: do not manipulate the environment when calling @@ -6,38 +6,31 @@ Subject: [PATCH] python module: do not manipulate the environment when calling Upstream-Status: Inappropriate [oe-core specific] Signed-off-by: Alexander Kanavin - --- - mesonbuild/modules/python.py | 12 ------------ - 1 file changed, 12 deletions(-) + mesonbuild/dependencies/python.py | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) -diff --git a/mesonbuild/modules/python.py b/mesonbuild/modules/python.py -index 422155b..aaf5844 100644 ---- a/mesonbuild/modules/python.py -+++ b/mesonbuild/modules/python.py -@@ -70,11 +70,6 @@ class PythonDependency(ExternalDependency): - old_pkg_libdir = os.environ.get('PKG_CONFIG_LIBDIR') - old_pkg_path = os.environ.get('PKG_CONFIG_PATH') +diff --git a/mesonbuild/dependencies/python.py b/mesonbuild/dependencies/python.py +index 326e605..f5eb50f 100644 +--- a/mesonbuild/dependencies/python.py ++++ b/mesonbuild/dependencies/python.py +@@ -403,9 +403,6 @@ def python_factory(env: 'Environment', for_machine: 'MachineChoice', + empty.name = 'python' + return empty -- os.environ.pop('PKG_CONFIG_PATH', None) -- -- if pkg_libdir: -- os.environ['PKG_CONFIG_LIBDIR'] = pkg_libdir -- +- old_pkg_libdir = os.environ.pop('PKG_CONFIG_LIBDIR', None) +- old_pkg_path = os.environ.pop('PKG_CONFIG_PATH', None) +- os.environ['PKG_CONFIG_LIBDIR'] = pkg_libdir try: - self.pkgdep = PkgConfigDependency(pkg_name, environment, kwargs) - mlog.debug(f'Found "{pkg_name}" via pkgconfig lookup in LIBPC ({pkg_libdir})') -@@ -83,13 +78,6 @@ class PythonDependency(ExternalDependency): - mlog.debug(f'"{pkg_name}" could not be found in LIBPC ({pkg_libdir})') - mlog.debug(e) - -- if old_pkg_path is not None: -- os.environ['PKG_CONFIG_PATH'] = old_pkg_path -- -- if old_pkg_libdir is not None: -- os.environ['PKG_CONFIG_LIBDIR'] = old_pkg_libdir -- else: -- os.environ.pop('PKG_CONFIG_LIBDIR', None) - else: - mlog.debug(f'"{pkg_name}" could not be found in LIBPC ({pkg_libdir}), this is likely due to a relocated python installation') + return PythonPkgConfigDependency(name, env, kwargs, installation, True) + finally: +@@ -414,8 +411,7 @@ def python_factory(env: 'Environment', for_machine: 'MachineChoice', + os.environ[name] = value + elif name in os.environ: + del os.environ[name] +- set_env('PKG_CONFIG_LIBDIR', old_pkg_libdir) +- set_env('PKG_CONFIG_PATH', old_pkg_path) ++ pass + candidates.append(functools.partial(wrap_in_pythons_pc_dir, pkg_name, env, kwargs, installation)) + # We only need to check both, if a python install has a LIBPC. It might point to the wrong location, diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/0002-Support-building-allarch-recipes-again.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/0002-Support-building-allarch-recipes-again.patch index dcc1ce9c..d3120e84 100644 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/0002-Support-building-allarch-recipes-again.patch +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/0002-Support-building-allarch-recipes-again.patch @@ -1,7 +1,7 @@ -From 656bf55fed01df2d2e2ad6d9d9887173cb16b85c Mon Sep 17 00:00:00 2001 +From bcdd72ed1956e0a1b1b725e552fa391c549c2099 Mon Sep 17 00:00:00 2001 From: Peter Kjellerstedt Date: Thu, 26 Jul 2018 16:32:49 +0200 -Subject: [PATCH 2/2] Support building allarch recipes again +Subject: [PATCH] Support building allarch recipes again This registers "allarch" as a known CPU family. @@ -12,10 +12,10 @@ Signed-off-by: Peter Kjellerstedt 1 file changed, 1 insertion(+) diff --git a/mesonbuild/envconfig.py b/mesonbuild/envconfig.py -index 4d58c91..ff01ad1 100644 +index 9703315..74f2477 100644 --- a/mesonbuild/envconfig.py +++ b/mesonbuild/envconfig.py -@@ -36,6 +36,7 @@ from pathlib import Path +@@ -28,6 +28,7 @@ from pathlib import Path known_cpu_families = ( @@ -23,6 +23,3 @@ index 4d58c91..ff01ad1 100644 'aarch64', 'alpha', 'arc', --- -2.24.0 - diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/disable-rpath-handling.patch b/meta-zephyr-sdk/recipes-devtools/meson/meson/disable-rpath-handling.patch deleted file mode 100644 index 7c766c61..00000000 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/disable-rpath-handling.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 27bbd3c9d8d86de545fcf6608564a14571c98a61 Mon Sep 17 00:00:00 2001 -From: Richard Purdie -Date: Fri, 23 Nov 2018 15:28:28 +0000 -Subject: [PATCH] meson: Disable rpath stripping at install time - -We need to allow our rpaths generated through the compiler flags to make it into -our binaries. Therefore disable the meson manipulations of these unless there -is a specific directive to do something differently in the project. - -RP 2018/11/23 - -Upstream-Status: Submitted [https://github.com/mesonbuild/meson/issues/2567] - ---- - mesonbuild/minstall.py | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/mesonbuild/minstall.py b/mesonbuild/minstall.py -index 212568a..06366d4 100644 ---- a/mesonbuild/minstall.py -+++ b/mesonbuild/minstall.py -@@ -653,8 +653,11 @@ class Installer: - if file_copied: - self.did_install_something = True - try: -- self.fix_rpath(outname, t.rpath_dirs_to_remove, install_rpath, final_path, -- install_name_mappings, verbose=False) -+ if install_rpath: -+ self.fix_rpath(outname, t.rpath_dirs_to_remove, install_rpath, final_path, -+ install_name_mappings, verbose=False) -+ else: -+ print("RPATH changes at install time disabled") - except SystemExit as e: - if isinstance(e.code, int) and e.code == 0: - pass diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-setup.py b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-setup.py index 7ac4e3ad..daaa551d 100755 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-setup.py +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-setup.py @@ -27,9 +27,17 @@ def __getitem__(self, name): template_file = os.path.join(sysroot, 'usr/share/meson/meson.cross.template') cross_file = os.path.join(sysroot, 'usr/share/meson/%smeson.cross' % os.environ["TARGET_PREFIX"]) +native_template_file = os.path.join(sysroot, 'usr/share/meson/meson.native.template') +native_file = os.path.join(sysroot, 'usr/share/meson/meson.native') with open(template_file) as in_file: template = in_file.read() output = Template(template).substitute(Environ()) with open(cross_file, "w") as out_file: out_file.write(output) + +with open(native_template_file) as in_file: + template = in_file.read() + output = Template(template).substitute({'OECORE_NATIVE_SYSROOT': os.environ['OECORE_NATIVE_SYSROOT']}) + with open(native_file, "w") as out_file: + out_file.write(output) diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-wrapper b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-wrapper index d4ffe60f..74559852 100755 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-wrapper +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson/meson-wrapper @@ -1,7 +1,11 @@ #!/bin/sh if [ -z "$OECORE_NATIVE_SYSROOT" ]; then - echo "OECORE_NATIVE_SYSROOT not set; are you in a Yocto SDK environment?" >&2 + exec "meson.real" "$@" +fi + +if [ -z "$SSL_CERT_DIR" ]; then + export SSL_CERT_DIR="$OECORE_NATIVE_SYSROOT/etc/ssl/certs/" fi # If these are set to a cross-compile path, meson will get confused and try to @@ -9,6 +13,19 @@ fi # config is already in meson.cross. unset CC CXX CPP LD AR NM STRIP +case "$1" in +setup|configure|dist|install|introspect|init|test|wrap|subprojects|rewrite|compile|devenv|env2mfile|help) MESON_CMD="$1" ;; +*) echo meson-wrapper: Implicit setup command assumed; MESON_CMD=setup ;; +esac + +if [ "$MESON_CMD" = "setup" ]; then + MESON_SETUP_OPTS=" \ + --cross-file="$OECORE_NATIVE_SYSROOT/usr/share/meson/${TARGET_PREFIX}meson.cross" \ + --native-file="$OECORE_NATIVE_SYSROOT/usr/share/meson/meson.native" \ + " + echo meson-wrapper: Running meson with setup options: \"$MESON_SETUP_OPTS\" +fi + exec "$OECORE_NATIVE_SYSROOT/usr/bin/meson.real" \ - --cross-file "${OECORE_NATIVE_SYSROOT}/usr/share/meson/${TARGET_PREFIX}meson.cross" \ - "$@" + "$@" \ + $MESON_SETUP_OPTS diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson_0.59.3.bb b/meta-zephyr-sdk/recipes-devtools/meson/meson_0.59.3.bb deleted file mode 100644 index de9b905c..00000000 --- a/meta-zephyr-sdk/recipes-devtools/meson/meson_0.59.3.bb +++ /dev/null @@ -1,4 +0,0 @@ -include meson.inc - -BBCLASSEXTEND = "native" - diff --git a/meta-zephyr-sdk/recipes-devtools/meson/meson_1.7.0.bb b/meta-zephyr-sdk/recipes-devtools/meson/meson_1.7.0.bb new file mode 100644 index 00000000..873c23b0 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/meson/meson_1.7.0.bb @@ -0,0 +1,159 @@ +HOMEPAGE = "http://mesonbuild.com" +SUMMARY = "A high performance build system" +DESCRIPTION = "Meson is a build system designed to increase programmer \ +productivity. It does this by providing a fast, simple and easy to use \ +interface for modern software development tools and practices." + +LICENSE = "Apache-2.0" +LIC_FILES_CHKSUM = "file://COPYING;md5=3b83ef96387f14655fc854ddc3c6bd57" + +GITHUB_BASE_URI = "https://github.com/mesonbuild/meson/releases/" +SRC_URI = "${GITHUB_BASE_URI}/download/${PV}/meson-${PV}.tar.gz \ + file://meson-setup.py \ + file://meson-wrapper \ + file://0001-python-module-do-not-manipulate-the-environment-when.patch \ + file://0001-Make-CPU-family-warnings-fatal.patch \ + file://0002-Support-building-allarch-recipes-again.patch \ + file://0001-dependencies-dev-prepend-sysroot-when-searching-for-.patch \ + " +SRC_URI[sha256sum] = "08efbe84803eed07f863b05092d653a9d348f7038761d900412fddf56deb0284" +UPSTREAM_CHECK_REGEX = "(?P\d+(\.\d+)+)$" + +inherit python_setuptools_build_meta github-releases + +RDEPENDS:${PN} = "ninja python3-modules python3-pkg-resources" + +FILES:${PN} += "${datadir}/polkit-1" + +do_install:append () { + # As per the same issue in the python recipe itself: + # Unfortunately the following pyc files are non-deterministc due to 'frozenset' + # being written without strict ordering, even with PYTHONHASHSEED = 0 + # Upstream is discussing ways to solve the issue properly, until then let's + # just not install the problematic files. + # More info: http://benno.id.au/blog/2013/01/15/python-determinism + rm -f ${D}${libdir}/python*/site-packages/mesonbuild/dependencies/__pycache__/mpi.cpython* +} + +BBCLASSEXTEND = "native nativesdk" + +inherit meson-routines + +# The cross file logic is similar but not identical to that in meson.bbclass, +# since it's generating for an SDK rather than a cross-compile. Important +# differences are: +# - We can't set vars like CC, CXX, etc. yet because they will be filled in with +# real paths by meson-setup.sh when the SDK is extracted. +# - Some overrides aren't needed, since the SDK injects paths that take care of +# them. +def var_list2str(var, d): + items = d.getVar(var).split() + return repr(items[0]) if len(items) == 1 else ', '.join(repr(s) for s in items) + +def generate_native_link_template(d): + val = ['-L@{OECORE_NATIVE_SYSROOT}${libdir_native}', + '-L@{OECORE_NATIVE_SYSROOT}${base_libdir_native}', + '-Wl,-rpath-link,@{OECORE_NATIVE_SYSROOT}${libdir_native}', + '-Wl,-rpath-link,@{OECORE_NATIVE_SYSROOT}${base_libdir_native}', + '-Wl,--allow-shlib-undefined' + ] + build_arch = d.getVar('BUILD_ARCH') + if 'x86_64' in build_arch: + loader = 'ld-linux-x86-64.so.2' + elif 'i686' in build_arch: + loader = 'ld-linux.so.2' + elif 'aarch64' in build_arch: + loader = 'ld-linux-aarch64.so.1' + elif 'ppc64le' in build_arch: + loader = 'ld64.so.2' + elif 'loongarch64' in build_arch: + loader = 'ld-linux-loongarch-lp64d.so.1' + elif 'riscv64' in build_arch: + loader = 'ld-linux-riscv64-lp64d.so.1' + + if loader: + val += ['-Wl,--dynamic-linker=@{OECORE_NATIVE_SYSROOT}${base_libdir_native}/' + loader] + + return repr(val) + +install_templates() { + install -d ${D}${datadir}/meson + + cat >${D}${datadir}/meson/meson.native.template <${D}${datadir}/meson/meson.cross.template <${D}${datadir}/meson/meson.cross.template < +Date: Fri, 28 Mar 2014 17:42:43 +0800 +Subject: [PATCH] qemu: Add addition environment space to boot loader + qemu-system-mips + +Upstream-Status: Inappropriate - OE uses deep paths + +If you create a project with very long directory names like 128 characters +deep and use NFS, the kernel arguments will be truncated. The kernel will +accept longer strings such as 1024 bytes, but the qemu boot loader defaulted +to only 256 bytes. This patch expands the limit. + +Signed-off-by: Jason Wessel +Signed-off-by: Roy Li +--- + hw/mips/malta.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/hw/mips/malta.c b/hw/mips/malta.c +index 664a2ae0a..5124b158a 100644 +--- a/hw/mips/malta.c ++++ b/hw/mips/malta.c +@@ -64,7 +64,7 @@ + #define ENVP_PADDR 0x2000 + #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) + #define ENVP_NB_ENTRIES 16 +-#define ENVP_ENTRY_SIZE 256 ++#define ENVP_ENTRY_SIZE 1024 + + /* Hardware addresses */ + #define FLASH_ADDRESS 0x1e000000ULL diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-sched_attr-Do-not-define-for-glibc-2.41.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-sched_attr-Do-not-define-for-glibc-2.41.patch new file mode 100644 index 00000000..1233a07f --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-sched_attr-Do-not-define-for-glibc-2.41.patch @@ -0,0 +1,45 @@ +From 7030c0cd98de9e6c42e69be314204727ae335912 Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Thu, 10 Oct 2024 22:40:32 -0700 +Subject: [PATCH] sched_attr: Do not define for glibc >= 2.41 + +glibc 2.41+ has added [1] definitions for sched_setattr and sched_getattr functions +and struct sched_attr. Therefore, it needs to be checked for here as well before +defining sched_attr + +Define sched_attr conditionally on SCHED_ATTR_SIZE_VER0 + +Fixes builds with glibc/trunk + +[1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=21571ca0d70302909cf72707b2a7736cf12190a0;hp=298bc488fdc047da37482f4003023cb9adef78f8 + +Upstream-Status: Submitted [https://patchwork.ozlabs.org/project/qemu-devel/patch/20241011193140.1047648-1-raj.khem@gmail.com/] +Signed-off-by: Khem Raj +Cc: Laurent Vivier +Cc: Paolo Bonzini +--- + linux-user/syscall.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/linux-user/syscall.c b/linux-user/syscall.c +index 27aa59594..b2c45b4c4 100644 +--- a/linux-user/syscall.c ++++ b/linux-user/syscall.c +@@ -361,7 +361,8 @@ _syscall3(int, sys_sched_getaffinity, pid_t, pid, unsigned int, len, + #define __NR_sys_sched_setaffinity __NR_sched_setaffinity + _syscall3(int, sys_sched_setaffinity, pid_t, pid, unsigned int, len, + unsigned long *, user_mask_ptr); +-/* sched_attr is not defined in glibc */ ++/* sched_attr is not defined in glibc < 2.41 */ ++#ifndef SCHED_ATTR_SIZE_VER0 + struct sched_attr { + uint32_t size; + uint32_t sched_policy; +@@ -374,6 +375,7 @@ struct sched_attr { + uint32_t sched_util_min; + uint32_t sched_util_max; + }; ++#endif + #define __NR_sys_sched_getattr __NR_sched_getattr + _syscall4(int, sys_sched_getattr, pid_t, pid, struct sched_attr *, attr, + unsigned int, size, unsigned int, flags); diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-target-xtensa-add-translation-for-wsr.mpucfg.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-target-xtensa-add-translation-for-wsr.mpucfg.patch new file mode 100644 index 00000000..2b33ef6b --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0001-target-xtensa-add-translation-for-wsr.mpucfg.patch @@ -0,0 +1,36 @@ +From 40de936cb535e9645d562ef32ef70d224f4f80ec Mon Sep 17 00:00:00 2001 +From: Max Filippov +Date: Thu, 14 Dec 2023 18:08:26 -0800 +Subject: [PATCH 1/4] target/xtensa: add translation for wsr.mpucfg + +Although MPUCFG is not writable, the opcode wsr.mpucfg is defined and it +just does nothing. Define wsr.mpucfg as nop. + +Signed-off-by: Max Filippov +--- + target/xtensa/translate.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c +index f4da4a40f9..80efc87c8f 100644 +--- a/target/xtensa/translate.c ++++ b/target/xtensa/translate.c +@@ -5303,6 +5303,15 @@ static const XtensaOpcodeOps core_ops[] = { + XTENSA_OPTION_TRACE_PORT, + }, + .op_flags = XTENSA_OP_PRIVILEGED, ++ }, { ++ .name = "wsr.mpucfg", ++ .translate = translate_nop, ++ .test_exceptions = test_exceptions_sr, ++ .par = (const uint32_t[]){ ++ MPUCFG, ++ XTENSA_OPTION_MPU, ++ }, ++ .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "wsr.mpuenb", + .translate = translate_wsr_mpuenb, +-- +2.43.0 + diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-apic-fixup-fallthrough-to-PIC.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-apic-fixup-fallthrough-to-PIC.patch new file mode 100644 index 00000000..bcb0d0c0 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-apic-fixup-fallthrough-to-PIC.patch @@ -0,0 +1,43 @@ +From 1ba58dbd2dce4e6ccaf3be3ad5c9ecc22565313f Mon Sep 17 00:00:00 2001 +From: Mark Asselstine +Date: Tue, 26 Feb 2013 11:43:28 -0500 +Subject: [PATCH] apic: fixup fallthrough to PIC + +Commit 0e21e12bb311c4c1095d0269dc2ef81196ccb60a [Don't route PIC +interrupts through the local APIC if the local APIC config says so.] +missed a check to ensure the local APIC is enabled. Since if the local +APIC is disabled it doesn't matter what the local APIC config says. + +If this check isn't done and the guest has disabled the local APIC the +guest will receive a general protection fault, similar to what is seen +here: + +https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02304.html + +The GPF is caused by an attempt to service interrupt 0xffffffff. This +comes about since cpu_get_pic_interrupt() calls apic_accept_pic_intr() +(with the local APIC disabled apic_get_interrupt() returns -1). +apic_accept_pic_intr() returns 0 and thus the interrupt number which +is returned from cpu_get_pic_interrupt(), and which is attempted to be +serviced, is -1. + +Signed-off-by: Mark Asselstine +Upstream-Status: Submitted [https://lists.gnu.org/archive/html/qemu-devel/2013-04/msg00878.html] +Signed-off-by: He Zhe +--- + hw/intc/apic.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/hw/intc/apic.c b/hw/intc/apic.c +index 4186c57b3..43cd805a9 100644 +--- a/hw/intc/apic.c ++++ b/hw/intc/apic.c +@@ -759,7 +759,7 @@ int apic_accept_pic_intr(DeviceState *dev) + APICCommonState *s = APIC(dev); + uint32_t lvt0; + +- if (!s) ++ if (!s || !(s->spurious_vec & APIC_SV_ENABLE)) + return -1; + + lvt0 = s->lvt[APIC_LVT_LINT0]; diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-target-xtensa-import-sample_controller32-core.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-target-xtensa-import-sample_controller32-core.patch new file mode 100644 index 00000000..5670d808 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0002-target-xtensa-import-sample_controller32-core.patch @@ -0,0 +1,12925 @@ +From f45b7fe1a7a5cbb2445f4bfd36a6a929fa22bef6 Mon Sep 17 00:00:00 2001 +From: Max Filippov +Date: Thu, 14 Dec 2023 16:47:09 -0800 +Subject: [PATCH 2/4] target/xtensa: import sample_controller32 core + +This is an LX core with MPU and exclusive access options. + +Signed-off-by: Max Filippov +--- + target/xtensa/core-sample_controller32.c | 25 + + .../core-sample_controller32/core-isa.h | 739 + + .../core-sample_controller32/core-matmap.h | 106 + + .../core-sample_controller32/gdb-config.c.inc | 144 + + .../xtensa-modules.c.inc | 11845 ++++++++++++++++ + target/xtensa/cores.list | 1 + + 6 files changed, 12860 insertions(+) + create mode 100644 target/xtensa/core-sample_controller32.c + create mode 100644 target/xtensa/core-sample_controller32/core-isa.h + create mode 100644 target/xtensa/core-sample_controller32/core-matmap.h + create mode 100644 target/xtensa/core-sample_controller32/gdb-config.c.inc + create mode 100644 target/xtensa/core-sample_controller32/xtensa-modules.c.inc + +diff --git a/target/xtensa/core-sample_controller32.c b/target/xtensa/core-sample_controller32.c +new file mode 100644 +index 0000000000..94e75ad6ef +--- /dev/null ++++ b/target/xtensa/core-sample_controller32.c +@@ -0,0 +1,25 @@ ++#include "qemu/osdep.h" ++#include "cpu.h" ++#include "gdbstub/helpers.h" ++#include "qemu/host-utils.h" ++ ++#include "core-sample_controller32/core-isa.h" ++#include "core-sample_controller32/core-matmap.h" ++#include "overlay_tool.h" ++ ++#define xtensa_modules xtensa_modules_sample_controller32 ++#include "core-sample_controller32/xtensa-modules.c.inc" ++ ++static XtensaConfig sample_controller32 __attribute__((unused)) = { ++ .name = "sample_controller32", ++ .gdb_regmap = { ++ .reg = { ++#include "core-sample_controller32/gdb-config.c.inc" ++ } ++ }, ++ .isa_internal = &xtensa_modules, ++ .clock_freq_khz = 40000, ++ DEFAULT_SECTIONS ++}; ++ ++REGISTER_CORE(sample_controller32) +diff --git a/target/xtensa/core-sample_controller32/core-isa.h b/target/xtensa/core-sample_controller32/core-isa.h +new file mode 100644 +index 0000000000..042232390f +--- /dev/null ++++ b/target/xtensa/core-sample_controller32/core-isa.h +@@ -0,0 +1,739 @@ ++/* ++ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa ++ * processor CORE configuration ++ * ++ * See , which includes this file, for more details. ++ */ ++ ++/* Xtensa processor core configuration information. ++ ++ Copyright (c) 1999-2019 Tensilica Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++#ifndef XTENSA_CORE_CONFIGURATION_H_ ++#define XTENSA_CORE_CONFIGURATION_H_ ++ ++//depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko) ++ ++/**************************************************************************** ++ Parameters Useful for Any Code, USER or PRIVILEGED ++ ****************************************************************************/ ++ ++/* ++ * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is ++ * configured, and a value of 0 otherwise. These macros are always defined. ++ */ ++ ++ ++/*---------------------------------------------------------------------- ++ ISA ++ ----------------------------------------------------------------------*/ ++ ++#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ ++#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ ++#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ ++#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ ++#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ ++#define XCHAL_HAVE_DEBUG 1 /* debug option */ ++#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ ++#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */ ++#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ ++#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ ++#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ ++#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ ++#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ ++#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */ ++#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ ++#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ ++#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ ++#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ ++#define XCHAL_HAVE_L32R 1 /* L32R instruction */ ++#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ ++#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ ++#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ ++#define XCHAL_HAVE_EXCLUSIVE 1 /* L32EX/S32EX instructions */ ++#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ ++#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ ++#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ ++#define XCHAL_HAVE_ABS 1 /* ABS instruction */ ++#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ ++#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ ++#define XCHAL_HAVE_SPECULATION 0 /* speculation */ ++#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ ++#define XCHAL_NUM_CONTEXTS 1 /* */ ++#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ ++#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ ++#define XCHAL_HAVE_PRID 1 /* processor ID register */ ++#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ ++#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ ++#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ ++#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ ++#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ ++#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ ++#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ ++#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ ++#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ ++#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ ++#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ ++#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ ++#define XCHAL_HAVE_LX 1 /* LX core */ ++#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ ++ ++#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ ++ ++#define XCHAL_HAVE_FUSION 0 /* Fusion*/ ++#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ ++#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ ++#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ ++#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ ++#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ ++#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ ++#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ ++#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ ++#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ ++#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ ++#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ ++#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */ ++#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */ ++#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */ ++#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */ ++#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ ++#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ ++#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ ++#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ ++#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ ++#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ ++#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ ++#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ ++#define XCHAL_HAVE_HIFI_MINI 0 ++ ++ ++ ++#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ ++#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ ++#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ ++#define XCHAL_HAVE_FP 0 /* single prec floating point */ ++#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ ++#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ ++#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ ++#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ ++#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ ++#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ ++#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ ++#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ ++#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ ++#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ ++#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ ++ ++#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ ++#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ ++#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ ++#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ ++ ++#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ ++#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ ++#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ ++#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ ++#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ ++#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ ++ ++#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ ++#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ ++#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ ++#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ ++#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ ++ ++#define XCHAL_HAVE_PDX 0 /* PDX-LX */ ++#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ ++#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ ++#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ ++#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ ++#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ ++ ++#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ ++#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ ++#define XCHAL_HAVE_BALL 0 ++#define XCHAL_HAVE_BALLAP 0 ++#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ ++#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ ++#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ ++#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ ++#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ ++#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ ++#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ ++#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ ++#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ ++#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ ++#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ ++#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ ++#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ ++#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ ++#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ ++#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ ++#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ ++#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ ++#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ ++#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ ++#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ ++#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ ++#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ ++ ++#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ ++#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ ++#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6 or Q7 */ ++#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ ++#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ ++#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ ++#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ ++#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ ++#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ ++ ++#define XCHAL_HAVE_VISIONC 0 /* Vision C */ ++ ++#define XCHAL_HAVE_XNNE 0 /* XNNE */ ++ ++/*---------------------------------------------------------------------- ++ MISC ++ ----------------------------------------------------------------------*/ ++ ++#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ ++#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ ++#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ ++#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ ++#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay ++ (1 = 5-stage, 2 = 7-stage) */ ++#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ ++#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ ++/* In T1050, applies to selected core load and store instructions (see ISA): */ ++#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ ++#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ ++#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ ++#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ ++ ++#define XCHAL_UNIFIED_LOADSTORE 0 ++ ++#define XCHAL_SW_VERSION 1402000 /* sw version of this header */ ++#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */ ++#define XCHAL_SW_VERSION_MINOR 2 /* minor ver# of sw */ ++#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ ++#define XCHAL_SW_MINOR_VERSION 1402000 /* with zeroed micro */ ++#define XCHAL_SW_MICRO_VERSION 1402000 ++ ++#define XCHAL_CORE_ID "sample_controller32" /* alphanum core name ++ (CoreID) set in the Xtensa ++ Processor Generator */ ++ ++#define XCHAL_BUILD_UNIQUE_ID 0x00086263 /* 22-bit sw build ID */ ++ ++/* ++ * These definitions describe the hardware targeted by this software. ++ */ ++#define XCHAL_HW_CONFIGID0 0xC0009286 /* ConfigID hi 32 bits*/ ++#define XCHAL_HW_CONFIGID1 0x28886263 /* ConfigID lo 32 bits*/ ++#define XCHAL_HW_VERSION_NAME "LX7.1.2" /* full version name */ ++#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ ++#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ ++#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ ++#define XCHAL_HW_VERSION 281020 /* major*100+(major<2810 ? minor : minor*10+micro) */ ++#define XCHAL_HW_REL_LX7 1 ++#define XCHAL_HW_REL_LX7_1 1 ++#define XCHAL_HW_REL_LX7_1_2 1 ++#define XCHAL_HW_CONFIGID_RELIABLE 1 ++/* If software targets a *range* of hardware versions, these are the bounds: */ ++#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ ++#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ ++#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ ++#define XCHAL_HW_MIN_VERSION 281020 /* earliest targeted hw */ ++#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ ++#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ ++#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ ++#define XCHAL_HW_MAX_VERSION 281020 /* latest targeted hw */ ++ ++/* Config is enabled for functional safety: */ ++#define XCHAL_HAVE_FUNC_SAFETY 0 ++ ++#define XCHAL_HAVE_APB 0 ++ ++/*---------------------------------------------------------------------- ++ CACHE ++ ----------------------------------------------------------------------*/ ++ ++#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ ++#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ ++#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ ++#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ ++ ++#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ ++#define XCHAL_ICACHE_SIZE_LOG2 0 ++#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ ++#define XCHAL_DCACHE_SIZE_LOG2 0 ++ ++#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ ++#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ ++ ++#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ ++#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */ ++#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ ++#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ ++#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ ++#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ ++#define XCHAL_HAVE_CME_DOWNGRADES 0 ++#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ ++#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ ++#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ ++#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ ++#define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */ ++#define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */ ++ ++#define XCHAL_L1SCACHE_SIZE 0 ++#define XCHAL_L1SCACHE_SIZE_LOG2 0 ++#define XCHAL_L1SCACHE_WAYS 1 ++#define XCHAL_L1SCACHE_WAYS_LOG2 0 ++#define XCHAL_L1SCACHE_ACCESS_SIZE 0 ++#define XCHAL_L1SCACHE_BANKS 1 ++ ++#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */ ++ ++/* This one is a form of caching, though not architecturally visible: */ ++#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ ++ ++ ++ ++ ++/**************************************************************************** ++ Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ++ ****************************************************************************/ ++ ++ ++#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY ++ ++/*---------------------------------------------------------------------- ++ CACHE ++ ----------------------------------------------------------------------*/ ++ ++#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ ++ ++#define XCHAL_HAVE_AXI 1 /* AXI bus */ ++#define XCHAL_HAVE_AXI_ECC 1 /* ECC on AXI bus */ ++#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ ++ ++#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ ++#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ ++ ++/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ ++ ++/* Number of cache sets in log2(lines per way): */ ++#define XCHAL_ICACHE_SETWIDTH 0 ++#define XCHAL_DCACHE_SETWIDTH 0 ++ ++/* Cache set associativity (number of ways): */ ++#define XCHAL_ICACHE_WAYS 1 ++#define XCHAL_ICACHE_WAYS_LOG2 0 ++#define XCHAL_DCACHE_WAYS 1 ++#define XCHAL_DCACHE_WAYS_LOG2 0 ++ ++/* Cache features: */ ++#define XCHAL_ICACHE_LINE_LOCKABLE 0 ++#define XCHAL_DCACHE_LINE_LOCKABLE 0 ++#define XCHAL_ICACHE_ECC_PARITY 0 ++#define XCHAL_DCACHE_ECC_PARITY 0 ++#define XCHAL_ICACHE_ECC_WIDTH 1 ++#define XCHAL_DCACHE_ECC_WIDTH 1 ++ ++/* Cache access size in bytes (affects operation of SICW instruction): */ ++#define XCHAL_ICACHE_ACCESS_SIZE 1 ++#define XCHAL_DCACHE_ACCESS_SIZE 1 ++ ++#define XCHAL_DCACHE_BANKS 0 /* number of banks */ ++ ++/* The number of Cache lines associated with a single cache tag */ ++#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 ++ ++/* Number of encoded cache attr bits (see for decoded bits): */ ++ ++ ++/*---------------------------------------------------------------------- ++ INTERNAL I/D RAM/ROMs and XLMI ++ ----------------------------------------------------------------------*/ ++#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ ++#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ ++#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ ++#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ ++#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ ++#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ ++#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ ++#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ ++ ++/* Instruction RAM 0: */ ++#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ ++#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ ++#define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */ ++#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ ++#define XCHAL_HAVE_INSTRAM0 1 ++#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ ++ ++/* Data RAM 0: */ ++#define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */ ++#define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */ ++#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */ ++#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ ++#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ ++#define XCHAL_HAVE_DATARAM0 1 ++#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ ++ ++/* Data RAM 1: */ ++#define XCHAL_DATARAM1_VADDR 0x3FFC0000 /* virtual address */ ++#define XCHAL_DATARAM1_PADDR 0x3FFC0000 /* physical address */ ++#define XCHAL_DATARAM1_SIZE 131072 /* size in bytes */ ++#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ ++#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ ++#define XCHAL_HAVE_DATARAM1 1 ++#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ ++ ++ ++#define XCHAL_HAVE_IDMA 0 ++ ++ ++#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ ++ ++/*---------------------------------------------------------------------- ++ INTERRUPTS and TIMERS ++ ----------------------------------------------------------------------*/ ++ ++#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ ++#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ ++#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ ++#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ ++#define XCHAL_NUM_INTERRUPTS 23 /* number of interrupts */ ++#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ ++#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ ++#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels ++ (not including level zero) */ ++ ++ ++#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ ++#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ ++ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ ++ ++/* Masks of interrupts at each interrupt level: */ ++#define XCHAL_INTLEVEL1_MASK 0x005F80FF ++#define XCHAL_INTLEVEL2_MASK 0x00000100 ++#define XCHAL_INTLEVEL3_MASK 0x00200E00 ++#define XCHAL_INTLEVEL4_MASK 0x00001000 ++#define XCHAL_INTLEVEL5_MASK 0x00002000 ++#define XCHAL_INTLEVEL6_MASK 0x00000000 ++#define XCHAL_INTLEVEL7_MASK 0x00004000 ++ ++/* Masks of interrupts at each range 1..n of interrupt levels: */ ++#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x005F80FF ++#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x005F81FF ++#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x007F8FFF ++#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x007F9FFF ++#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x007FBFFF ++#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x007FBFFF ++#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x007FFFFF ++ ++/* Level of each interrupt: */ ++#define XCHAL_INT0_LEVEL 1 ++#define XCHAL_INT1_LEVEL 1 ++#define XCHAL_INT2_LEVEL 1 ++#define XCHAL_INT3_LEVEL 1 ++#define XCHAL_INT4_LEVEL 1 ++#define XCHAL_INT5_LEVEL 1 ++#define XCHAL_INT6_LEVEL 1 ++#define XCHAL_INT7_LEVEL 1 ++#define XCHAL_INT8_LEVEL 2 ++#define XCHAL_INT9_LEVEL 3 ++#define XCHAL_INT10_LEVEL 3 ++#define XCHAL_INT11_LEVEL 3 ++#define XCHAL_INT12_LEVEL 4 ++#define XCHAL_INT13_LEVEL 5 ++#define XCHAL_INT14_LEVEL 7 ++#define XCHAL_INT15_LEVEL 1 ++#define XCHAL_INT16_LEVEL 1 ++#define XCHAL_INT17_LEVEL 1 ++#define XCHAL_INT18_LEVEL 1 ++#define XCHAL_INT19_LEVEL 1 ++#define XCHAL_INT20_LEVEL 1 ++#define XCHAL_INT21_LEVEL 3 ++#define XCHAL_INT22_LEVEL 1 ++#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ ++#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ ++#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with ++ EXCSAVE/EPS/EPC_n, RFI n) */ ++ ++/* Type of each interrupt: */ ++#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE ++#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE ++#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL ++#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER ++#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI ++#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE ++#define XCHAL_INT22_TYPE XTHAL_INTTYPE_WRITE_ERROR ++ ++/* Masks of interrupts for each type of interrupt: */ ++#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFF800000 ++#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F ++#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 ++#define XCHAL_INTTYPE_MASK_NMI 0x00004000 ++#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 ++#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 ++#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00400000 ++#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 ++#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 ++#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 ++#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 ++#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 ++#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 ++#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 ++#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 ++#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 ++#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 ++ ++/* Interrupt numbers assigned to specific interrupt sources: */ ++#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ ++#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ ++#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ ++#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED ++#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ ++#define XCHAL_WRITE_ERROR_INTERRUPT 22 ++ ++/* Interrupt numbers for levels at which only one interrupt is configured: */ ++#define XCHAL_INTLEVEL2_NUM 8 ++#define XCHAL_INTLEVEL4_NUM 12 ++#define XCHAL_INTLEVEL5_NUM 13 ++#define XCHAL_INTLEVEL7_NUM 14 ++/* (There are many interrupts each at level(s) 1, 3.) */ ++ ++ ++/* ++ * External interrupt mapping. ++ * These macros describe how Xtensa processor interrupt numbers ++ * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) ++ * map to external BInterrupt pins, for those interrupts ++ * configured as external (level-triggered, edge-triggered, or NMI). ++ * See the Xtensa processor databook for more details. ++ */ ++ ++/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ ++#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ ++#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ ++#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ ++#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ ++#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ ++#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ ++#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ ++#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ ++#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ ++#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ ++#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ ++#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ ++#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ ++#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ ++#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ ++#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ ++#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ ++/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ ++#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ ++#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ ++#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ ++#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ ++#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ ++#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ ++#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ ++#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ ++#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ ++#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ ++#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ ++#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ ++#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ ++#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ ++#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ ++#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ ++#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ ++ ++#define XCHAL_HAVE_ISB 0 /* No ISB */ ++#define XCHAL_ISB_VADDR 0 /* N/A */ ++#define XCHAL_HAVE_ITB 0 /* No ITB */ ++#define XCHAL_ITB_VADDR 0 /* N/A */ ++ ++#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ ++#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ ++#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ ++ ++ ++/*---------------------------------------------------------------------- ++ EXCEPTIONS and VECTORS ++ ----------------------------------------------------------------------*/ ++ ++#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture ++ number: 1 == XEA1 (until T1050) ++ 2 == XEA2 (T1040 onwards) ++ 3 == XEA3 (LX8/NX/SX onwards) ++ 0 == XEAX (extern) or TX */ ++#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ ++#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ ++#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ ++#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ ++#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ ++#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ ++#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ ++#define XCHAL_HAVE_HALT 0 /* halt architecture option */ ++#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ ++#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ ++#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ ++#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ ++#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ ++#define XCHAL_VECBASE_RESET_PADDR 0x40000000 ++#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ ++ ++#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 ++#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 ++#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 ++#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 ++#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR ++#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR ++#define XCHAL_USER_VECOFS 0x00000340 ++#define XCHAL_USER_VECTOR_VADDR 0x40000340 ++#define XCHAL_USER_VECTOR_PADDR 0x40000340 ++#define XCHAL_KERNEL_VECOFS 0x00000300 ++#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 ++#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 ++#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 ++#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 ++#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 ++#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 ++#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 ++#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 ++#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 ++#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 ++#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 ++#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 ++#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 ++#define XCHAL_INTLEVEL2_VECOFS 0x00000180 ++#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 ++#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 ++#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 ++#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 ++#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 ++#define XCHAL_INTLEVEL4_VECOFS 0x00000200 ++#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 ++#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 ++#define XCHAL_INTLEVEL5_VECOFS 0x00000240 ++#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 ++#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 ++#define XCHAL_INTLEVEL6_VECOFS 0x00000280 ++#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 ++#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 ++#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS ++#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR ++#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR ++#define XCHAL_NMI_VECOFS 0x000002C0 ++#define XCHAL_NMI_VECTOR_VADDR 0x400002C0 ++#define XCHAL_NMI_VECTOR_PADDR 0x400002C0 ++#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS ++#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR ++#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR ++ ++ ++/*---------------------------------------------------------------------- ++ DEBUG MODULE ++ ----------------------------------------------------------------------*/ ++ ++/* Misc */ ++#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ ++#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ ++#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ ++ ++/* On-Chip Debug (OCD) */ ++#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ ++#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ ++#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ ++#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ ++#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ ++ ++/* TRAX (in core) */ ++#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ ++#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ ++#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ ++#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ ++#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ ++ ++/* Perf counters */ ++#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ ++ ++ ++/*---------------------------------------------------------------------- ++ MMU ++ ----------------------------------------------------------------------*/ ++ ++/* See core-matmap.h header file for more details. */ ++ ++#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ ++#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ ++#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ ++#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ ++#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ ++#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ ++#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table ++ [autorefill] and protection) ++ usable for an MMU-based OS */ ++ ++/* If none of the above last 5 are set, it's a custom TLB configuration. */ ++ ++#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ ++#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ ++#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ ++ ++/*---------------------------------------------------------------------- ++ MPU ++ ----------------------------------------------------------------------*/ ++#define XCHAL_HAVE_MPU 1 ++#define XCHAL_MPU_ENTRIES 32 ++ ++#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ ++#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ ++#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ ++ ++#define XCHAL_MPU_ALIGN_BITS 12 ++#define XCHAL_MPU_ALIGN 4096 ++ ++#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ ++ ++ ++#endif /* XTENSA_CORE_CONFIGURATION_H_ */ ++ +diff --git a/target/xtensa/core-sample_controller32/core-matmap.h b/target/xtensa/core-sample_controller32/core-matmap.h +new file mode 100644 +index 0000000000..2818d8918a +--- /dev/null ++++ b/target/xtensa/core-sample_controller32/core-matmap.h +@@ -0,0 +1,106 @@ ++/* ++ * xtensa/config/core-matmap.h -- Memory access and translation mapping ++ * parameters (CHAL) of the Xtensa processor core configuration. ++ * ++ * If you are using Xtensa Tools, see (which includes ++ * this file) for more details. ++ * ++ * In the Xtensa processor products released to date, all parameters ++ * defined in this file are derivable (at least in theory) from ++ * information contained in the core-isa.h header file. ++ * In particular, the following core configuration parameters are relevant: ++ * XCHAL_HAVE_CACHEATTR ++ * XCHAL_HAVE_MIMIC_CACHEATTR ++ * XCHAL_HAVE_XLT_CACHEATTR ++ * XCHAL_HAVE_PTP_MMU ++ * XCHAL_ITLB_ARF_ENTRIES_LOG2 ++ * XCHAL_DTLB_ARF_ENTRIES_LOG2 ++ * XCHAL_DCACHE_IS_WRITEBACK ++ * XCHAL_ICACHE_SIZE (presence of I-cache) ++ * XCHAL_DCACHE_SIZE (presence of D-cache) ++ * XCHAL_HW_VERSION_MAJOR ++ * XCHAL_HW_VERSION_MINOR ++ */ ++ ++/* Copyright (c) 1999-2019 Tensilica Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++ ++#ifndef XTENSA_CONFIG_CORE_MATMAP_H ++#define XTENSA_CONFIG_CORE_MATMAP_H ++ ++ ++/*---------------------------------------------------------------------- ++ CACHE (MEMORY ACCESS) ATTRIBUTES ++ ----------------------------------------------------------------------*/ ++/*---------------------------------------------------------------------- ++ MPU ++ ----------------------------------------------------------------------*/ ++ ++/* Mappings for legacy constants where appropriate */ ++ ++#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx) ++ ++#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx ) ++ ++#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx) ++ ++#define XCHAL_CA_ILLEGAL (XTHAL_AR_NONE | XTHAL_MEM_DEVICE) ++#define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE) ++#define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\ ++ XTHAL_MEM_BUFFERABLE) ++#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX | XTHAL_MEM_DEVICE) ++#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW | XTHAL_MEM_DEVICE) ++#define XCHAL_CA_BYPASS_R (XTHAL_AR_R | XTHAL_MEM_DEVICE) ++#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 ++ ++#define XCHAL_CA_R (XTHAL_AR_R) ++#define XCHAL_CA_RX (XTHAL_AR_RX) ++#define XCHAL_CA_RW (XTHAL_AR_RW) ++#define XCHAL_CA_RWX (XTHAL_AR_RWX) ++ ++ ++/* ++ * Contents of MPU background map. ++ * NOTE: caller must define the XCHAL_MPU_BGMAP() macro (not defined here ++ * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro. ++ * ++ * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) ++ * ++ * s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand ++ * vaddr_start = first byte of region (always 0 for first entry) ++ * vaddr_end = last byte of region (always 0xFFFFFFFF for last entry) ++ * rights = access rights ++ * memtype = memory type ++ * x = reserved for future use (0 until then) ++ */ ++/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ ++#define XCHAL_MPU_BACKGROUND_MAP(s) \ ++ XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff, 7, 6, 0) \ ++ XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0) \ ++/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ ++ ++ /* end */ ++ ++ ++ ++#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ ++ +diff --git a/target/xtensa/core-sample_controller32/gdb-config.c.inc b/target/xtensa/core-sample_controller32/gdb-config.c.inc +new file mode 100644 +index 0000000000..08f1a189f1 +--- /dev/null ++++ b/target/xtensa/core-sample_controller32/gdb-config.c.inc +@@ -0,0 +1,144 @@ ++/* Configuration for the Xtensa architecture for GDB, the GNU debugger. ++ ++ Copyright (c) 2003-2019 Tensilica Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0) ++ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) ++ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) ++ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) ++ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) ++ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) ++ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) ++ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) ++ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) ++ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) ++ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) ++ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) ++ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) ++ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) ++ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) ++ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) ++ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) ++ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) ++ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) ++ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) ++ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) ++ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) ++ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) ++ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) ++ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) ++ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) ++ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) ++ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) ++ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) ++ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) ++ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) ++ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) ++ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) ++ XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) ++ XTREG( 34,136, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) ++ XTREG( 35,140, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) ++ XTREG( 36,144,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) ++ XTREG( 37,148,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) ++ XTREG( 38,152,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) ++ XTREG( 39,156,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) ++ XTREG( 40,160,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) ++ XTREG( 41,164,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,mpuenb, 0,0,0,0,0,0) ++ XTREG( 42,168,16, 4, 4,0x025f,0x0007,-2, 2,0x1000,eraccess, 0,0,0,0,0,0) ++ XTREG( 43,172, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) ++ XTREG( 44,176, 8, 4, 4,0x0262,0x0007,-2, 2,0x1000,cacheadrdis, 0,0,0,0,0,0) ++ XTREG( 45,180, 9, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) ++ XTREG( 46,184,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) ++ XTREG( 47,188,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) ++ XTREG( 48,192,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) ++ XTREG( 49,196,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) ++ XTREG( 50,200,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) ++ XTREG( 51,204,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) ++ XTREG( 52,208,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) ++ XTREG( 53,212,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) ++ XTREG( 54,216,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) ++ XTREG( 55,220,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) ++ XTREG( 56,224,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) ++ XTREG( 57,228,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) ++ XTREG( 58,232,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) ++ XTREG( 59,236,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) ++ XTREG( 60,240,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) ++ XTREG( 61,244,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) ++ XTREG( 62,248,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) ++ XTREG( 63,252,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) ++ XTREG( 64,256,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) ++ XTREG( 65,260,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) ++ XTREG( 66,264,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) ++ XTREG( 67,268,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) ++ XTREG( 68,272,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) ++ XTREG( 69,276,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) ++ XTREG( 70,280,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) ++ XTREG( 71,284,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) ++ XTREG( 72,288,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) ++ XTREG( 73,292,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) ++ XTREG( 74,296,23, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) ++ XTREG( 75,300,23, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) ++ XTREG( 76,304,23, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) ++ XTREG( 77,308,23, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) ++ XTREG( 78,312,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) ++ XTREG( 79,316, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) ++ XTREG( 80,320,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) ++ XTREG( 81,324,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) ++ XTREG( 82,328,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) ++ XTREG( 83,332,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) ++ XTREG( 84,336, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) ++ XTREG( 85,340,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) ++ XTREG( 86,344,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) ++ XTREG( 87,348,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) ++ XTREG( 88,352,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) ++ XTREG( 89,356,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) ++ XTREG( 90,360,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) ++ XTREG( 91,364,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0) ++ XTREG( 92,368,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0) ++ XTREG( 93,372,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0) ++ XTREG( 94,376,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0) ++ XTREG( 95,380,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0) ++ XTREG( 96,384,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0) ++ XTREG( 97,388,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0) ++ XTREG( 98,392,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0) ++ XTREG( 99,396,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0) ++ XTREG(100,400,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0) ++ XTREG(101,404,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0) ++ XTREG(102,408,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0) ++ XTREG(103,412,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0) ++ XTREG(104,416,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0) ++ XTREG(105,420,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0) ++ XTREG(106,424,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0) ++ XTREG(107,428, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, ++ 0,0,&xtensa_mask0,0,0,0) ++ XTREG(108,432, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, ++ 0,0,&xtensa_mask1,0,0,0) ++ XTREG(109,436, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, ++ 0,0,&xtensa_mask2,0,0,0) ++ XTREG(110,440, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, ++ 0,0,&xtensa_mask3,0,0,0) ++ XTREG(111,444, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, ++ 0,0,&xtensa_mask4,0,0,0) ++ XTREG(112,448, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, ++ 0,0,&xtensa_mask5,0,0,0) ++ XTREG(113,452, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, ++ 0,0,&xtensa_mask6,0,0,0) ++ XTREG_END +diff --git a/target/xtensa/core-sample_controller32/xtensa-modules.c.inc b/target/xtensa/core-sample_controller32/xtensa-modules.c.inc +new file mode 100644 +index 0000000000..854e594705 +--- /dev/null ++++ b/target/xtensa/core-sample_controller32/xtensa-modules.c.inc +@@ -0,0 +1,11845 @@ ++/* Xtensa configuration-specific ISA information. ++ ++ Copyright (c) 2003-2019 Tensilica Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++#include "xtensa-isa.h" ++#include "xtensa-isa-internal.h" ++ ++ ++/* Sysregs. */ ++ ++static xtensa_sysreg_internal sysregs[] = { ++ { "MMID", 89, 0 }, ++ { "DDR", 104, 0 }, ++ { "CONFIGID0", 176, 0 }, ++ { "CONFIGID1", 208, 0 }, ++ { "INTERRUPT", 226, 0 }, ++ { "INTCLEAR", 227, 0 }, ++ { "CCOUNT", 234, 0 }, ++ { "PRID", 235, 0 }, ++ { "ICOUNT", 236, 0 }, ++ { "CCOMPARE0", 240, 0 }, ++ { "CCOMPARE1", 241, 0 }, ++ { "CCOMPARE2", 242, 0 }, ++ { "VECBASE", 231, 0 }, ++ { "EPC1", 177, 0 }, ++ { "EPC2", 178, 0 }, ++ { "EPC3", 179, 0 }, ++ { "EPC4", 180, 0 }, ++ { "EPC5", 181, 0 }, ++ { "EPC6", 182, 0 }, ++ { "EPC7", 183, 0 }, ++ { "EXCSAVE1", 209, 0 }, ++ { "EXCSAVE2", 210, 0 }, ++ { "EXCSAVE3", 211, 0 }, ++ { "EXCSAVE4", 212, 0 }, ++ { "EXCSAVE5", 213, 0 }, ++ { "EXCSAVE6", 214, 0 }, ++ { "EXCSAVE7", 215, 0 }, ++ { "EPS2", 194, 0 }, ++ { "EPS3", 195, 0 }, ++ { "EPS4", 196, 0 }, ++ { "EPS5", 197, 0 }, ++ { "EPS6", 198, 0 }, ++ { "EPS7", 199, 0 }, ++ { "EXCCAUSE", 232, 0 }, ++ { "DEPC", 192, 0 }, ++ { "EXCVADDR", 238, 0 }, ++ { "WINDOWBASE", 72, 0 }, ++ { "WINDOWSTART", 73, 0 }, ++ { "SAR", 3, 0 }, ++ { "PS", 230, 0 }, ++ { "MISC0", 244, 0 }, ++ { "MISC1", 245, 0 }, ++ { "INTENABLE", 228, 0 }, ++ { "DBREAKA0", 144, 0 }, ++ { "DBREAKC0", 160, 0 }, ++ { "DBREAKA1", 145, 0 }, ++ { "DBREAKC1", 161, 0 }, ++ { "IBREAKA0", 128, 0 }, ++ { "IBREAKA1", 129, 0 }, ++ { "IBREAKENABLE", 96, 0 }, ++ { "ICOUNTLEVEL", 237, 0 }, ++ { "DEBUGCAUSE", 233, 0 }, ++ { "CACHEADRDIS", 98, 0 }, ++ { "MPUENB", 90, 0 }, ++ { "ATOMCTL", 99, 0 }, ++ { "ERACCESS", 95, 0 }, ++ { "EXPSTATE", 230, 1 } ++}; ++ ++#define NUM_SYSREGS 57 ++#define MAX_SPECIAL_REG 245 ++#define MAX_USER_REG 230 ++ ++ ++/* Processor states. */ ++ ++static xtensa_state_internal states[] = { ++ { "PC", 32, 0 }, ++ { "ICOUNT", 32, 0 }, ++ { "DDR", 32, 0 }, ++ { "INTERRUPT", 23, 0 }, ++ { "CCOUNT", 32, 0 }, ++ { "XTSYNC", 1, 0 }, ++ { "VECBASE", 22, 0 }, ++ { "EPC1", 32, 0 }, ++ { "EPC2", 32, 0 }, ++ { "EPC3", 32, 0 }, ++ { "EPC4", 32, 0 }, ++ { "EPC5", 32, 0 }, ++ { "EPC6", 32, 0 }, ++ { "EPC7", 32, 0 }, ++ { "EXCSAVE1", 32, 0 }, ++ { "EXCSAVE2", 32, 0 }, ++ { "EXCSAVE3", 32, 0 }, ++ { "EXCSAVE4", 32, 0 }, ++ { "EXCSAVE5", 32, 0 }, ++ { "EXCSAVE6", 32, 0 }, ++ { "EXCSAVE7", 32, 0 }, ++ { "EPS2", 15, 0 }, ++ { "EPS3", 15, 0 }, ++ { "EPS4", 15, 0 }, ++ { "EPS5", 15, 0 }, ++ { "EPS6", 15, 0 }, ++ { "EPS7", 15, 0 }, ++ { "EXCCAUSE", 6, 0 }, ++ { "PSINTLEVEL", 4, 0 }, ++ { "PSUM", 1, 0 }, ++ { "PSWOE", 1, 0 }, ++ { "PSRING", 2, 0 }, ++ { "PSEXCM", 1, 0 }, ++ { "DEPC", 32, 0 }, ++ { "EXCVADDR", 32, 0 }, ++ { "WindowBase", 3, 0 }, ++ { "WindowStart", 8, 0 }, ++ { "PSCALLINC", 2, 0 }, ++ { "PSOWB", 4, 0 }, ++ { "SAR", 6, 0 }, ++ { "MISC0", 32, 0 }, ++ { "MISC1", 32, 0 }, ++ { "MPUNUMENTRIES", 6, 0 }, ++ { "InOCDMode", 1, 0 }, ++ { "INTENABLE", 23, 0 }, ++ { "DBREAKA0", 32, 0 }, ++ { "DBREAKC0", 8, 0 }, ++ { "DBREAKA1", 32, 0 }, ++ { "DBREAKC1", 8, 0 }, ++ { "IBREAKA0", 32, 0 }, ++ { "IBREAKA1", 32, 0 }, ++ { "IBREAKENABLE", 2, 0 }, ++ { "ICOUNTLEVEL", 4, 0 }, ++ { "DEBUGCAUSE", 6, 0 }, ++ { "DBNUM", 4, 0 }, ++ { "CCOMPARE0", 32, 0 }, ++ { "CCOMPARE1", 32, 0 }, ++ { "CCOMPARE2", 32, 0 }, ++ { "CACHEADRDIS", 8, 0 }, ++ { "MPUENB", 32, 0 }, ++ { "ATOMCTL", 9, 0 }, ++ { "ERACCESS", 16, 0 }, ++ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } ++}; ++ ++#define NUM_STATES 63 ++ ++enum xtensa_state_id { ++ STATE_PC, ++ STATE_ICOUNT, ++ STATE_DDR, ++ STATE_INTERRUPT, ++ STATE_CCOUNT, ++ STATE_XTSYNC, ++ STATE_VECBASE, ++ STATE_EPC1, ++ STATE_EPC2, ++ STATE_EPC3, ++ STATE_EPC4, ++ STATE_EPC5, ++ STATE_EPC6, ++ STATE_EPC7, ++ STATE_EXCSAVE1, ++ STATE_EXCSAVE2, ++ STATE_EXCSAVE3, ++ STATE_EXCSAVE4, ++ STATE_EXCSAVE5, ++ STATE_EXCSAVE6, ++ STATE_EXCSAVE7, ++ STATE_EPS2, ++ STATE_EPS3, ++ STATE_EPS4, ++ STATE_EPS5, ++ STATE_EPS6, ++ STATE_EPS7, ++ STATE_EXCCAUSE, ++ STATE_PSINTLEVEL, ++ STATE_PSUM, ++ STATE_PSWOE, ++ STATE_PSRING, ++ STATE_PSEXCM, ++ STATE_DEPC, ++ STATE_EXCVADDR, ++ STATE_WindowBase, ++ STATE_WindowStart, ++ STATE_PSCALLINC, ++ STATE_PSOWB, ++ STATE_SAR, ++ STATE_MISC0, ++ STATE_MISC1, ++ STATE_MPUNUMENTRIES, ++ STATE_InOCDMode, ++ STATE_INTENABLE, ++ STATE_DBREAKA0, ++ STATE_DBREAKC0, ++ STATE_DBREAKA1, ++ STATE_DBREAKC1, ++ STATE_IBREAKA0, ++ STATE_IBREAKA1, ++ STATE_IBREAKENABLE, ++ STATE_ICOUNTLEVEL, ++ STATE_DEBUGCAUSE, ++ STATE_DBNUM, ++ STATE_CCOMPARE0, ++ STATE_CCOMPARE1, ++ STATE_CCOMPARE2, ++ STATE_CACHEADRDIS, ++ STATE_MPUENB, ++ STATE_ATOMCTL, ++ STATE_ERACCESS, ++ STATE_EXPSTATE ++}; ++ ++ ++/* Field definitions. */ ++ ++static unsigned ++Field_t_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++} ++ ++static unsigned ++Field_s_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++} ++ ++static unsigned ++Field_r_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_op2_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); ++} ++ ++static unsigned ++Field_op1_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); ++} ++ ++static unsigned ++Field_op0_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++} ++ ++static unsigned ++Field_n_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ return tie_t; ++} ++ ++static void ++Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++} ++ ++static unsigned ++Field_m_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); ++ return tie_t; ++} ++ ++static void ++Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); ++} ++ ++static unsigned ++Field_sr_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 24) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); ++ return tie_t; ++} ++ ++static void ++Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); ++} ++ ++static unsigned ++Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); ++ return tie_t; ++} ++ ++static void ++Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); ++} ++ ++static unsigned ++Field_st_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 24) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++} ++ ++static unsigned ++Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++} ++ ++static unsigned ++Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++} ++ ++static unsigned ++Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++} ++ ++static unsigned ++Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x40) | (tie_t << 6); ++} ++ ++static unsigned ++Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x80) | (tie_t << 7); ++} ++ ++static unsigned ++Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++} ++ ++static unsigned ++Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++} ++ ++static unsigned ++Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); ++ return tie_t; ++} ++ ++static void ++Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 20) >> 20; ++ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); ++ return tie_t; ++} ++ ++static void ++Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 24) >> 24; ++ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); ++} ++ ++static unsigned ++Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++} ++ ++static unsigned ++Field_s8_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x800) | (tie_t << 11); ++} ++ ++static unsigned ++Field_imms8_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); ++ return tie_t; ++} ++ ++static void ++Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0x700) | (tie_t << 8); ++} ++ ++static unsigned ++Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); ++ return tie_t; ++} ++ ++static void ++Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 24) >> 24; ++ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); ++ tie_t = (val << 20) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++} ++ ++static unsigned ++Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); ++ return tie_t; ++} ++ ++static void ++Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 16) >> 16; ++ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); ++} ++ ++static unsigned ++Field_offset_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); ++ return tie_t; ++} ++ ++static void ++Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 14) >> 14; ++ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); ++} ++ ++static unsigned ++Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); ++ return tie_t; ++} ++ ++static void ++Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); ++} ++ ++static unsigned ++Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); ++} ++ ++static unsigned ++Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); ++} ++ ++static unsigned ++Field_sae_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); ++} ++ ++static unsigned ++Field_sal_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); ++} ++ ++static unsigned ++Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); ++} ++ ++static unsigned ++Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x10) | (tie_t << 4); ++} ++ ++static unsigned ++Field_sas_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x10) | (tie_t << 4); ++} ++ ++static unsigned ++Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_mn_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ return tie_t; ++} ++ ++static void ++Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++ tie_t = (val << 28) >> 30; ++ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); ++} ++ ++static unsigned ++Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x80) | (tie_t << 7); ++} ++ ++static unsigned ++Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ return tie_t; ++} ++ ++static void ++Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++} ++ ++static unsigned ++Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ return tie_t; ++} ++ ++static void ++Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++} ++ ++static unsigned ++Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++} ++ ++static unsigned ++Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); ++ return tie_t; ++} ++ ++static void ++Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); ++} ++ ++static unsigned ++Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); ++ return tie_t; ++} ++ ++static void ++Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); ++} ++ ++static unsigned ++Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); ++ return tie_t; ++} ++ ++static void ++Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x40) | (tie_t << 6); ++} ++ ++static unsigned ++Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ tie_t = (val << 26) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++} ++ ++static unsigned ++Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ return tie_t; ++} ++ ++static void ++Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ tie_t = (val << 25) >> 29; ++ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); ++} ++ ++static unsigned ++Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); ++ return tie_t; ++} ++ ++static void ++Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 17) >> 17; ++ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); ++} ++ ++static unsigned ++Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); ++ return tie_t; ++} ++ ++static void ++Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 14) >> 14; ++ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); ++} ++ ++static unsigned ++Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) ++{ ++ unsigned tie_t = 0; ++ tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); ++ return tie_t; ++} ++ ++static void ++Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++{ ++ uint32 tie_t; ++ tie_t = (val << 27) >> 27; ++ insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); ++} ++ ++static void ++Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, ++ uint32 val ATTRIBUTE_UNUSED) ++{ ++ /* Do nothing. */ ++} ++ ++static unsigned ++Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} ++ ++static unsigned ++Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) ++{ ++ return 4; ++} ++ ++static unsigned ++Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) ++{ ++ return 8; ++} ++ ++static unsigned ++Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) ++{ ++ return 12; ++} ++ ++enum xtensa_field_id { ++ FIELD_t, ++ FIELD_bbi4, ++ FIELD_bbi, ++ FIELD_imm12, ++ FIELD_imm8, ++ FIELD_s, ++ FIELD_s8, ++ FIELD_imms8, ++ FIELD_imm12b, ++ FIELD_imm16, ++ FIELD_m, ++ FIELD_n, ++ FIELD_offset, ++ FIELD_op0, ++ FIELD_op1, ++ FIELD_op2, ++ FIELD_r, ++ FIELD_r_disp, ++ FIELD_r_3, ++ FIELD_sa4, ++ FIELD_sae4, ++ FIELD_sae, ++ FIELD_sal, ++ FIELD_sargt, ++ FIELD_sas4, ++ FIELD_sas, ++ FIELD_sr, ++ FIELD_st, ++ FIELD_thi3, ++ FIELD_imm4, ++ FIELD_mn, ++ FIELD_i, ++ FIELD_imm6lo, ++ FIELD_imm6hi, ++ FIELD_imm7lo, ++ FIELD_imm7hi, ++ FIELD_z, ++ FIELD_imm6, ++ FIELD_imm7, ++ FIELD_xt_wbr15_imm, ++ FIELD_xt_wbr18_imm, ++ FIELD_bitindex, ++ FIELD_s3to1, ++ FIELD__ar0, ++ FIELD__ar4, ++ FIELD__ar8, ++ FIELD__ar12 ++}; ++ ++ ++/* Functional units. */ ++ ++static xtensa_funcUnit_internal funcUnits[] = { ++ {"XT_LOADSTORE_UNIT", 1} ++}; ++ ++enum xtensa_funcUnit_id { ++ FUNCUNIT_XT_LOADSTORE_UNIT ++}; ++ ++ ++/* Register files. */ ++ ++enum xtensa_regfile_id { ++ REGFILE_AR ++}; ++ ++static xtensa_regfile_internal regfiles[] = { ++ { "AR", "a", REGFILE_AR, 32, 32 } ++}; ++ ++ ++/* Interfaces. */ ++ ++static xtensa_interface_internal interfaces[] = { ++ { "IMPWIRE", 32, 0, 0, 'i' } ++}; ++ ++enum xtensa_interface_id { ++ INTERFACE_IMPWIRE ++}; ++ ++ ++/* Constant tables. */ ++ ++/* constant table ai4c */ ++static const unsigned CONST_TBL_ai4c_0[] = { ++ 0xffffffff, ++ 0x1, ++ 0x2, ++ 0x3, ++ 0x4, ++ 0x5, ++ 0x6, ++ 0x7, ++ 0x8, ++ 0x9, ++ 0xa, ++ 0xb, ++ 0xc, ++ 0xd, ++ 0xe, ++ 0xf, ++ 0 ++}; ++ ++/* constant table b4c */ ++static const unsigned CONST_TBL_b4c_0[] = { ++ 0xffffffff, ++ 0x1, ++ 0x2, ++ 0x3, ++ 0x4, ++ 0x5, ++ 0x6, ++ 0x7, ++ 0x8, ++ 0xa, ++ 0xc, ++ 0x10, ++ 0x20, ++ 0x40, ++ 0x80, ++ 0x100, ++ 0 ++}; ++ ++/* constant table b4cu */ ++static const unsigned CONST_TBL_b4cu_0[] = { ++ 0x8000, ++ 0x10000, ++ 0x2, ++ 0x3, ++ 0x4, ++ 0x5, ++ 0x6, ++ 0x7, ++ 0x8, ++ 0xa, ++ 0xc, ++ 0x10, ++ 0x20, ++ 0x40, ++ 0x80, ++ 0x100, ++ 0 ++}; ++ ++ ++/* Instruction operands. */ ++ ++static int ++OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) ++{ ++ unsigned soffsetx4_out_0; ++ unsigned soffsetx4_in_0; ++ soffsetx4_in_0 = *valp & 0x3ffff; ++ soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); ++ *valp = soffsetx4_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) ++{ ++ unsigned soffsetx4_in_0; ++ unsigned soffsetx4_out_0; ++ soffsetx4_out_0 = *valp; ++ soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; ++ *valp = soffsetx4_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_immr_decode (uint32 *valp) ++{ ++ unsigned immr_out_0; ++ unsigned immr_in_0; ++ immr_in_0 = *valp & 0xf; ++ immr_out_0 = immr_in_0; ++ *valp = immr_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_immr_encode (uint32 *valp) ++{ ++ unsigned immr_in_0; ++ unsigned immr_out_0; ++ immr_out_0 = *valp; ++ immr_in_0 = (immr_out_0 & 0xf); ++ *valp = immr_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) ++{ ++ unsigned uimm12x8_out_0; ++ unsigned uimm12x8_in_0; ++ uimm12x8_in_0 = *valp & 0xfff; ++ uimm12x8_out_0 = uimm12x8_in_0 << 3; ++ *valp = uimm12x8_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) ++{ ++ unsigned uimm12x8_in_0; ++ unsigned uimm12x8_out_0; ++ uimm12x8_out_0 = *valp; ++ uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); ++ *valp = uimm12x8_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm4_decode (uint32 *valp) ++{ ++ unsigned simm4_out_0; ++ unsigned simm4_in_0; ++ simm4_in_0 = *valp & 0xf; ++ simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; ++ *valp = simm4_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm4_encode (uint32 *valp) ++{ ++ unsigned simm4_in_0; ++ unsigned simm4_out_0; ++ simm4_out_0 = *valp; ++ simm4_in_0 = (simm4_out_0 & 0xf); ++ *valp = simm4_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_AR_encode (uint32 *valp) ++{ ++ int error; ++ error = (*valp >= 32); ++ return error; ++} ++ ++static int ++OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_AR_0_encode (uint32 *valp) ++{ ++ int error; ++ error = (*valp >= 32); ++ return error; ++} ++ ++static int ++OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_AR_4_encode (uint32 *valp) ++{ ++ int error; ++ error = (*valp >= 32); ++ return error; ++} ++ ++static int ++OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_AR_8_encode (uint32 *valp) ++{ ++ int error; ++ error = (*valp >= 32); ++ return error; ++} ++ ++static int ++OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_AR_12_encode (uint32 *valp) ++{ ++ int error; ++ error = (*valp >= 32); ++ return error; ++} ++ ++static int ++OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) ++{ ++ int error; ++ error = (*valp >= 32); ++ return error; ++} ++ ++static int ++OperandSem_opnd_sem_immrx4_decode (uint32 *valp) ++{ ++ unsigned immrx4_out_0; ++ unsigned immrx4_in_0; ++ immrx4_in_0 = *valp & 0xf; ++ immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; ++ *valp = immrx4_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_immrx4_encode (uint32 *valp) ++{ ++ unsigned immrx4_in_0; ++ unsigned immrx4_out_0; ++ immrx4_out_0 = *valp; ++ immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); ++ *valp = immrx4_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) ++{ ++ unsigned lsi4x4_out_0; ++ unsigned lsi4x4_in_0; ++ lsi4x4_in_0 = *valp & 0xf; ++ lsi4x4_out_0 = lsi4x4_in_0 << 2; ++ *valp = lsi4x4_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) ++{ ++ unsigned lsi4x4_in_0; ++ unsigned lsi4x4_out_0; ++ lsi4x4_out_0 = *valp; ++ lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); ++ *valp = lsi4x4_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm7_decode (uint32 *valp) ++{ ++ unsigned simm7_out_0; ++ unsigned simm7_in_0; ++ simm7_in_0 = *valp & 0x7f; ++ simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; ++ *valp = simm7_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm7_encode (uint32 *valp) ++{ ++ unsigned simm7_in_0; ++ unsigned simm7_out_0; ++ simm7_out_0 = *valp; ++ simm7_in_0 = (simm7_out_0 & 0x7f); ++ *valp = simm7_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm6_decode (uint32 *valp) ++{ ++ unsigned uimm6_out_0; ++ unsigned uimm6_in_0; ++ uimm6_in_0 = *valp & 0x3f; ++ uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); ++ *valp = uimm6_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm6_encode (uint32 *valp) ++{ ++ unsigned uimm6_in_0; ++ unsigned uimm6_out_0; ++ uimm6_out_0 = *valp; ++ uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; ++ *valp = uimm6_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_ai4const_decode (uint32 *valp) ++{ ++ unsigned ai4const_out_0; ++ unsigned ai4const_in_0; ++ ai4const_in_0 = *valp & 0xf; ++ ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; ++ *valp = ai4const_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_ai4const_encode (uint32 *valp) ++{ ++ unsigned ai4const_in_0; ++ unsigned ai4const_out_0; ++ ai4const_out_0 = *valp; ++ switch (ai4const_out_0) ++ { ++ case 0xffffffff: ai4const_in_0 = 0; break; ++ case 0x1: ai4const_in_0 = 0x1; break; ++ case 0x2: ai4const_in_0 = 0x2; break; ++ case 0x3: ai4const_in_0 = 0x3; break; ++ case 0x4: ai4const_in_0 = 0x4; break; ++ case 0x5: ai4const_in_0 = 0x5; break; ++ case 0x6: ai4const_in_0 = 0x6; break; ++ case 0x7: ai4const_in_0 = 0x7; break; ++ case 0x8: ai4const_in_0 = 0x8; break; ++ case 0x9: ai4const_in_0 = 0x9; break; ++ case 0xa: ai4const_in_0 = 0xa; break; ++ case 0xb: ai4const_in_0 = 0xb; break; ++ case 0xc: ai4const_in_0 = 0xc; break; ++ case 0xd: ai4const_in_0 = 0xd; break; ++ case 0xe: ai4const_in_0 = 0xe; break; ++ default: ai4const_in_0 = 0xf; break; ++ } ++ *valp = ai4const_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_b4const_decode (uint32 *valp) ++{ ++ unsigned b4const_out_0; ++ unsigned b4const_in_0; ++ b4const_in_0 = *valp & 0xf; ++ b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; ++ *valp = b4const_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_b4const_encode (uint32 *valp) ++{ ++ unsigned b4const_in_0; ++ unsigned b4const_out_0; ++ b4const_out_0 = *valp; ++ switch (b4const_out_0) ++ { ++ case 0xffffffff: b4const_in_0 = 0; break; ++ case 0x1: b4const_in_0 = 0x1; break; ++ case 0x2: b4const_in_0 = 0x2; break; ++ case 0x3: b4const_in_0 = 0x3; break; ++ case 0x4: b4const_in_0 = 0x4; break; ++ case 0x5: b4const_in_0 = 0x5; break; ++ case 0x6: b4const_in_0 = 0x6; break; ++ case 0x7: b4const_in_0 = 0x7; break; ++ case 0x8: b4const_in_0 = 0x8; break; ++ case 0xa: b4const_in_0 = 0x9; break; ++ case 0xc: b4const_in_0 = 0xa; break; ++ case 0x10: b4const_in_0 = 0xb; break; ++ case 0x20: b4const_in_0 = 0xc; break; ++ case 0x40: b4const_in_0 = 0xd; break; ++ case 0x80: b4const_in_0 = 0xe; break; ++ default: b4const_in_0 = 0xf; break; ++ } ++ *valp = b4const_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_b4constu_decode (uint32 *valp) ++{ ++ unsigned b4constu_out_0; ++ unsigned b4constu_in_0; ++ b4constu_in_0 = *valp & 0xf; ++ b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; ++ *valp = b4constu_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_b4constu_encode (uint32 *valp) ++{ ++ unsigned b4constu_in_0; ++ unsigned b4constu_out_0; ++ b4constu_out_0 = *valp; ++ switch (b4constu_out_0) ++ { ++ case 0x8000: b4constu_in_0 = 0; break; ++ case 0x10000: b4constu_in_0 = 0x1; break; ++ case 0x2: b4constu_in_0 = 0x2; break; ++ case 0x3: b4constu_in_0 = 0x3; break; ++ case 0x4: b4constu_in_0 = 0x4; break; ++ case 0x5: b4constu_in_0 = 0x5; break; ++ case 0x6: b4constu_in_0 = 0x6; break; ++ case 0x7: b4constu_in_0 = 0x7; break; ++ case 0x8: b4constu_in_0 = 0x8; break; ++ case 0xa: b4constu_in_0 = 0x9; break; ++ case 0xc: b4constu_in_0 = 0xa; break; ++ case 0x10: b4constu_in_0 = 0xb; break; ++ case 0x20: b4constu_in_0 = 0xc; break; ++ case 0x40: b4constu_in_0 = 0xd; break; ++ case 0x80: b4constu_in_0 = 0xe; break; ++ default: b4constu_in_0 = 0xf; break; ++ } ++ *valp = b4constu_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_immt_decode (uint32 *valp) ++{ ++ unsigned immt_out_0; ++ unsigned immt_in_0; ++ immt_in_0 = *valp & 0xf; ++ immt_out_0 = immt_in_0; ++ *valp = immt_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_immt_encode (uint32 *valp) ++{ ++ unsigned immt_in_0; ++ unsigned immt_out_0; ++ immt_out_0 = *valp; ++ immt_in_0 = immt_out_0 & 0xf; ++ *valp = immt_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimms8_decode (uint32 *valp) ++{ ++ unsigned uimms8_out_0; ++ unsigned uimms8_in_0; ++ uimms8_in_0 = *valp & 0x7; ++ uimms8_out_0 = uimms8_in_0; ++ *valp = uimms8_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimms8_encode (uint32 *valp) ++{ ++ unsigned uimms8_in_0; ++ unsigned uimms8_out_0; ++ uimms8_out_0 = *valp; ++ uimms8_in_0 = uimms8_out_0 & 0x7; ++ *valp = uimms8_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm8_decode (uint32 *valp) ++{ ++ unsigned uimm8_out_0; ++ unsigned uimm8_in_0; ++ uimm8_in_0 = *valp & 0xff; ++ uimm8_out_0 = uimm8_in_0; ++ *valp = uimm8_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm8_encode (uint32 *valp) ++{ ++ unsigned uimm8_in_0; ++ unsigned uimm8_out_0; ++ uimm8_out_0 = *valp; ++ uimm8_in_0 = (uimm8_out_0 & 0xff); ++ *valp = uimm8_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) ++{ ++ unsigned uimm8x2_out_0; ++ unsigned uimm8x2_in_0; ++ uimm8x2_in_0 = *valp & 0xff; ++ uimm8x2_out_0 = uimm8x2_in_0 << 1; ++ *valp = uimm8x2_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) ++{ ++ unsigned uimm8x2_in_0; ++ unsigned uimm8x2_out_0; ++ uimm8x2_out_0 = *valp; ++ uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); ++ *valp = uimm8x2_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) ++{ ++ unsigned uimm8x4_out_0; ++ unsigned uimm8x4_in_0; ++ uimm8x4_in_0 = *valp & 0xff; ++ uimm8x4_out_0 = uimm8x4_in_0 << 2; ++ *valp = uimm8x4_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) ++{ ++ unsigned uimm8x4_in_0; ++ unsigned uimm8x4_out_0; ++ uimm8x4_out_0 = *valp; ++ uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); ++ *valp = uimm8x4_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) ++{ ++ unsigned uimm4x16_out_0; ++ unsigned uimm4x16_in_0; ++ uimm4x16_in_0 = *valp & 0xf; ++ uimm4x16_out_0 = uimm4x16_in_0 << 4; ++ *valp = uimm4x16_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) ++{ ++ unsigned uimm4x16_in_0; ++ unsigned uimm4x16_out_0; ++ uimm4x16_out_0 = *valp; ++ uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); ++ *valp = uimm4x16_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) ++{ ++ unsigned uimmrx4_out_0; ++ unsigned uimmrx4_in_0; ++ uimmrx4_in_0 = *valp & 0xf; ++ uimmrx4_out_0 = uimmrx4_in_0 << 2; ++ *valp = uimmrx4_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) ++{ ++ unsigned uimmrx4_in_0; ++ unsigned uimmrx4_out_0; ++ uimmrx4_out_0 = *valp; ++ uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); ++ *valp = uimmrx4_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm8_decode (uint32 *valp) ++{ ++ unsigned simm8_out_0; ++ unsigned simm8_in_0; ++ simm8_in_0 = *valp & 0xff; ++ simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; ++ *valp = simm8_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm8_encode (uint32 *valp) ++{ ++ unsigned simm8_in_0; ++ unsigned simm8_out_0; ++ simm8_out_0 = *valp; ++ simm8_in_0 = (simm8_out_0 & 0xff); ++ *valp = simm8_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) ++{ ++ unsigned simm8x256_out_0; ++ unsigned simm8x256_in_0; ++ simm8x256_in_0 = *valp & 0xff; ++ simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; ++ *valp = simm8x256_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) ++{ ++ unsigned simm8x256_in_0; ++ unsigned simm8x256_out_0; ++ simm8x256_out_0 = *valp; ++ simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); ++ *valp = simm8x256_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm12b_decode (uint32 *valp) ++{ ++ unsigned simm12b_out_0; ++ unsigned simm12b_in_0; ++ simm12b_in_0 = *valp & 0xfff; ++ simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; ++ *valp = simm12b_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_simm12b_encode (uint32 *valp) ++{ ++ unsigned simm12b_in_0; ++ unsigned simm12b_out_0; ++ simm12b_out_0 = *valp; ++ simm12b_in_0 = (simm12b_out_0 & 0xfff); ++ *valp = simm12b_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_msalp32_decode (uint32 *valp) ++{ ++ unsigned msalp32_out_0; ++ unsigned msalp32_in_0; ++ msalp32_in_0 = *valp & 0x1f; ++ msalp32_out_0 = 0x20 - msalp32_in_0; ++ *valp = msalp32_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_msalp32_encode (uint32 *valp) ++{ ++ unsigned msalp32_in_0; ++ unsigned msalp32_out_0; ++ msalp32_out_0 = *valp; ++ msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; ++ *valp = msalp32_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_op2p1_decode (uint32 *valp) ++{ ++ unsigned op2p1_out_0; ++ unsigned op2p1_in_0; ++ op2p1_in_0 = *valp & 0xf; ++ op2p1_out_0 = op2p1_in_0 + 0x1; ++ *valp = op2p1_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_op2p1_encode (uint32 *valp) ++{ ++ unsigned op2p1_in_0; ++ unsigned op2p1_out_0; ++ op2p1_out_0 = *valp; ++ op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; ++ *valp = op2p1_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_label8_decode (uint32 *valp) ++{ ++ unsigned label8_out_0; ++ unsigned label8_in_0; ++ label8_in_0 = *valp & 0xff; ++ label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); ++ *valp = label8_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_label8_encode (uint32 *valp) ++{ ++ unsigned label8_in_0; ++ unsigned label8_out_0; ++ label8_out_0 = *valp; ++ label8_in_0 = (label8_out_0 - 0x4) & 0xff; ++ *valp = label8_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_label12_decode (uint32 *valp) ++{ ++ unsigned label12_out_0; ++ unsigned label12_in_0; ++ label12_in_0 = *valp & 0xfff; ++ label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); ++ *valp = label12_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_label12_encode (uint32 *valp) ++{ ++ unsigned label12_in_0; ++ unsigned label12_out_0; ++ label12_out_0 = *valp; ++ label12_in_0 = (label12_out_0 - 0x4) & 0xfff; ++ *valp = label12_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_soffset_decode (uint32 *valp) ++{ ++ unsigned soffset_out_0; ++ unsigned soffset_in_0; ++ soffset_in_0 = *valp & 0x3ffff; ++ soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); ++ *valp = soffset_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_soffset_encode (uint32 *valp) ++{ ++ unsigned soffset_in_0; ++ unsigned soffset_out_0; ++ soffset_out_0 = *valp; ++ soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; ++ *valp = soffset_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) ++{ ++ unsigned uimm16x4_out_0; ++ unsigned uimm16x4_in_0; ++ uimm16x4_in_0 = *valp & 0xffff; ++ uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; ++ *valp = uimm16x4_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) ++{ ++ unsigned uimm16x4_in_0; ++ unsigned uimm16x4_out_0; ++ uimm16x4_out_0 = *valp; ++ uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; ++ *valp = uimm16x4_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_imms_decode (uint32 *valp) ++{ ++ unsigned imms_out_0; ++ unsigned imms_in_0; ++ imms_in_0 = *valp & 0xf; ++ imms_out_0 = imms_in_0; ++ *valp = imms_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_imms_encode (uint32 *valp) ++{ ++ unsigned imms_in_0; ++ unsigned imms_out_0; ++ imms_out_0 = *valp; ++ imms_in_0 = imms_out_0 & 0xf; ++ *valp = imms_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_tp7_decode (uint32 *valp) ++{ ++ unsigned tp7_out_0; ++ unsigned tp7_in_0; ++ tp7_in_0 = *valp & 0xf; ++ tp7_out_0 = tp7_in_0 + 0x7; ++ *valp = tp7_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_tp7_encode (uint32 *valp) ++{ ++ unsigned tp7_in_0; ++ unsigned tp7_out_0; ++ tp7_out_0 = *valp; ++ tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; ++ *valp = tp7_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) ++{ ++ unsigned xt_wbr15_label_out_0; ++ unsigned xt_wbr15_label_in_0; ++ xt_wbr15_label_in_0 = *valp & 0x7fff; ++ xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); ++ *valp = xt_wbr15_label_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) ++{ ++ unsigned xt_wbr15_label_in_0; ++ unsigned xt_wbr15_label_out_0; ++ xt_wbr15_label_out_0 = *valp; ++ xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; ++ *valp = xt_wbr15_label_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) ++{ ++ unsigned xt_wbr18_label_out_0; ++ unsigned xt_wbr18_label_in_0; ++ xt_wbr18_label_in_0 = *valp & 0x3ffff; ++ xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); ++ *valp = xt_wbr18_label_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) ++{ ++ unsigned xt_wbr18_label_in_0; ++ unsigned xt_wbr18_label_out_0; ++ xt_wbr18_label_out_0 = *valp; ++ xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; ++ *valp = xt_wbr18_label_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_bbi_decode (uint32 *valp) ++{ ++ unsigned bbi_out_0; ++ unsigned bbi_in_0; ++ bbi_in_0 = *valp & 0x1f; ++ bbi_out_0 = (0 << 5) | bbi_in_0; ++ *valp = bbi_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_bbi_encode (uint32 *valp) ++{ ++ unsigned bbi_in_0; ++ unsigned bbi_out_0; ++ bbi_out_0 = *valp; ++ bbi_in_0 = (bbi_out_0 & 0x1f); ++ *valp = bbi_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_s_decode (uint32 *valp) ++{ ++ unsigned s_out_0; ++ unsigned s_in_0; ++ s_in_0 = *valp & 0xf; ++ s_out_0 = (0 << 4) | s_in_0; ++ *valp = s_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_s_encode (uint32 *valp) ++{ ++ unsigned s_in_0; ++ unsigned s_out_0; ++ s_out_0 = *valp; ++ s_in_0 = (s_out_0 & 0xf); ++ *valp = s_in_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_bitindex_decode (uint32 *valp) ++{ ++ unsigned bitindex_out_0; ++ unsigned bitindex_in_0; ++ bitindex_in_0 = *valp & 0x1f; ++ bitindex_out_0 = (0 << 5) | bitindex_in_0; ++ *valp = bitindex_out_0; ++ return 0; ++} ++ ++static int ++OperandSem_opnd_sem_bitindex_encode (uint32 *valp) ++{ ++ unsigned bitindex_in_0; ++ unsigned bitindex_out_0; ++ bitindex_out_0 = *valp; ++ bitindex_in_0 = (bitindex_out_0 & 0x1f); ++ *valp = bitindex_in_0; ++ return 0; ++} ++ ++static int ++Operand_soffsetx4_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= (pc & ~0x3); ++ return 0; ++} ++ ++static int ++Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += (pc & ~0x3); ++ return 0; ++} ++ ++static int ++Operand_uimm6_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= pc; ++ return 0; ++} ++ ++static int ++Operand_uimm6_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += pc; ++ return 0; ++} ++ ++static int ++Operand_label8_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= pc; ++ return 0; ++} ++ ++static int ++Operand_label8_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += pc; ++ return 0; ++} ++ ++static int ++Operand_label12_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= pc; ++ return 0; ++} ++ ++static int ++Operand_label12_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += pc; ++ return 0; ++} ++ ++static int ++Operand_soffset_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= pc; ++ return 0; ++} ++ ++static int ++Operand_soffset_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += pc; ++ return 0; ++} ++ ++static int ++Operand_uimm16x4_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= ((pc + 3) & ~0x3); ++ return 0; ++} ++ ++static int ++Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += ((pc + 3) & ~0x3); ++ return 0; ++} ++ ++static int ++Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= pc; ++ return 0; ++} ++ ++static int ++Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += pc; ++ return 0; ++} ++ ++static int ++Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) ++{ ++ *valp -= pc; ++ return 0; ++} ++ ++static int ++Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) ++{ ++ *valp += pc; ++ return 0; ++} ++ ++static xtensa_operand_internal operands[] = { ++ { "soffsetx4", FIELD_offset, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, ++ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, ++ { "immr", FIELD_r, -1, 0, ++ 0, ++ OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, ++ 0, 0 }, ++ { "uimm12x8", FIELD_imm12, -1, 0, ++ 0, ++ OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, ++ 0, 0 }, ++ { "simm4", FIELD_mn, -1, 0, ++ 0, ++ OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, ++ 0, 0 }, ++ { "arr", FIELD_r, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER, ++ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, ++ 0, 0 }, ++ { "ars", FIELD_s, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER, ++ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, ++ 0, 0 }, ++ { "*ars_invisible", FIELD_s, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, ++ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, ++ 0, 0 }, ++ { "art", FIELD_t, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER, ++ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, ++ 0, 0 }, ++ { "ar0", FIELD__ar0, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, ++ OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, ++ 0, 0 }, ++ { "ar4", FIELD__ar4, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, ++ OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, ++ 0, 0 }, ++ { "ar8", FIELD__ar8, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, ++ OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, ++ 0, 0 }, ++ { "ar12", FIELD__ar12, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, ++ OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, ++ 0, 0 }, ++ { "ars_entry", FIELD_s, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER, ++ OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, ++ 0, 0 }, ++ { "immrx4", FIELD_r, -1, 0, ++ 0, ++ OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, ++ 0, 0 }, ++ { "lsi4x4", FIELD_r, -1, 0, ++ 0, ++ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, ++ 0, 0 }, ++ { "simm7", FIELD_imm7, -1, 0, ++ 0, ++ OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, ++ 0, 0 }, ++ { "uimm6", FIELD_imm6, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, ++ Operand_uimm6_ator, Operand_uimm6_rtoa }, ++ { "ai4const", FIELD_t, -1, 0, ++ 0, ++ OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, ++ 0, 0 }, ++ { "b4const", FIELD_r, -1, 0, ++ 0, ++ OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, ++ 0, 0 }, ++ { "b4constu", FIELD_r, -1, 0, ++ 0, ++ OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, ++ 0, 0 }, ++ { "immt", FIELD_t, -1, 0, ++ 0, ++ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, ++ 0, 0 }, ++ { "uimms8", FIELD_imms8, -1, 0, ++ 0, ++ OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode, ++ 0, 0 }, ++ { "uimm8", FIELD_imm8, -1, 0, ++ 0, ++ OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, ++ 0, 0 }, ++ { "uimm8x2", FIELD_imm8, -1, 0, ++ 0, ++ OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, ++ 0, 0 }, ++ { "uimm8x4", FIELD_imm8, -1, 0, ++ 0, ++ OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, ++ 0, 0 }, ++ { "uimm4x16", FIELD_op2, -1, 0, ++ 0, ++ OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, ++ 0, 0 }, ++ { "uimmrx4", FIELD_r, -1, 0, ++ 0, ++ OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, ++ 0, 0 }, ++ { "simm8", FIELD_imm8, -1, 0, ++ 0, ++ OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, ++ 0, 0 }, ++ { "simm8x256", FIELD_imm8, -1, 0, ++ 0, ++ OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, ++ 0, 0 }, ++ { "simm12b", FIELD_imm12b, -1, 0, ++ 0, ++ OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, ++ 0, 0 }, ++ { "msalp32", FIELD_sal, -1, 0, ++ 0, ++ OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, ++ 0, 0 }, ++ { "op2p1", FIELD_op2, -1, 0, ++ 0, ++ OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, ++ 0, 0 }, ++ { "label8", FIELD_imm8, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, ++ Operand_label8_ator, Operand_label8_rtoa }, ++ { "label12", FIELD_imm12, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, ++ Operand_label12_ator, Operand_label12_rtoa }, ++ { "soffset", FIELD_offset, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, ++ Operand_soffset_ator, Operand_soffset_rtoa }, ++ { "uimm16x4", FIELD_imm16, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, ++ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, ++ { "imms", FIELD_s, -1, 0, ++ 0, ++ OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, ++ 0, 0 }, ++ { "imms1", FIELD_s, -1, 0, ++ 0, ++ OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, ++ 0, 0 }, ++ { "tp7", FIELD_t, -1, 0, ++ 0, ++ OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, ++ 0, 0 }, ++ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, ++ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, ++ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, ++ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, ++ { "bbi", FIELD_bbi, -1, 0, ++ 0, ++ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, ++ 0, 0 }, ++ { "sae", FIELD_sae, -1, 0, ++ 0, ++ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, ++ 0, 0 }, ++ { "sas", FIELD_sas, -1, 0, ++ 0, ++ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, ++ 0, 0 }, ++ { "sargt", FIELD_sargt, -1, 0, ++ 0, ++ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, ++ 0, 0 }, ++ { "s", FIELD_s, -1, 0, ++ 0, ++ OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, ++ 0, 0 }, ++ { "bitindex", FIELD_bitindex, -1, 0, ++ 0, ++ OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, ++ 0, 0 }, ++ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, ++ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, ++ { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, ++ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, ++ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, ++ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, ++ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, ++ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, ++ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, ++ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, ++ { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, ++ { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, ++ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, ++ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, ++ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, ++ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, ++ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, ++ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, ++ { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } ++}; ++ ++enum xtensa_operand_id { ++ OPERAND_soffsetx4, ++ OPERAND_immr, ++ OPERAND_uimm12x8, ++ OPERAND_simm4, ++ OPERAND_arr, ++ OPERAND_ars, ++ OPERAND__ars_invisible, ++ OPERAND_art, ++ OPERAND_ar0, ++ OPERAND_ar4, ++ OPERAND_ar8, ++ OPERAND_ar12, ++ OPERAND_ars_entry, ++ OPERAND_immrx4, ++ OPERAND_lsi4x4, ++ OPERAND_simm7, ++ OPERAND_uimm6, ++ OPERAND_ai4const, ++ OPERAND_b4const, ++ OPERAND_b4constu, ++ OPERAND_immt, ++ OPERAND_uimms8, ++ OPERAND_uimm8, ++ OPERAND_uimm8x2, ++ OPERAND_uimm8x4, ++ OPERAND_uimm4x16, ++ OPERAND_uimmrx4, ++ OPERAND_simm8, ++ OPERAND_simm8x256, ++ OPERAND_simm12b, ++ OPERAND_msalp32, ++ OPERAND_op2p1, ++ OPERAND_label8, ++ OPERAND_label12, ++ OPERAND_soffset, ++ OPERAND_uimm16x4, ++ OPERAND_imms, ++ OPERAND_imms1, ++ OPERAND_tp7, ++ OPERAND_xt_wbr15_label, ++ OPERAND_xt_wbr18_label, ++ OPERAND_bbi, ++ OPERAND_sae, ++ OPERAND_sas, ++ OPERAND_sargt, ++ OPERAND_s, ++ OPERAND_bitindex, ++ OPERAND_t, ++ OPERAND_bbi4, ++ OPERAND_imm12, ++ OPERAND_imm8, ++ OPERAND_s8, ++ OPERAND_imms8, ++ OPERAND_imm12b, ++ OPERAND_imm16, ++ OPERAND_m, ++ OPERAND_n, ++ OPERAND_offset, ++ OPERAND_op0, ++ OPERAND_op1, ++ OPERAND_op2, ++ OPERAND_r, ++ OPERAND_r_disp, ++ OPERAND_r_3, ++ OPERAND_sa4, ++ OPERAND_sae4, ++ OPERAND_sal, ++ OPERAND_sas4, ++ OPERAND_sr, ++ OPERAND_st, ++ OPERAND_thi3, ++ OPERAND_imm4, ++ OPERAND_mn, ++ OPERAND_i, ++ OPERAND_imm6lo, ++ OPERAND_imm6hi, ++ OPERAND_imm7lo, ++ OPERAND_imm7hi, ++ OPERAND_z, ++ OPERAND_imm6, ++ OPERAND_imm7, ++ OPERAND_xt_wbr15_imm, ++ OPERAND_xt_wbr18_imm, ++ OPERAND_s3to1 ++}; ++ ++ ++/* Iclass table. */ ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_PSEXCM }, 'm' }, ++ { { STATE_EPC1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DEPC }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { ++ { { OPERAND_soffsetx4 }, 'i' }, ++ { { OPERAND_ar12 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { ++ { { STATE_PSCALLINC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { ++ { { OPERAND_soffsetx4 }, 'i' }, ++ { { OPERAND_ar8 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { ++ { { STATE_PSCALLINC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { ++ { { OPERAND_soffsetx4 }, 'i' }, ++ { { OPERAND_ar4 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { ++ { { STATE_PSCALLINC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_ar12 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { ++ { { STATE_PSCALLINC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_ar8 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { ++ { { STATE_PSCALLINC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_ar4 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { ++ { { STATE_PSCALLINC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { ++ { { OPERAND_ars_entry }, 's' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm12x8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { ++ { { STATE_PSCALLINC }, 'i' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSWOE }, 'i' }, ++ { { STATE_WindowBase }, 'm' }, ++ { { STATE_WindowStart }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { ++ { { STATE_WindowBase }, 'i' }, ++ { { STATE_WindowStart }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { ++ { { OPERAND_simm4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowBase }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { ++ { { OPERAND__ars_invisible }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { ++ { { STATE_WindowBase }, 'm' }, ++ { { STATE_WindowStart }, 'm' }, ++ { { STATE_PSCALLINC }, 'o' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSWOE }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { ++ { { STATE_EPC1 }, 'i' }, ++ { { STATE_PSEXCM }, 'm' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowBase }, 'm' }, ++ { { STATE_WindowStart }, 'm' }, ++ { { STATE_PSOWB }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_immrx4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_immrx4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowBase }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowBase }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowBase }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowStart }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowStart }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_WindowStart }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_ai4const }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm6 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_lsi4x4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { ++ { { OPERAND_ars }, 'o' }, ++ { { OPERAND_simm7 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { ++ { { OPERAND__ars_invisible }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_lsi4x4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_simm8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_simm8x256 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_b4const }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_bbi }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_b4constu }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_label12 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { ++ { { OPERAND_soffsetx4 }, 'i' }, ++ { { OPERAND_ar0 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_ar0 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_sae }, 'i' }, ++ { { OPERAND_op2p1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { ++ { { OPERAND_soffset }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x2 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x2 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_uimm16x4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_simm12b }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { ++ { { OPERAND_arr }, 'm' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l32ex_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l32ex_stateArgs[] = { ++ { { STATE_XTSYNC }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s32ex_args[] = { ++ { { OPERAND_art }, 'm' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s32ex_stateArgs[] = { ++ { { STATE_XTSYNC }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_getex_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_getex_stateArgs[] = { ++ { { STATE_XTSYNC }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_clrex_stateArgs[] = { ++ { { STATE_XTSYNC }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { ++ { { OPERAND__ars_invisible }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = { ++ { { OPERAND_immt }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x2 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimmrx4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { ++ { { STATE_SAR }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { ++ { { OPERAND_sas }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { ++ { { STATE_SAR }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_msalp32 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_sargt }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_s }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { ++ { { STATE_XTSYNC }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_s }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { ++ { { STATE_PSWOE }, 'i' }, ++ { { STATE_PSCALLINC }, 'i' }, ++ { { STATE_PSOWB }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_PSUM }, 'i' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { ++ { { STATE_SAR }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { ++ { { STATE_SAR }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { ++ { { STATE_PSWOE }, 'i' }, ++ { { STATE_PSCALLINC }, 'i' }, ++ { { STATE_PSOWB }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_PSUM }, 'i' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { ++ { { STATE_PSWOE }, 'o' }, ++ { { STATE_PSCALLINC }, 'o' }, ++ { { STATE_PSOWB }, 'o' }, ++ { { STATE_PSRING }, 'm' }, ++ { { STATE_PSUM }, 'o' }, ++ { { STATE_PSEXCM }, 'm' }, ++ { { STATE_PSINTLEVEL }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { ++ { { STATE_PSWOE }, 'm' }, ++ { { STATE_PSCALLINC }, 'm' }, ++ { { STATE_PSOWB }, 'm' }, ++ { { STATE_PSRING }, 'm' }, ++ { { STATE_PSUM }, 'm' }, ++ { { STATE_PSEXCM }, 'm' }, ++ { { STATE_PSINTLEVEL }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC1 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC1 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE1 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE1 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC2 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC2 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC2 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE2 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE2 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE2 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC3 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC3 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC3 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE3 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE3 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE3 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC4 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC4 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE4 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE4 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC5 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC5 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC5 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE5 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE5 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE5 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC6 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC6 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC6 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE6 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE6 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE6 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC7 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC7 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPC7 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE7 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE7 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCSAVE7 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS2 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS2 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS2 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS3 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS3 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS3 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS4 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS4 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS5 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS5 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS5 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS6 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS6 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS6 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS7 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS7 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EPS7 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCVADDR }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCVADDR }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCVADDR }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DEPC }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DEPC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DEPC }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCCAUSE }, 'i' }, ++ { { STATE_XTSYNC }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCCAUSE }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_EXCCAUSE }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MISC0 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MISC0 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MISC0 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MISC1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MISC1 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MISC1 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_VECBASE }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_VECBASE }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_VECBASE }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MPUNUMENTRIES }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MPUNUMENTRIES }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_mul16_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_mul32_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { ++ { { OPERAND_s }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { ++ { { STATE_PSWOE }, 'o' }, ++ { { STATE_PSCALLINC }, 'o' }, ++ { { STATE_PSOWB }, 'o' }, ++ { { STATE_PSRING }, 'm' }, ++ { { STATE_PSUM }, 'o' }, ++ { { STATE_PSEXCM }, 'm' }, ++ { { STATE_PSINTLEVEL }, 'o' }, ++ { { STATE_EPC1 }, 'i' }, ++ { { STATE_EPC2 }, 'i' }, ++ { { STATE_EPC3 }, 'i' }, ++ { { STATE_EPC4 }, 'i' }, ++ { { STATE_EPC5 }, 'i' }, ++ { { STATE_EPC6 }, 'i' }, ++ { { STATE_EPC7 }, 'i' }, ++ { { STATE_EPS2 }, 'i' }, ++ { { STATE_EPS3 }, 'i' }, ++ { { STATE_EPS4 }, 'i' }, ++ { { STATE_EPS5 }, 'i' }, ++ { { STATE_EPS6 }, 'i' }, ++ { { STATE_EPS7 }, 'i' }, ++ { { STATE_InOCDMode }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { ++ { { OPERAND_s }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_INTERRUPT }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_INTENABLE }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_INTENABLE }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_INTENABLE }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { ++ { { OPERAND_imms }, 'i' }, ++ { { OPERAND_immt }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { ++ { { OPERAND_imms }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKA0 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKA0 }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKA0 }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKC0 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKC0 }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKC0 }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKA1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKA1 }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKA1 }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKC1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKC1 }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DBREAKC1 }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKA0 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKA0 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKA0 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKA1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKA1 }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKA1 }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKENABLE }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKENABLE }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_IBREAKENABLE }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DEBUGCAUSE }, 'i' }, ++ { { STATE_DBNUM }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DEBUGCAUSE }, 'o' }, ++ { { STATE_DBNUM }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DEBUGCAUSE }, 'm' }, ++ { { STATE_DBNUM }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ICOUNT }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_ICOUNT }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_ICOUNT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ICOUNTLEVEL }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ICOUNTLEVEL }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ICOUNTLEVEL }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_DDR }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_DDR }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_DDR }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { ++ { { OPERAND_ars }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_InOCDMode }, 'i' }, ++ { { STATE_DDR }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { ++ { { OPERAND_ars }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_InOCDMode }, 'i' }, ++ { { STATE_DDR }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { ++ { { OPERAND_imms }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { ++ { { STATE_InOCDMode }, 'm' }, ++ { { STATE_EPC6 }, 'i' }, ++ { { STATE_PSWOE }, 'o' }, ++ { { STATE_PSCALLINC }, 'o' }, ++ { { STATE_PSOWB }, 'o' }, ++ { { STATE_PSRING }, 'o' }, ++ { { STATE_PSUM }, 'o' }, ++ { { STATE_PSEXCM }, 'o' }, ++ { { STATE_PSINTLEVEL }, 'o' }, ++ { { STATE_EPS6 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { ++ { { STATE_InOCDMode }, 'm' }, ++ { { STATE_VECBASE }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOUNT }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_CCOUNT }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_CCOUNT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE0 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE0 }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE0 }, 'm' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE1 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE1 }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE1 }, 'm' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE2 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE2 }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CCOMPARE2 }, 'm' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CACHEADRDIS }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CACHEADRDIS }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_CACHEADRDIS }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rptlb0_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rptlb0_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MPUENB }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rptlb_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rptlb_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wptlb_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wptlb_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MPUENB }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MPUENB }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MPUENB }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_MPUENB }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_tp7 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x4 }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ATOMCTL }, 'i' }, ++ { { STATE_XTSYNC }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ATOMCTL }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ATOMCTL }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ERACCESS }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ERACCESS }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { ++ { { OPERAND_art }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' }, ++ { { STATE_ERACCESS }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { ++ { { STATE_ERACCESS }, 'i' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { ++ { { STATE_ERACCESS }, 'i' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSRING }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { ++ { { OPERAND_art }, 'o' } ++}; ++ ++static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { ++ INTERFACE_IMPWIRE ++}; ++ ++static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { ++ { { OPERAND_bitindex }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { ++ { { STATE_EXPSTATE }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { ++ { { OPERAND_bitindex }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { ++ { { STATE_EXPSTATE }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { ++ { { STATE_EXPSTATE }, 'm' } ++}; ++ ++static xtensa_arg_internal Iclass_rur_expstate_args[] = { ++ { { OPERAND_arr }, 'o' } ++}; ++ ++static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { ++ { { STATE_EXPSTATE }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_wur_expstate_args[] = { ++ { { OPERAND_art }, 'i' } ++}; ++ ++static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { ++ { { STATE_EXPSTATE }, 'o' } ++}; ++ ++static xtensa_iclass_internal iclasses[] = { ++ { 0, 0 /* xt_iclass_excw */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_rfe */, ++ 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_rfde */, ++ 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_syscall */, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_call12_args, ++ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_call8_args, ++ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_call4_args, ++ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_callx12_args, ++ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_callx8_args, ++ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_callx4_args, ++ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_entry_args, ++ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_movsp_args, ++ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rotw_args, ++ 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_retw_args, ++ 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_rfwou */, ++ 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_l32e_args, ++ 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_s32e_args, ++ 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_windowbase_args, ++ 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_windowbase_args, ++ 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_windowbase_args, ++ 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_windowstart_args, ++ 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_windowstart_args, ++ 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_windowstart_args, ++ 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_add_n_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addi_n_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_bz6_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_ill_n */, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_loadi4_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_mov_n_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_movi_n_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_nopn */, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_retn_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_storei4_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addi_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addmi_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addsub_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bit_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bsi8_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bsi8b_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bsi8u_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bst8_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_bsz12_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_call0_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_callx0_args, ++ 0, 0, 0, 0 }, ++ { 4, Iclass_xt_iclass_exti_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_ill */, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_jump_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_jumpx_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l16ui_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l16si_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l32i_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_l32r_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l8i_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_movi_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_movz_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_neg_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_nop */, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_l32ex_args, ++ 1, Iclass_xt_iclass_l32ex_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_s32ex_args, ++ 1, Iclass_xt_iclass_s32ex_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_getex_args, ++ 1, Iclass_xt_iclass_getex_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_clrex */, ++ 1, Iclass_xt_iclass_clrex_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_return_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_simcall_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s16i_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s32i_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s32nb_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s8i_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_sar_args, ++ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_sari_args, ++ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_shifts_args, ++ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_shiftst_args, ++ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_shiftt_args, ++ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_slli_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_srai_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_srli_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_memw */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_extw */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_isync */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_sync */, ++ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_rsil_args, ++ 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_sar_args, ++ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_sar_args, ++ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_sar_args, ++ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_memctl_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_memctl_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_memctl_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_configid0_args, ++ 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_configid0_args, ++ 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_configid1_args, ++ 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ps_args, ++ 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ps_args, ++ 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ps_args, ++ 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc1_args, ++ 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc1_args, ++ 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc1_args, ++ 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave1_args, ++ 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave1_args, ++ 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave1_args, ++ 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc2_args, ++ 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc2_args, ++ 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc2_args, ++ 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave2_args, ++ 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave2_args, ++ 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave2_args, ++ 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc3_args, ++ 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc3_args, ++ 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc3_args, ++ 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave3_args, ++ 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave3_args, ++ 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave3_args, ++ 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc4_args, ++ 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc4_args, ++ 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc4_args, ++ 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave4_args, ++ 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave4_args, ++ 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave4_args, ++ 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc5_args, ++ 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc5_args, ++ 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc5_args, ++ 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave5_args, ++ 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave5_args, ++ 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave5_args, ++ 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc6_args, ++ 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc6_args, ++ 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc6_args, ++ 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave6_args, ++ 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave6_args, ++ 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave6_args, ++ 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc7_args, ++ 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc7_args, ++ 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc7_args, ++ 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave7_args, ++ 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave7_args, ++ 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave7_args, ++ 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps2_args, ++ 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps2_args, ++ 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps2_args, ++ 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps3_args, ++ 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps3_args, ++ 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps3_args, ++ 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps4_args, ++ 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps4_args, ++ 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps4_args, ++ 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps5_args, ++ 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps5_args, ++ 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps5_args, ++ 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps6_args, ++ 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps6_args, ++ 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps6_args, ++ 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps7_args, ++ 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps7_args, ++ 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps7_args, ++ 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excvaddr_args, ++ 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excvaddr_args, ++ 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excvaddr_args, ++ 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_depc_args, ++ 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_depc_args, ++ 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_depc_args, ++ 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_exccause_args, ++ 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_exccause_args, ++ 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_exccause_args, ++ 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_misc0_args, ++ 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_misc0_args, ++ 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_misc0_args, ++ 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_misc1_args, ++ 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_misc1_args, ++ 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_misc1_args, ++ 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_prid_args, ++ 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_vecbase_args, ++ 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_vecbase_args, ++ 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_vecbase_args, ++ 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_mpucfg_args, ++ 3, Iclass_xt_iclass_rsr_mpucfg_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_mpucfg_args, ++ 3, Iclass_xt_iclass_wsr_mpucfg_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_salt_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_mul16_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_mul32_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rfi_args, ++ 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wait_args, ++ 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_interrupt_args, ++ 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_intset_args, ++ 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_intclear_args, ++ 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_intenable_args, ++ 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_intenable_args, ++ 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_intenable_args, ++ 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_break_args, ++ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_break_n_args, ++ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_dbreaka0_args, ++ 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_dbreaka0_args, ++ 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_dbreaka0_args, ++ 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_dbreakc0_args, ++ 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_dbreakc0_args, ++ 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_dbreakc0_args, ++ 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_dbreaka1_args, ++ 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_dbreaka1_args, ++ 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_dbreaka1_args, ++ 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_dbreakc1_args, ++ 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_dbreakc1_args, ++ 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_dbreakc1_args, ++ 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ibreaka0_args, ++ 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ibreaka0_args, ++ 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ibreaka0_args, ++ 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ibreaka1_args, ++ 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ibreaka1_args, ++ 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ibreaka1_args, ++ 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ibreakenable_args, ++ 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ibreakenable_args, ++ 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ibreakenable_args, ++ 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_debugcause_args, ++ 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_debugcause_args, ++ 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_debugcause_args, ++ 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_icount_args, ++ 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_icount_args, ++ 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_icount_args, ++ 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_icountlevel_args, ++ 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_icountlevel_args, ++ 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_icountlevel_args, ++ 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ddr_args, ++ 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ddr_args, ++ 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ddr_args, ++ 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_lddr32_p_args, ++ 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_sddr32_p_args, ++ 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rfdo_args, ++ 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_rfdd */, ++ 2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_mmid_args, ++ 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ccount_args, ++ 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ccount_args, ++ 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ccount_args, ++ 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ccompare0_args, ++ 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ccompare0_args, ++ 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ccompare0_args, ++ 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ccompare1_args, ++ 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ccompare1_args, ++ 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ccompare1_args, ++ 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ccompare2_args, ++ 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ccompare2_args, ++ 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ccompare2_args, ++ 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_cacheadrdis_args, ++ 4, Iclass_xt_iclass_wsr_cacheadrdis_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_cacheadrdis_args, ++ 3, Iclass_xt_iclass_rsr_cacheadrdis_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_cacheadrdis_args, ++ 4, Iclass_xt_iclass_xsr_cacheadrdis_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_rptlb0_args, ++ 3, Iclass_xt_iclass_rptlb0_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_rptlb_args, ++ 2, Iclass_xt_iclass_rptlb_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_wptlb_args, ++ 4, Iclass_xt_iclass_wptlb_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_mpuenb_args, ++ 3, Iclass_xt_iclass_rsr_mpuenb_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_mpuenb_args, ++ 4, Iclass_xt_iclass_wsr_mpuenb_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_mpuenb_args, ++ 4, Iclass_xt_iclass_xsr_mpuenb_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_minmax_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_nsa_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_sx_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l32ai_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s32ri_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_atomctl_args, ++ 4, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_atomctl_args, ++ 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_atomctl_args, ++ 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_div_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eraccess_args, ++ 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eraccess_args, ++ 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eraccess_args, ++ 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_rer_args, ++ 3, Iclass_xt_iclass_rer_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_wer_args, ++ 3, Iclass_xt_iclass_wer_stateArgs, 0, 0 }, ++ { 1, Iclass_iclass_READ_IMPWIRE_args, ++ 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, ++ { 1, Iclass_iclass_SETB_EXPSTATE_args, ++ 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, ++ { 1, Iclass_iclass_CLRB_EXPSTATE_args, ++ 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, ++ { 2, Iclass_iclass_WRMSK_EXPSTATE_args, ++ 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }, ++ { 1, Iclass_rur_expstate_args, ++ 1, Iclass_rur_expstate_stateArgs, 0, 0 }, ++ { 1, Iclass_wur_expstate_args, ++ 1, Iclass_wur_expstate_stateArgs, 0, 0 } ++}; ++ ++enum xtensa_iclass_id { ++ ICLASS_xt_iclass_excw, ++ ICLASS_xt_iclass_rfe, ++ ICLASS_xt_iclass_rfde, ++ ICLASS_xt_iclass_syscall, ++ ICLASS_xt_iclass_call12, ++ ICLASS_xt_iclass_call8, ++ ICLASS_xt_iclass_call4, ++ ICLASS_xt_iclass_callx12, ++ ICLASS_xt_iclass_callx8, ++ ICLASS_xt_iclass_callx4, ++ ICLASS_xt_iclass_entry, ++ ICLASS_xt_iclass_movsp, ++ ICLASS_xt_iclass_rotw, ++ ICLASS_xt_iclass_retw, ++ ICLASS_xt_iclass_rfwou, ++ ICLASS_xt_iclass_l32e, ++ ICLASS_xt_iclass_s32e, ++ ICLASS_xt_iclass_rsr_windowbase, ++ ICLASS_xt_iclass_wsr_windowbase, ++ ICLASS_xt_iclass_xsr_windowbase, ++ ICLASS_xt_iclass_rsr_windowstart, ++ ICLASS_xt_iclass_wsr_windowstart, ++ ICLASS_xt_iclass_xsr_windowstart, ++ ICLASS_xt_iclass_add_n, ++ ICLASS_xt_iclass_addi_n, ++ ICLASS_xt_iclass_bz6, ++ ICLASS_xt_iclass_ill_n, ++ ICLASS_xt_iclass_loadi4, ++ ICLASS_xt_iclass_mov_n, ++ ICLASS_xt_iclass_movi_n, ++ ICLASS_xt_iclass_nopn, ++ ICLASS_xt_iclass_retn, ++ ICLASS_xt_iclass_storei4, ++ ICLASS_xt_iclass_addi, ++ ICLASS_xt_iclass_addmi, ++ ICLASS_xt_iclass_addsub, ++ ICLASS_xt_iclass_bit, ++ ICLASS_xt_iclass_bsi8, ++ ICLASS_xt_iclass_bsi8b, ++ ICLASS_xt_iclass_bsi8u, ++ ICLASS_xt_iclass_bst8, ++ ICLASS_xt_iclass_bsz12, ++ ICLASS_xt_iclass_call0, ++ ICLASS_xt_iclass_callx0, ++ ICLASS_xt_iclass_exti, ++ ICLASS_xt_iclass_ill, ++ ICLASS_xt_iclass_jump, ++ ICLASS_xt_iclass_jumpx, ++ ICLASS_xt_iclass_l16ui, ++ ICLASS_xt_iclass_l16si, ++ ICLASS_xt_iclass_l32i, ++ ICLASS_xt_iclass_l32r, ++ ICLASS_xt_iclass_l8i, ++ ICLASS_xt_iclass_movi, ++ ICLASS_xt_iclass_movz, ++ ICLASS_xt_iclass_neg, ++ ICLASS_xt_iclass_nop, ++ ICLASS_xt_iclass_l32ex, ++ ICLASS_xt_iclass_s32ex, ++ ICLASS_xt_iclass_getex, ++ ICLASS_xt_iclass_clrex, ++ ICLASS_xt_iclass_return, ++ ICLASS_xt_iclass_simcall, ++ ICLASS_xt_iclass_s16i, ++ ICLASS_xt_iclass_s32i, ++ ICLASS_xt_iclass_s32nb, ++ ICLASS_xt_iclass_s8i, ++ ICLASS_xt_iclass_sar, ++ ICLASS_xt_iclass_sari, ++ ICLASS_xt_iclass_shifts, ++ ICLASS_xt_iclass_shiftst, ++ ICLASS_xt_iclass_shiftt, ++ ICLASS_xt_iclass_slli, ++ ICLASS_xt_iclass_srai, ++ ICLASS_xt_iclass_srli, ++ ICLASS_xt_iclass_memw, ++ ICLASS_xt_iclass_extw, ++ ICLASS_xt_iclass_isync, ++ ICLASS_xt_iclass_sync, ++ ICLASS_xt_iclass_rsil, ++ ICLASS_xt_iclass_rsr_sar, ++ ICLASS_xt_iclass_wsr_sar, ++ ICLASS_xt_iclass_xsr_sar, ++ ICLASS_xt_iclass_rsr_memctl, ++ ICLASS_xt_iclass_wsr_memctl, ++ ICLASS_xt_iclass_xsr_memctl, ++ ICLASS_xt_iclass_rsr_configid0, ++ ICLASS_xt_iclass_wsr_configid0, ++ ICLASS_xt_iclass_rsr_configid1, ++ ICLASS_xt_iclass_rsr_ps, ++ ICLASS_xt_iclass_wsr_ps, ++ ICLASS_xt_iclass_xsr_ps, ++ ICLASS_xt_iclass_rsr_epc1, ++ ICLASS_xt_iclass_wsr_epc1, ++ ICLASS_xt_iclass_xsr_epc1, ++ ICLASS_xt_iclass_rsr_excsave1, ++ ICLASS_xt_iclass_wsr_excsave1, ++ ICLASS_xt_iclass_xsr_excsave1, ++ ICLASS_xt_iclass_rsr_epc2, ++ ICLASS_xt_iclass_wsr_epc2, ++ ICLASS_xt_iclass_xsr_epc2, ++ ICLASS_xt_iclass_rsr_excsave2, ++ ICLASS_xt_iclass_wsr_excsave2, ++ ICLASS_xt_iclass_xsr_excsave2, ++ ICLASS_xt_iclass_rsr_epc3, ++ ICLASS_xt_iclass_wsr_epc3, ++ ICLASS_xt_iclass_xsr_epc3, ++ ICLASS_xt_iclass_rsr_excsave3, ++ ICLASS_xt_iclass_wsr_excsave3, ++ ICLASS_xt_iclass_xsr_excsave3, ++ ICLASS_xt_iclass_rsr_epc4, ++ ICLASS_xt_iclass_wsr_epc4, ++ ICLASS_xt_iclass_xsr_epc4, ++ ICLASS_xt_iclass_rsr_excsave4, ++ ICLASS_xt_iclass_wsr_excsave4, ++ ICLASS_xt_iclass_xsr_excsave4, ++ ICLASS_xt_iclass_rsr_epc5, ++ ICLASS_xt_iclass_wsr_epc5, ++ ICLASS_xt_iclass_xsr_epc5, ++ ICLASS_xt_iclass_rsr_excsave5, ++ ICLASS_xt_iclass_wsr_excsave5, ++ ICLASS_xt_iclass_xsr_excsave5, ++ ICLASS_xt_iclass_rsr_epc6, ++ ICLASS_xt_iclass_wsr_epc6, ++ ICLASS_xt_iclass_xsr_epc6, ++ ICLASS_xt_iclass_rsr_excsave6, ++ ICLASS_xt_iclass_wsr_excsave6, ++ ICLASS_xt_iclass_xsr_excsave6, ++ ICLASS_xt_iclass_rsr_epc7, ++ ICLASS_xt_iclass_wsr_epc7, ++ ICLASS_xt_iclass_xsr_epc7, ++ ICLASS_xt_iclass_rsr_excsave7, ++ ICLASS_xt_iclass_wsr_excsave7, ++ ICLASS_xt_iclass_xsr_excsave7, ++ ICLASS_xt_iclass_rsr_eps2, ++ ICLASS_xt_iclass_wsr_eps2, ++ ICLASS_xt_iclass_xsr_eps2, ++ ICLASS_xt_iclass_rsr_eps3, ++ ICLASS_xt_iclass_wsr_eps3, ++ ICLASS_xt_iclass_xsr_eps3, ++ ICLASS_xt_iclass_rsr_eps4, ++ ICLASS_xt_iclass_wsr_eps4, ++ ICLASS_xt_iclass_xsr_eps4, ++ ICLASS_xt_iclass_rsr_eps5, ++ ICLASS_xt_iclass_wsr_eps5, ++ ICLASS_xt_iclass_xsr_eps5, ++ ICLASS_xt_iclass_rsr_eps6, ++ ICLASS_xt_iclass_wsr_eps6, ++ ICLASS_xt_iclass_xsr_eps6, ++ ICLASS_xt_iclass_rsr_eps7, ++ ICLASS_xt_iclass_wsr_eps7, ++ ICLASS_xt_iclass_xsr_eps7, ++ ICLASS_xt_iclass_rsr_excvaddr, ++ ICLASS_xt_iclass_wsr_excvaddr, ++ ICLASS_xt_iclass_xsr_excvaddr, ++ ICLASS_xt_iclass_rsr_depc, ++ ICLASS_xt_iclass_wsr_depc, ++ ICLASS_xt_iclass_xsr_depc, ++ ICLASS_xt_iclass_rsr_exccause, ++ ICLASS_xt_iclass_wsr_exccause, ++ ICLASS_xt_iclass_xsr_exccause, ++ ICLASS_xt_iclass_rsr_misc0, ++ ICLASS_xt_iclass_wsr_misc0, ++ ICLASS_xt_iclass_xsr_misc0, ++ ICLASS_xt_iclass_rsr_misc1, ++ ICLASS_xt_iclass_wsr_misc1, ++ ICLASS_xt_iclass_xsr_misc1, ++ ICLASS_xt_iclass_rsr_prid, ++ ICLASS_xt_iclass_rsr_vecbase, ++ ICLASS_xt_iclass_wsr_vecbase, ++ ICLASS_xt_iclass_xsr_vecbase, ++ ICLASS_xt_iclass_rsr_mpucfg, ++ ICLASS_xt_iclass_wsr_mpucfg, ++ ICLASS_xt_iclass_salt, ++ ICLASS_xt_mul16, ++ ICLASS_xt_mul32, ++ ICLASS_xt_iclass_rfi, ++ ICLASS_xt_iclass_wait, ++ ICLASS_xt_iclass_rsr_interrupt, ++ ICLASS_xt_iclass_wsr_intset, ++ ICLASS_xt_iclass_wsr_intclear, ++ ICLASS_xt_iclass_rsr_intenable, ++ ICLASS_xt_iclass_wsr_intenable, ++ ICLASS_xt_iclass_xsr_intenable, ++ ICLASS_xt_iclass_break, ++ ICLASS_xt_iclass_break_n, ++ ICLASS_xt_iclass_rsr_dbreaka0, ++ ICLASS_xt_iclass_wsr_dbreaka0, ++ ICLASS_xt_iclass_xsr_dbreaka0, ++ ICLASS_xt_iclass_rsr_dbreakc0, ++ ICLASS_xt_iclass_wsr_dbreakc0, ++ ICLASS_xt_iclass_xsr_dbreakc0, ++ ICLASS_xt_iclass_rsr_dbreaka1, ++ ICLASS_xt_iclass_wsr_dbreaka1, ++ ICLASS_xt_iclass_xsr_dbreaka1, ++ ICLASS_xt_iclass_rsr_dbreakc1, ++ ICLASS_xt_iclass_wsr_dbreakc1, ++ ICLASS_xt_iclass_xsr_dbreakc1, ++ ICLASS_xt_iclass_rsr_ibreaka0, ++ ICLASS_xt_iclass_wsr_ibreaka0, ++ ICLASS_xt_iclass_xsr_ibreaka0, ++ ICLASS_xt_iclass_rsr_ibreaka1, ++ ICLASS_xt_iclass_wsr_ibreaka1, ++ ICLASS_xt_iclass_xsr_ibreaka1, ++ ICLASS_xt_iclass_rsr_ibreakenable, ++ ICLASS_xt_iclass_wsr_ibreakenable, ++ ICLASS_xt_iclass_xsr_ibreakenable, ++ ICLASS_xt_iclass_rsr_debugcause, ++ ICLASS_xt_iclass_wsr_debugcause, ++ ICLASS_xt_iclass_xsr_debugcause, ++ ICLASS_xt_iclass_rsr_icount, ++ ICLASS_xt_iclass_wsr_icount, ++ ICLASS_xt_iclass_xsr_icount, ++ ICLASS_xt_iclass_rsr_icountlevel, ++ ICLASS_xt_iclass_wsr_icountlevel, ++ ICLASS_xt_iclass_xsr_icountlevel, ++ ICLASS_xt_iclass_rsr_ddr, ++ ICLASS_xt_iclass_wsr_ddr, ++ ICLASS_xt_iclass_xsr_ddr, ++ ICLASS_xt_iclass_lddr32_p, ++ ICLASS_xt_iclass_sddr32_p, ++ ICLASS_xt_iclass_rfdo, ++ ICLASS_xt_iclass_rfdd, ++ ICLASS_xt_iclass_wsr_mmid, ++ ICLASS_xt_iclass_rsr_ccount, ++ ICLASS_xt_iclass_wsr_ccount, ++ ICLASS_xt_iclass_xsr_ccount, ++ ICLASS_xt_iclass_rsr_ccompare0, ++ ICLASS_xt_iclass_wsr_ccompare0, ++ ICLASS_xt_iclass_xsr_ccompare0, ++ ICLASS_xt_iclass_rsr_ccompare1, ++ ICLASS_xt_iclass_wsr_ccompare1, ++ ICLASS_xt_iclass_xsr_ccompare1, ++ ICLASS_xt_iclass_rsr_ccompare2, ++ ICLASS_xt_iclass_wsr_ccompare2, ++ ICLASS_xt_iclass_xsr_ccompare2, ++ ICLASS_xt_iclass_wsr_cacheadrdis, ++ ICLASS_xt_iclass_rsr_cacheadrdis, ++ ICLASS_xt_iclass_xsr_cacheadrdis, ++ ICLASS_xt_iclass_rptlb0, ++ ICLASS_xt_iclass_rptlb, ++ ICLASS_xt_iclass_wptlb, ++ ICLASS_xt_iclass_rsr_mpuenb, ++ ICLASS_xt_iclass_wsr_mpuenb, ++ ICLASS_xt_iclass_xsr_mpuenb, ++ ICLASS_xt_iclass_minmax, ++ ICLASS_xt_iclass_nsa, ++ ICLASS_xt_iclass_sx, ++ ICLASS_xt_iclass_l32ai, ++ ICLASS_xt_iclass_s32ri, ++ ICLASS_xt_iclass_rsr_atomctl, ++ ICLASS_xt_iclass_wsr_atomctl, ++ ICLASS_xt_iclass_xsr_atomctl, ++ ICLASS_xt_iclass_div, ++ ICLASS_xt_iclass_rsr_eraccess, ++ ICLASS_xt_iclass_wsr_eraccess, ++ ICLASS_xt_iclass_xsr_eraccess, ++ ICLASS_xt_iclass_rer, ++ ICLASS_xt_iclass_wer, ++ ICLASS_iclass_READ_IMPWIRE, ++ ICLASS_iclass_SETB_EXPSTATE, ++ ICLASS_iclass_CLRB_EXPSTATE, ++ ICLASS_iclass_WRMSK_EXPSTATE, ++ ICLASS_rur_expstate, ++ ICLASS_wur_expstate ++}; ++ ++ ++/* Opcode encodings. */ ++ ++static void ++Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2080; ++} ++ ++static void ++Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3000; ++} ++ ++static void ++Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3200; ++} ++ ++static void ++Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x5000; ++} ++ ++static void ++Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x35; ++} ++ ++static void ++Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x25; ++} ++ ++static void ++Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x15; ++} ++ ++static void ++Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf0; ++} ++ ++static void ++Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe0; ++} ++ ++static void ++Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd0; ++} ++ ++static void ++Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36; ++} ++ ++static void ++Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x1000; ++} ++ ++static void ++Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x408000; ++} ++ ++static void ++Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x90; ++} ++ ++static void ++Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf01d; ++} ++ ++static void ++Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3400; ++} ++ ++static void ++Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3500; ++} ++ ++static void ++Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x90000; ++} ++ ++static void ++Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x490000; ++} ++ ++static void ++Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x34800; ++} ++ ++static void ++Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x134800; ++} ++ ++static void ++Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x614800; ++} ++ ++static void ++Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x34900; ++} ++ ++static void ++Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x134900; ++} ++ ++static void ++Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x614900; ++} ++ ++static void ++Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa; ++} ++ ++static void ++Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xb; ++} ++ ++static void ++Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x8c; ++} ++ ++static void ++Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xcc; ++} ++ ++static void ++Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf06d; ++} ++ ++static void ++Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x8; ++} ++ ++static void ++Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd; ++} ++ ++static void ++Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc; ++} ++ ++static void ++Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf03d; ++} ++ ++static void ++Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf00d; ++} ++ ++static void ++Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x9; ++} ++ ++static void ++Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc002; ++} ++ ++static void ++Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd002; ++} ++ ++static void ++Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x800000; ++} ++ ++static void ++Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x900000; ++} ++ ++static void ++Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa00000; ++} ++ ++static void ++Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xb00000; ++} ++ ++static void ++Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc00000; ++} ++ ++static void ++Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd00000; ++} ++ ++static void ++Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe00000; ++} ++ ++static void ++Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf00000; ++} ++ ++static void ++Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x100000; ++} ++ ++static void ++Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x200000; ++} ++ ++static void ++Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x300000; ++} ++ ++static void ++Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x26; ++} ++ ++static void ++Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe6; ++} ++ ++static void ++Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa6; ++} ++ ++static void ++Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x66; ++} ++ ++static void ++Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x6007; ++} ++ ++static void ++Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe007; ++} ++ ++static void ++Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf6; ++} ++ ++static void ++Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xb6; ++} ++ ++static void ++Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x4007; ++} ++ ++static void ++Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x8007; ++} ++ ++static void ++Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x5007; ++} ++ ++static void ++Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd007; ++} ++ ++static void ++Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x1007; ++} ++ ++static void ++Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa007; ++} ++ ++static void ++Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xb007; ++} ++ ++static void ++Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2007; ++} ++ ++static void ++Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3007; ++} ++ ++static void ++Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc007; ++} ++ ++static void ++Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x9007; ++} ++ ++static void ++Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x7; ++} ++ ++static void ++Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x16; ++} ++ ++static void ++Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd6; ++} ++ ++static void ++Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x96; ++} ++ ++static void ++Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x56; ++} ++ ++static void ++Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x5; ++} ++ ++static void ++Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc0; ++} ++ ++static void ++Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x40000; ++} ++ ++static void ++Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0; ++} ++ ++static void ++Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x6; ++} ++ ++static void ++Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa0; ++} ++ ++static void ++Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x1002; ++} ++ ++static void ++Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x9002; ++} ++ ++static void ++Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2002; ++} ++ ++static void ++Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x1; ++} ++ ++static void ++Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2; ++} ++ ++static void ++Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa002; ++} ++ ++static void ++Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x830000; ++} ++ ++static void ++Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xb30000; ++} ++ ++static void ++Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa30000; ++} ++ ++static void ++Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x930000; ++} ++ ++static void ++Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x600100; ++} ++ ++static void ++Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x600000; ++} ++ ++static void ++Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x20f0; ++} ++ ++static void ++Opcode_l32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf14000; ++} ++ ++static void ++Opcode_s32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf15000; ++} ++ ++static void ++Opcode_getex_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x40a000; ++} ++ ++static void ++Opcode_clrex_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3120; ++} ++ ++static void ++Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x80; ++} ++ ++static void ++Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x5100; ++} ++ ++static void ++Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x5002; ++} ++ ++static void ++Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x6002; ++} ++ ++static void ++Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x590000; ++} ++ ++static void ++Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x4002; ++} ++ ++static void ++Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x403000; ++} ++ ++static void ++Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x402000; ++} ++ ++static void ++Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x401000; ++} ++ ++static void ++Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x400000; ++} ++ ++static void ++Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x404000; ++} ++ ++static void ++Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xa10000; ++} ++ ++static void ++Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x810000; ++} ++ ++static void ++Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xb10000; ++} ++ ++static void ++Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x910000; ++} ++ ++static void ++Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x10000; ++} ++ ++static void ++Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x210000; ++} ++ ++static void ++Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x410000; ++} ++ ++static void ++Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x20c0; ++} ++ ++static void ++Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x20d0; ++} ++ ++static void ++Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2000; ++} ++ ++static void ++Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2030; ++} ++ ++static void ++Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2020; ++} ++ ++static void ++Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x2010; ++} ++ ++static void ++Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x6000; ++} ++ ++static void ++Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x30300; ++} ++ ++static void ++Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x130300; ++} ++ ++static void ++Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x610300; ++} ++ ++static void ++Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36100; ++} ++ ++static void ++Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x136100; ++} ++ ++static void ++Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x616100; ++} ++ ++static void ++Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b000; ++} ++ ++static void ++Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b000; ++} ++ ++static void ++Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d000; ++} ++ ++static void ++Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e600; ++} ++ ++static void ++Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e600; ++} ++ ++static void ++Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e600; ++} ++ ++static void ++Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b100; ++} ++ ++static void ++Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b100; ++} ++ ++static void ++Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b100; ++} ++ ++static void ++Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d100; ++} ++ ++static void ++Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d100; ++} ++ ++static void ++Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d100; ++} ++ ++static void ++Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b200; ++} ++ ++static void ++Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b200; ++} ++ ++static void ++Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b200; ++} ++ ++static void ++Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d200; ++} ++ ++static void ++Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d200; ++} ++ ++static void ++Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d200; ++} ++ ++static void ++Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b300; ++} ++ ++static void ++Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b300; ++} ++ ++static void ++Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b300; ++} ++ ++static void ++Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d300; ++} ++ ++static void ++Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d300; ++} ++ ++static void ++Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d300; ++} ++ ++static void ++Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b400; ++} ++ ++static void ++Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b400; ++} ++ ++static void ++Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b400; ++} ++ ++static void ++Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d400; ++} ++ ++static void ++Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d400; ++} ++ ++static void ++Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d400; ++} ++ ++static void ++Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b500; ++} ++ ++static void ++Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b500; ++} ++ ++static void ++Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b500; ++} ++ ++static void ++Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d500; ++} ++ ++static void ++Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d500; ++} ++ ++static void ++Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d500; ++} ++ ++static void ++Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b600; ++} ++ ++static void ++Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b600; ++} ++ ++static void ++Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b600; ++} ++ ++static void ++Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d600; ++} ++ ++static void ++Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d600; ++} ++ ++static void ++Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d600; ++} ++ ++static void ++Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b700; ++} ++ ++static void ++Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b700; ++} ++ ++static void ++Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b700; ++} ++ ++static void ++Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d700; ++} ++ ++static void ++Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d700; ++} ++ ++static void ++Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d700; ++} ++ ++static void ++Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c200; ++} ++ ++static void ++Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c200; ++} ++ ++static void ++Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c200; ++} ++ ++static void ++Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c300; ++} ++ ++static void ++Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c300; ++} ++ ++static void ++Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c300; ++} ++ ++static void ++Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c400; ++} ++ ++static void ++Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c400; ++} ++ ++static void ++Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c400; ++} ++ ++static void ++Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c500; ++} ++ ++static void ++Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c500; ++} ++ ++static void ++Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c500; ++} ++ ++static void ++Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c600; ++} ++ ++static void ++Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c600; ++} ++ ++static void ++Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c600; ++} ++ ++static void ++Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c700; ++} ++ ++static void ++Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c700; ++} ++ ++static void ++Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c700; ++} ++ ++static void ++Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ee00; ++} ++ ++static void ++Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ee00; ++} ++ ++static void ++Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ee00; ++} ++ ++static void ++Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c000; ++} ++ ++static void ++Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c000; ++} ++ ++static void ++Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c000; ++} ++ ++static void ++Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e800; ++} ++ ++static void ++Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e800; ++} ++ ++static void ++Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e800; ++} ++ ++static void ++Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3f400; ++} ++ ++static void ++Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13f400; ++} ++ ++static void ++Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61f400; ++} ++ ++static void ++Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3f500; ++} ++ ++static void ++Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13f500; ++} ++ ++static void ++Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61f500; ++} ++ ++static void ++Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3eb00; ++} ++ ++static void ++Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e700; ++} ++ ++static void ++Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e700; ++} ++ ++static void ++Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e700; ++} ++ ++static void ++Opcode_rsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x35c00; ++} ++ ++static void ++Opcode_wsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x135c00; ++} ++ ++static void ++Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x720000; ++} ++ ++static void ++Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x620000; ++} ++ ++static void ++Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd10000; ++} ++ ++static void ++Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc10000; ++} ++ ++static void ++Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x820000; ++} ++ ++static void ++Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3010; ++} ++ ++static void ++Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x7000; ++} ++ ++static void ++Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e200; ++} ++ ++static void ++Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e200; ++} ++ ++static void ++Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e300; ++} ++ ++static void ++Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e400; ++} ++ ++static void ++Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e400; ++} ++ ++static void ++Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e400; ++} ++ ++static void ++Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x4000; ++} ++ ++static void ++Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf02d; ++} ++ ++static void ++Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x39000; ++} ++ ++static void ++Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x139000; ++} ++ ++static void ++Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x619000; ++} ++ ++static void ++Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3a000; ++} ++ ++static void ++Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13a000; ++} ++ ++static void ++Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61a000; ++} ++ ++static void ++Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x39100; ++} ++ ++static void ++Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x139100; ++} ++ ++static void ++Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x619100; ++} ++ ++static void ++Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3a100; ++} ++ ++static void ++Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13a100; ++} ++ ++static void ++Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61a100; ++} ++ ++static void ++Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x38000; ++} ++ ++static void ++Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x138000; ++} ++ ++static void ++Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x618000; ++} ++ ++static void ++Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x38100; ++} ++ ++static void ++Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x138100; ++} ++ ++static void ++Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x618100; ++} ++ ++static void ++Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36000; ++} ++ ++static void ++Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x136000; ++} ++ ++static void ++Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x616000; ++} ++ ++static void ++Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e900; ++} ++ ++static void ++Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e900; ++} ++ ++static void ++Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e900; ++} ++ ++static void ++Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ec00; ++} ++ ++static void ++Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ec00; ++} ++ ++static void ++Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ec00; ++} ++ ++static void ++Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ed00; ++} ++ ++static void ++Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ed00; ++} ++ ++static void ++Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ed00; ++} ++ ++static void ++Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36800; ++} ++ ++static void ++Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x136800; ++} ++ ++static void ++Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x616800; ++} ++ ++static void ++Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x70e0; ++} ++ ++static void ++Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x70f0; ++} ++ ++static void ++Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf1e000; ++} ++ ++static void ++Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf1e010; ++} ++ ++static void ++Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x135900; ++} ++ ++static void ++Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ea00; ++} ++ ++static void ++Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ea00; ++} ++ ++static void ++Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ea00; ++} ++ ++static void ++Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3f000; ++} ++ ++static void ++Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13f000; ++} ++ ++static void ++Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61f000; ++} ++ ++static void ++Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3f100; ++} ++ ++static void ++Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13f100; ++} ++ ++static void ++Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61f100; ++} ++ ++static void ++Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3f200; ++} ++ ++static void ++Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13f200; ++} ++ ++static void ++Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61f200; ++} ++ ++static void ++Opcode_wsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x136200; ++} ++ ++static void ++Opcode_rsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36200; ++} ++ ++static void ++Opcode_xsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x616200; ++} ++ ++static void ++Opcode_rptlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50b000; ++} ++ ++static void ++Opcode_pptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50d000; ++} ++ ++static void ++Opcode_rptlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50f000; ++} ++ ++static void ++Opcode_wptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50e000; ++} ++ ++static void ++Opcode_rsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x35a00; ++} ++ ++static void ++Opcode_wsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x135a00; ++} ++ ++static void ++Opcode_xsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x615a00; ++} ++ ++static void ++Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x530000; ++} ++ ++static void ++Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x730000; ++} ++ ++static void ++Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x430000; ++} ++ ++static void ++Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x630000; ++} ++ ++static void ++Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x40e000; ++} ++ ++static void ++Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x40f000; ++} ++ ++static void ++Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x230000; ++} ++ ++static void ++Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xb002; ++} ++ ++static void ++Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf002; ++} ++ ++static void ++Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36300; ++} ++ ++static void ++Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x136300; ++} ++ ++static void ++Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x616300; ++} ++ ++static void ++Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd20000; ++} ++ ++static void ++Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc20000; ++} ++ ++static void ++Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf20000; ++} ++ ++static void ++Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe20000; ++} ++ ++static void ++Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x35f00; ++} ++ ++static void ++Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x135f00; ++} ++ ++static void ++Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x615f00; ++} ++ ++static void ++Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x406000; ++} ++ ++static void ++Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x407000; ++} ++ ++static void ++Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe0000; ++} ++ ++static void ++Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe1000; ++} ++ ++static void ++Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe1200; ++} ++ ++static void ++Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe2000; ++} ++ ++static void ++Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xe30e60; ++} ++ ++static void ++Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf3e600; ++} ++ ++static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { ++ Opcode_excw_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { ++ Opcode_rfe_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { ++ Opcode_rfde_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { ++ Opcode_syscall_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { ++ Opcode_call12_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { ++ Opcode_call8_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { ++ Opcode_call4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { ++ Opcode_callx12_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { ++ Opcode_callx8_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { ++ Opcode_callx4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { ++ Opcode_entry_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { ++ Opcode_movsp_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { ++ Opcode_rotw_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { ++ Opcode_retw_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { ++ 0, 0, Opcode_retw_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { ++ Opcode_rfwo_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { ++ Opcode_rfwu_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { ++ Opcode_l32e_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { ++ Opcode_s32e_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { ++ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { ++ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { ++ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { ++ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { ++ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { ++ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { ++ 0, Opcode_add_n_Slot_inst16a_encode, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { ++ 0, Opcode_addi_n_Slot_inst16a_encode, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { ++ 0, 0, Opcode_beqz_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { ++ 0, 0, Opcode_bnez_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { ++ 0, 0, Opcode_ill_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { ++ 0, Opcode_l32i_n_Slot_inst16a_encode, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { ++ 0, 0, Opcode_mov_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { ++ 0, 0, Opcode_movi_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { ++ 0, 0, Opcode_nop_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { ++ 0, 0, Opcode_ret_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { ++ 0, Opcode_s32i_n_Slot_inst16a_encode, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { ++ Opcode_addi_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { ++ Opcode_addmi_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { ++ Opcode_add_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { ++ Opcode_addx2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { ++ Opcode_addx4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { ++ Opcode_addx8_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { ++ Opcode_sub_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { ++ Opcode_subx2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { ++ Opcode_subx4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { ++ Opcode_subx8_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { ++ Opcode_and_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { ++ Opcode_or_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { ++ Opcode_xor_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { ++ Opcode_beqi_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { ++ Opcode_bgei_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { ++ Opcode_blti_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { ++ Opcode_bnei_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { ++ Opcode_bbci_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { ++ Opcode_bbsi_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { ++ Opcode_bgeui_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { ++ Opcode_bltui_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { ++ Opcode_ball_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { ++ Opcode_bany_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { ++ Opcode_bbc_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { ++ Opcode_bbs_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { ++ Opcode_beq_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { ++ Opcode_bge_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { ++ Opcode_bgeu_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { ++ Opcode_blt_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { ++ Opcode_bltu_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { ++ Opcode_bnall_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { ++ Opcode_bne_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { ++ Opcode_bnone_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { ++ Opcode_beqz_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { ++ Opcode_bgez_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { ++ Opcode_bltz_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { ++ Opcode_bnez_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { ++ Opcode_call0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { ++ Opcode_callx0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { ++ Opcode_extui_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { ++ Opcode_ill_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { ++ Opcode_j_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { ++ Opcode_jx_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { ++ Opcode_l16ui_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { ++ Opcode_l16si_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { ++ Opcode_l32i_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { ++ Opcode_l32r_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { ++ Opcode_l8ui_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { ++ Opcode_movi_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { ++ Opcode_moveqz_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { ++ Opcode_movgez_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { ++ Opcode_movltz_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { ++ Opcode_movnez_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { ++ Opcode_abs_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { ++ Opcode_neg_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { ++ Opcode_nop_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l32ex_encode_fns[] = { ++ Opcode_l32ex_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s32ex_encode_fns[] = { ++ Opcode_s32ex_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_getex_encode_fns[] = { ++ Opcode_getex_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_clrex_encode_fns[] = { ++ Opcode_clrex_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { ++ Opcode_ret_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { ++ Opcode_simcall_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { ++ Opcode_s16i_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { ++ Opcode_s32i_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { ++ Opcode_s32nb_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { ++ Opcode_s8i_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { ++ Opcode_ssa8b_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { ++ Opcode_ssa8l_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { ++ Opcode_ssl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { ++ Opcode_ssr_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { ++ Opcode_ssai_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { ++ Opcode_sll_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { ++ Opcode_src_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { ++ Opcode_sra_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { ++ Opcode_srl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { ++ Opcode_slli_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { ++ Opcode_srai_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { ++ Opcode_srli_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { ++ Opcode_memw_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { ++ Opcode_extw_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { ++ Opcode_isync_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { ++ Opcode_dsync_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { ++ Opcode_esync_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { ++ Opcode_rsync_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { ++ Opcode_rsil_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { ++ Opcode_rsr_sar_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { ++ Opcode_wsr_sar_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { ++ Opcode_xsr_sar_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { ++ Opcode_rsr_memctl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { ++ Opcode_wsr_memctl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { ++ Opcode_xsr_memctl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { ++ Opcode_rsr_configid0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { ++ Opcode_wsr_configid0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { ++ Opcode_rsr_configid1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { ++ Opcode_rsr_ps_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { ++ Opcode_wsr_ps_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { ++ Opcode_xsr_ps_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { ++ Opcode_rsr_epc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { ++ Opcode_wsr_epc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { ++ Opcode_xsr_epc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { ++ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { ++ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { ++ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { ++ Opcode_rsr_epc2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { ++ Opcode_wsr_epc2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { ++ Opcode_xsr_epc2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { ++ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { ++ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { ++ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { ++ Opcode_rsr_epc3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { ++ Opcode_wsr_epc3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { ++ Opcode_xsr_epc3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { ++ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { ++ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { ++ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { ++ Opcode_rsr_epc4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { ++ Opcode_wsr_epc4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { ++ Opcode_xsr_epc4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { ++ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { ++ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { ++ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { ++ Opcode_rsr_epc5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { ++ Opcode_wsr_epc5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { ++ Opcode_xsr_epc5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { ++ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { ++ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { ++ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { ++ Opcode_rsr_epc6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { ++ Opcode_wsr_epc6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { ++ Opcode_xsr_epc6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { ++ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { ++ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { ++ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { ++ Opcode_rsr_epc7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { ++ Opcode_wsr_epc7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { ++ Opcode_xsr_epc7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { ++ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { ++ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { ++ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { ++ Opcode_rsr_eps2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { ++ Opcode_wsr_eps2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { ++ Opcode_xsr_eps2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { ++ Opcode_rsr_eps3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { ++ Opcode_wsr_eps3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { ++ Opcode_xsr_eps3_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { ++ Opcode_rsr_eps4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { ++ Opcode_wsr_eps4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { ++ Opcode_xsr_eps4_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { ++ Opcode_rsr_eps5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { ++ Opcode_wsr_eps5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { ++ Opcode_xsr_eps5_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { ++ Opcode_rsr_eps6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { ++ Opcode_wsr_eps6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { ++ Opcode_xsr_eps6_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { ++ Opcode_rsr_eps7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { ++ Opcode_wsr_eps7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { ++ Opcode_xsr_eps7_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { ++ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { ++ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { ++ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { ++ Opcode_rsr_depc_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { ++ Opcode_wsr_depc_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { ++ Opcode_xsr_depc_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { ++ Opcode_rsr_exccause_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { ++ Opcode_wsr_exccause_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { ++ Opcode_xsr_exccause_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { ++ Opcode_rsr_misc0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { ++ Opcode_wsr_misc0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { ++ Opcode_xsr_misc0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { ++ Opcode_rsr_misc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { ++ Opcode_wsr_misc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { ++ Opcode_xsr_misc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { ++ Opcode_rsr_prid_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { ++ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { ++ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { ++ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_mpucfg_encode_fns[] = { ++ Opcode_rsr_mpucfg_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_mpucfg_encode_fns[] = { ++ Opcode_wsr_mpucfg_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { ++ Opcode_salt_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { ++ Opcode_saltu_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { ++ Opcode_mul16s_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { ++ Opcode_mul16u_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { ++ Opcode_mull_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { ++ Opcode_rfi_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { ++ Opcode_waiti_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { ++ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { ++ Opcode_wsr_intset_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { ++ Opcode_wsr_intclear_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { ++ Opcode_rsr_intenable_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { ++ Opcode_wsr_intenable_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { ++ Opcode_xsr_intenable_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { ++ Opcode_break_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { ++ 0, 0, Opcode_break_n_Slot_inst16b_encode ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { ++ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { ++ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { ++ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { ++ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { ++ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { ++ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { ++ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { ++ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { ++ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { ++ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { ++ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { ++ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { ++ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { ++ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { ++ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { ++ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { ++ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { ++ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { ++ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { ++ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { ++ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { ++ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { ++ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { ++ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { ++ Opcode_rsr_icount_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { ++ Opcode_wsr_icount_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { ++ Opcode_xsr_icount_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { ++ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { ++ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { ++ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { ++ Opcode_rsr_ddr_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { ++ Opcode_wsr_ddr_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { ++ Opcode_xsr_ddr_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { ++ Opcode_lddr32_p_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { ++ Opcode_sddr32_p_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { ++ Opcode_rfdo_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { ++ Opcode_rfdd_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { ++ Opcode_wsr_mmid_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { ++ Opcode_rsr_ccount_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { ++ Opcode_wsr_ccount_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { ++ Opcode_xsr_ccount_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { ++ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { ++ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { ++ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { ++ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { ++ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { ++ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { ++ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { ++ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { ++ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_cacheadrdis_encode_fns[] = { ++ Opcode_wsr_cacheadrdis_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_cacheadrdis_encode_fns[] = { ++ Opcode_rsr_cacheadrdis_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_cacheadrdis_encode_fns[] = { ++ Opcode_xsr_cacheadrdis_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rptlb0_encode_fns[] = { ++ Opcode_rptlb0_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_pptlb_encode_fns[] = { ++ Opcode_pptlb_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rptlb1_encode_fns[] = { ++ Opcode_rptlb1_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wptlb_encode_fns[] = { ++ Opcode_wptlb_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_mpuenb_encode_fns[] = { ++ Opcode_rsr_mpuenb_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_mpuenb_encode_fns[] = { ++ Opcode_wsr_mpuenb_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_mpuenb_encode_fns[] = { ++ Opcode_xsr_mpuenb_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { ++ Opcode_max_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { ++ Opcode_maxu_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { ++ Opcode_min_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { ++ Opcode_minu_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { ++ Opcode_nsa_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { ++ Opcode_nsau_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { ++ Opcode_sext_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { ++ Opcode_l32ai_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { ++ Opcode_s32ri_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { ++ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { ++ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { ++ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { ++ Opcode_quos_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { ++ Opcode_quou_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { ++ Opcode_rems_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { ++ Opcode_remu_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { ++ Opcode_rsr_eraccess_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { ++ Opcode_wsr_eraccess_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { ++ Opcode_xsr_eraccess_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { ++ Opcode_rer_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { ++ Opcode_wer_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { ++ Opcode_read_impwire_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { ++ Opcode_setb_expstate_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { ++ Opcode_clrb_expstate_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { ++ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { ++ Opcode_rur_expstate_Slot_inst_encode, 0, 0 ++}; ++ ++static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { ++ Opcode_wur_expstate_Slot_inst_encode, 0, 0 ++}; ++ ++ ++ ++ ++ ++/* Opcode table. */ ++ ++static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l32ex_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s32ex_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { ++ { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } ++}; ++ ++static xtensa_opcode_internal opcodes[] = { ++ { "excw", ICLASS_xt_iclass_excw, ++ 0, ++ Opcode_excw_encode_fns, 0, 0 }, ++ { "rfe", ICLASS_xt_iclass_rfe, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfe_encode_fns, 0, 0 }, ++ { "rfde", ICLASS_xt_iclass_rfde, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfde_encode_fns, 0, 0 }, ++ { "syscall", ICLASS_xt_iclass_syscall, ++ 0, ++ Opcode_syscall_encode_fns, 0, 0 }, ++ { "call12", ICLASS_xt_iclass_call12, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_call12_encode_fns, 0, 0 }, ++ { "call8", ICLASS_xt_iclass_call8, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_call8_encode_fns, 0, 0 }, ++ { "call4", ICLASS_xt_iclass_call4, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_call4_encode_fns, 0, 0 }, ++ { "callx12", ICLASS_xt_iclass_callx12, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_callx12_encode_fns, 0, 0 }, ++ { "callx8", ICLASS_xt_iclass_callx8, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_callx8_encode_fns, 0, 0 }, ++ { "callx4", ICLASS_xt_iclass_callx4, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_callx4_encode_fns, 0, 0 }, ++ { "entry", ICLASS_xt_iclass_entry, ++ 0, ++ Opcode_entry_encode_fns, 0, 0 }, ++ { "movsp", ICLASS_xt_iclass_movsp, ++ 0, ++ Opcode_movsp_encode_fns, 0, 0 }, ++ { "rotw", ICLASS_xt_iclass_rotw, ++ 0, ++ Opcode_rotw_encode_fns, 0, 0 }, ++ { "retw", ICLASS_xt_iclass_retw, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_retw_encode_fns, 0, 0 }, ++ { "retw.n", ICLASS_xt_iclass_retw, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_retw_n_encode_fns, 0, 0 }, ++ { "rfwo", ICLASS_xt_iclass_rfwou, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfwo_encode_fns, 0, 0 }, ++ { "rfwu", ICLASS_xt_iclass_rfwou, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfwu_encode_fns, 0, 0 }, ++ { "l32e", ICLASS_xt_iclass_l32e, ++ 0, ++ Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, ++ { "s32e", ICLASS_xt_iclass_s32e, ++ 0, ++ Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, ++ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, ++ 0, ++ Opcode_rsr_windowbase_encode_fns, 0, 0 }, ++ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, ++ 0, ++ Opcode_wsr_windowbase_encode_fns, 0, 0 }, ++ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, ++ 0, ++ Opcode_xsr_windowbase_encode_fns, 0, 0 }, ++ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, ++ 0, ++ Opcode_rsr_windowstart_encode_fns, 0, 0 }, ++ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, ++ 0, ++ Opcode_wsr_windowstart_encode_fns, 0, 0 }, ++ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, ++ 0, ++ Opcode_xsr_windowstart_encode_fns, 0, 0 }, ++ { "add.n", ICLASS_xt_iclass_add_n, ++ 0, ++ Opcode_add_n_encode_fns, 0, 0 }, ++ { "addi.n", ICLASS_xt_iclass_addi_n, ++ 0, ++ Opcode_addi_n_encode_fns, 0, 0 }, ++ { "beqz.n", ICLASS_xt_iclass_bz6, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beqz_n_encode_fns, 0, 0 }, ++ { "bnez.n", ICLASS_xt_iclass_bz6, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnez_n_encode_fns, 0, 0 }, ++ { "ill.n", ICLASS_xt_iclass_ill_n, ++ 0, ++ Opcode_ill_n_encode_fns, 0, 0 }, ++ { "l32i.n", ICLASS_xt_iclass_loadi4, ++ 0, ++ Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, ++ { "mov.n", ICLASS_xt_iclass_mov_n, ++ 0, ++ Opcode_mov_n_encode_fns, 0, 0 }, ++ { "movi.n", ICLASS_xt_iclass_movi_n, ++ 0, ++ Opcode_movi_n_encode_fns, 0, 0 }, ++ { "nop.n", ICLASS_xt_iclass_nopn, ++ 0, ++ Opcode_nop_n_encode_fns, 0, 0 }, ++ { "ret.n", ICLASS_xt_iclass_retn, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_ret_n_encode_fns, 0, 0 }, ++ { "s32i.n", ICLASS_xt_iclass_storei4, ++ 0, ++ Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, ++ { "addi", ICLASS_xt_iclass_addi, ++ 0, ++ Opcode_addi_encode_fns, 0, 0 }, ++ { "addmi", ICLASS_xt_iclass_addmi, ++ 0, ++ Opcode_addmi_encode_fns, 0, 0 }, ++ { "add", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_add_encode_fns, 0, 0 }, ++ { "addx2", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_addx2_encode_fns, 0, 0 }, ++ { "addx4", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_addx4_encode_fns, 0, 0 }, ++ { "addx8", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_addx8_encode_fns, 0, 0 }, ++ { "sub", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_sub_encode_fns, 0, 0 }, ++ { "subx2", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_subx2_encode_fns, 0, 0 }, ++ { "subx4", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_subx4_encode_fns, 0, 0 }, ++ { "subx8", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_subx8_encode_fns, 0, 0 }, ++ { "and", ICLASS_xt_iclass_bit, ++ 0, ++ Opcode_and_encode_fns, 0, 0 }, ++ { "or", ICLASS_xt_iclass_bit, ++ 0, ++ Opcode_or_encode_fns, 0, 0 }, ++ { "xor", ICLASS_xt_iclass_bit, ++ 0, ++ Opcode_xor_encode_fns, 0, 0 }, ++ { "beqi", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beqi_encode_fns, 0, 0 }, ++ { "bgei", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgei_encode_fns, 0, 0 }, ++ { "blti", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_blti_encode_fns, 0, 0 }, ++ { "bnei", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnei_encode_fns, 0, 0 }, ++ { "bbci", ICLASS_xt_iclass_bsi8b, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbci_encode_fns, 0, 0 }, ++ { "bbsi", ICLASS_xt_iclass_bsi8b, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbsi_encode_fns, 0, 0 }, ++ { "bgeui", ICLASS_xt_iclass_bsi8u, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgeui_encode_fns, 0, 0 }, ++ { "bltui", ICLASS_xt_iclass_bsi8u, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bltui_encode_fns, 0, 0 }, ++ { "ball", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_ball_encode_fns, 0, 0 }, ++ { "bany", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bany_encode_fns, 0, 0 }, ++ { "bbc", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbc_encode_fns, 0, 0 }, ++ { "bbs", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbs_encode_fns, 0, 0 }, ++ { "beq", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beq_encode_fns, 0, 0 }, ++ { "bge", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bge_encode_fns, 0, 0 }, ++ { "bgeu", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgeu_encode_fns, 0, 0 }, ++ { "blt", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_blt_encode_fns, 0, 0 }, ++ { "bltu", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bltu_encode_fns, 0, 0 }, ++ { "bnall", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnall_encode_fns, 0, 0 }, ++ { "bne", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bne_encode_fns, 0, 0 }, ++ { "bnone", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnone_encode_fns, 0, 0 }, ++ { "beqz", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beqz_encode_fns, 0, 0 }, ++ { "bgez", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgez_encode_fns, 0, 0 }, ++ { "bltz", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bltz_encode_fns, 0, 0 }, ++ { "bnez", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnez_encode_fns, 0, 0 }, ++ { "call0", ICLASS_xt_iclass_call0, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_call0_encode_fns, 0, 0 }, ++ { "callx0", ICLASS_xt_iclass_callx0, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_callx0_encode_fns, 0, 0 }, ++ { "extui", ICLASS_xt_iclass_exti, ++ 0, ++ Opcode_extui_encode_fns, 0, 0 }, ++ { "ill", ICLASS_xt_iclass_ill, ++ 0, ++ Opcode_ill_encode_fns, 0, 0 }, ++ { "j", ICLASS_xt_iclass_jump, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_j_encode_fns, 0, 0 }, ++ { "jx", ICLASS_xt_iclass_jumpx, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_jx_encode_fns, 0, 0 }, ++ { "l16ui", ICLASS_xt_iclass_l16ui, ++ 0, ++ Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, ++ { "l16si", ICLASS_xt_iclass_l16si, ++ 0, ++ Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, ++ { "l32i", ICLASS_xt_iclass_l32i, ++ 0, ++ Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, ++ { "l32r", ICLASS_xt_iclass_l32r, ++ 0, ++ Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, ++ { "l8ui", ICLASS_xt_iclass_l8i, ++ 0, ++ Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, ++ { "movi", ICLASS_xt_iclass_movi, ++ 0, ++ Opcode_movi_encode_fns, 0, 0 }, ++ { "moveqz", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_moveqz_encode_fns, 0, 0 }, ++ { "movgez", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_movgez_encode_fns, 0, 0 }, ++ { "movltz", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_movltz_encode_fns, 0, 0 }, ++ { "movnez", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_movnez_encode_fns, 0, 0 }, ++ { "abs", ICLASS_xt_iclass_neg, ++ 0, ++ Opcode_abs_encode_fns, 0, 0 }, ++ { "neg", ICLASS_xt_iclass_neg, ++ 0, ++ Opcode_neg_encode_fns, 0, 0 }, ++ { "nop", ICLASS_xt_iclass_nop, ++ 0, ++ Opcode_nop_encode_fns, 0, 0 }, ++ { "l32ex", ICLASS_xt_iclass_l32ex, ++ 0, ++ Opcode_l32ex_encode_fns, 1, Opcode_l32ex_funcUnit_uses }, ++ { "s32ex", ICLASS_xt_iclass_s32ex, ++ 0, ++ Opcode_s32ex_encode_fns, 1, Opcode_s32ex_funcUnit_uses }, ++ { "getex", ICLASS_xt_iclass_getex, ++ 0, ++ Opcode_getex_encode_fns, 0, 0 }, ++ { "clrex", ICLASS_xt_iclass_clrex, ++ 0, ++ Opcode_clrex_encode_fns, 0, 0 }, ++ { "ret", ICLASS_xt_iclass_return, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_ret_encode_fns, 0, 0 }, ++ { "simcall", ICLASS_xt_iclass_simcall, ++ 0, ++ Opcode_simcall_encode_fns, 0, 0 }, ++ { "s16i", ICLASS_xt_iclass_s16i, ++ 0, ++ Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, ++ { "s32i", ICLASS_xt_iclass_s32i, ++ 0, ++ Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, ++ { "s32nb", ICLASS_xt_iclass_s32nb, ++ 0, ++ Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, ++ { "s8i", ICLASS_xt_iclass_s8i, ++ 0, ++ Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, ++ { "ssa8b", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssa8b_encode_fns, 0, 0 }, ++ { "ssa8l", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssa8l_encode_fns, 0, 0 }, ++ { "ssl", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssl_encode_fns, 0, 0 }, ++ { "ssr", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssr_encode_fns, 0, 0 }, ++ { "ssai", ICLASS_xt_iclass_sari, ++ 0, ++ Opcode_ssai_encode_fns, 0, 0 }, ++ { "sll", ICLASS_xt_iclass_shifts, ++ 0, ++ Opcode_sll_encode_fns, 0, 0 }, ++ { "src", ICLASS_xt_iclass_shiftst, ++ 0, ++ Opcode_src_encode_fns, 0, 0 }, ++ { "sra", ICLASS_xt_iclass_shiftt, ++ 0, ++ Opcode_sra_encode_fns, 0, 0 }, ++ { "srl", ICLASS_xt_iclass_shiftt, ++ 0, ++ Opcode_srl_encode_fns, 0, 0 }, ++ { "slli", ICLASS_xt_iclass_slli, ++ 0, ++ Opcode_slli_encode_fns, 0, 0 }, ++ { "srai", ICLASS_xt_iclass_srai, ++ 0, ++ Opcode_srai_encode_fns, 0, 0 }, ++ { "srli", ICLASS_xt_iclass_srli, ++ 0, ++ Opcode_srli_encode_fns, 0, 0 }, ++ { "memw", ICLASS_xt_iclass_memw, ++ 0, ++ Opcode_memw_encode_fns, 0, 0 }, ++ { "extw", ICLASS_xt_iclass_extw, ++ 0, ++ Opcode_extw_encode_fns, 0, 0 }, ++ { "isync", ICLASS_xt_iclass_isync, ++ 0, ++ Opcode_isync_encode_fns, 0, 0 }, ++ { "dsync", ICLASS_xt_iclass_sync, ++ 0, ++ Opcode_dsync_encode_fns, 0, 0 }, ++ { "esync", ICLASS_xt_iclass_sync, ++ 0, ++ Opcode_esync_encode_fns, 0, 0 }, ++ { "rsync", ICLASS_xt_iclass_sync, ++ 0, ++ Opcode_rsync_encode_fns, 0, 0 }, ++ { "rsil", ICLASS_xt_iclass_rsil, ++ 0, ++ Opcode_rsil_encode_fns, 0, 0 }, ++ { "rsr.sar", ICLASS_xt_iclass_rsr_sar, ++ 0, ++ Opcode_rsr_sar_encode_fns, 0, 0 }, ++ { "wsr.sar", ICLASS_xt_iclass_wsr_sar, ++ 0, ++ Opcode_wsr_sar_encode_fns, 0, 0 }, ++ { "xsr.sar", ICLASS_xt_iclass_xsr_sar, ++ 0, ++ Opcode_xsr_sar_encode_fns, 0, 0 }, ++ { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, ++ 0, ++ Opcode_rsr_memctl_encode_fns, 0, 0 }, ++ { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, ++ 0, ++ Opcode_wsr_memctl_encode_fns, 0, 0 }, ++ { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, ++ 0, ++ Opcode_xsr_memctl_encode_fns, 0, 0 }, ++ { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, ++ 0, ++ Opcode_rsr_configid0_encode_fns, 0, 0 }, ++ { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, ++ 0, ++ Opcode_wsr_configid0_encode_fns, 0, 0 }, ++ { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, ++ 0, ++ Opcode_rsr_configid1_encode_fns, 0, 0 }, ++ { "rsr.ps", ICLASS_xt_iclass_rsr_ps, ++ 0, ++ Opcode_rsr_ps_encode_fns, 0, 0 }, ++ { "wsr.ps", ICLASS_xt_iclass_wsr_ps, ++ 0, ++ Opcode_wsr_ps_encode_fns, 0, 0 }, ++ { "xsr.ps", ICLASS_xt_iclass_xsr_ps, ++ 0, ++ Opcode_xsr_ps_encode_fns, 0, 0 }, ++ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, ++ 0, ++ Opcode_rsr_epc1_encode_fns, 0, 0 }, ++ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, ++ 0, ++ Opcode_wsr_epc1_encode_fns, 0, 0 }, ++ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, ++ 0, ++ Opcode_xsr_epc1_encode_fns, 0, 0 }, ++ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, ++ 0, ++ Opcode_rsr_excsave1_encode_fns, 0, 0 }, ++ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, ++ 0, ++ Opcode_wsr_excsave1_encode_fns, 0, 0 }, ++ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, ++ 0, ++ Opcode_xsr_excsave1_encode_fns, 0, 0 }, ++ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, ++ 0, ++ Opcode_rsr_epc2_encode_fns, 0, 0 }, ++ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, ++ 0, ++ Opcode_wsr_epc2_encode_fns, 0, 0 }, ++ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, ++ 0, ++ Opcode_xsr_epc2_encode_fns, 0, 0 }, ++ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, ++ 0, ++ Opcode_rsr_excsave2_encode_fns, 0, 0 }, ++ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, ++ 0, ++ Opcode_wsr_excsave2_encode_fns, 0, 0 }, ++ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, ++ 0, ++ Opcode_xsr_excsave2_encode_fns, 0, 0 }, ++ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, ++ 0, ++ Opcode_rsr_epc3_encode_fns, 0, 0 }, ++ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, ++ 0, ++ Opcode_wsr_epc3_encode_fns, 0, 0 }, ++ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, ++ 0, ++ Opcode_xsr_epc3_encode_fns, 0, 0 }, ++ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, ++ 0, ++ Opcode_rsr_excsave3_encode_fns, 0, 0 }, ++ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, ++ 0, ++ Opcode_wsr_excsave3_encode_fns, 0, 0 }, ++ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, ++ 0, ++ Opcode_xsr_excsave3_encode_fns, 0, 0 }, ++ { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, ++ 0, ++ Opcode_rsr_epc4_encode_fns, 0, 0 }, ++ { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, ++ 0, ++ Opcode_wsr_epc4_encode_fns, 0, 0 }, ++ { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, ++ 0, ++ Opcode_xsr_epc4_encode_fns, 0, 0 }, ++ { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, ++ 0, ++ Opcode_rsr_excsave4_encode_fns, 0, 0 }, ++ { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, ++ 0, ++ Opcode_wsr_excsave4_encode_fns, 0, 0 }, ++ { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, ++ 0, ++ Opcode_xsr_excsave4_encode_fns, 0, 0 }, ++ { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, ++ 0, ++ Opcode_rsr_epc5_encode_fns, 0, 0 }, ++ { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, ++ 0, ++ Opcode_wsr_epc5_encode_fns, 0, 0 }, ++ { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, ++ 0, ++ Opcode_xsr_epc5_encode_fns, 0, 0 }, ++ { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, ++ 0, ++ Opcode_rsr_excsave5_encode_fns, 0, 0 }, ++ { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, ++ 0, ++ Opcode_wsr_excsave5_encode_fns, 0, 0 }, ++ { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, ++ 0, ++ Opcode_xsr_excsave5_encode_fns, 0, 0 }, ++ { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, ++ 0, ++ Opcode_rsr_epc6_encode_fns, 0, 0 }, ++ { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, ++ 0, ++ Opcode_wsr_epc6_encode_fns, 0, 0 }, ++ { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, ++ 0, ++ Opcode_xsr_epc6_encode_fns, 0, 0 }, ++ { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, ++ 0, ++ Opcode_rsr_excsave6_encode_fns, 0, 0 }, ++ { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, ++ 0, ++ Opcode_wsr_excsave6_encode_fns, 0, 0 }, ++ { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, ++ 0, ++ Opcode_xsr_excsave6_encode_fns, 0, 0 }, ++ { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, ++ 0, ++ Opcode_rsr_epc7_encode_fns, 0, 0 }, ++ { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, ++ 0, ++ Opcode_wsr_epc7_encode_fns, 0, 0 }, ++ { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, ++ 0, ++ Opcode_xsr_epc7_encode_fns, 0, 0 }, ++ { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, ++ 0, ++ Opcode_rsr_excsave7_encode_fns, 0, 0 }, ++ { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, ++ 0, ++ Opcode_wsr_excsave7_encode_fns, 0, 0 }, ++ { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, ++ 0, ++ Opcode_xsr_excsave7_encode_fns, 0, 0 }, ++ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, ++ 0, ++ Opcode_rsr_eps2_encode_fns, 0, 0 }, ++ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, ++ 0, ++ Opcode_wsr_eps2_encode_fns, 0, 0 }, ++ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, ++ 0, ++ Opcode_xsr_eps2_encode_fns, 0, 0 }, ++ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, ++ 0, ++ Opcode_rsr_eps3_encode_fns, 0, 0 }, ++ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, ++ 0, ++ Opcode_wsr_eps3_encode_fns, 0, 0 }, ++ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, ++ 0, ++ Opcode_xsr_eps3_encode_fns, 0, 0 }, ++ { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, ++ 0, ++ Opcode_rsr_eps4_encode_fns, 0, 0 }, ++ { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, ++ 0, ++ Opcode_wsr_eps4_encode_fns, 0, 0 }, ++ { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, ++ 0, ++ Opcode_xsr_eps4_encode_fns, 0, 0 }, ++ { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, ++ 0, ++ Opcode_rsr_eps5_encode_fns, 0, 0 }, ++ { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, ++ 0, ++ Opcode_wsr_eps5_encode_fns, 0, 0 }, ++ { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, ++ 0, ++ Opcode_xsr_eps5_encode_fns, 0, 0 }, ++ { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, ++ 0, ++ Opcode_rsr_eps6_encode_fns, 0, 0 }, ++ { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, ++ 0, ++ Opcode_wsr_eps6_encode_fns, 0, 0 }, ++ { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, ++ 0, ++ Opcode_xsr_eps6_encode_fns, 0, 0 }, ++ { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, ++ 0, ++ Opcode_rsr_eps7_encode_fns, 0, 0 }, ++ { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, ++ 0, ++ Opcode_wsr_eps7_encode_fns, 0, 0 }, ++ { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, ++ 0, ++ Opcode_xsr_eps7_encode_fns, 0, 0 }, ++ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, ++ 0, ++ Opcode_rsr_excvaddr_encode_fns, 0, 0 }, ++ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, ++ 0, ++ Opcode_wsr_excvaddr_encode_fns, 0, 0 }, ++ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, ++ 0, ++ Opcode_xsr_excvaddr_encode_fns, 0, 0 }, ++ { "rsr.depc", ICLASS_xt_iclass_rsr_depc, ++ 0, ++ Opcode_rsr_depc_encode_fns, 0, 0 }, ++ { "wsr.depc", ICLASS_xt_iclass_wsr_depc, ++ 0, ++ Opcode_wsr_depc_encode_fns, 0, 0 }, ++ { "xsr.depc", ICLASS_xt_iclass_xsr_depc, ++ 0, ++ Opcode_xsr_depc_encode_fns, 0, 0 }, ++ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, ++ 0, ++ Opcode_rsr_exccause_encode_fns, 0, 0 }, ++ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, ++ 0, ++ Opcode_wsr_exccause_encode_fns, 0, 0 }, ++ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, ++ 0, ++ Opcode_xsr_exccause_encode_fns, 0, 0 }, ++ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, ++ 0, ++ Opcode_rsr_misc0_encode_fns, 0, 0 }, ++ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, ++ 0, ++ Opcode_wsr_misc0_encode_fns, 0, 0 }, ++ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, ++ 0, ++ Opcode_xsr_misc0_encode_fns, 0, 0 }, ++ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, ++ 0, ++ Opcode_rsr_misc1_encode_fns, 0, 0 }, ++ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, ++ 0, ++ Opcode_wsr_misc1_encode_fns, 0, 0 }, ++ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, ++ 0, ++ Opcode_xsr_misc1_encode_fns, 0, 0 }, ++ { "rsr.prid", ICLASS_xt_iclass_rsr_prid, ++ 0, ++ Opcode_rsr_prid_encode_fns, 0, 0 }, ++ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, ++ 0, ++ Opcode_rsr_vecbase_encode_fns, 0, 0 }, ++ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, ++ 0, ++ Opcode_wsr_vecbase_encode_fns, 0, 0 }, ++ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, ++ 0, ++ Opcode_xsr_vecbase_encode_fns, 0, 0 }, ++ { "rsr.mpucfg", ICLASS_xt_iclass_rsr_mpucfg, ++ 0, ++ Opcode_rsr_mpucfg_encode_fns, 0, 0 }, ++ { "wsr.mpucfg", ICLASS_xt_iclass_wsr_mpucfg, ++ 0, ++ Opcode_wsr_mpucfg_encode_fns, 0, 0 }, ++ { "salt", ICLASS_xt_iclass_salt, ++ 0, ++ Opcode_salt_encode_fns, 0, 0 }, ++ { "saltu", ICLASS_xt_iclass_salt, ++ 0, ++ Opcode_saltu_encode_fns, 0, 0 }, ++ { "mul16s", ICLASS_xt_mul16, ++ 0, ++ Opcode_mul16s_encode_fns, 0, 0 }, ++ { "mul16u", ICLASS_xt_mul16, ++ 0, ++ Opcode_mul16u_encode_fns, 0, 0 }, ++ { "mull", ICLASS_xt_mul32, ++ 0, ++ Opcode_mull_encode_fns, 0, 0 }, ++ { "rfi", ICLASS_xt_iclass_rfi, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfi_encode_fns, 0, 0 }, ++ { "waiti", ICLASS_xt_iclass_wait, ++ 0, ++ Opcode_waiti_encode_fns, 0, 0 }, ++ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, ++ 0, ++ Opcode_rsr_interrupt_encode_fns, 0, 0 }, ++ { "wsr.intset", ICLASS_xt_iclass_wsr_intset, ++ 0, ++ Opcode_wsr_intset_encode_fns, 0, 0 }, ++ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, ++ 0, ++ Opcode_wsr_intclear_encode_fns, 0, 0 }, ++ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, ++ 0, ++ Opcode_rsr_intenable_encode_fns, 0, 0 }, ++ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, ++ 0, ++ Opcode_wsr_intenable_encode_fns, 0, 0 }, ++ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, ++ 0, ++ Opcode_xsr_intenable_encode_fns, 0, 0 }, ++ { "break", ICLASS_xt_iclass_break, ++ 0, ++ Opcode_break_encode_fns, 0, 0 }, ++ { "break.n", ICLASS_xt_iclass_break_n, ++ 0, ++ Opcode_break_n_encode_fns, 0, 0 }, ++ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, ++ 0, ++ Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, ++ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, ++ 0, ++ Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, ++ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, ++ 0, ++ Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, ++ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, ++ 0, ++ Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, ++ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, ++ 0, ++ Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, ++ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, ++ 0, ++ Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, ++ { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, ++ 0, ++ Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, ++ { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, ++ 0, ++ Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, ++ { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, ++ 0, ++ Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, ++ { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, ++ 0, ++ Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, ++ { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, ++ 0, ++ Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, ++ { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, ++ 0, ++ Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, ++ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, ++ 0, ++ Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, ++ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, ++ 0, ++ Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, ++ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, ++ 0, ++ Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, ++ { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, ++ 0, ++ Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, ++ { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, ++ 0, ++ Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, ++ { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, ++ 0, ++ Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, ++ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, ++ 0, ++ Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, ++ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, ++ 0, ++ Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, ++ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, ++ 0, ++ Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, ++ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, ++ 0, ++ Opcode_rsr_debugcause_encode_fns, 0, 0 }, ++ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, ++ 0, ++ Opcode_wsr_debugcause_encode_fns, 0, 0 }, ++ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, ++ 0, ++ Opcode_xsr_debugcause_encode_fns, 0, 0 }, ++ { "rsr.icount", ICLASS_xt_iclass_rsr_icount, ++ 0, ++ Opcode_rsr_icount_encode_fns, 0, 0 }, ++ { "wsr.icount", ICLASS_xt_iclass_wsr_icount, ++ 0, ++ Opcode_wsr_icount_encode_fns, 0, 0 }, ++ { "xsr.icount", ICLASS_xt_iclass_xsr_icount, ++ 0, ++ Opcode_xsr_icount_encode_fns, 0, 0 }, ++ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, ++ 0, ++ Opcode_rsr_icountlevel_encode_fns, 0, 0 }, ++ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, ++ 0, ++ Opcode_wsr_icountlevel_encode_fns, 0, 0 }, ++ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, ++ 0, ++ Opcode_xsr_icountlevel_encode_fns, 0, 0 }, ++ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, ++ 0, ++ Opcode_rsr_ddr_encode_fns, 0, 0 }, ++ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, ++ 0, ++ Opcode_wsr_ddr_encode_fns, 0, 0 }, ++ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, ++ 0, ++ Opcode_xsr_ddr_encode_fns, 0, 0 }, ++ { "lddr32.p", ICLASS_xt_iclass_lddr32_p, ++ 0, ++ Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, ++ { "sddr32.p", ICLASS_xt_iclass_sddr32_p, ++ 0, ++ Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, ++ { "rfdo", ICLASS_xt_iclass_rfdo, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfdo_encode_fns, 0, 0 }, ++ { "rfdd", ICLASS_xt_iclass_rfdd, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfdd_encode_fns, 0, 0 }, ++ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, ++ 0, ++ Opcode_wsr_mmid_encode_fns, 0, 0 }, ++ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, ++ 0, ++ Opcode_rsr_ccount_encode_fns, 0, 0 }, ++ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, ++ 0, ++ Opcode_wsr_ccount_encode_fns, 0, 0 }, ++ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, ++ 0, ++ Opcode_xsr_ccount_encode_fns, 0, 0 }, ++ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, ++ 0, ++ Opcode_rsr_ccompare0_encode_fns, 0, 0 }, ++ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, ++ 0, ++ Opcode_wsr_ccompare0_encode_fns, 0, 0 }, ++ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, ++ 0, ++ Opcode_xsr_ccompare0_encode_fns, 0, 0 }, ++ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, ++ 0, ++ Opcode_rsr_ccompare1_encode_fns, 0, 0 }, ++ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, ++ 0, ++ Opcode_wsr_ccompare1_encode_fns, 0, 0 }, ++ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, ++ 0, ++ Opcode_xsr_ccompare1_encode_fns, 0, 0 }, ++ { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, ++ 0, ++ Opcode_rsr_ccompare2_encode_fns, 0, 0 }, ++ { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, ++ 0, ++ Opcode_wsr_ccompare2_encode_fns, 0, 0 }, ++ { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, ++ 0, ++ Opcode_xsr_ccompare2_encode_fns, 0, 0 }, ++ { "wsr.cacheadrdis", ICLASS_xt_iclass_wsr_cacheadrdis, ++ 0, ++ Opcode_wsr_cacheadrdis_encode_fns, 0, 0 }, ++ { "rsr.cacheadrdis", ICLASS_xt_iclass_rsr_cacheadrdis, ++ 0, ++ Opcode_rsr_cacheadrdis_encode_fns, 0, 0 }, ++ { "xsr.cacheadrdis", ICLASS_xt_iclass_xsr_cacheadrdis, ++ 0, ++ Opcode_xsr_cacheadrdis_encode_fns, 0, 0 }, ++ { "rptlb0", ICLASS_xt_iclass_rptlb0, ++ 0, ++ Opcode_rptlb0_encode_fns, 0, 0 }, ++ { "pptlb", ICLASS_xt_iclass_rptlb, ++ 0, ++ Opcode_pptlb_encode_fns, 0, 0 }, ++ { "rptlb1", ICLASS_xt_iclass_rptlb, ++ 0, ++ Opcode_rptlb1_encode_fns, 0, 0 }, ++ { "wptlb", ICLASS_xt_iclass_wptlb, ++ 0, ++ Opcode_wptlb_encode_fns, 0, 0 }, ++ { "rsr.mpuenb", ICLASS_xt_iclass_rsr_mpuenb, ++ 0, ++ Opcode_rsr_mpuenb_encode_fns, 0, 0 }, ++ { "wsr.mpuenb", ICLASS_xt_iclass_wsr_mpuenb, ++ 0, ++ Opcode_wsr_mpuenb_encode_fns, 0, 0 }, ++ { "xsr.mpuenb", ICLASS_xt_iclass_xsr_mpuenb, ++ 0, ++ Opcode_xsr_mpuenb_encode_fns, 0, 0 }, ++ { "max", ICLASS_xt_iclass_minmax, ++ 0, ++ Opcode_max_encode_fns, 0, 0 }, ++ { "maxu", ICLASS_xt_iclass_minmax, ++ 0, ++ Opcode_maxu_encode_fns, 0, 0 }, ++ { "min", ICLASS_xt_iclass_minmax, ++ 0, ++ Opcode_min_encode_fns, 0, 0 }, ++ { "minu", ICLASS_xt_iclass_minmax, ++ 0, ++ Opcode_minu_encode_fns, 0, 0 }, ++ { "nsa", ICLASS_xt_iclass_nsa, ++ 0, ++ Opcode_nsa_encode_fns, 0, 0 }, ++ { "nsau", ICLASS_xt_iclass_nsa, ++ 0, ++ Opcode_nsau_encode_fns, 0, 0 }, ++ { "sext", ICLASS_xt_iclass_sx, ++ 0, ++ Opcode_sext_encode_fns, 0, 0 }, ++ { "l32ai", ICLASS_xt_iclass_l32ai, ++ 0, ++ Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, ++ { "s32ri", ICLASS_xt_iclass_s32ri, ++ 0, ++ Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, ++ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, ++ 0, ++ Opcode_rsr_atomctl_encode_fns, 0, 0 }, ++ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, ++ 0, ++ Opcode_wsr_atomctl_encode_fns, 0, 0 }, ++ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, ++ 0, ++ Opcode_xsr_atomctl_encode_fns, 0, 0 }, ++ { "quos", ICLASS_xt_iclass_div, ++ 0, ++ Opcode_quos_encode_fns, 0, 0 }, ++ { "quou", ICLASS_xt_iclass_div, ++ 0, ++ Opcode_quou_encode_fns, 0, 0 }, ++ { "rems", ICLASS_xt_iclass_div, ++ 0, ++ Opcode_rems_encode_fns, 0, 0 }, ++ { "remu", ICLASS_xt_iclass_div, ++ 0, ++ Opcode_remu_encode_fns, 0, 0 }, ++ { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, ++ 0, ++ Opcode_rsr_eraccess_encode_fns, 0, 0 }, ++ { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, ++ 0, ++ Opcode_wsr_eraccess_encode_fns, 0, 0 }, ++ { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, ++ 0, ++ Opcode_xsr_eraccess_encode_fns, 0, 0 }, ++ { "rer", ICLASS_xt_iclass_rer, ++ 0, ++ Opcode_rer_encode_fns, 0, 0 }, ++ { "wer", ICLASS_xt_iclass_wer, ++ 0, ++ Opcode_wer_encode_fns, 0, 0 }, ++ { "read_impwire", ICLASS_iclass_READ_IMPWIRE, ++ 0, ++ Opcode_read_impwire_encode_fns, 0, 0 }, ++ { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, ++ 0, ++ Opcode_setb_expstate_encode_fns, 0, 0 }, ++ { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, ++ 0, ++ Opcode_clrb_expstate_encode_fns, 0, 0 }, ++ { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, ++ 0, ++ Opcode_wrmsk_expstate_encode_fns, 0, 0 }, ++ { "rur.expstate", ICLASS_rur_expstate, ++ 0, ++ Opcode_rur_expstate_encode_fns, 0, 0 }, ++ { "wur.expstate", ICLASS_wur_expstate, ++ 0, ++ Opcode_wur_expstate_encode_fns, 0, 0 } ++}; ++ ++enum xtensa_opcode_id { ++ OPCODE_EXCW, ++ OPCODE_RFE, ++ OPCODE_RFDE, ++ OPCODE_SYSCALL, ++ OPCODE_CALL12, ++ OPCODE_CALL8, ++ OPCODE_CALL4, ++ OPCODE_CALLX12, ++ OPCODE_CALLX8, ++ OPCODE_CALLX4, ++ OPCODE_ENTRY, ++ OPCODE_MOVSP, ++ OPCODE_ROTW, ++ OPCODE_RETW, ++ OPCODE_RETW_N, ++ OPCODE_RFWO, ++ OPCODE_RFWU, ++ OPCODE_L32E, ++ OPCODE_S32E, ++ OPCODE_RSR_WINDOWBASE, ++ OPCODE_WSR_WINDOWBASE, ++ OPCODE_XSR_WINDOWBASE, ++ OPCODE_RSR_WINDOWSTART, ++ OPCODE_WSR_WINDOWSTART, ++ OPCODE_XSR_WINDOWSTART, ++ OPCODE_ADD_N, ++ OPCODE_ADDI_N, ++ OPCODE_BEQZ_N, ++ OPCODE_BNEZ_N, ++ OPCODE_ILL_N, ++ OPCODE_L32I_N, ++ OPCODE_MOV_N, ++ OPCODE_MOVI_N, ++ OPCODE_NOP_N, ++ OPCODE_RET_N, ++ OPCODE_S32I_N, ++ OPCODE_ADDI, ++ OPCODE_ADDMI, ++ OPCODE_ADD, ++ OPCODE_ADDX2, ++ OPCODE_ADDX4, ++ OPCODE_ADDX8, ++ OPCODE_SUB, ++ OPCODE_SUBX2, ++ OPCODE_SUBX4, ++ OPCODE_SUBX8, ++ OPCODE_AND, ++ OPCODE_OR, ++ OPCODE_XOR, ++ OPCODE_BEQI, ++ OPCODE_BGEI, ++ OPCODE_BLTI, ++ OPCODE_BNEI, ++ OPCODE_BBCI, ++ OPCODE_BBSI, ++ OPCODE_BGEUI, ++ OPCODE_BLTUI, ++ OPCODE_BALL, ++ OPCODE_BANY, ++ OPCODE_BBC, ++ OPCODE_BBS, ++ OPCODE_BEQ, ++ OPCODE_BGE, ++ OPCODE_BGEU, ++ OPCODE_BLT, ++ OPCODE_BLTU, ++ OPCODE_BNALL, ++ OPCODE_BNE, ++ OPCODE_BNONE, ++ OPCODE_BEQZ, ++ OPCODE_BGEZ, ++ OPCODE_BLTZ, ++ OPCODE_BNEZ, ++ OPCODE_CALL0, ++ OPCODE_CALLX0, ++ OPCODE_EXTUI, ++ OPCODE_ILL, ++ OPCODE_J, ++ OPCODE_JX, ++ OPCODE_L16UI, ++ OPCODE_L16SI, ++ OPCODE_L32I, ++ OPCODE_L32R, ++ OPCODE_L8UI, ++ OPCODE_MOVI, ++ OPCODE_MOVEQZ, ++ OPCODE_MOVGEZ, ++ OPCODE_MOVLTZ, ++ OPCODE_MOVNEZ, ++ OPCODE_ABS, ++ OPCODE_NEG, ++ OPCODE_NOP, ++ OPCODE_L32EX, ++ OPCODE_S32EX, ++ OPCODE_GETEX, ++ OPCODE_CLREX, ++ OPCODE_RET, ++ OPCODE_SIMCALL, ++ OPCODE_S16I, ++ OPCODE_S32I, ++ OPCODE_S32NB, ++ OPCODE_S8I, ++ OPCODE_SSA8B, ++ OPCODE_SSA8L, ++ OPCODE_SSL, ++ OPCODE_SSR, ++ OPCODE_SSAI, ++ OPCODE_SLL, ++ OPCODE_SRC, ++ OPCODE_SRA, ++ OPCODE_SRL, ++ OPCODE_SLLI, ++ OPCODE_SRAI, ++ OPCODE_SRLI, ++ OPCODE_MEMW, ++ OPCODE_EXTW, ++ OPCODE_ISYNC, ++ OPCODE_DSYNC, ++ OPCODE_ESYNC, ++ OPCODE_RSYNC, ++ OPCODE_RSIL, ++ OPCODE_RSR_SAR, ++ OPCODE_WSR_SAR, ++ OPCODE_XSR_SAR, ++ OPCODE_RSR_MEMCTL, ++ OPCODE_WSR_MEMCTL, ++ OPCODE_XSR_MEMCTL, ++ OPCODE_RSR_CONFIGID0, ++ OPCODE_WSR_CONFIGID0, ++ OPCODE_RSR_CONFIGID1, ++ OPCODE_RSR_PS, ++ OPCODE_WSR_PS, ++ OPCODE_XSR_PS, ++ OPCODE_RSR_EPC1, ++ OPCODE_WSR_EPC1, ++ OPCODE_XSR_EPC1, ++ OPCODE_RSR_EXCSAVE1, ++ OPCODE_WSR_EXCSAVE1, ++ OPCODE_XSR_EXCSAVE1, ++ OPCODE_RSR_EPC2, ++ OPCODE_WSR_EPC2, ++ OPCODE_XSR_EPC2, ++ OPCODE_RSR_EXCSAVE2, ++ OPCODE_WSR_EXCSAVE2, ++ OPCODE_XSR_EXCSAVE2, ++ OPCODE_RSR_EPC3, ++ OPCODE_WSR_EPC3, ++ OPCODE_XSR_EPC3, ++ OPCODE_RSR_EXCSAVE3, ++ OPCODE_WSR_EXCSAVE3, ++ OPCODE_XSR_EXCSAVE3, ++ OPCODE_RSR_EPC4, ++ OPCODE_WSR_EPC4, ++ OPCODE_XSR_EPC4, ++ OPCODE_RSR_EXCSAVE4, ++ OPCODE_WSR_EXCSAVE4, ++ OPCODE_XSR_EXCSAVE4, ++ OPCODE_RSR_EPC5, ++ OPCODE_WSR_EPC5, ++ OPCODE_XSR_EPC5, ++ OPCODE_RSR_EXCSAVE5, ++ OPCODE_WSR_EXCSAVE5, ++ OPCODE_XSR_EXCSAVE5, ++ OPCODE_RSR_EPC6, ++ OPCODE_WSR_EPC6, ++ OPCODE_XSR_EPC6, ++ OPCODE_RSR_EXCSAVE6, ++ OPCODE_WSR_EXCSAVE6, ++ OPCODE_XSR_EXCSAVE6, ++ OPCODE_RSR_EPC7, ++ OPCODE_WSR_EPC7, ++ OPCODE_XSR_EPC7, ++ OPCODE_RSR_EXCSAVE7, ++ OPCODE_WSR_EXCSAVE7, ++ OPCODE_XSR_EXCSAVE7, ++ OPCODE_RSR_EPS2, ++ OPCODE_WSR_EPS2, ++ OPCODE_XSR_EPS2, ++ OPCODE_RSR_EPS3, ++ OPCODE_WSR_EPS3, ++ OPCODE_XSR_EPS3, ++ OPCODE_RSR_EPS4, ++ OPCODE_WSR_EPS4, ++ OPCODE_XSR_EPS4, ++ OPCODE_RSR_EPS5, ++ OPCODE_WSR_EPS5, ++ OPCODE_XSR_EPS5, ++ OPCODE_RSR_EPS6, ++ OPCODE_WSR_EPS6, ++ OPCODE_XSR_EPS6, ++ OPCODE_RSR_EPS7, ++ OPCODE_WSR_EPS7, ++ OPCODE_XSR_EPS7, ++ OPCODE_RSR_EXCVADDR, ++ OPCODE_WSR_EXCVADDR, ++ OPCODE_XSR_EXCVADDR, ++ OPCODE_RSR_DEPC, ++ OPCODE_WSR_DEPC, ++ OPCODE_XSR_DEPC, ++ OPCODE_RSR_EXCCAUSE, ++ OPCODE_WSR_EXCCAUSE, ++ OPCODE_XSR_EXCCAUSE, ++ OPCODE_RSR_MISC0, ++ OPCODE_WSR_MISC0, ++ OPCODE_XSR_MISC0, ++ OPCODE_RSR_MISC1, ++ OPCODE_WSR_MISC1, ++ OPCODE_XSR_MISC1, ++ OPCODE_RSR_PRID, ++ OPCODE_RSR_VECBASE, ++ OPCODE_WSR_VECBASE, ++ OPCODE_XSR_VECBASE, ++ OPCODE_RSR_MPUCFG, ++ OPCODE_WSR_MPUCFG, ++ OPCODE_SALT, ++ OPCODE_SALTU, ++ OPCODE_MUL16S, ++ OPCODE_MUL16U, ++ OPCODE_MULL, ++ OPCODE_RFI, ++ OPCODE_WAITI, ++ OPCODE_RSR_INTERRUPT, ++ OPCODE_WSR_INTSET, ++ OPCODE_WSR_INTCLEAR, ++ OPCODE_RSR_INTENABLE, ++ OPCODE_WSR_INTENABLE, ++ OPCODE_XSR_INTENABLE, ++ OPCODE_BREAK, ++ OPCODE_BREAK_N, ++ OPCODE_RSR_DBREAKA0, ++ OPCODE_WSR_DBREAKA0, ++ OPCODE_XSR_DBREAKA0, ++ OPCODE_RSR_DBREAKC0, ++ OPCODE_WSR_DBREAKC0, ++ OPCODE_XSR_DBREAKC0, ++ OPCODE_RSR_DBREAKA1, ++ OPCODE_WSR_DBREAKA1, ++ OPCODE_XSR_DBREAKA1, ++ OPCODE_RSR_DBREAKC1, ++ OPCODE_WSR_DBREAKC1, ++ OPCODE_XSR_DBREAKC1, ++ OPCODE_RSR_IBREAKA0, ++ OPCODE_WSR_IBREAKA0, ++ OPCODE_XSR_IBREAKA0, ++ OPCODE_RSR_IBREAKA1, ++ OPCODE_WSR_IBREAKA1, ++ OPCODE_XSR_IBREAKA1, ++ OPCODE_RSR_IBREAKENABLE, ++ OPCODE_WSR_IBREAKENABLE, ++ OPCODE_XSR_IBREAKENABLE, ++ OPCODE_RSR_DEBUGCAUSE, ++ OPCODE_WSR_DEBUGCAUSE, ++ OPCODE_XSR_DEBUGCAUSE, ++ OPCODE_RSR_ICOUNT, ++ OPCODE_WSR_ICOUNT, ++ OPCODE_XSR_ICOUNT, ++ OPCODE_RSR_ICOUNTLEVEL, ++ OPCODE_WSR_ICOUNTLEVEL, ++ OPCODE_XSR_ICOUNTLEVEL, ++ OPCODE_RSR_DDR, ++ OPCODE_WSR_DDR, ++ OPCODE_XSR_DDR, ++ OPCODE_LDDR32_P, ++ OPCODE_SDDR32_P, ++ OPCODE_RFDO, ++ OPCODE_RFDD, ++ OPCODE_WSR_MMID, ++ OPCODE_RSR_CCOUNT, ++ OPCODE_WSR_CCOUNT, ++ OPCODE_XSR_CCOUNT, ++ OPCODE_RSR_CCOMPARE0, ++ OPCODE_WSR_CCOMPARE0, ++ OPCODE_XSR_CCOMPARE0, ++ OPCODE_RSR_CCOMPARE1, ++ OPCODE_WSR_CCOMPARE1, ++ OPCODE_XSR_CCOMPARE1, ++ OPCODE_RSR_CCOMPARE2, ++ OPCODE_WSR_CCOMPARE2, ++ OPCODE_XSR_CCOMPARE2, ++ OPCODE_WSR_CACHEADRDIS, ++ OPCODE_RSR_CACHEADRDIS, ++ OPCODE_XSR_CACHEADRDIS, ++ OPCODE_RPTLB0, ++ OPCODE_PPTLB, ++ OPCODE_RPTLB1, ++ OPCODE_WPTLB, ++ OPCODE_RSR_MPUENB, ++ OPCODE_WSR_MPUENB, ++ OPCODE_XSR_MPUENB, ++ OPCODE_MAX, ++ OPCODE_MAXU, ++ OPCODE_MIN, ++ OPCODE_MINU, ++ OPCODE_NSA, ++ OPCODE_NSAU, ++ OPCODE_SEXT, ++ OPCODE_L32AI, ++ OPCODE_S32RI, ++ OPCODE_RSR_ATOMCTL, ++ OPCODE_WSR_ATOMCTL, ++ OPCODE_XSR_ATOMCTL, ++ OPCODE_QUOS, ++ OPCODE_QUOU, ++ OPCODE_REMS, ++ OPCODE_REMU, ++ OPCODE_RSR_ERACCESS, ++ OPCODE_WSR_ERACCESS, ++ OPCODE_XSR_ERACCESS, ++ OPCODE_RER, ++ OPCODE_WER, ++ OPCODE_READ_IMPWIRE, ++ OPCODE_SETB_EXPSTATE, ++ OPCODE_CLRB_EXPSTATE, ++ OPCODE_WRMSK_EXPSTATE, ++ OPCODE_RUR_EXPSTATE, ++ OPCODE_WUR_EXPSTATE ++}; ++ ++ ++/* Slot-specific opcode decode functions. */ ++ ++static int ++Slot_inst_decode (const xtensa_insnbuf insn) ++{ ++ if (Field_op0_Slot_inst_get (insn) == 0) ++ { ++ if (Field_op1_Slot_inst_get (insn) == 0) ++ { ++ if (Field_op2_Slot_inst_get (insn) == 0) ++ { ++ if (Field_r_Slot_inst_get (insn) == 0) ++ { ++ if (Field_m_Slot_inst_get (insn) == 0 && ++ Field_s_Slot_inst_get (insn) == 0 && ++ Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_ILL; ++ if (Field_m_Slot_inst_get (insn) == 2) ++ { ++ if (Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_RET; ++ if (Field_n_Slot_inst_get (insn) == 1) ++ return OPCODE_RETW; ++ if (Field_n_Slot_inst_get (insn) == 2) ++ return OPCODE_JX; ++ } ++ if (Field_m_Slot_inst_get (insn) == 3) ++ { ++ if (Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_CALLX0; ++ if (Field_n_Slot_inst_get (insn) == 1) ++ return OPCODE_CALLX4; ++ if (Field_n_Slot_inst_get (insn) == 2) ++ return OPCODE_CALLX8; ++ if (Field_n_Slot_inst_get (insn) == 3) ++ return OPCODE_CALLX12; ++ } ++ } ++ if (Field_r_Slot_inst_get (insn) == 1) ++ return OPCODE_MOVSP; ++ if (Field_r_Slot_inst_get (insn) == 2) ++ { ++ if (Field_s_Slot_inst_get (insn) == 0) ++ { ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_ISYNC; ++ if (Field_t_Slot_inst_get (insn) == 1) ++ return OPCODE_RSYNC; ++ if (Field_t_Slot_inst_get (insn) == 2) ++ return OPCODE_ESYNC; ++ if (Field_t_Slot_inst_get (insn) == 3) ++ return OPCODE_DSYNC; ++ if (Field_t_Slot_inst_get (insn) == 8) ++ return OPCODE_EXCW; ++ if (Field_t_Slot_inst_get (insn) == 12) ++ return OPCODE_MEMW; ++ if (Field_t_Slot_inst_get (insn) == 13) ++ return OPCODE_EXTW; ++ if (Field_t_Slot_inst_get (insn) == 15) ++ return OPCODE_NOP; ++ } ++ } ++ if (Field_r_Slot_inst_get (insn) == 3) ++ { ++ if (Field_t_Slot_inst_get (insn) == 0) ++ { ++ if (Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_RFE; ++ if (Field_s_Slot_inst_get (insn) == 2) ++ return OPCODE_RFDE; ++ if (Field_s_Slot_inst_get (insn) == 4) ++ return OPCODE_RFWO; ++ if (Field_s_Slot_inst_get (insn) == 5) ++ return OPCODE_RFWU; ++ } ++ if (Field_t_Slot_inst_get (insn) == 1) ++ return OPCODE_RFI; ++ if (Field_t_Slot_inst_get (insn) == 2 && ++ Field_s_Slot_inst_get (insn) == 1) ++ return OPCODE_CLREX; ++ } ++ if (Field_r_Slot_inst_get (insn) == 4) ++ return OPCODE_BREAK; ++ if (Field_r_Slot_inst_get (insn) == 5) ++ { ++ if (Field_s_Slot_inst_get (insn) == 0 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SYSCALL; ++ if (Field_s_Slot_inst_get (insn) == 1) ++ return OPCODE_SIMCALL; ++ } ++ if (Field_r_Slot_inst_get (insn) == 6) ++ return OPCODE_RSIL; ++ if (Field_r_Slot_inst_get (insn) == 7 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_WAITI; ++ if (Field_r_Slot_inst_get (insn) == 7) ++ { ++ if (Field_t_Slot_inst_get (insn) == 14) ++ return OPCODE_LDDR32_P; ++ if (Field_t_Slot_inst_get (insn) == 15) ++ return OPCODE_SDDR32_P; ++ } ++ } ++ if (Field_op2_Slot_inst_get (insn) == 1) ++ return OPCODE_AND; ++ if (Field_op2_Slot_inst_get (insn) == 2) ++ return OPCODE_OR; ++ if (Field_op2_Slot_inst_get (insn) == 3) ++ return OPCODE_XOR; ++ if (Field_op2_Slot_inst_get (insn) == 4) ++ { ++ if (Field_r_Slot_inst_get (insn) == 0 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSR; ++ if (Field_r_Slot_inst_get (insn) == 1 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSL; ++ if (Field_r_Slot_inst_get (insn) == 2 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSA8L; ++ if (Field_r_Slot_inst_get (insn) == 3 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSA8B; ++ if (Field_r_Slot_inst_get (insn) == 4 && ++ Field_thi3_Slot_inst_get (insn) == 0) ++ return OPCODE_SSAI; ++ if (Field_r_Slot_inst_get (insn) == 6) ++ return OPCODE_RER; ++ if (Field_r_Slot_inst_get (insn) == 7) ++ return OPCODE_WER; ++ if (Field_r_Slot_inst_get (insn) == 8 && ++ Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_ROTW; ++ if (Field_r_Slot_inst_get (insn) == 10 && ++ Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_GETEX; ++ if (Field_r_Slot_inst_get (insn) == 14) ++ return OPCODE_NSA; ++ if (Field_r_Slot_inst_get (insn) == 15) ++ return OPCODE_NSAU; ++ } ++ if (Field_op2_Slot_inst_get (insn) == 5) ++ { ++ if (Field_r_Slot_inst_get (insn) == 11) ++ return OPCODE_RPTLB0; ++ if (Field_r_Slot_inst_get (insn) == 13) ++ return OPCODE_PPTLB; ++ if (Field_r_Slot_inst_get (insn) == 14) ++ return OPCODE_WPTLB; ++ if (Field_r_Slot_inst_get (insn) == 15) ++ return OPCODE_RPTLB1; ++ } ++ if (Field_op2_Slot_inst_get (insn) == 6) ++ { ++ if (Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_NEG; ++ if (Field_s_Slot_inst_get (insn) == 1) ++ return OPCODE_ABS; ++ } ++ if (Field_op2_Slot_inst_get (insn) == 8) ++ return OPCODE_ADD; ++ if (Field_op2_Slot_inst_get (insn) == 9) ++ return OPCODE_ADDX2; ++ if (Field_op2_Slot_inst_get (insn) == 10) ++ return OPCODE_ADDX4; ++ if (Field_op2_Slot_inst_get (insn) == 11) ++ return OPCODE_ADDX8; ++ if (Field_op2_Slot_inst_get (insn) == 12) ++ return OPCODE_SUB; ++ if (Field_op2_Slot_inst_get (insn) == 13) ++ return OPCODE_SUBX2; ++ if (Field_op2_Slot_inst_get (insn) == 14) ++ return OPCODE_SUBX4; ++ if (Field_op2_Slot_inst_get (insn) == 15) ++ return OPCODE_SUBX8; ++ } ++ if (Field_op1_Slot_inst_get (insn) == 1) ++ { ++ if ((Field_op2_Slot_inst_get (insn) == 0 || ++ Field_op2_Slot_inst_get (insn) == 1)) ++ return OPCODE_SLLI; ++ if ((Field_op2_Slot_inst_get (insn) == 2 || ++ Field_op2_Slot_inst_get (insn) == 3)) ++ return OPCODE_SRAI; ++ if (Field_op2_Slot_inst_get (insn) == 4) ++ return OPCODE_SRLI; ++ if (Field_op2_Slot_inst_get (insn) == 6) ++ { ++ if (Field_sr_Slot_inst_get (insn) == 3) ++ return OPCODE_XSR_SAR; ++ if (Field_sr_Slot_inst_get (insn) == 72) ++ return OPCODE_XSR_WINDOWBASE; ++ if (Field_sr_Slot_inst_get (insn) == 73) ++ return OPCODE_XSR_WINDOWSTART; ++ if (Field_sr_Slot_inst_get (insn) == 90) ++ return OPCODE_XSR_MPUENB; ++ if (Field_sr_Slot_inst_get (insn) == 95) ++ return OPCODE_XSR_ERACCESS; ++ if (Field_sr_Slot_inst_get (insn) == 96) ++ return OPCODE_XSR_IBREAKENABLE; ++ if (Field_sr_Slot_inst_get (insn) == 97) ++ return OPCODE_XSR_MEMCTL; ++ if (Field_sr_Slot_inst_get (insn) == 98) ++ return OPCODE_XSR_CACHEADRDIS; ++ if (Field_sr_Slot_inst_get (insn) == 99) ++ return OPCODE_XSR_ATOMCTL; ++ if (Field_sr_Slot_inst_get (insn) == 104) ++ return OPCODE_XSR_DDR; ++ if (Field_sr_Slot_inst_get (insn) == 128) ++ return OPCODE_XSR_IBREAKA0; ++ if (Field_sr_Slot_inst_get (insn) == 129) ++ return OPCODE_XSR_IBREAKA1; ++ if (Field_sr_Slot_inst_get (insn) == 144) ++ return OPCODE_XSR_DBREAKA0; ++ if (Field_sr_Slot_inst_get (insn) == 145) ++ return OPCODE_XSR_DBREAKA1; ++ if (Field_sr_Slot_inst_get (insn) == 160) ++ return OPCODE_XSR_DBREAKC0; ++ if (Field_sr_Slot_inst_get (insn) == 161) ++ return OPCODE_XSR_DBREAKC1; ++ if (Field_sr_Slot_inst_get (insn) == 177) ++ return OPCODE_XSR_EPC1; ++ if (Field_sr_Slot_inst_get (insn) == 178) ++ return OPCODE_XSR_EPC2; ++ if (Field_sr_Slot_inst_get (insn) == 179) ++ return OPCODE_XSR_EPC3; ++ if (Field_sr_Slot_inst_get (insn) == 180) ++ return OPCODE_XSR_EPC4; ++ if (Field_sr_Slot_inst_get (insn) == 181) ++ return OPCODE_XSR_EPC5; ++ if (Field_sr_Slot_inst_get (insn) == 182) ++ return OPCODE_XSR_EPC6; ++ if (Field_sr_Slot_inst_get (insn) == 183) ++ return OPCODE_XSR_EPC7; ++ if (Field_sr_Slot_inst_get (insn) == 192) ++ return OPCODE_XSR_DEPC; ++ if (Field_sr_Slot_inst_get (insn) == 194) ++ return OPCODE_XSR_EPS2; ++ if (Field_sr_Slot_inst_get (insn) == 195) ++ return OPCODE_XSR_EPS3; ++ if (Field_sr_Slot_inst_get (insn) == 196) ++ return OPCODE_XSR_EPS4; ++ if (Field_sr_Slot_inst_get (insn) == 197) ++ return OPCODE_XSR_EPS5; ++ if (Field_sr_Slot_inst_get (insn) == 198) ++ return OPCODE_XSR_EPS6; ++ if (Field_sr_Slot_inst_get (insn) == 199) ++ return OPCODE_XSR_EPS7; ++ if (Field_sr_Slot_inst_get (insn) == 209) ++ return OPCODE_XSR_EXCSAVE1; ++ if (Field_sr_Slot_inst_get (insn) == 210) ++ return OPCODE_XSR_EXCSAVE2; ++ if (Field_sr_Slot_inst_get (insn) == 211) ++ return OPCODE_XSR_EXCSAVE3; ++ if (Field_sr_Slot_inst_get (insn) == 212) ++ return OPCODE_XSR_EXCSAVE4; ++ if (Field_sr_Slot_inst_get (insn) == 213) ++ return OPCODE_XSR_EXCSAVE5; ++ if (Field_sr_Slot_inst_get (insn) == 214) ++ return OPCODE_XSR_EXCSAVE6; ++ if (Field_sr_Slot_inst_get (insn) == 215) ++ return OPCODE_XSR_EXCSAVE7; ++ if (Field_sr_Slot_inst_get (insn) == 228) ++ return OPCODE_XSR_INTENABLE; ++ if (Field_sr_Slot_inst_get (insn) == 230) ++ return OPCODE_XSR_PS; ++ if (Field_sr_Slot_inst_get (insn) == 231) ++ return OPCODE_XSR_VECBASE; ++ if (Field_sr_Slot_inst_get (insn) == 232) ++ return OPCODE_XSR_EXCCAUSE; ++ if (Field_sr_Slot_inst_get (insn) == 233) ++ return OPCODE_XSR_DEBUGCAUSE; ++ if (Field_sr_Slot_inst_get (insn) == 234) ++ return OPCODE_XSR_CCOUNT; ++ if (Field_sr_Slot_inst_get (insn) == 236) ++ return OPCODE_XSR_ICOUNT; ++ if (Field_sr_Slot_inst_get (insn) == 237) ++ return OPCODE_XSR_ICOUNTLEVEL; ++ if (Field_sr_Slot_inst_get (insn) == 238) ++ return OPCODE_XSR_EXCVADDR; ++ if (Field_sr_Slot_inst_get (insn) == 240) ++ return OPCODE_XSR_CCOMPARE0; ++ if (Field_sr_Slot_inst_get (insn) == 241) ++ return OPCODE_XSR_CCOMPARE1; ++ if (Field_sr_Slot_inst_get (insn) == 242) ++ return OPCODE_XSR_CCOMPARE2; ++ if (Field_sr_Slot_inst_get (insn) == 244) ++ return OPCODE_XSR_MISC0; ++ if (Field_sr_Slot_inst_get (insn) == 245) ++ return OPCODE_XSR_MISC1; ++ } ++ if (Field_op2_Slot_inst_get (insn) == 8) ++ return OPCODE_SRC; ++ if (Field_op2_Slot_inst_get (insn) == 9 && ++ Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_SRL; ++ if (Field_op2_Slot_inst_get (insn) == 10 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SLL; ++ if (Field_op2_Slot_inst_get (insn) == 11 && ++ Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_SRA; ++ if (Field_op2_Slot_inst_get (insn) == 12) ++ return OPCODE_MUL16U; ++ if (Field_op2_Slot_inst_get (insn) == 13) ++ return OPCODE_MUL16S; ++ if (Field_op2_Slot_inst_get (insn) == 15) ++ { ++ if (Field_r_Slot_inst_get (insn) == 4) ++ return OPCODE_L32EX; ++ if (Field_r_Slot_inst_get (insn) == 5) ++ return OPCODE_S32EX; ++ if (Field_r_Slot_inst_get (insn) == 14 && ++ Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_RFDO; ++ if (Field_r_Slot_inst_get (insn) == 14 && ++ Field_t_Slot_inst_get (insn) == 1) ++ return OPCODE_RFDD; ++ } ++ } ++ if (Field_op1_Slot_inst_get (insn) == 2) ++ { ++ if (Field_op2_Slot_inst_get (insn) == 6) ++ return OPCODE_SALTU; ++ if (Field_op2_Slot_inst_get (insn) == 7) ++ return OPCODE_SALT; ++ if (Field_op2_Slot_inst_get (insn) == 8) ++ return OPCODE_MULL; ++ if (Field_op2_Slot_inst_get (insn) == 12) ++ return OPCODE_QUOU; ++ if (Field_op2_Slot_inst_get (insn) == 13) ++ return OPCODE_QUOS; ++ if (Field_op2_Slot_inst_get (insn) == 14) ++ return OPCODE_REMU; ++ if (Field_op2_Slot_inst_get (insn) == 15) ++ return OPCODE_REMS; ++ } ++ if (Field_op1_Slot_inst_get (insn) == 3) ++ { ++ if (Field_op2_Slot_inst_get (insn) == 0) ++ { ++ if (Field_sr_Slot_inst_get (insn) == 3) ++ return OPCODE_RSR_SAR; ++ if (Field_sr_Slot_inst_get (insn) == 72) ++ return OPCODE_RSR_WINDOWBASE; ++ if (Field_sr_Slot_inst_get (insn) == 73) ++ return OPCODE_RSR_WINDOWSTART; ++ if (Field_sr_Slot_inst_get (insn) == 90) ++ return OPCODE_RSR_MPUENB; ++ if (Field_sr_Slot_inst_get (insn) == 92) ++ return OPCODE_RSR_MPUCFG; ++ if (Field_sr_Slot_inst_get (insn) == 95) ++ return OPCODE_RSR_ERACCESS; ++ if (Field_sr_Slot_inst_get (insn) == 96) ++ return OPCODE_RSR_IBREAKENABLE; ++ if (Field_sr_Slot_inst_get (insn) == 97) ++ return OPCODE_RSR_MEMCTL; ++ if (Field_sr_Slot_inst_get (insn) == 98) ++ return OPCODE_RSR_CACHEADRDIS; ++ if (Field_sr_Slot_inst_get (insn) == 99) ++ return OPCODE_RSR_ATOMCTL; ++ if (Field_sr_Slot_inst_get (insn) == 104) ++ return OPCODE_RSR_DDR; ++ if (Field_sr_Slot_inst_get (insn) == 128) ++ return OPCODE_RSR_IBREAKA0; ++ if (Field_sr_Slot_inst_get (insn) == 129) ++ return OPCODE_RSR_IBREAKA1; ++ if (Field_sr_Slot_inst_get (insn) == 144) ++ return OPCODE_RSR_DBREAKA0; ++ if (Field_sr_Slot_inst_get (insn) == 145) ++ return OPCODE_RSR_DBREAKA1; ++ if (Field_sr_Slot_inst_get (insn) == 160) ++ return OPCODE_RSR_DBREAKC0; ++ if (Field_sr_Slot_inst_get (insn) == 161) ++ return OPCODE_RSR_DBREAKC1; ++ if (Field_sr_Slot_inst_get (insn) == 176) ++ return OPCODE_RSR_CONFIGID0; ++ if (Field_sr_Slot_inst_get (insn) == 177) ++ return OPCODE_RSR_EPC1; ++ if (Field_sr_Slot_inst_get (insn) == 178) ++ return OPCODE_RSR_EPC2; ++ if (Field_sr_Slot_inst_get (insn) == 179) ++ return OPCODE_RSR_EPC3; ++ if (Field_sr_Slot_inst_get (insn) == 180) ++ return OPCODE_RSR_EPC4; ++ if (Field_sr_Slot_inst_get (insn) == 181) ++ return OPCODE_RSR_EPC5; ++ if (Field_sr_Slot_inst_get (insn) == 182) ++ return OPCODE_RSR_EPC6; ++ if (Field_sr_Slot_inst_get (insn) == 183) ++ return OPCODE_RSR_EPC7; ++ if (Field_sr_Slot_inst_get (insn) == 192) ++ return OPCODE_RSR_DEPC; ++ if (Field_sr_Slot_inst_get (insn) == 194) ++ return OPCODE_RSR_EPS2; ++ if (Field_sr_Slot_inst_get (insn) == 195) ++ return OPCODE_RSR_EPS3; ++ if (Field_sr_Slot_inst_get (insn) == 196) ++ return OPCODE_RSR_EPS4; ++ if (Field_sr_Slot_inst_get (insn) == 197) ++ return OPCODE_RSR_EPS5; ++ if (Field_sr_Slot_inst_get (insn) == 198) ++ return OPCODE_RSR_EPS6; ++ if (Field_sr_Slot_inst_get (insn) == 199) ++ return OPCODE_RSR_EPS7; ++ if (Field_sr_Slot_inst_get (insn) == 208) ++ return OPCODE_RSR_CONFIGID1; ++ if (Field_sr_Slot_inst_get (insn) == 209) ++ return OPCODE_RSR_EXCSAVE1; ++ if (Field_sr_Slot_inst_get (insn) == 210) ++ return OPCODE_RSR_EXCSAVE2; ++ if (Field_sr_Slot_inst_get (insn) == 211) ++ return OPCODE_RSR_EXCSAVE3; ++ if (Field_sr_Slot_inst_get (insn) == 212) ++ return OPCODE_RSR_EXCSAVE4; ++ if (Field_sr_Slot_inst_get (insn) == 213) ++ return OPCODE_RSR_EXCSAVE5; ++ if (Field_sr_Slot_inst_get (insn) == 214) ++ return OPCODE_RSR_EXCSAVE6; ++ if (Field_sr_Slot_inst_get (insn) == 215) ++ return OPCODE_RSR_EXCSAVE7; ++ if (Field_sr_Slot_inst_get (insn) == 226) ++ return OPCODE_RSR_INTERRUPT; ++ if (Field_sr_Slot_inst_get (insn) == 228) ++ return OPCODE_RSR_INTENABLE; ++ if (Field_sr_Slot_inst_get (insn) == 230) ++ return OPCODE_RSR_PS; ++ if (Field_sr_Slot_inst_get (insn) == 231) ++ return OPCODE_RSR_VECBASE; ++ if (Field_sr_Slot_inst_get (insn) == 232) ++ return OPCODE_RSR_EXCCAUSE; ++ if (Field_sr_Slot_inst_get (insn) == 233) ++ return OPCODE_RSR_DEBUGCAUSE; ++ if (Field_sr_Slot_inst_get (insn) == 234) ++ return OPCODE_RSR_CCOUNT; ++ if (Field_sr_Slot_inst_get (insn) == 235) ++ return OPCODE_RSR_PRID; ++ if (Field_sr_Slot_inst_get (insn) == 236) ++ return OPCODE_RSR_ICOUNT; ++ if (Field_sr_Slot_inst_get (insn) == 237) ++ return OPCODE_RSR_ICOUNTLEVEL; ++ if (Field_sr_Slot_inst_get (insn) == 238) ++ return OPCODE_RSR_EXCVADDR; ++ if (Field_sr_Slot_inst_get (insn) == 240) ++ return OPCODE_RSR_CCOMPARE0; ++ if (Field_sr_Slot_inst_get (insn) == 241) ++ return OPCODE_RSR_CCOMPARE1; ++ if (Field_sr_Slot_inst_get (insn) == 242) ++ return OPCODE_RSR_CCOMPARE2; ++ if (Field_sr_Slot_inst_get (insn) == 244) ++ return OPCODE_RSR_MISC0; ++ if (Field_sr_Slot_inst_get (insn) == 245) ++ return OPCODE_RSR_MISC1; ++ } ++ if (Field_op2_Slot_inst_get (insn) == 1) ++ { ++ if (Field_sr_Slot_inst_get (insn) == 3) ++ return OPCODE_WSR_SAR; ++ if (Field_sr_Slot_inst_get (insn) == 72) ++ return OPCODE_WSR_WINDOWBASE; ++ if (Field_sr_Slot_inst_get (insn) == 73) ++ return OPCODE_WSR_WINDOWSTART; ++ if (Field_sr_Slot_inst_get (insn) == 89) ++ return OPCODE_WSR_MMID; ++ if (Field_sr_Slot_inst_get (insn) == 90) ++ return OPCODE_WSR_MPUENB; ++ if (Field_sr_Slot_inst_get (insn) == 92) ++ return OPCODE_WSR_MPUCFG; ++ if (Field_sr_Slot_inst_get (insn) == 95) ++ return OPCODE_WSR_ERACCESS; ++ if (Field_sr_Slot_inst_get (insn) == 96) ++ return OPCODE_WSR_IBREAKENABLE; ++ if (Field_sr_Slot_inst_get (insn) == 97) ++ return OPCODE_WSR_MEMCTL; ++ if (Field_sr_Slot_inst_get (insn) == 98) ++ return OPCODE_WSR_CACHEADRDIS; ++ if (Field_sr_Slot_inst_get (insn) == 99) ++ return OPCODE_WSR_ATOMCTL; ++ if (Field_sr_Slot_inst_get (insn) == 104) ++ return OPCODE_WSR_DDR; ++ if (Field_sr_Slot_inst_get (insn) == 128) ++ return OPCODE_WSR_IBREAKA0; ++ if (Field_sr_Slot_inst_get (insn) == 129) ++ return OPCODE_WSR_IBREAKA1; ++ if (Field_sr_Slot_inst_get (insn) == 144) ++ return OPCODE_WSR_DBREAKA0; ++ if (Field_sr_Slot_inst_get (insn) == 145) ++ return OPCODE_WSR_DBREAKA1; ++ if (Field_sr_Slot_inst_get (insn) == 160) ++ return OPCODE_WSR_DBREAKC0; ++ if (Field_sr_Slot_inst_get (insn) == 161) ++ return OPCODE_WSR_DBREAKC1; ++ if (Field_sr_Slot_inst_get (insn) == 176) ++ return OPCODE_WSR_CONFIGID0; ++ if (Field_sr_Slot_inst_get (insn) == 177) ++ return OPCODE_WSR_EPC1; ++ if (Field_sr_Slot_inst_get (insn) == 178) ++ return OPCODE_WSR_EPC2; ++ if (Field_sr_Slot_inst_get (insn) == 179) ++ return OPCODE_WSR_EPC3; ++ if (Field_sr_Slot_inst_get (insn) == 180) ++ return OPCODE_WSR_EPC4; ++ if (Field_sr_Slot_inst_get (insn) == 181) ++ return OPCODE_WSR_EPC5; ++ if (Field_sr_Slot_inst_get (insn) == 182) ++ return OPCODE_WSR_EPC6; ++ if (Field_sr_Slot_inst_get (insn) == 183) ++ return OPCODE_WSR_EPC7; ++ if (Field_sr_Slot_inst_get (insn) == 192) ++ return OPCODE_WSR_DEPC; ++ if (Field_sr_Slot_inst_get (insn) == 194) ++ return OPCODE_WSR_EPS2; ++ if (Field_sr_Slot_inst_get (insn) == 195) ++ return OPCODE_WSR_EPS3; ++ if (Field_sr_Slot_inst_get (insn) == 196) ++ return OPCODE_WSR_EPS4; ++ if (Field_sr_Slot_inst_get (insn) == 197) ++ return OPCODE_WSR_EPS5; ++ if (Field_sr_Slot_inst_get (insn) == 198) ++ return OPCODE_WSR_EPS6; ++ if (Field_sr_Slot_inst_get (insn) == 199) ++ return OPCODE_WSR_EPS7; ++ if (Field_sr_Slot_inst_get (insn) == 209) ++ return OPCODE_WSR_EXCSAVE1; ++ if (Field_sr_Slot_inst_get (insn) == 210) ++ return OPCODE_WSR_EXCSAVE2; ++ if (Field_sr_Slot_inst_get (insn) == 211) ++ return OPCODE_WSR_EXCSAVE3; ++ if (Field_sr_Slot_inst_get (insn) == 212) ++ return OPCODE_WSR_EXCSAVE4; ++ if (Field_sr_Slot_inst_get (insn) == 213) ++ return OPCODE_WSR_EXCSAVE5; ++ if (Field_sr_Slot_inst_get (insn) == 214) ++ return OPCODE_WSR_EXCSAVE6; ++ if (Field_sr_Slot_inst_get (insn) == 215) ++ return OPCODE_WSR_EXCSAVE7; ++ if (Field_sr_Slot_inst_get (insn) == 226) ++ return OPCODE_WSR_INTSET; ++ if (Field_sr_Slot_inst_get (insn) == 227) ++ return OPCODE_WSR_INTCLEAR; ++ if (Field_sr_Slot_inst_get (insn) == 228) ++ return OPCODE_WSR_INTENABLE; ++ if (Field_sr_Slot_inst_get (insn) == 230) ++ return OPCODE_WSR_PS; ++ if (Field_sr_Slot_inst_get (insn) == 231) ++ return OPCODE_WSR_VECBASE; ++ if (Field_sr_Slot_inst_get (insn) == 232) ++ return OPCODE_WSR_EXCCAUSE; ++ if (Field_sr_Slot_inst_get (insn) == 233) ++ return OPCODE_WSR_DEBUGCAUSE; ++ if (Field_sr_Slot_inst_get (insn) == 234) ++ return OPCODE_WSR_CCOUNT; ++ if (Field_sr_Slot_inst_get (insn) == 236) ++ return OPCODE_WSR_ICOUNT; ++ if (Field_sr_Slot_inst_get (insn) == 237) ++ return OPCODE_WSR_ICOUNTLEVEL; ++ if (Field_sr_Slot_inst_get (insn) == 238) ++ return OPCODE_WSR_EXCVADDR; ++ if (Field_sr_Slot_inst_get (insn) == 240) ++ return OPCODE_WSR_CCOMPARE0; ++ if (Field_sr_Slot_inst_get (insn) == 241) ++ return OPCODE_WSR_CCOMPARE1; ++ if (Field_sr_Slot_inst_get (insn) == 242) ++ return OPCODE_WSR_CCOMPARE2; ++ if (Field_sr_Slot_inst_get (insn) == 244) ++ return OPCODE_WSR_MISC0; ++ if (Field_sr_Slot_inst_get (insn) == 245) ++ return OPCODE_WSR_MISC1; ++ } ++ if (Field_op2_Slot_inst_get (insn) == 2) ++ return OPCODE_SEXT; ++ if (Field_op2_Slot_inst_get (insn) == 4) ++ return OPCODE_MIN; ++ if (Field_op2_Slot_inst_get (insn) == 5) ++ return OPCODE_MAX; ++ if (Field_op2_Slot_inst_get (insn) == 6) ++ return OPCODE_MINU; ++ if (Field_op2_Slot_inst_get (insn) == 7) ++ return OPCODE_MAXU; ++ if (Field_op2_Slot_inst_get (insn) == 8) ++ return OPCODE_MOVEQZ; ++ if (Field_op2_Slot_inst_get (insn) == 9) ++ return OPCODE_MOVNEZ; ++ if (Field_op2_Slot_inst_get (insn) == 10) ++ return OPCODE_MOVLTZ; ++ if (Field_op2_Slot_inst_get (insn) == 11) ++ return OPCODE_MOVGEZ; ++ if (Field_op2_Slot_inst_get (insn) == 14) ++ { ++ if (Field_st_Slot_inst_get (insn) == 230) ++ return OPCODE_RUR_EXPSTATE; ++ } ++ if (Field_op2_Slot_inst_get (insn) == 15) ++ { ++ if (Field_sr_Slot_inst_get (insn) == 230) ++ return OPCODE_WUR_EXPSTATE; ++ } ++ } ++ if ((Field_op1_Slot_inst_get (insn) == 4 || ++ Field_op1_Slot_inst_get (insn) == 5)) ++ return OPCODE_EXTUI; ++ if (Field_op1_Slot_inst_get (insn) == 9) ++ { ++ if (Field_op2_Slot_inst_get (insn) == 0) ++ return OPCODE_L32E; ++ if (Field_op2_Slot_inst_get (insn) == 4) ++ return OPCODE_S32E; ++ if (Field_op2_Slot_inst_get (insn) == 5) ++ return OPCODE_S32NB; ++ } ++ if (Field_r_Slot_inst_get (insn) == 0 && ++ Field_s_Slot_inst_get (insn) == 0 && ++ Field_op2_Slot_inst_get (insn) == 0 && ++ Field_op1_Slot_inst_get (insn) == 14) ++ return OPCODE_READ_IMPWIRE; ++ if (Field_r_Slot_inst_get (insn) == 1 && ++ Field_s3to1_Slot_inst_get (insn) == 0 && ++ Field_op2_Slot_inst_get (insn) == 0 && ++ Field_op1_Slot_inst_get (insn) == 14) ++ return OPCODE_SETB_EXPSTATE; ++ if (Field_r_Slot_inst_get (insn) == 1 && ++ Field_s3to1_Slot_inst_get (insn) == 1 && ++ Field_op2_Slot_inst_get (insn) == 0 && ++ Field_op1_Slot_inst_get (insn) == 14) ++ return OPCODE_CLRB_EXPSTATE; ++ if (Field_r_Slot_inst_get (insn) == 2 && ++ Field_op2_Slot_inst_get (insn) == 0 && ++ Field_op1_Slot_inst_get (insn) == 14) ++ return OPCODE_WRMSK_EXPSTATE; ++ } ++ if (Field_op0_Slot_inst_get (insn) == 1) ++ return OPCODE_L32R; ++ if (Field_op0_Slot_inst_get (insn) == 2) ++ { ++ if (Field_r_Slot_inst_get (insn) == 0) ++ return OPCODE_L8UI; ++ if (Field_r_Slot_inst_get (insn) == 1) ++ return OPCODE_L16UI; ++ if (Field_r_Slot_inst_get (insn) == 2) ++ return OPCODE_L32I; ++ if (Field_r_Slot_inst_get (insn) == 4) ++ return OPCODE_S8I; ++ if (Field_r_Slot_inst_get (insn) == 5) ++ return OPCODE_S16I; ++ if (Field_r_Slot_inst_get (insn) == 6) ++ return OPCODE_S32I; ++ if (Field_r_Slot_inst_get (insn) == 9) ++ return OPCODE_L16SI; ++ if (Field_r_Slot_inst_get (insn) == 10) ++ return OPCODE_MOVI; ++ if (Field_r_Slot_inst_get (insn) == 11) ++ return OPCODE_L32AI; ++ if (Field_r_Slot_inst_get (insn) == 12) ++ return OPCODE_ADDI; ++ if (Field_r_Slot_inst_get (insn) == 13) ++ return OPCODE_ADDMI; ++ if (Field_r_Slot_inst_get (insn) == 15) ++ return OPCODE_S32RI; ++ } ++ if (Field_op0_Slot_inst_get (insn) == 5) ++ { ++ if (Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_CALL0; ++ if (Field_n_Slot_inst_get (insn) == 1) ++ return OPCODE_CALL4; ++ if (Field_n_Slot_inst_get (insn) == 2) ++ return OPCODE_CALL8; ++ if (Field_n_Slot_inst_get (insn) == 3) ++ return OPCODE_CALL12; ++ } ++ if (Field_op0_Slot_inst_get (insn) == 6) ++ { ++ if (Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_J; ++ if (Field_n_Slot_inst_get (insn) == 1) ++ { ++ if (Field_m_Slot_inst_get (insn) == 0) ++ return OPCODE_BEQZ; ++ if (Field_m_Slot_inst_get (insn) == 1) ++ return OPCODE_BNEZ; ++ if (Field_m_Slot_inst_get (insn) == 2) ++ return OPCODE_BLTZ; ++ if (Field_m_Slot_inst_get (insn) == 3) ++ return OPCODE_BGEZ; ++ } ++ if (Field_n_Slot_inst_get (insn) == 2) ++ { ++ if (Field_m_Slot_inst_get (insn) == 0) ++ return OPCODE_BEQI; ++ if (Field_m_Slot_inst_get (insn) == 1) ++ return OPCODE_BNEI; ++ if (Field_m_Slot_inst_get (insn) == 2) ++ return OPCODE_BLTI; ++ if (Field_m_Slot_inst_get (insn) == 3) ++ return OPCODE_BGEI; ++ } ++ if (Field_n_Slot_inst_get (insn) == 3) ++ { ++ if (Field_m_Slot_inst_get (insn) == 0) ++ return OPCODE_ENTRY; ++ if (Field_m_Slot_inst_get (insn) == 2) ++ return OPCODE_BLTUI; ++ if (Field_m_Slot_inst_get (insn) == 3) ++ return OPCODE_BGEUI; ++ } ++ } ++ if (Field_op0_Slot_inst_get (insn) == 7) ++ { ++ if (Field_r_Slot_inst_get (insn) == 0) ++ return OPCODE_BNONE; ++ if (Field_r_Slot_inst_get (insn) == 1) ++ return OPCODE_BEQ; ++ if (Field_r_Slot_inst_get (insn) == 2) ++ return OPCODE_BLT; ++ if (Field_r_Slot_inst_get (insn) == 3) ++ return OPCODE_BLTU; ++ if (Field_r_Slot_inst_get (insn) == 4) ++ return OPCODE_BALL; ++ if (Field_r_Slot_inst_get (insn) == 5) ++ return OPCODE_BBC; ++ if ((Field_r_Slot_inst_get (insn) == 6 || ++ Field_r_Slot_inst_get (insn) == 7)) ++ return OPCODE_BBCI; ++ if (Field_r_Slot_inst_get (insn) == 8) ++ return OPCODE_BANY; ++ if (Field_r_Slot_inst_get (insn) == 9) ++ return OPCODE_BNE; ++ if (Field_r_Slot_inst_get (insn) == 10) ++ return OPCODE_BGE; ++ if (Field_r_Slot_inst_get (insn) == 11) ++ return OPCODE_BGEU; ++ if (Field_r_Slot_inst_get (insn) == 12) ++ return OPCODE_BNALL; ++ if (Field_r_Slot_inst_get (insn) == 13) ++ return OPCODE_BBS; ++ if ((Field_r_Slot_inst_get (insn) == 14 || ++ Field_r_Slot_inst_get (insn) == 15)) ++ return OPCODE_BBSI; ++ } ++ return XTENSA_UNDEFINED; ++} ++ ++static int ++Slot_inst16b_decode (const xtensa_insnbuf insn) ++{ ++ if (Field_op0_Slot_inst16b_get (insn) == 12) ++ { ++ if (Field_i_Slot_inst16b_get (insn) == 0) ++ return OPCODE_MOVI_N; ++ if (Field_i_Slot_inst16b_get (insn) == 1) ++ { ++ if (Field_z_Slot_inst16b_get (insn) == 0) ++ return OPCODE_BEQZ_N; ++ if (Field_z_Slot_inst16b_get (insn) == 1) ++ return OPCODE_BNEZ_N; ++ } ++ } ++ if (Field_op0_Slot_inst16b_get (insn) == 13) ++ { ++ if (Field_r_Slot_inst16b_get (insn) == 0) ++ return OPCODE_MOV_N; ++ if (Field_r_Slot_inst16b_get (insn) == 15) ++ { ++ if (Field_t_Slot_inst16b_get (insn) == 0) ++ return OPCODE_RET_N; ++ if (Field_t_Slot_inst16b_get (insn) == 1) ++ return OPCODE_RETW_N; ++ if (Field_t_Slot_inst16b_get (insn) == 2) ++ return OPCODE_BREAK_N; ++ if (Field_t_Slot_inst16b_get (insn) == 3 && ++ Field_s_Slot_inst16b_get (insn) == 0) ++ return OPCODE_NOP_N; ++ if (Field_t_Slot_inst16b_get (insn) == 6 && ++ Field_s_Slot_inst16b_get (insn) == 0) ++ return OPCODE_ILL_N; ++ } ++ } ++ return XTENSA_UNDEFINED; ++} ++ ++static int ++Slot_inst16a_decode (const xtensa_insnbuf insn) ++{ ++ if (Field_op0_Slot_inst16a_get (insn) == 8) ++ return OPCODE_L32I_N; ++ if (Field_op0_Slot_inst16a_get (insn) == 9) ++ return OPCODE_S32I_N; ++ if (Field_op0_Slot_inst16a_get (insn) == 10) ++ return OPCODE_ADD_N; ++ if (Field_op0_Slot_inst16a_get (insn) == 11) ++ return OPCODE_ADDI_N; ++ return XTENSA_UNDEFINED; ++} ++ ++ ++/* Instruction slots. */ ++ ++static void ++Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, ++ xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = (insn[0] & 0xffffff); ++} ++ ++static void ++Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, ++ const xtensa_insnbuf slotbuf) ++{ ++ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); ++} ++ ++static void ++Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, ++ xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = (insn[0] & 0xffff); ++} ++ ++static void ++Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, ++ const xtensa_insnbuf slotbuf) ++{ ++ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); ++} ++ ++static void ++Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, ++ xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = (insn[0] & 0xffff); ++} ++ ++static void ++Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, ++ const xtensa_insnbuf slotbuf) ++{ ++ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); ++} ++ ++static xtensa_get_field_fn ++Slot_inst_get_field_fns[] = { ++ Field_t_Slot_inst_get, ++ Field_bbi4_Slot_inst_get, ++ Field_bbi_Slot_inst_get, ++ Field_imm12_Slot_inst_get, ++ Field_imm8_Slot_inst_get, ++ Field_s_Slot_inst_get, ++ Field_s8_Slot_inst_get, ++ Field_imms8_Slot_inst_get, ++ Field_imm12b_Slot_inst_get, ++ Field_imm16_Slot_inst_get, ++ Field_m_Slot_inst_get, ++ Field_n_Slot_inst_get, ++ Field_offset_Slot_inst_get, ++ Field_op0_Slot_inst_get, ++ Field_op1_Slot_inst_get, ++ Field_op2_Slot_inst_get, ++ Field_r_Slot_inst_get, ++ Field_r_disp_Slot_inst_get, ++ Field_r_3_Slot_inst_get, ++ Field_sa4_Slot_inst_get, ++ Field_sae4_Slot_inst_get, ++ Field_sae_Slot_inst_get, ++ Field_sal_Slot_inst_get, ++ Field_sargt_Slot_inst_get, ++ Field_sas4_Slot_inst_get, ++ Field_sas_Slot_inst_get, ++ Field_sr_Slot_inst_get, ++ Field_st_Slot_inst_get, ++ Field_thi3_Slot_inst_get, ++ Field_imm4_Slot_inst_get, ++ Field_mn_Slot_inst_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_xt_wbr15_imm_Slot_inst_get, ++ Field_xt_wbr18_imm_Slot_inst_get, ++ Field_bitindex_Slot_inst_get, ++ Field_s3to1_Slot_inst_get, ++ Implicit_Field_ar0_get, ++ Implicit_Field_ar4_get, ++ Implicit_Field_ar8_get, ++ Implicit_Field_ar12_get ++}; ++ ++static xtensa_set_field_fn ++Slot_inst_set_field_fns[] = { ++ Field_t_Slot_inst_set, ++ Field_bbi4_Slot_inst_set, ++ Field_bbi_Slot_inst_set, ++ Field_imm12_Slot_inst_set, ++ Field_imm8_Slot_inst_set, ++ Field_s_Slot_inst_set, ++ Field_s8_Slot_inst_set, ++ Field_imms8_Slot_inst_set, ++ Field_imm12b_Slot_inst_set, ++ Field_imm16_Slot_inst_set, ++ Field_m_Slot_inst_set, ++ Field_n_Slot_inst_set, ++ Field_offset_Slot_inst_set, ++ Field_op0_Slot_inst_set, ++ Field_op1_Slot_inst_set, ++ Field_op2_Slot_inst_set, ++ Field_r_Slot_inst_set, ++ Field_r_disp_Slot_inst_set, ++ Field_r_3_Slot_inst_set, ++ Field_sa4_Slot_inst_set, ++ Field_sae4_Slot_inst_set, ++ Field_sae_Slot_inst_set, ++ Field_sal_Slot_inst_set, ++ Field_sargt_Slot_inst_set, ++ Field_sas4_Slot_inst_set, ++ Field_sas_Slot_inst_set, ++ Field_sr_Slot_inst_set, ++ Field_st_Slot_inst_set, ++ Field_thi3_Slot_inst_set, ++ Field_imm4_Slot_inst_set, ++ Field_mn_Slot_inst_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_xt_wbr15_imm_Slot_inst_set, ++ Field_xt_wbr18_imm_Slot_inst_set, ++ Field_bitindex_Slot_inst_set, ++ Field_s3to1_Slot_inst_set, ++ Implicit_Field_set, ++ Implicit_Field_set, ++ Implicit_Field_set, ++ Implicit_Field_set ++}; ++ ++static xtensa_get_field_fn ++Slot_inst16a_get_field_fns[] = { ++ Field_t_Slot_inst16a_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_s_Slot_inst16a_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_op0_Slot_inst16a_get, ++ 0, ++ 0, ++ Field_r_Slot_inst16a_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_i_Slot_inst16a_get, ++ Field_imm6lo_Slot_inst16a_get, ++ Field_imm6hi_Slot_inst16a_get, ++ Field_imm7lo_Slot_inst16a_get, ++ Field_imm7hi_Slot_inst16a_get, ++ Field_z_Slot_inst16a_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Implicit_Field_ar0_get, ++ Implicit_Field_ar4_get, ++ Implicit_Field_ar8_get, ++ Implicit_Field_ar12_get ++}; ++ ++static xtensa_set_field_fn ++Slot_inst16a_set_field_fns[] = { ++ Field_t_Slot_inst16a_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_s_Slot_inst16a_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_op0_Slot_inst16a_set, ++ 0, ++ 0, ++ Field_r_Slot_inst16a_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_i_Slot_inst16a_set, ++ Field_imm6lo_Slot_inst16a_set, ++ Field_imm6hi_Slot_inst16a_set, ++ Field_imm7lo_Slot_inst16a_set, ++ Field_imm7hi_Slot_inst16a_set, ++ Field_z_Slot_inst16a_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Implicit_Field_set, ++ Implicit_Field_set, ++ Implicit_Field_set, ++ Implicit_Field_set ++}; ++ ++static xtensa_get_field_fn ++Slot_inst16b_get_field_fns[] = { ++ Field_t_Slot_inst16b_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_s_Slot_inst16b_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_op0_Slot_inst16b_get, ++ 0, ++ 0, ++ Field_r_Slot_inst16b_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_i_Slot_inst16b_get, ++ Field_imm6lo_Slot_inst16b_get, ++ Field_imm6hi_Slot_inst16b_get, ++ Field_imm7lo_Slot_inst16b_get, ++ Field_imm7hi_Slot_inst16b_get, ++ Field_z_Slot_inst16b_get, ++ Field_imm6_Slot_inst16b_get, ++ Field_imm7_Slot_inst16b_get, ++ 0, ++ 0, ++ 0, ++ 0, ++ Implicit_Field_ar0_get, ++ Implicit_Field_ar4_get, ++ Implicit_Field_ar8_get, ++ Implicit_Field_ar12_get ++}; ++ ++static xtensa_set_field_fn ++Slot_inst16b_set_field_fns[] = { ++ Field_t_Slot_inst16b_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_s_Slot_inst16b_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_op0_Slot_inst16b_set, ++ 0, ++ 0, ++ Field_r_Slot_inst16b_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ Field_i_Slot_inst16b_set, ++ Field_imm6lo_Slot_inst16b_set, ++ Field_imm6hi_Slot_inst16b_set, ++ Field_imm7lo_Slot_inst16b_set, ++ Field_imm7hi_Slot_inst16b_set, ++ Field_z_Slot_inst16b_set, ++ Field_imm6_Slot_inst16b_set, ++ Field_imm7_Slot_inst16b_set, ++ 0, ++ 0, ++ 0, ++ 0, ++ Implicit_Field_set, ++ Implicit_Field_set, ++ Implicit_Field_set, ++ Implicit_Field_set ++}; ++ ++static xtensa_slot_internal slots[] = { ++ { "Inst", "x24", 0, ++ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, ++ Slot_inst_get_field_fns, Slot_inst_set_field_fns, ++ Slot_inst_decode, "nop" }, ++ { "Inst16a", "x16a", 0, ++ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, ++ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, ++ Slot_inst16a_decode, "" }, ++ { "Inst16b", "x16b", 0, ++ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, ++ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, ++ Slot_inst16b_decode, "nop.n" } ++}; ++ ++ ++/* Instruction formats. */ ++ ++static void ++Format_x24_encode (xtensa_insnbuf insn) ++{ ++ insn[0] = 0; ++} ++ ++static void ++Format_x16a_encode (xtensa_insnbuf insn) ++{ ++ insn[0] = 0x8; ++} ++ ++static void ++Format_x16b_encode (xtensa_insnbuf insn) ++{ ++ insn[0] = 0xc; ++} ++ ++static int Format_x24_slots[] = { 0 }; ++ ++static int Format_x16a_slots[] = { 1 }; ++ ++static int Format_x16b_slots[] = { 2 }; ++ ++static xtensa_format_internal formats[] = { ++ { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, ++ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, ++ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } ++}; ++ ++ ++static int ++format_decoder (const xtensa_insnbuf insn) ++{ ++ if ((insn[0] & 0x8) == 0) ++ return 0; /* x24 */ ++ if ((insn[0] & 0xc) == 0x8) ++ return 1; /* x16a */ ++ if ((insn[0] & 0xe) == 0xc) ++ return 2; /* x16b */ ++ return -1; ++} ++ ++static int length_table[256] = { ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 3, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ 2, ++ -1, ++ -1 ++}; ++ ++static int ++length_decoder (const unsigned char *insn) ++{ ++ int l = insn[0]; ++ return length_table[l]; ++} ++ ++ ++/* Top-level ISA structure. */ ++ ++static xtensa_isa_internal xtensa_modules = { ++ 0 /* little-endian */, ++ 3 /* insn_size */, 0, ++ 3, formats, format_decoder, length_decoder, ++ 3, slots, ++ 47 /* num_fields */, ++ 84, operands, ++ 265, iclasses, ++ 316, opcodes, 0, ++ 1, regfiles, ++ NUM_STATES, states, 0, ++ NUM_SYSREGS, sysregs, 0, ++ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, ++ 1, interfaces, 0, ++ 1, funcUnits, 0 ++}; +diff --git a/target/xtensa/cores.list b/target/xtensa/cores.list +index a526a71cfd..be689275ac 100644 +--- a/target/xtensa/cores.list ++++ b/target/xtensa/cores.list +@@ -6,5 +6,6 @@ core-dsp3400.c + core-fsf.c + core-lx106.c + core-sample_controller.c ++core-sample_controller32.c + core-test_kc705_be.c + core-test_mmuhifi_c3.c +-- +2.43.0 + diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-tests-tcg-xtensa-tidy-test-linker-script.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-tests-tcg-xtensa-tidy-test-linker-script.patch new file mode 100644 index 00000000..e3c51dd7 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0003-tests-tcg-xtensa-tidy-test-linker-script.patch @@ -0,0 +1,103 @@ +From c700aa6373e4cee40cba849f3bbb4927165d7243 Mon Sep 17 00:00:00 2001 +From: Max Filippov +Date: Thu, 14 Dec 2023 16:46:08 -0800 +Subject: [PATCH 3/4] tests/tcg/xtensa: tidy test linker script + +Drop MEMORY clause and related size definitions and output section +region specifications. Drop .rodata output section as the tests don't +use it. Add DATA_SEGMENT_ALIGN/DATA_SEGMENT_END around .data and .bss to +let the linker make an RW segment for data. Reserve 1M for stack instead +of almost 128M. + +Signed-off-by: Max Filippov +--- + tests/tcg/xtensa/linker.ld.S | 34 +++++++++++----------------------- + 1 file changed, 11 insertions(+), 23 deletions(-) + +diff --git a/tests/tcg/xtensa/linker.ld.S b/tests/tcg/xtensa/linker.ld.S +index ac89b0054e..0e21eee31c 100644 +--- a/tests/tcg/xtensa/linker.ld.S ++++ b/tests/tcg/xtensa/linker.ld.S +@@ -10,9 +10,8 @@ + #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 + #endif + +-#define RAM_SIZE 0x08000000 /* 128M */ +-#define ROM_SIZE 0x00001000 /* 4k */ + #define VECTORS_RESERVED_SIZE 0x1000 ++#define STACK_SIZE 0x00100000 + + #if XCHAL_HAVE_BE + OUTPUT_FORMAT("elf32-xtensa-be") +@@ -21,18 +20,13 @@ OUTPUT_FORMAT("elf32-xtensa-le") + #endif + ENTRY(_start) + +-MEMORY { +- ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE +- rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = ROM_SIZE +-} +- + SECTIONS + { +- .init : ++ .init XCHAL_RESET_VECTOR_VADDR : + { + *(.init) + *(.init.*) +- } > rom ++ } + + #if XCHAL_HAVE_WINDOWED + .vector.window XCHAL_WINDOW_VECTORS_VADDR : +@@ -119,23 +113,16 @@ SECTIONS + *(.vector.kernel.*) + *(.vector.user.*) + *(.vector.double.*) +- } > ram ++ } + + .text : + { + _ftext = .; + *(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*) + _etext = .; +- } > ram ++ } + +- .rodata : +- { +- . = ALIGN(4); +- _frodata = .; +- *(.rodata .rodata.* .gnu.linkonce.r.*) +- *(.rodata1) +- _erodata = .; +- } > ram ++ . = DATA_SEGMENT_ALIGN(0x1000, 0x1000); + + .data : + { +@@ -146,7 +133,7 @@ SECTIONS + _gp = ALIGN(16); + *(.sdata .sdata.* .gnu.linkonce.s.*) + _edata = .; +- } > ram ++ } + + .bss : + { +@@ -160,7 +147,8 @@ SECTIONS + *(COMMON) + _ebss = .; + _end = .; +- } > ram +-} ++ } + +-PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16); ++ . = DATA_SEGMENT_END(.); ++ _fstack = ALIGN(. + STACK_SIZE, 16); ++} +-- +2.43.0 + diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-Do-not-include-file-if-not-exists.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-Do-not-include-file-if-not-exists.patch new file mode 100644 index 00000000..2b4f2b17 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-qemu-Do-not-include-file-if-not-exists.patch @@ -0,0 +1,31 @@ +From 081c1e4ee93b22ec00136db45c36650427213c09 Mon Sep 17 00:00:00 2001 +From: Oleksiy Obitotskyy +Date: Wed, 25 Mar 2020 21:21:35 +0200 +Subject: [PATCH] qemu: Do not include file if not exists + +Script configure checks for if_alg.h and check failed but +if_alg.h still included. + +Upstream-Status: Submitted [https://lists.gnu.org/archive/html/qemu-devel/2020-03/msg07188.html] +Signed-off-by: Oleksiy Obitotskyy + +[update patch context] +Signed-off-by: Sakib Sajal +--- + linux-user/syscall.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/linux-user/syscall.c b/linux-user/syscall.c +index 9d5415674..22df46859 100644 +--- a/linux-user/syscall.c ++++ b/linux-user/syscall.c +@@ -117,7 +117,9 @@ + #include + #include + #include ++#if defined(CONFIG_AF_ALG) + #include ++#endif + #include + #include + #ifdef HAVE_BTRFS_H diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-tests-tcg-xtensa-fix-SR-test-for-configs-with-MPU.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-tests-tcg-xtensa-fix-SR-test-for-configs-with-MPU.patch new file mode 100644 index 00000000..c01e56b6 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0004-tests-tcg-xtensa-fix-SR-test-for-configs-with-MPU.patch @@ -0,0 +1,70 @@ +From f814bc5b4d16403b15fcd80b1678d12202dab0f2 Mon Sep 17 00:00:00 2001 +From: Max Filippov +Date: Thu, 14 Dec 2023 18:14:00 -0800 +Subject: [PATCH 4/4] tests/tcg/xtensa: fix SR test for configs with MPU + +- atomctl is available not only in the presence of s32c1i, but also with + the exclusive access option +- cacheadrdis SR has the same number as cacheattr, mpuenb SR has the + same number as rasid and mpucfg SR has the same number as dtlbcfg, + add MPU case to the tests of these SR numbers + +Signed-off-by: Max Filippov +--- + tests/tcg/xtensa/test_sr.S | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S +index 34441c7aff..661ef6c66e 100644 +--- a/tests/tcg/xtensa/test_sr.S ++++ b/tests/tcg/xtensa/test_sr.S +@@ -62,7 +62,7 @@ test_sr_mask /*acchi*/17, 0, 0 + test_sr_mask /*acclo*/16, 0, 0 + #endif + +-#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000 ++#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000 || XCHAL_HAVE_EXCLUSIVE + test_sr atomctl, 1 + #else + test_sr_mask /*atomctl*/99, 0, 0 +@@ -74,7 +74,11 @@ test_sr br, 1 + test_sr_mask /*br*/4, 0, 0 + #endif + ++#if XCHAL_HAVE_MPU ++test_sr cacheadrdis, 1 ++#else + test_sr_mask /*cacheattr*/98, 0, 0 ++#endif + + #if XCHAL_HAVE_CCOUNT + test_sr ccompare0, 1 +@@ -106,6 +110,8 @@ test_sr depc, 1 + + #if XCHAL_HAVE_PTP_MMU + test_sr dtlbcfg, 1 ++#elif XCHAL_HAVE_MPU ++test_sr_mask /*mpucfg*/92, 0, 3 + #else + test_sr_mask /*dtlbcfg*/92, 0, 0 + #endif +@@ -205,9 +211,15 @@ test_sr ps, 1 + + #if XCHAL_HAVE_PTP_MMU + test_sr ptevaddr, 1 +-test_sr rasid, 1 + #else + test_sr_mask /*ptevaddr*/83, 0, 0 ++#endif ++ ++#if XCHAL_HAVE_PTP_MMU ++test_sr rasid, 1 ++#elif XCHAL_HAVE_MPU ++test_sr mpuenb, 1 ++#else + test_sr_mask /*rasid*/90, 0, 0 + #endif + +-- +2.43.0 + diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-qemu-Add-some-user-space-mmap-tweaks-to-address-musl.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-qemu-Add-some-user-space-mmap-tweaks-to-address-musl.patch new file mode 100644 index 00000000..26ddf5e5 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0005-qemu-Add-some-user-space-mmap-tweaks-to-address-musl.patch @@ -0,0 +1,47 @@ +From 76efeccfd73a76834ac1c75d3c94de1899085714 Mon Sep 17 00:00:00 2001 +From: Richard Purdie +Date: Fri, 8 Jan 2021 17:27:06 +0000 +Subject: [PATCH] qemu: Add some user space mmap tweaks to address musl 32 bit + +When using qemu-i386 to build qemux86 webkitgtk on musl, it sits in an +infinite loop of mremap calls of ever decreasing/increasing addresses. + +I suspect something in the musl memory allocation code loops indefinitely +if it only sees ENOMEM and only exits when it hits EFAULT. + +According to the docs, trying to mremap outside the address space +can/should return EFAULT and changing this allows the build to succeed. + +A better return value for the other cases of invalid addresses is EINVAL +rather than ENOMEM so adjust the other part of the test to this. + +Upstream-Status: Submitted [https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg01355.html] +Signed-off-by: Richard Purdie +Date: Mon, 1 Mar 2021 13:00:47 +0000 +Subject: [PATCH] qemu: Determinism fixes + +When sources are included within debug information, a couple of areas of the +qemu build are not reproducible due to either full buildpaths or timestamps. + +Replace the full paths with relative ones. I couldn't figure out how to get +meson to pass relative paths but we can fix that in the script. + +Upstream-Status: Pending [some version of all/part of this may be accepted] +RP 2021/3/1 +--- + scripts/decodetree.py | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/scripts/decodetree.py b/scripts/decodetree.py +index e8b72da3a..5cd86b142 100644 +--- a/scripts/decodetree.py ++++ b/scripts/decodetree.py +@@ -1558,7 +1558,7 @@ def main(): + toppat = ExcMultiPattern(0) + + for filename in args: +- input_file = filename ++ input_file = os.path.relpath(filename) + f = open(filename, 'rt', encoding='utf-8') + parse_file(f, toppat) + f.close() diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-tests-meson.build-use-relative-path-to-refer-to-file.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-tests-meson.build-use-relative-path-to-refer-to-file.patch new file mode 100644 index 00000000..cd919048 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0007-tests-meson.build-use-relative-path-to-refer-to-file.patch @@ -0,0 +1,43 @@ +From 1a574aa22c9b3700af7e5c0901abef59c72bb874 Mon Sep 17 00:00:00 2001 +From: Changqing Li +Date: Thu, 14 Jan 2021 06:33:04 +0000 +Subject: [PATCH] tests/meson.build: use relative path to refer to files + +Fix error like: +Fatal error: can't create tests/ptimer-test.p/..._qemu-5.2.0_hw_core_ptimer.c.o: File name too long + +when build path is too long, use meson.source_root() will make this +filename too long. Fixed by using relative path to refer to files + +Upstream-Status: Submitted [send to qemu-devel] + +Signed-off-by: Changqing Li +--- + tests/unit/meson.build | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/tests/unit/meson.build b/tests/unit/meson.build +index 490ab8182..d19ee5606 100644 +--- a/tests/unit/meson.build ++++ b/tests/unit/meson.build +@@ -128,17 +128,17 @@ endif + + if have_system + tests += { +- 'ptimer-test': ['ptimer-test-stubs.c', meson.project_source_root() / 'hw/core/ptimer.c'], ++ 'ptimer-test': ['ptimer-test-stubs.c', '../../hw/core/ptimer.c'], + 'test-iov': [], + 'test-opts-visitor': [testqapi], + 'test-xs-node': [qom], +- 'test-virtio-dmabuf': [meson.project_source_root() / 'hw/display/virtio-dmabuf.c'], ++ 'test-virtio-dmabuf': ['../../hw/display/virtio-dmabuf.c'], + 'test-qmp-cmds': [testqapi], + 'test-xbzrle': [migration], + 'test-util-sockets': ['socket-helpers.c'], + 'test-base64': [], + 'test-bufferiszero': [], +- 'test-smp-parse': [qom, meson.project_source_root() / 'hw/core/machine-smp.c'], ++ 'test-smp-parse': [qom, '../../hw/core/machine-smp.c'], + 'test-vmstate': [migration, io], + 'test-yank': ['socket-helpers.c', qom, io, chardev] + } diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-Define-MAP_SYNC-and-MAP_SHARED_VALIDATE-on-needed-li.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-Define-MAP_SYNC-and-MAP_SHARED_VALIDATE-on-needed-li.patch new file mode 100644 index 00000000..7bbd96df --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0008-Define-MAP_SYNC-and-MAP_SHARED_VALIDATE-on-needed-li.patch @@ -0,0 +1,45 @@ +From 06b5b26a0a1f7687576d90066e492cf2665fff1d Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Mon, 21 Mar 2022 10:09:38 -0700 +Subject: [PATCH] Define MAP_SYNC and MAP_SHARED_VALIDATE on needed linux + systems + +linux only wires MAP_SYNC and MAP_SHARED_VALIDATE for architectures +which include asm-generic/mman.h and mips/powerpc are not including this +file in linux/mman.h, therefore these should be defined for such +architectures on Linux as well. This fixes build on mips/musl/linux + +Upstream-Status: Submitted [https://lists.nongnu.org/archive/html/qemu-devel/2022-03/msg05298.html] +Signed-off-by: Khem Raj +Cc: Zhang Yi +Cc: Michael S. Tsirkin +--- + util/mmap-alloc.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/util/mmap-alloc.c b/util/mmap-alloc.c +index ed14f9c64..038f5b4b5 100644 +--- a/util/mmap-alloc.c ++++ b/util/mmap-alloc.c +@@ -10,14 +10,18 @@ + * later. See the COPYING file in the top-level directory. + */ + ++#include "qemu/osdep.h" + #ifdef CONFIG_LINUX + #include +-#else /* !CONFIG_LINUX */ ++#endif /* CONFIG_LINUX */ ++ ++#ifndef MAP_SYNC + #define MAP_SYNC 0x0 ++#endif /* MAP_SYNC */ ++#ifndef MAP_SHARED_VALIDATE + #define MAP_SHARED_VALIDATE 0x0 +-#endif /* CONFIG_LINUX */ ++#endif /* MAP_SHARED_VALIDATE */ + +-#include "qemu/osdep.h" + #include "qemu/mmap-alloc.h" + #include "qemu/host-utils.h" + #include "qemu/cutils.h" diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-configure-lookup-meson-exutable-from-PATH.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-configure-lookup-meson-exutable-from-PATH.patch new file mode 100644 index 00000000..f20851bf --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0010-configure-lookup-meson-exutable-from-PATH.patch @@ -0,0 +1,28 @@ +From 2e9642b9001df523628ab2cacbbbf2b208c49437 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Martin=20Hundeb=C3=B8ll?= +Date: Wed, 22 May 2024 14:02:55 +0200 +Subject: [PATCH] configure: lookup meson exutable from PATH + +Upstream-Status: Inappropriate [workaround, would need a real fix for upstream] +--- + configure | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/configure b/configure +index d08b71f14..af0bd2c66 100755 +--- a/configure ++++ b/configure +@@ -958,12 +958,7 @@ mkvenv="$python ${source_path}/python/scripts/mkvenv.py" + $mkvenv ensuregroup --dir "${source_path}/python/wheels" \ + ${source_path}/pythondeps.toml meson || exit 1 + +-# At this point, we expect Meson to be installed and available. +-# We expect mkvenv or pip to have created pyvenv/bin/meson for us. +-# We ignore PATH completely here: we want to use the venv's Meson +-# *exclusively*. +- +-meson="$(cd pyvenv/bin; pwd)/meson" ++meson=`which meson` + + # Conditionally ensure Sphinx is installed. + diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-qemu-Ensure-pip-and-the-python-venv-aren-t-used-for-.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-qemu-Ensure-pip-and-the-python-venv-aren-t-used-for-.patch new file mode 100644 index 00000000..4adb2e5f --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/0011-qemu-Ensure-pip-and-the-python-venv-aren-t-used-for-.patch @@ -0,0 +1,51 @@ +From 68a13afd6606c2aaf1f0debd325d7314aaa61411 Mon Sep 17 00:00:00 2001 +From: Richard Purdie +Date: Wed, 22 May 2024 13:58:23 +0200 +Subject: [PATCH] qemu: Ensure pip and the python venv aren't used for meson + +Qemu wants to use a supported python version and a specific meson version +to "help" users and uses pip and creates a venv to do this. This is a nightmare +for us. Our versions stay up to date and should be supported so we don't +really need/want this wrapping. Tweak things to disable it. + +There was breakage from the wrapper shown by: + +bitbake qemu-system-native + +bitbake qemu-system-native -c configure + +which would crash. The issue is the change in configuration removes pieces +from the sysroot but pyc files remainm as do pieces of pip which causes +problems. + +Ideally we'd convince upstream to allow some way to disable the venv on +the understanding that if/when it breaks, we keep the pieces. The patch +as it stands is a workaround. + +Upstream-Status: Inappropriate [oe specific] +Signed-off-by: Richard Purdie +--- + configure | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/configure b/configure +index af0bd2c66..88dab6a95 100755 +--- a/configure ++++ b/configure +@@ -944,14 +944,14 @@ python="$(command -v "$python")" + echo "python determined to be '$python'" + echo "python version: $($python --version)" + +-python="$($python -B "${source_path}/python/scripts/mkvenv.py" create pyvenv)" ++python=python3 + if test "$?" -ne 0 ; then + error_exit "python venv creation failed" + fi + + # Suppress writing compiled files + python="$python -B" +-mkvenv="$python ${source_path}/python/scripts/mkvenv.py" ++mkvenv=true + + # Finish preparing the virtual environment using vendored .whl files + diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/cross.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/cross.patch deleted file mode 100644 index fd6d4268..00000000 --- a/meta-zephyr-sdk/recipes-devtools/qemu/files/cross.patch +++ /dev/null @@ -1,30 +0,0 @@ -We need to be able to trigger configure's cross code but we don't want -to set cross_prefix as it does other things we don't want. Patch things -so we can do what we need in the target config case. - -Upstream-Status: Inappropriate [may be rewritten in a way upstream may accept?] -Signed-off-by: Richard Purdie - - -Index: qemu/configure -=================================================================== ---- a/configure -+++ b/configure -@@ -3932,7 +3932,6 @@ if test "$skip_meson" = no; then - fi - echo "strip = [$(meson_quote $strip)]" >> $cross - echo "windres = [$(meson_quote $windres)]" >> $cross -- if test "$cross_compile" = "yes"; then - cross_arg="--cross-file config-meson.cross" - echo "[host_machine]" >> $cross - if test "$mingw32" = "yes" ; then -@@ -3964,9 +3963,6 @@ if test "$skip_meson" = no; then - else - echo "endian = 'little'" >> $cross - fi -- else -- cross_arg="--native-file config-meson.cross" -- fi - mv $cross config-meson.cross - - rm -rf meson-private meson-info meson-logs diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/fix-strerrorname_np.patch b/meta-zephyr-sdk/recipes-devtools/qemu/files/fix-strerrorname_np.patch new file mode 100644 index 00000000..b57c4811 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/fix-strerrorname_np.patch @@ -0,0 +1,35 @@ +From 9de5de85fa917af58e7bc9cdd88f8f7ef8da2ca9 Mon Sep 17 00:00:00 2001 +From: Natanael Copa +Date: Wed, 18 Sep 2024 16:19:37 -0700 +Subject: [PATCH] target/riscv/kvm: do not use non-portable strerrorname_np() + +strerrorname_np is non-portable and breaks building with musl libc. + +Use strerror(errno) instead, like we do other places. + +Upstream-Status: Submitted [https://mail.gnu.org/archive/html/qemu-stable/2023-12/msg00069.html] + +Cc: qemu-stable@nongnu.org +Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve 'init_multiext_cfg' error +msg) +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2041 +Buglink: https://gitlab.alpinelinux.org/alpine/aports/-/issues/15541 +Signed-off-by: Natanael Copa +--- + target/riscv/kvm/kvm-cpu.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c +index f6e3156b8..fad9eb21c 100644 +--- a/target/riscv/kvm/kvm-cpu.c ++++ b/target/riscv/kvm/kvm-cpu.c +@@ -1859,8 +1859,7 @@ static bool kvm_cpu_realize(CPUState *cs, Error **errp) + if (riscv_has_ext(&cpu->env, RVV)) { + ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); + if (ret) { +- error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", +- strerrorname_np(errno)); ++ error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, error %d", errno); + return false; + } + } diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/powerpc_rom.bin b/meta-zephyr-sdk/recipes-devtools/qemu/files/powerpc_rom.bin new file mode 100644 index 00000000..c4044296 Binary files /dev/null and b/meta-zephyr-sdk/recipes-devtools/qemu/files/powerpc_rom.bin differ diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/qemu-guest-agent.init b/meta-zephyr-sdk/recipes-devtools/qemu/files/qemu-guest-agent.init new file mode 100644 index 00000000..5ebaadde --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/qemu-guest-agent.init @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Initially written by: Michael Tokarev +# For QEMU Debian downstream package + +set -e + +. /etc/init.d/functions + +PATH=/sbin:/usr/sbin:/bin:/usr/bin +DESC="QEMU Guest Agent" +NAME=qemu-ga +DAEMON=@bindir@/$NAME +PIDFILE=/var/run/$NAME.pid + +# config +DAEMON_ARGS="" +# default transport +TRANSPORT=virtio-serial:/dev/virtio-ports/org.qemu.guest_agent.0 +NO_START=0 + +test ! -r /etc/default/qemu-guest-agent || . /etc/default/qemu-guest-agent +test "$NO_START" = "0" || exit 0 +test -x "$DAEMON" || exit 0 + +# +# Function that checks whenever system has necessary environment +# It also splits $TRANSPORT into $method and $path +# +do_check_transport() { + method=${TRANSPORT%%:*}; + path=${TRANSPORT#*:} + case "$method" in + virtio-serial | isa-serial) + if [ ! -e "$path" ]; then + echo "$NAME: transport endpoint not found, not starting" + return 1 + fi + ;; + esac +} + +case "$1" in + start) + do_check_transport || exit 0 + echo -n "Starting $DESC: " + start-stop-daemon -S -p $PIDFILE -x "$DAEMON" -- \ + $DAEMON_ARGS -d -m "$method" -p "$path" + echo "$NAME." + ;; + stop) + echo -n "Stopping $DESC: " + start-stop-daemon -K -x "$DAEMON" -p $PIDFILE + echo "$NAME." + ;; + status) + status "$DAEMON" + exit $? + ;; + restart|force-reload) + do_check_transport || exit 0 + echo -n "Restarting $DESC: " + start-stop-daemon -K -x "$DAEMON" -p $PIDFILE + sleep 1 + start-stop-daemon -S -p $PIDFILE -x "$DAEMON" -- \ + $DAEMON_ARGS -d -m "$method" -p "$path" + echo "$NAME." + ;; + *) + N=/etc/init.d/$NAME + echo "Usage: $N {start|stop|status|restart|force-reload}" >&2 + exit 1 + ;; +esac + +exit 0 diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/qemu-guest-agent.udev b/meta-zephyr-sdk/recipes-devtools/qemu/files/qemu-guest-agent.udev new file mode 100644 index 00000000..47097057 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/qemu-guest-agent.udev @@ -0,0 +1,2 @@ +SUBSYSTEM=="virtio-ports", ATTR{name}=="org.qemu.guest_agent.0", \ + TAG+="systemd", ENV{SYSTEMD_WANTS}="qemu-guest-agent.service" diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/files/run-ptest b/meta-zephyr-sdk/recipes-devtools/qemu/files/run-ptest new file mode 100644 index 00000000..f9a4e8fb --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/files/run-ptest @@ -0,0 +1,13 @@ +#!/bin/sh +# +#This script is used to run qemu test suites +# + +ptestdir=$(dirname "$(readlink -f "$0")") +export SRC_PATH=$ptestdir + +cd $ptestdir/tests +tests=$(find . -name "test-*" ! -name "*.p") +for f in $tests; do + $f | sed '/^ok/ s/ok/PASS:/g' +done diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/qemu-zephyr_9.2.1.bb b/meta-zephyr-sdk/recipes-devtools/qemu/qemu-zephyr_9.2.1.bb new file mode 100644 index 00000000..e45cc799 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/qemu-zephyr_9.2.1.bb @@ -0,0 +1,243 @@ +BBCLASSEXTEND = "nativesdk" + +BPN = "qemu" + +SUMMARY = "Fast open source processor emulator" +DESCRIPTION = "QEMU is a hosted virtual machine monitor: it emulates the \ +machine's processor through dynamic binary translation and provides a set \ +of different hardware and device models for the machine, enabling it to run \ +a variety of guest operating systems" +HOMEPAGE = "http://qemu.org" +LICENSE = "GPL-2.0-only & LGPL-2.1-only" + +DEPENDS += "bison-native meson-native ninja-native" + +DEPENDS += "glib-2.0 zlib pixman" + +CFLAGS += "${@bb.utils.contains('DISTRO_FEATURES', 'x11', '', '-DEGL_NO_X11=1', d)}" + +RDEPENDS:${PN}-common:class-target += "bash" + +DISABLE_STATIC = "" + +PACKAGECONFIG ??= " \ + fdt sdl kvm pie slirp \ + ${@bb.utils.filter('DISTRO_FEATURES', 'alsa pulseaudio xen', d)} \ + ${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'virglrenderer epoxy', '', d)} \ + ${@bb.utils.filter('DISTRO_FEATURES', 'seccomp', d)} \ +" +PACKAGECONFIG:class-nativesdk ??= "fdt sdl kvm pie slirp \ + ${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'virglrenderer epoxy', '', d)} \ +" + +# https://gitlab.com/qemu-project/qemu/-/commit/81e2b198a8cb4ee5fdf108bd438f44b193ee3a36 means +# we need a full python3-native setup +inherit pkgconfig systemd python3native + +LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ + file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" + +SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \ + file://run-ptest \ + file://fix-strerrorname_np.patch \ + file://0001-qemu-Add-addition-environment-space-to-boot-loader-q.patch \ + file://0002-apic-fixup-fallthrough-to-PIC.patch \ + file://0004-qemu-Do-not-include-file-if-not-exists.patch \ + file://0005-qemu-Add-some-user-space-mmap-tweaks-to-address-musl.patch \ + file://0006-qemu-Determinism-fixes.patch \ + file://0007-tests-meson.build-use-relative-path-to-refer-to-file.patch \ + file://0008-Define-MAP_SYNC-and-MAP_SHARED_VALIDATE-on-needed-li.patch \ + file://0010-configure-lookup-meson-exutable-from-PATH.patch \ + file://0011-qemu-Ensure-pip-and-the-python-venv-aren-t-used-for-.patch \ + file://0001-sched_attr-Do-not-define-for-glibc-2.41.patch \ + file://qemu-guest-agent.init \ + file://qemu-guest-agent.udev \ + file://0001-target-xtensa-add-translation-for-wsr.mpucfg.patch \ + file://0002-target-xtensa-import-sample_controller32-core.patch \ + file://0003-tests-tcg-xtensa-tidy-test-linker-script.patch \ + file://0004-tests-tcg-xtensa-fix-SR-test-for-configs-with-MPU.patch \ + " +UPSTREAM_CHECK_REGEX = "qemu-(?P\d+(\.\d+)+)\.tar" + +SRC_URI[sha256sum] = "b7b0782ead63a5373fdfe08e084d3949a9395ec196180286b841f78a464d169c" + +CVE_STATUS[CVE-2007-0998] = "not-applicable-config: The VNC server can expose host files uder some circumstances. We don't enable it by default." + +# https://bugzilla.redhat.com/show_bug.cgi?id=1609015#c11 +CVE_STATUS[CVE-2018-18438] = "disputed: The issues identified by this CVE were determined to not constitute a vulnerability." + +# As per https://bugzilla.redhat.com/show_bug.cgi?id=2203387 +CVE_STATUS[CVE-2023-2680] = "not-applicable-platform: RHEL specific issue." + +# NVD DB has this CVE as version-less (with "-") +CVE_STATUS[CVE-2024-6505] = "fixed-version: this CVE is fixed since 9.1.0" + +COMPATIBLE_HOST:mipsarchn32 = "null" +COMPATIBLE_HOST:mipsarchn64 = "null" +COMPATIBLE_HOST:riscv32 = "null" + +# Per https://lists.nongnu.org/archive/html/qemu-devel/2020-09/msg03873.html +# upstream states qemu doesn't work without optimization +DEBUG_BUILD = "0" + +do_install:append() { + # Prevent QA warnings about installed ${localstatedir}/run + if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi +} + +EXTRA_OECONF = " \ + --prefix=${prefix} \ + --bindir=${bindir} \ + --includedir=${includedir} \ + --libdir=${libdir} \ + --mandir=${mandir} \ + --datadir=${datadir} \ + --docdir=${docdir}/${BPN} \ + --sysconfdir=${sysconfdir} \ + --libexecdir=${libexecdir} \ + --localstatedir=${localstatedir} \ + --with-suffix=${BPN} \ + --disable-strip \ + --disable-werror \ + --extra-cflags='${CFLAGS}' \ + --extra-ldflags='${LDFLAGS}' \ + --disable-download \ + --disable-docs \ + --host-cc='${BUILD_CC}' \ + --disable-af-xdp \ + ${PACKAGECONFIG_CONFARGS} \ + " +QEMU_TARGETS = "aarch64-softmmu arm-softmmu i386-softmmu or1k-softmmu mips-softmmu mipsel-softmmu xtensa-softmmu riscv32-softmmu riscv64-softmmu x86_64-softmmu" + +EXTRA_OECONF:append:class-target = " --cross-prefix=${HOST_PREFIX}" +EXTRA_OECONF:append:class-nativesdk = " --cross-prefix=${HOST_PREFIX}" + +B = "${WORKDIR}/build" + +#EXTRA_OECONF:append = " --python=${HOSTTOOLS_DIR}/python3" + +do_configure:prepend:class-native() { + # Append build host pkg-config paths for native target since the host may provide sdl + BHOST_PKGCONFIG_PATH=$(PATH=/usr/bin:/bin pkg-config --variable pc_path pkg-config || echo "") + if [ ! -z "$BHOST_PKGCONFIG_PATH" ]; then + export PKG_CONFIG_PATH=$PKG_CONFIG_PATH:$BHOST_PKGCONFIG_PATH + fi +} + +do_configure() { + export PKG_CONFIG=pkg-config + ${S}/configure ${EXTRA_OECONF} --target-list="${QEMU_TARGETS}" +} +do_configure[cleandirs] += "${B}" + +do_install () { + export STRIP="" + oe_runmake 'DESTDIR=${D}' install + + # If we built the guest agent, also install startup/udev rules + if [ -e "${D}${bindir}/qemu-ga" ]; then + install -d ${D}${sysconfdir}/init.d/ + install -m 0755 ${WORKDIR}/qemu-guest-agent.init ${D}${sysconfdir}/init.d/qemu-guest-agent + sed -i 's:@bindir@:${bindir}:' ${D}${sysconfdir}/init.d/qemu-guest-agent + + install -d ${D}${sysconfdir}/udev/rules.d/ + install -m 0644 ${WORKDIR}/qemu-guest-agent.udev ${D}${sysconfdir}/udev/rules.d/60-qemu-guest-agent.rules + + install -d ${D}${systemd_unitdir}/system/ + install -m 0644 ${S}/contrib/systemd/qemu-guest-agent.service ${D}${systemd_unitdir}/system + sed -i -e 's,-/usr/bin/,-${bindir}/,g' ${D}${systemd_unitdir}/system/qemu-guest-agent.service + fi + # ELF binary /usr/share/qemu/s390-netboot.img has relocations in .text + rm ${D}${datadir}/qemu/s390-netboot.img -f + # ELF binary /usr/share/qemu/s390-ccw.img has relocations in .text [textrel] + rm ${D}${datadir}/qemu/s390-ccw.img -f + # We don't support PARISC and these cause strip and SDK relocation errors + rm ${D}${datadir}/qemu/hppa* -f + + # remove icons + rm -rf ${D}${datadir}/icons +} + +do_install:append() { + # Link Xilinx QEMU executables + ln -sf ../xilinx/bin/qemu-system-aarch64 ${D}${bindir}/qemu-system-xilinx-aarch64 + ln -sf ../xilinx/bin/qemu-system-microblazeel ${D}${bindir}/qemu-system-xilinx-microblazeel + + ln -sf ../xilinx/bin/qemu-system-riscv32 ${D}${bindir}/qemu-system-xilinx-riscv32 + ln -sf ../xilinx/bin/qemu-system-riscv64 ${D}${bindir}/qemu-system-xilinx-riscv64 + + # Link ARC (Synopsys) QEMU executables + ln -sf ../synopsys/bin/qemu-system-arc ${D}${bindir}/qemu-system-arc + ln -sf ../synopsys/bin/qemu-system-arc64 ${D}${bindir}/qemu-system-arc64 + + # Link other legacy QEMU executables + ln -sf ../legacy/bin/qemu-system-nios2 ${D}${bindir}/qemu-system-nios2 + ln -sf ../legacy/bin/qemu-system-sparc ${D}${bindir}/qemu-system-sparc +} + +# Disable kvm/virgl/mesa on targets that do not support it +PACKAGECONFIG:remove:darwin = "kvm virglrenderer epoxy gtk+" +PACKAGECONFIG:remove:mingw32 = "kvm virglrenderer epoxy gtk+ pie" + +PACKAGECONFIG[sdl] = "--enable-sdl,--disable-sdl,libsdl2" +PACKAGECONFIG[png] = "--enable-png,--disable-png,libpng" +PACKAGECONFIG[virtfs] = "--enable-virtfs --enable-attr --enable-cap-ng,--disable-virtfs,libcap-ng attr," +PACKAGECONFIG[aio] = "--enable-linux-aio,--disable-linux-aio,libaio," +PACKAGECONFIG[uring] = "--enable-linux-io-uring,--disable-linux-io-uring,liburing" +PACKAGECONFIG[xen] = "--enable-xen,--disable-xen,xen-tools,xen-tools-libxenstore xen-tools-libxenctrl xen-tools-libxenguest" +PACKAGECONFIG[vnc-sasl] = "--enable-vnc --enable-vnc-sasl,--disable-vnc-sasl,cyrus-sasl," +PACKAGECONFIG[vnc-jpeg] = "--enable-vnc --enable-vnc-jpeg,--disable-vnc-jpeg,jpeg," +PACKAGECONFIG[libcurl] = "--enable-curl,--disable-curl,curl," +PACKAGECONFIG[nss] = "--enable-smartcard,--disable-smartcard,nss," +PACKAGECONFIG[curses] = "--enable-curses,--disable-curses,ncurses," +PACKAGECONFIG[gtk+] = "--enable-gtk,--disable-gtk,gtk+3 gettext-native" +PACKAGECONFIG[vte] = "--enable-vte,--disable-vte,vte gettext-native" +PACKAGECONFIG[libcap-ng] = "--enable-cap-ng,--disable-cap-ng,libcap-ng," +PACKAGECONFIG[ssh] = "--enable-libssh,--disable-libssh,libssh," +PACKAGECONFIG[gcrypt] = "--enable-gcrypt,--disable-gcrypt,libgcrypt," +PACKAGECONFIG[nettle] = "--enable-nettle,--disable-nettle,nettle" +PACKAGECONFIG[libusb] = "--enable-libusb,--disable-libusb,libusb1" +PACKAGECONFIG[fdt] = "--enable-fdt,--disable-fdt,dtc" +PACKAGECONFIG[alsa] = "--audio-drv-list=default,,alsa-lib" +PACKAGECONFIG[epoxy] = "--enable-opengl,--disable-opengl,libepoxy" +PACKAGECONFIG[lzo] = "--enable-lzo,--disable-lzo,lzo" +PACKAGECONFIG[dax] = "--enable-libdaxctl,--disable-libdaxctl,ndctl" +PACKAGECONFIG[numa] = "--enable-numa,--disable-numa,numactl" +PACKAGECONFIG[gnutls] = "--enable-gnutls,--disable-gnutls,gnutls" +PACKAGECONFIG[bzip2] = "--enable-bzip2,--disable-bzip2,bzip2" +PACKAGECONFIG[libiscsi] = "--enable-libiscsi,--disable-libiscsi" +PACKAGECONFIG[kvm] = "--enable-kvm,--disable-kvm" +PACKAGECONFIG[virglrenderer] = "--enable-virglrenderer,--disable-virglrenderer,virglrenderer" +# spice will be in meta-networking layer +PACKAGECONFIG[spice] = "--enable-spice,--disable-spice,spice" +# usbredir will be in meta-networking layer +PACKAGECONFIG[dbus-display] = "--enable-dbus-display,--disable-dbus-display,glib-2.0-native,dbus" +PACKAGECONFIG[usb-redir] = "--enable-usb-redir,--disable-usb-redir,usbredir" +PACKAGECONFIG[snappy] = "--enable-snappy,--disable-snappy,snappy" +PACKAGECONFIG[glusterfs] = "--enable-glusterfs,--disable-glusterfs,glusterfs" +PACKAGECONFIG[xkbcommon] = "--enable-xkbcommon,--disable-xkbcommon,libxkbcommon" +PACKAGECONFIG[libudev] = "--enable-libudev,--disable-libudev,udev" +PACKAGECONFIG[attr] = "--enable-attr,--disable-attr,attr," +PACKAGECONFIG[rbd] = "--enable-rbd,--disable-rbd,ceph,ceph" +PACKAGECONFIG[vhost] = "--enable-vhost-net,--disable-vhost-net,," +PACKAGECONFIG[ust] = "--enable-trace-backends=ust,,lttng-ust," +PACKAGECONFIG[pie] = "--enable-pie,--disable-pie,," +PACKAGECONFIG[seccomp] = "--enable-seccomp,--disable-seccomp,libseccomp" +# libnfs is currently provided by meta-kodi +PACKAGECONFIG[libnfs] = "--enable-libnfs,--disable-libnfs,libnfs" +PACKAGECONFIG[pmem] = "--enable-libpmem,--disable-libpmem,pmdk" +PACKAGECONFIG[pulseaudio] = "--enable-pa,--disable-pa,pulseaudio" +PACKAGECONFIG[selinux] = "--enable-selinux,--disable-selinux" +PACKAGECONFIG[bpf] = "--enable-bpf,--disable-bpf,libbpf" +PACKAGECONFIG[capstone] = "--enable-capstone,--disable-capstone" +PACKAGECONFIG[rdma] = "--enable-rdma,--disable-rdma" +PACKAGECONFIG[vde] = "--enable-vde,--disable-vde" +PACKAGECONFIG[fuse] = "--enable-fuse --enable-fuse-lseek,--disable-fuse --disable-fuse-lseek,fuse3" +PACKAGECONFIG[slirp] = "--enable-slirp,--disable-slirp,libslirp" +PACKAGECONFIG[brlapi] = "--enable-brlapi,--disable-brlapi" +PACKAGECONFIG[jack] = "--enable-jack,--disable-jack,jack," +PACKAGECONFIG[debuginfo] = "--enable-libdw,--disable-libdw,elfutils" +PACKAGECONFIG[pipewire] = "--enable-pipewire,--disable-pipewire,pipewire" +PACKAGECONFIG[sndio] = "--enable-sndio,--disable-sndio,sndio" + +INSANE_SKIP:${PN}-common = "arch" diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/qemu.inc b/meta-zephyr-sdk/recipes-devtools/qemu/qemu.inc new file mode 100644 index 00000000..f6d27bb7 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu/qemu.inc @@ -0,0 +1,284 @@ +SUMMARY = "Fast open source processor emulator" +DESCRIPTION = "QEMU is a hosted virtual machine monitor: it emulates the \ +machine's processor through dynamic binary translation and provides a set \ +of different hardware and device models for the machine, enabling it to run \ +a variety of guest operating systems" +HOMEPAGE = "http://qemu.org" +LICENSE = "GPL-2.0-only & LGPL-2.1-only" + +DEPENDS += "bison-native meson-native ninja-native" + +RDEPENDS:${PN}-ptest = "bash" + +require qemu-targets.inc +# https://gitlab.com/qemu-project/qemu/-/commit/81e2b198a8cb4ee5fdf108bd438f44b193ee3a36 means +# we need a full python3-native setup +inherit pkgconfig ptest update-rc.d systemd python3native + +LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ + file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" + +SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \ + file://powerpc_rom.bin \ + file://run-ptest \ + file://fix-strerrorname_np.patch \ + file://0001-qemu-Add-addition-environment-space-to-boot-loader-q.patch \ + file://0002-apic-fixup-fallthrough-to-PIC.patch \ + file://0004-qemu-Do-not-include-file-if-not-exists.patch \ + file://0005-qemu-Add-some-user-space-mmap-tweaks-to-address-musl.patch \ + file://0006-qemu-Determinism-fixes.patch \ + file://0007-tests-meson.build-use-relative-path-to-refer-to-file.patch \ + file://0008-Define-MAP_SYNC-and-MAP_SHARED_VALIDATE-on-needed-li.patch \ + file://0010-configure-lookup-meson-exutable-from-PATH.patch \ + file://0011-qemu-Ensure-pip-and-the-python-venv-aren-t-used-for-.patch \ + file://0001-sched_attr-Do-not-define-for-glibc-2.41.patch \ + file://qemu-guest-agent.init \ + file://qemu-guest-agent.udev \ + " +UPSTREAM_CHECK_REGEX = "qemu-(?P\d+(\.\d+)+)\.tar" + +SRC_URI[sha256sum] = "f859f0bc65e1f533d040bbe8c92bcfecee5af2c921a6687c652fb44d089bd894" + +CVE_STATUS[CVE-2007-0998] = "not-applicable-config: The VNC server can expose host files uder some circumstances. We don't enable it by default." + +# https://bugzilla.redhat.com/show_bug.cgi?id=1609015#c11 +CVE_STATUS[CVE-2018-18438] = "disputed: The issues identified by this CVE were determined to not constitute a vulnerability." + +# As per https://bugzilla.redhat.com/show_bug.cgi?id=2203387 +CVE_STATUS[CVE-2023-2680] = "not-applicable-platform: RHEL specific issue." + +# NVD DB has this CVE as version-less (with "-") +CVE_STATUS[CVE-2024-6505] = "fixed-version: this CVE is fixed since 9.1.0" + +COMPATIBLE_HOST:mipsarchn32 = "null" +COMPATIBLE_HOST:mipsarchn64 = "null" +COMPATIBLE_HOST:riscv32 = "null" + +# Per https://lists.nongnu.org/archive/html/qemu-devel/2020-09/msg03873.html +# upstream states qemu doesn't work without optimization +DEBUG_BUILD = "0" + +do_install:append() { + # Prevent QA warnings about installed ${localstatedir}/run + if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi +} + +do_install_ptest() { + cp -rL ${B}/tests ${D}${PTEST_PATH} + find ${D}${PTEST_PATH}/tests -type f -name "*.[Sshcodp]" | xargs -i rm -rf {} + + # Don't check the file genreated by configure + sed -i -e "1s,#!/usr/bin/bash,#!${base_bindir}/bash," ${D}${PTEST_PATH}/tests/data/acpi/disassemle-aml.sh + + # Strip the paths from the QEMU variable, we can use PATH + makfiles=$(find ${D}${PTEST_PATH} -name "*.mak") + sed -i -e "s#^QEMU=.*/qemu-#QEMU=qemu-#g" $makfiles + + # Strip compiler flags as they break reproducibility + sed -i -e "s,^CC=.*,CC=gcc," \ + -e "s,^CCAS=.*,CCAS=gcc," \ + -e "s,^LD=.*,LD=ld," $makfiles + + # Update SRC_PATH variable to the right place on target + sed -i -e "s#^SRC_PATH=.*#SRC_PATH=${PTEST_PATH}#g" $makfiles + + # https://gitlab.com/qemu-project/qemu/-/issues/1403 + rm ${D}${PTEST_PATH}/tests/unit/test-io-channel-command +} + +EXTRA_OECONF = " \ + --prefix=${prefix} \ + --bindir=${bindir} \ + --includedir=${includedir} \ + --libdir=${libdir} \ + --mandir=${mandir} \ + --datadir=${datadir} \ + --docdir=${docdir}/${BPN} \ + --sysconfdir=${sysconfdir} \ + --libexecdir=${libexecdir} \ + --localstatedir=${localstatedir} \ + --with-suffix=${BPN} \ + --disable-strip \ + --disable-werror \ + --extra-cflags='${CFLAGS}' \ + --extra-ldflags='${LDFLAGS}' \ + --disable-download \ + --disable-docs \ + --host-cc='${BUILD_CC}' \ + --disable-af-xdp \ + ${PACKAGECONFIG_CONFARGS} \ + " +QEMU_TARGETS = "aarch64-softmmu arm-softmmu i386-softmmu mips-softmmu mipsel-softmmu xtensa-softmmu riscv32-softmmu riscv64-softmmu x86_64-softmmu" + +EXTRA_OECONF:append:class-target = " --target-list=${QEMU_TARGETS}" +EXTRA_OECONF:append:class-target:mipsarcho32 = "${@bb.utils.contains('BBEXTENDCURR', 'multilib', ' --disable-capstone', '', d)}" +EXTRA_OECONF:append:class-nativesdk = " --target-list=${QEMU_TARGETS}" + + +EXTRA_OECONF:append:class-target = " --cross-prefix=${HOST_PREFIX}" +EXTRA_OECONF:append:class-nativesdk = " --cross-prefix=${HOST_PREFIX}" + +B = "${WORKDIR}/build" + +#EXTRA_OECONF:append = " --python=${HOSTTOOLS_DIR}/python3" + +do_configure:prepend:class-native() { + # Append build host pkg-config paths for native target since the host may provide sdl + BHOST_PKGCONFIG_PATH=$(PATH=/usr/bin:/bin pkg-config --variable pc_path pkg-config || echo "") + if [ ! -z "$BHOST_PKGCONFIG_PATH" ]; then + export PKG_CONFIG_PATH=$PKG_CONFIG_PATH:$BHOST_PKGCONFIG_PATH + fi +} + +do_configure() { + export PKG_CONFIG=pkg-config + ${S}/configure ${EXTRA_OECONF} +} +do_configure[cleandirs] += "${B}" + +do_install () { + export STRIP="" + oe_runmake 'DESTDIR=${D}' install + + # If we built the guest agent, also install startup/udev rules + if [ -e "${D}${bindir}/qemu-ga" ]; then + install -d ${D}${sysconfdir}/init.d/ + install -m 0755 ${WORKDIR}/qemu-guest-agent.init ${D}${sysconfdir}/init.d/qemu-guest-agent + sed -i 's:@bindir@:${bindir}:' ${D}${sysconfdir}/init.d/qemu-guest-agent + + install -d ${D}${sysconfdir}/udev/rules.d/ + install -m 0644 ${WORKDIR}/qemu-guest-agent.udev ${D}${sysconfdir}/udev/rules.d/60-qemu-guest-agent.rules + + install -d ${D}${systemd_unitdir}/system/ + install -m 0644 ${S}/contrib/systemd/qemu-guest-agent.service ${D}${systemd_unitdir}/system + sed -i -e 's,-/usr/bin/,-${bindir}/,g' ${D}${systemd_unitdir}/system/qemu-guest-agent.service + fi + # ELF binary /usr/share/qemu/s390-netboot.img has relocations in .text + rm ${D}${datadir}/qemu/s390-netboot.img -f + # ELF binary /usr/share/qemu/s390-ccw.img has relocations in .text [textrel] + rm ${D}${datadir}/qemu/s390-ccw.img -f + # We don't support PARISC and these cause strip and SDK relocation errors + rm ${D}${datadir}/qemu/hppa* -f +} + +do_install:append() { + # Link Xilinx QEMU executables + ln -sf ../xilinx/bin/qemu-system-aarch64 ${D}${bindir}/qemu-system-xilinx-aarch64 + ln -sf ../xilinx/bin/qemu-system-microblazeel ${D}${bindir}/qemu-system-xilinx-microblazeel + + # Link ARC (Synopsys) QEMU executables + ln -sf ../synopsys/bin/qemu-system-arc ${D}${bindir}/qemu-system-arc + ln -sf ../synopsys/bin/qemu-system-arc64 ${D}${bindir}/qemu-system-arc64 + + # Link other legacy QEMU executables + ln -sf ../legacy/bin/qemu-system-nios2 ${D}${bindir}/qemu-system-nios2 + ln -sf ../legacy/bin/qemu-system-sparc ${D}${bindir}/qemu-system-sparc +} + +# Disable kvm/virgl/mesa on targets that do not support it +PACKAGECONFIG:remove:darwin = "kvm virglrenderer epoxy gtk+" +PACKAGECONFIG:remove:mingw32 = "kvm virglrenderer epoxy gtk+ pie" + +PACKAGECONFIG[sdl] = "--enable-sdl,--disable-sdl,libsdl2" +PACKAGECONFIG[png] = "--enable-png,--disable-png,libpng" +PACKAGECONFIG[virtfs] = "--enable-virtfs --enable-attr --enable-cap-ng,--disable-virtfs,libcap-ng attr," +PACKAGECONFIG[aio] = "--enable-linux-aio,--disable-linux-aio,libaio," +PACKAGECONFIG[uring] = "--enable-linux-io-uring,--disable-linux-io-uring,liburing" +PACKAGECONFIG[xen] = "--enable-xen,--disable-xen,xen-tools,xen-tools-libxenstore xen-tools-libxenctrl xen-tools-libxenguest" +PACKAGECONFIG[vnc-sasl] = "--enable-vnc --enable-vnc-sasl,--disable-vnc-sasl,cyrus-sasl," +PACKAGECONFIG[vnc-jpeg] = "--enable-vnc --enable-vnc-jpeg,--disable-vnc-jpeg,jpeg," +PACKAGECONFIG[libcurl] = "--enable-curl,--disable-curl,curl," +PACKAGECONFIG[nss] = "--enable-smartcard,--disable-smartcard,nss," +PACKAGECONFIG[curses] = "--enable-curses,--disable-curses,ncurses," +PACKAGECONFIG[gtk+] = "--enable-gtk,--disable-gtk,gtk+3 gettext-native" +PACKAGECONFIG[vte] = "--enable-vte,--disable-vte,vte gettext-native" +PACKAGECONFIG[libcap-ng] = "--enable-cap-ng,--disable-cap-ng,libcap-ng," +PACKAGECONFIG[ssh] = "--enable-libssh,--disable-libssh,libssh," +PACKAGECONFIG[gcrypt] = "--enable-gcrypt,--disable-gcrypt,libgcrypt," +PACKAGECONFIG[nettle] = "--enable-nettle,--disable-nettle,nettle" +PACKAGECONFIG[libusb] = "--enable-libusb,--disable-libusb,libusb1" +PACKAGECONFIG[fdt] = "--enable-fdt,--disable-fdt,dtc" +PACKAGECONFIG[alsa] = "--audio-drv-list=default,,alsa-lib" +PACKAGECONFIG[epoxy] = "--enable-opengl,--disable-opengl,libepoxy" +PACKAGECONFIG[lzo] = "--enable-lzo,--disable-lzo,lzo" +PACKAGECONFIG[dax] = "--enable-libdaxctl,--disable-libdaxctl,ndctl" +PACKAGECONFIG[numa] = "--enable-numa,--disable-numa,numactl" +PACKAGECONFIG[gnutls] = "--enable-gnutls,--disable-gnutls,gnutls" +PACKAGECONFIG[bzip2] = "--enable-bzip2,--disable-bzip2,bzip2" +PACKAGECONFIG[libiscsi] = "--enable-libiscsi,--disable-libiscsi" +PACKAGECONFIG[kvm] = "--enable-kvm,--disable-kvm" +PACKAGECONFIG[virglrenderer] = "--enable-virglrenderer,--disable-virglrenderer,virglrenderer" +# spice will be in meta-networking layer +PACKAGECONFIG[spice] = "--enable-spice,--disable-spice,spice" +# usbredir will be in meta-networking layer +PACKAGECONFIG[dbus-display] = "--enable-dbus-display,--disable-dbus-display,glib-2.0-native,dbus" +PACKAGECONFIG[usb-redir] = "--enable-usb-redir,--disable-usb-redir,usbredir" +PACKAGECONFIG[snappy] = "--enable-snappy,--disable-snappy,snappy" +PACKAGECONFIG[glusterfs] = "--enable-glusterfs,--disable-glusterfs,glusterfs" +PACKAGECONFIG[xkbcommon] = "--enable-xkbcommon,--disable-xkbcommon,libxkbcommon" +PACKAGECONFIG[libudev] = "--enable-libudev,--disable-libudev,udev" +PACKAGECONFIG[attr] = "--enable-attr,--disable-attr,attr," +PACKAGECONFIG[rbd] = "--enable-rbd,--disable-rbd,ceph,ceph" +PACKAGECONFIG[vhost] = "--enable-vhost-net,--disable-vhost-net,," +PACKAGECONFIG[ust] = "--enable-trace-backends=ust,,lttng-ust," +PACKAGECONFIG[pie] = "--enable-pie,--disable-pie,," +PACKAGECONFIG[seccomp] = "--enable-seccomp,--disable-seccomp,libseccomp" +# libnfs is currently provided by meta-kodi +PACKAGECONFIG[libnfs] = "--enable-libnfs,--disable-libnfs,libnfs" +PACKAGECONFIG[pmem] = "--enable-libpmem,--disable-libpmem,pmdk" +PACKAGECONFIG[pulseaudio] = "--enable-pa,--disable-pa,pulseaudio" +PACKAGECONFIG[selinux] = "--enable-selinux,--disable-selinux" +PACKAGECONFIG[bpf] = "--enable-bpf,--disable-bpf,libbpf" +PACKAGECONFIG[capstone] = "--enable-capstone,--disable-capstone" +PACKAGECONFIG[rdma] = "--enable-rdma,--disable-rdma" +PACKAGECONFIG[vde] = "--enable-vde,--disable-vde" +PACKAGECONFIG[fuse] = "--enable-fuse --enable-fuse-lseek,--disable-fuse --disable-fuse-lseek,fuse3" +PACKAGECONFIG[slirp] = "--enable-slirp,--disable-slirp,libslirp" +PACKAGECONFIG[brlapi] = "--enable-brlapi,--disable-brlapi" +PACKAGECONFIG[jack] = "--enable-jack,--disable-jack,jack," +PACKAGECONFIG[debuginfo] = "--enable-libdw,--disable-libdw,elfutils" +PACKAGECONFIG[pipewire] = "--enable-pipewire,--disable-pipewire,pipewire" +PACKAGECONFIG[sndio] = "--enable-sndio,--disable-sndio,sndio" + +INSANE_SKIP:${PN}-common = "arch" + +FILES:${PN} += "${datadir}/icons" + +# For user who want to install all arch packages +PACKAGES =+ "${PN}-common" +RDEPENDS:${PN} += "${PN}-common" + +ALLOW_EMPTY:${PN} = "1" +FILES:${PN} = "" + +FILES:${PN}-common = "${bindir}/* ${includedir}/* ${libexecdir}/* ${datadir}/* ${localstatedir}" + +PACKAGES_DYNAMIC += "^${PN}-user-.* ^${PN}-system-.*" + +#PACKAGESPLITFUNCS =+ "split_qemu_packages" + +python split_qemu_packages () { + archdir = d.expand('${bindir}/') + subpackages = do_split_packages(d, archdir, r'^qemu-system-(.*)$', '${PN}-system-%s', 'QEMU full system emulation binaries(%s)' , prepend=True, extra_depends='${PN}-common') + + subpackages += do_split_packages(d, archdir, r'^qemu-((?!system|edid|ga|img|io|nbd|pr-helper|storage-daemon).*)$', '${PN}-user-%s', 'QEMU full user emulation binaries(%s)' , prepend=True, extra_depends='${PN}-common') + if subpackages: + d.appendVar('RDEPENDS:' + d.getVar('PN'), ' ' + ' '.join(subpackages)) +} + +# Put the guest agent in a separate package +PACKAGES =+ "${PN}-guest-agent" +SUMMARY:${PN}-guest-agent = "QEMU guest agent" +FILES:${PN}-guest-agent += " \ + ${bindir}/qemu-ga \ + ${sysconfdir}/udev/rules.d/60-qemu-guest-agent.rules \ + ${sysconfdir}/init.d/qemu-guest-agent \ + ${systemd_unitdir}/system/qemu-guest-agent.service \ +" + +INITSCRIPT_PACKAGES = "${PN}-guest-agent" +INITSCRIPT_NAME:${PN}-guest-agent = "qemu-guest-agent" +INITSCRIPT_PARAMS:${PN}-guest-agent = "defaults" + +SYSTEMD_PACKAGES = "${PN}-guest-agent" +SYSTEMD_SERVICE:${PN}-guest-agent = "qemu-guest-agent.service" diff --git a/meta-zephyr-sdk/recipes-devtools/qemu_arc/files/cross.patch b/meta-zephyr-sdk/recipes-devtools/qemu_arc/files/cross.patch new file mode 100644 index 00000000..64012894 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu_arc/files/cross.patch @@ -0,0 +1,35 @@ +From 0f45ccc448ff392e9844ea7f66bb697f334eefa7 Mon Sep 17 00:00:00 2001 +From: Anas Nashif +Date: Sun, 16 Feb 2025 07:44:37 -0500 +Subject: [PATCH] cross patch + +Signed-off-by: Anas Nashif +--- + configure | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/configure b/configure +index 529d28fa5a..7ecbe94dc0 100755 +--- a/configure ++++ b/configure +@@ -3122,7 +3122,6 @@ if test "$skip_meson" = no; then + fi + echo "strip = [$(meson_quote $strip)]" >> $cross + echo "windres = [$(meson_quote $windres)]" >> $cross +- if test "$cross_compile" = "yes"; then + cross_arg="--cross-file config-meson.cross" + echo "[host_machine]" >> $cross + echo "system = '$targetos'" >> $cross +@@ -3140,9 +3139,6 @@ if test "$skip_meson" = no; then + else + echo "endian = 'little'" >> $cross + fi +- else +- cross_arg="--native-file config-meson.cross" +- fi + mv $cross config-meson.cross + + rm -rf meson-private meson-info meson-logs +-- +2.43.0 + diff --git a/meta-zephyr-sdk/recipes-devtools/arc_qemu/arc-qemu_git.bb b/meta-zephyr-sdk/recipes-devtools/qemu_arc/qemu-arc_git.bb similarity index 97% rename from meta-zephyr-sdk/recipes-devtools/arc_qemu/arc-qemu_git.bb rename to meta-zephyr-sdk/recipes-devtools/qemu_arc/qemu-arc_git.bb index 82dc8a52..dcf336a8 100644 --- a/meta-zephyr-sdk/recipes-devtools/arc_qemu/arc-qemu_git.bb +++ b/meta-zephyr-sdk/recipes-devtools/qemu_arc/qemu-arc_git.bb @@ -1,12 +1,12 @@ DEPENDS = "glib-2.0 zlib pixman gnutls libtasn1 dtc ninja-native meson-native" LICENSE = "GPLv2" -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" +#FILESEXTRAPATHS_prepend := "${THISDIR}/files:" LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" SRCREV = "b46c4ec2d07a4c56c426b3d48195d6f2902226e5" -SRC_URI = "git://github.com/foss-for-synopsys-dwc-arc-processors/qemu.git;protocol=https;nobranch=1 \ +SRC_URI = "gitsm://github.com/foss-for-synopsys-dwc-arc-processors/qemu.git;protocol=https;nobranch=1 \ file://cross.patch \ " @@ -199,7 +199,7 @@ QEMU_FLAGS = "--disable-docs --disable-sdl --disable-debug-info --disable-cap- --disable-tpm --disable-numa --disable-glusterfs \ --disable-virtfs --disable-xen --disable-curl --disable-attr --disable-curses --disable-iconv \ --disable-kvm --disable-parallels --disable-replication \ - --disable-live-block-migration --disable-dmg --disable-fdt --disable-blobs \ + --disable-live-block-migration --disable-dmg --disable-fdt --disable-blobs --disable-werror \ " # NOTE: Once --prefix is set, QEMU configure script automatically figures out adequate sysconfdir, @@ -223,12 +223,14 @@ do_configure() { unset firmwarepath unset localedir - ${S}/configure ${QEMU_FLAGS} --target-list="${QEMUS_BUILT}" --prefix=${arc_qemu_prefix} \ + ${S}/configure ${QEMU_FLAGS} --target-list="${QEMUS_BUILT}" --prefix=${arc_qemu_prefix} \ --meson=meson } -FILES_${PN} = " \ - /opt/zephyr-sdk \ + +FILES:${PN} = " \ + ${arc_qemu_prefix} \ " + INSANE_SKIP_${PN} = "already-stripped" diff --git a/meta-zephyr-sdk/recipes-devtools/qemu_legacy/files/cross.patch b/meta-zephyr-sdk/recipes-devtools/qemu_legacy/files/cross.patch new file mode 100644 index 00000000..a7735a53 --- /dev/null +++ b/meta-zephyr-sdk/recipes-devtools/qemu_legacy/files/cross.patch @@ -0,0 +1,22 @@ +diff --git a/configure b/configure +index 7c08c18358..0613279f91 100755 +--- a/configure ++++ b/configure +@@ -3118,7 +3118,6 @@ if test "$skip_meson" = no; then + fi + echo "strip = [$(meson_quote $strip)]" >> $cross + echo "windres = [$(meson_quote $windres)]" >> $cross +- if test "$cross_compile" = "yes"; then + cross_arg="--cross-file config-meson.cross" + echo "[host_machine]" >> $cross + echo "system = '$targetos'" >> $cross +@@ -3136,9 +3135,6 @@ if test "$skip_meson" = no; then + else + echo "endian = 'little'" >> $cross + fi +- else +- cross_arg="--native-file config-meson.cross" +- fi + mv $cross config-meson.cross + + rm -rf meson-private meson-info meson-logs diff --git a/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb b/meta-zephyr-sdk/recipes-devtools/qemu_legacy/qemu-legacy_git.bb similarity index 87% rename from meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb rename to meta-zephyr-sdk/recipes-devtools/qemu_legacy/qemu-legacy_git.bb index 36f9dfb4..e64b98c7 100644 --- a/meta-zephyr-sdk/recipes-devtools/qemu/zephyr-qemu_git.bb +++ b/meta-zephyr-sdk/recipes-devtools/qemu_legacy/qemu-legacy_git.bb @@ -1,26 +1,22 @@ DEPENDS = "glib-2.0 zlib pixman gnutls libtasn1 dtc ninja-native meson-native" LICENSE = "GPLv2" -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" SRCREV = "06740e68dcb2c2ae168875a730f233f5661eb8b6" -SRC_URI = "git://github.com/zephyrproject-rtos/qemu.git;protocol=https;nobranch=1 \ - https://github.com/zephyrproject-rtos/seabios/releases/download/zephyr-v1.0.0/bios-128k.bin;name=bios-128k \ - https://github.com/zephyrproject-rtos/seabios/releases/download/zephyr-v1.0.0/bios-256k.bin;name=bios-256k \ +SRC_URI = "gitsm://github.com/zephyrproject-rtos/qemu.git;protocol=https;nobranch=1 \ file://cross.patch \ " -SRC_URI[bios-128k.sha256sum] = "943c077c3925ee7ec85601fb12937a0988c478a95523a628cd7e61c639dd6e81" -SRC_URI[bios-256k.sha256sum] = "19133167cc0bfb2a9e8ce9567efcd013a4ab80d2f3522ac66df0c23c68c18984" - BBCLASSEXTEND = "native nativesdk" INHIBIT_PACKAGE_DEBUG_SPLIT = "1" INHIBIT_PACKAGE_STRIP = "1" S = "${WORKDIR}/git" +legacy_prefix = "${base_prefix}/usr/legacy" + inherit autotools pkgconfig # Standard options: @@ -199,43 +195,34 @@ inherit autotools pkgconfig #--disable-fdt: Cannot use if supporting ARM #--disable-kvm: AArch64 has a QEMU/KVM board -QEMUS_BUILT = "aarch64-softmmu arm-softmmu i386-softmmu mips-softmmu mipsel-softmmu nios2-softmmu xtensa-softmmu riscv32-softmmu riscv64-softmmu sparc-softmmu x86_64-softmmu" +QEMUS_BUILT = "nios2-softmmu sparc-softmmu" QEMU_FLAGS = "--disable-docs --disable-sdl --disable-debug-info --disable-cap-ng \ --disable-libnfs --disable-libusb --disable-libiscsi --disable-usb-redir --disable-linux-aio\ --disable-guest-agent --disable-libssh --disable-vnc-png --disable-seccomp \ --disable-tpm --disable-numa --disable-glusterfs \ --disable-virtfs --disable-xen --disable-curl --disable-attr --disable-curses --disable-iconv \ --disable-parallels --disable-replication \ - --disable-live-block-migration --disable-dmg \ + --disable-live-block-migration --disable-dmg --disable-werror \ " -copy_seabios() { - cp ${WORKDIR}/bios-128k.bin ${S}/pc-bios/bios.bin - cp ${WORKDIR}/bios-256k.bin ${S}/pc-bios/bios-256k.bin -} - -do_unpack_append() { - bb.build.exec_func('copy_seabios', d) -} - do_configure() { - ${S}/configure ${QEMU_FLAGS} --target-list="${QEMUS_BUILT}" --prefix=${prefix} \ - --sysconfdir=${sysconfdir} --libexecdir=${libexecdir} --localstatedir=${localstatedir} \ - --meson=meson -} - -do_install_append() { - # Link Xilinx QEMU executables - ln -sf ../xilinx/bin/qemu-system-aarch64 ${D}${bindir}/qemu-system-xilinx-aarch64 - ln -sf ../xilinx/bin/qemu-system-microblazeel ${D}${bindir}/qemu-system-xilinx-microblazeel - - # Link ARC (Synopsys) QEMU executables - ln -sf ../synopsys/bin/qemu-system-arc ${D}${bindir}/qemu-system-arc - ln -sf ../synopsys/bin/qemu-system-arc64 ${D}${bindir}/qemu-system-arc64 + unset libdir + unset libexecdir + unset includedir + unset bindir + unset mandir + unset datadir + unset docdir + unset sysconfdir + unset local_statedir + unset firmwarepath + unset localedir + ${S}/configure ${QEMU_FLAGS} --target-list="${QEMUS_BUILT}" --prefix=${legacy_prefix} \ + --meson=meson } -FILES_${PN} = " \ - /opt/zephyr-sdk \ +FILES:${PN} = " \ + ${legacy_prefix} \ " -INSANE_SKIP_${PN} = "already-stripped" +INSANE_SKIP:${PN} = "already-stripped" diff --git a/meta-zephyr-sdk/recipes-devtools/xilinx_qemu/files/0001-Revert-target-arm-Revert-back-to-YIELD-for-WFI.patch b/meta-zephyr-sdk/recipes-devtools/qemu_xilinx/files/0001-Revert-target-arm-Revert-back-to-YIELD-for-WFI.patch similarity index 100% rename from meta-zephyr-sdk/recipes-devtools/xilinx_qemu/files/0001-Revert-target-arm-Revert-back-to-YIELD-for-WFI.patch rename to meta-zephyr-sdk/recipes-devtools/qemu_xilinx/files/0001-Revert-target-arm-Revert-back-to-YIELD-for-WFI.patch diff --git a/meta-zephyr-sdk/recipes-devtools/xilinx_qemu/files/0002-Enable-WFI-CPU-halting-in-icount-mode.patch b/meta-zephyr-sdk/recipes-devtools/qemu_xilinx/files/0002-Enable-WFI-CPU-halting-in-icount-mode.patch similarity index 100% rename from meta-zephyr-sdk/recipes-devtools/xilinx_qemu/files/0002-Enable-WFI-CPU-halting-in-icount-mode.patch rename to meta-zephyr-sdk/recipes-devtools/qemu_xilinx/files/0002-Enable-WFI-CPU-halting-in-icount-mode.patch diff --git a/meta-zephyr-sdk/recipes-devtools/xilinx_qemu/xilinx-qemu_git.bb b/meta-zephyr-sdk/recipes-devtools/qemu_xilinx/qemu-xilinx_git.bb similarity index 96% rename from meta-zephyr-sdk/recipes-devtools/xilinx_qemu/xilinx-qemu_git.bb rename to meta-zephyr-sdk/recipes-devtools/qemu_xilinx/qemu-xilinx_git.bb index 5773bcb5..cdcbcb4a 100644 --- a/meta-zephyr-sdk/recipes-devtools/xilinx_qemu/xilinx-qemu_git.bb +++ b/meta-zephyr-sdk/recipes-devtools/qemu_xilinx/qemu-xilinx_git.bb @@ -1,12 +1,11 @@ DEPENDS = "glib-2.0 zlib pixman gnutls dtc" LICENSE = "GPLv2" -FILESEXTRAPATHS_prepend := "${THISDIR}/files:" LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" SRCREV = "e40b634b24b37fe521bb2857c5e93ee1d30c2e37" -SRC_URI = "git://github.com/Xilinx/qemu.git;protocol=https \ +SRC_URI = "gitsm://github.com/Xilinx/qemu.git;protocol=https;nobranch=1 \ file://0001-Revert-target-arm-Revert-back-to-YIELD-for-WFI.patch \ file://0002-Enable-WFI-CPU-halting-in-icount-mode.patch \ " @@ -201,7 +200,7 @@ QEMU_FLAGS = "--disable-docs --disable-sdl --disable-debug-info --disable-cap- --disable-tpm --disable-numa --disable-glusterfs --disable-blobs \ --disable-virtfs --disable-xen --disable-curl --disable-attr --disable-curses --disable-iconv \ --disable-kvm --disable-sheepdog --disable-parallels --disable-replication \ - --disable-live-block-migration --disable-dmg \ + --disable-live-block-migration --disable-dmg --disable-werror \ " # NOTE: Once --prefix is set, QEMU configure script automatically figures out adequate sysconfdir, @@ -211,11 +210,22 @@ QEMU_FLAGS = "--disable-docs --disable-sdl --disable-debug-info --disable-cap- # /usr. do_configure() { + unset libdir + unset libexecdir + unset includedir + unset bindir + unset mandir + unset datadir + unset docdir + unset sysconfdir + unset local_statedir + unset firmwarepath + unset localedir ${S}/configure ${QEMU_FLAGS} --target-list="${QEMUS_BUILT}" --prefix=${xilinx_qemu_prefix} } -FILES_${PN} = " \ - /opt/zephyr-sdk \ +FILES:${PN} = " \ + ${xilinx_qemu_prefix} \ " INSANE_SKIP_${PN} = "already-stripped" diff --git a/meta-zephyr-sdk/recipes-hosttools/bossa/bossa_git.bb b/meta-zephyr-sdk/recipes-hosttools/bossa/bossa_git.bb index 92c83549..b3193652 100644 --- a/meta-zephyr-sdk/recipes-hosttools/bossa/bossa_git.bb +++ b/meta-zephyr-sdk/recipes-hosttools/bossa/bossa_git.bb @@ -6,14 +6,14 @@ HOMEPAGE = "https://github.com/shumatech/BOSSA" # sudo apt-get install wx2.8-headers libwxgtk2.8-0 libwxgtk2.8-dev # -LICENSE = "BSD" +LICENSE = "BSD-3-Clause" LIC_FILES_CHKSUM = "file://LICENSE;md5=bcf9399f7b9b96149837290bcdc3ad39" DEPENDS = "readline" PR = "r0" SRCREV = "3532de82efd28fadbabc2b258d84dddf14298107" -SRC_URI = "git://github.com/shumatech/BOSSA.git;protocol=https \ +SRC_URI = "git://github.com/shumatech/BOSSA.git;protocol=https;branch=master \ file://0001-Wait-for-EEFC-flash-to-complete-operations-before-re.patch \ file://0001-Flash.h-Add-flash-override-samba-error.patch \ file://0002-CalwFlash-Add-SAM4L-Flashcalw-controller.patch \ diff --git a/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb b/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb index 396251dc..50696643 100644 --- a/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb +++ b/meta-zephyr-sdk/recipes-hosttools/hosttools/hosttools-tarball.bb @@ -6,23 +6,24 @@ LIC_FILES_CHKSUM = "file://${COREBASE}/meta/COPYING.MIT;md5=3da9cfbcb788c80a0384 TOOLCHAIN_TARGET_TASK ?= "" TOOLCHAIN_HOST_TASK ?= "\ - nativesdk-arc-qemu \ - nativesdk-zephyr-qemu \ - nativesdk-xilinx-qemu \ - nativesdk-openocd \ nativesdk-bossa \ + nativesdk-openocd \ nativesdk-dtc \ + nativesdk-qemu-arc \ + nativesdk-qemu-legacy \ + nativesdk-qemu-xilinx \ + nativesdk-qemu-zephyr \ " TOOLCHAIN_OUTPUTNAME ?= "${DISTRO}-${SDKMACHINE}-hosttools-standalone-${DISTRO_VERSION}" RDEPENDS = "${TOOLCHAIN_HOST_TASK}" -inherit meta +#inherit meta inherit populate_sdk inherit toolchain-scripts -create_sdk_files_append () { +create_sdk_files:append () { rm -f ${SDK_OUTPUT}/${SDKPATH}/site-config-* rm -f ${SDK_OUTPUT}/${SDKPATH}/environment-setup-* rm -f ${SDK_OUTPUT}/${SDKPATH}/version-* diff --git a/meta-zephyr-sdk/recipes-hosttools/openocd/openocd_git.bb b/meta-zephyr-sdk/recipes-hosttools/openocd/openocd_git.bb index 7b2ff114..c5c0618d 100644 --- a/meta-zephyr-sdk/recipes-hosttools/openocd/openocd_git.bb +++ b/meta-zephyr-sdk/recipes-hosttools/openocd/openocd_git.bb @@ -1,12 +1,12 @@ LICENSE = "GPLv2" LIC_FILES_CHKSUM = "file://LICENSES/preferred/GPL-2.0;md5=71ce3767d42ca42cd575f91c56eefe79" -DEPENDS = "libusb-compat hidapi libftdi" +DEPENDS = "hidapi libftdi" RDEPENDS_${PN} = "libusb1 hidapi" SRC_URI = " \ - git://github.com/zephyrproject-rtos/openocd.git;protocol=https;nobranch=1 \ + gitsm://github.com/zephyrproject-rtos/openocd.git;protocol=https;nobranch=1 \ " -SRCREV = "b6f95a16c1360e347a06faf91befd122c0d15864" +SRCREV = "51dbf7050b34a40f28c3fc7b5f4e49326c3e3aa6" S = "${WORKDIR}/git" @@ -14,7 +14,7 @@ inherit pkgconfig autotools gettext BBCLASSEXTEND += "nativesdk" -EXTRA_OECONF = "--enable-ftdi --enable-cmsis-dap --enable-jlink --enable-stlink --disable-doxygen-html " +EXTRA_OECONF = "--enable-ftdi --enable-cmsis-dap --enable-jlink --enable-stlink --disable-doxygen-html --disable-git-update" do_configure() { cd ${S} diff --git a/meta-zephyr-sdk/recipes-kernel/kmod/kmod_git.bbappend b/meta-zephyr-sdk/recipes-kernel/kmod/kmod_git.bbappend deleted file mode 100644 index 0d0c76f9..00000000 --- a/meta-zephyr-sdk/recipes-kernel/kmod/kmod_git.bbappend +++ /dev/null @@ -1 +0,0 @@ -BBCLASSEXTEND = "nativesdk" diff --git a/meta-zephyr-sdk/recipes-support/hidapi/hidapi_git.bb b/meta-zephyr-sdk/recipes-support/hidapi/hidapi_git.bb index d85081b5..ca672e66 100644 --- a/meta-zephyr-sdk/recipes-support/hidapi/hidapi_git.bb +++ b/meta-zephyr-sdk/recipes-support/hidapi/hidapi_git.bb @@ -12,7 +12,7 @@ BBCLASSEXTEND += " native nativesdk" inherit autotools pkgconfig -SRC_URI = "git://github.com/libusb/hidapi.git;protocol=https" -PV = "0.9.0" -SRCREV = "7da5cc91fc0d2dbe4df4f08cd31f6ca1a262418f" +SRC_URI = "git://github.com/libusb/hidapi.git;protocol=https;branch=master" +PV = "0.14.0" +SRCREV = "d3013f0af3f4029d82872c1a9487ea461a56dee4" S = "${WORKDIR}/git" diff --git a/meta-zephyr-sdk/recipes-support/libpcre/libpcre2_%.bbappend b/meta-zephyr-sdk/recipes-support/libpcre/libpcre2_%.bbappend index aa6de52b..8d54baa3 100644 --- a/meta-zephyr-sdk/recipes-support/libpcre/libpcre2_%.bbappend +++ b/meta-zephyr-sdk/recipes-support/libpcre/libpcre2_%.bbappend @@ -1,4 +1,4 @@ # Override the source URL for libpcre2 since the old mirror specified in the # meta layer is no longer available. -SRC_URI_prepend = "https://github.com/PhilipHazel/pcre2/releases/download/pcre2-${PV}/pcre2-${PV}.tar.bz2 " +SRC_URI:prepend = "https://github.com/PhilipHazel/pcre2/releases/download/pcre2-${PV}/pcre2-${PV}.tar.bz2 " diff --git a/meta-zephyr-sdk/recipes-support/libpcre/libpcre_%.bbappend b/meta-zephyr-sdk/recipes-support/libpcre/libpcre_%.bbappend index 64e26887..d394f84b 100644 --- a/meta-zephyr-sdk/recipes-support/libpcre/libpcre_%.bbappend +++ b/meta-zephyr-sdk/recipes-support/libpcre/libpcre_%.bbappend @@ -1,4 +1,4 @@ # Override the source URL for libpcre since the old mirror specified in the # meta layer is no longer available. -SRC_URI_prepend = "${SOURCEFORGE_MIRROR}/pcre/pcre-${PV}.tar.bz2 " +SRC_URI:prepend = "${SOURCEFORGE_MIRROR}/pcre/pcre-${PV}.tar.bz2 " diff --git a/meta-zephyr-sdk/recipes-support/libusb/libusb-compat/0001-usb.h-Include-sys-types.h.patch b/meta-zephyr-sdk/recipes-support/libusb/libusb-compat/0001-usb.h-Include-sys-types.h.patch index f4f759c8..c6149c4b 100644 --- a/meta-zephyr-sdk/recipes-support/libusb/libusb-compat/0001-usb.h-Include-sys-types.h.patch +++ b/meta-zephyr-sdk/recipes-support/libusb/libusb-compat/0001-usb.h-Include-sys-types.h.patch @@ -1,24 +1,9 @@ -From 840795dcb48214b74cfde75e7ce5e8a1a6c64a46 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Thu, 2 Apr 2015 19:18:45 -0700 -Subject: [PATCH] usb.h: Include sys/types.h - -We need the definitions for things like u_intX_t - -Upstream-Status: Pending - -Signed-off-by: Khem Raj - ---- - libusb/usb.h | 2 ++ - 1 file changed, 2 insertions(+) - diff --git a/libusb/usb.h b/libusb/usb.h -index fa0e6c6..4e88eb8 100644 +index ea62543..4f1752d 100644 --- a/libusb/usb.h +++ b/libusb/usb.h -@@ -45,6 +45,8 @@ typedef unsigned __int32 uint32_t; - #include +@@ -51,6 +51,8 @@ typedef unsigned __int32 uint32_t; + #include #endif +#include diff --git a/meta-zephyr-sdk/recipes-support/libusb/libusb-compat_0.1.7.bb b/meta-zephyr-sdk/recipes-support/libusb/libusb-compat_0.1.8.bb similarity index 93% rename from meta-zephyr-sdk/recipes-support/libusb/libusb-compat_0.1.7.bb rename to meta-zephyr-sdk/recipes-support/libusb/libusb-compat_0.1.8.bb index 21fa478b..1c8e8120 100644 --- a/meta-zephyr-sdk/recipes-support/libusb/libusb-compat_0.1.7.bb +++ b/meta-zephyr-sdk/recipes-support/libusb/libusb-compat_0.1.8.bb @@ -19,10 +19,10 @@ BBCLASSEXTEND = "native nativesdk" PE = "1" SRC_URI = " \ - git://github.com/libusb/libusb-compat-0.1.git;protocol=https \ + git://github.com/libusb/libusb-compat-0.1.git;protocol=https;branch=master \ file://0001-usb.h-Include-sys-types.h.patch \ " -SRCREV = "4a27760ec5954ec8605e052a3207afbe0979eeef" +SRCREV = "3e8a88d296b5405902c22d2ada61937bd9a89415" S = "${WORKDIR}/git" UPSTREAM_CHECK_URI = "https://github.com/libusb/libusb-compat-0.1/releases" @@ -33,7 +33,7 @@ inherit autotools pkgconfig binconfig-disabled lib_package EXTRA_OECONF = "--libdir=${base_libdir}" -do_install_append() { +do_install:append() { install -d ${D}${libdir} if [ ! ${D}${libdir} -ef ${D}${base_libdir} ]; then mv ${D}${base_libdir}/pkgconfig ${D}${libdir} diff --git a/meta-zephyr-sdk/scripts/meta-zephyr-sdk-clone.sh b/meta-zephyr-sdk/scripts/meta-zephyr-sdk-clone.sh index 3dcf564b..41e4898f 100755 --- a/meta-zephyr-sdk/scripts/meta-zephyr-sdk-clone.sh +++ b/meta-zephyr-sdk/scripts/meta-zephyr-sdk-clone.sh @@ -18,7 +18,7 @@ # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. # -POKY_KNOWN_COMMIT=${POKY_COMMIT:-"54488c030cef432c682c2f91b5e3f43dbd560a1c"} +POKY_KNOWN_COMMIT=${POKY_COMMIT:-"80838b8aa5a74bf3ba03dc5934c39192300a69f1"} META_ZEPHYR_SDK_SOURCE=${SDK_SOURCE:-"meta-zephyr-sdk"} META_POKY_SOURCE=${POKY_SOURCE:-"poky"} META_ZEPHYR_SDK_SOURCE=$(readlink -f $META_ZEPHYR_SDK_SOURCE) diff --git a/scripts/template_setup_posix b/scripts/template_setup_posix index 71ea4e90..2329d33c 100644 --- a/scripts/template_setup_posix +++ b/scripts/template_setup_posix @@ -237,7 +237,7 @@ if [ "${do_hosttools}" = "y" ]; then echo "Installing host tools ..." case ${host} in linux-*) - ./zephyr-sdk-${HOSTTYPE}-hosttools-standalone-0.9.sh -y -d . &> /dev/null + ./zephyr-sdk-${HOSTTYPE}-hosttools-standalone-0.10.sh -y -d . &> /dev/null assert_rc "ERROR: Host tools installation failed" 30 ;; macos-*)