trusted-firmware-m: platform: nrf5340: fix target configuration

Add configuration of the XL1/XL2 pins that can be done only from secure
code. This configuration enables the low-frequency crystal oscillator
(LFXO) functionality that may be required in the non-secure code image
or in the network core firmware.

Signed-off-by: Andrzej Głąbek <[email protected]>
Change-Id: Ic2cb923aa6049fd37d10e857335354bde78fb50b

Signed-off-by: Ioannis Glaropoulos <[email protected]>

Author: anangl

trusted-firmware-m/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c

@@ -22,7 +22,10 @@
 
 #include <spu.h>
 #include <nrfx.h>
+#include <hal/nrf_gpio.h>
 
+#define PIN_XL1 0
+#define PIN_XL2 1
 
 struct tfm_spm_partition_platform_data_t tfm_peripheral_timer0 = {
         NRF_TIMER0_S_BASE,
@@ -270,6 +273,14 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
     spu_gpio_config_non_secure(0, false);
     spu_gpio_config_non_secure(1, false);
 
+    /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal
+     * oscillator (LFXO) can be used.
+     * This configuration can be done only from secure code, as otherwise those
+     * register fields are not accessible.  That's why it is placed here.
+     */
+    nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
+    nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
+
     return TFM_PLAT_ERR_SUCCESS;
 }