diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index 33b49909f4..31b0e3b60a 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -24,7 +24,15 @@ endif() # At the time of writing there is no systematic way to identify which # NVM technology is used by the SoC from the Kconfig, so we just # hardcode this information here instead. -if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR (TFM_PLATFORM MATCHES "nordic\_nrf\/nrf54l15dk\_nrf54l1[05]\_cpuapp") OR (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$")) +if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR + (NRF_SOC_VARIANT MATCHES "^nrf54lv10a?$") OR + (NRF_SOC_VARIANT MATCHES "^nrf54lm20a?$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54l15dk_nrf54l1[05]_cpuapp") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lv10dk_nrf54lv10a?_cpuapp") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lm20dk_nrf54lm20a?_cpuapp") OR + (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$") OR + (PSA_API_TEST_TARGET MATCHES "^nrf54lv10a?$") OR + (PSA_API_TEST_TARGET MATCHES "^nrf54lm20a?$")) # Maybe we only need to check one of these options but these # variables keep changing so we check both to be future proof set(HAS_RRAMC 1) @@ -136,7 +144,9 @@ if(TFM_SPM_LOG_RAW_ENABLED) cmsis_drivers/Driver_USART.c ${HAL_NORDIC_PATH}/nrfx/drivers/src/nrfx_uarte.c ) +endif() +if(TFM_SPM_LOG_RAW_ENABLED OR SECURE_UART1) target_compile_definitions(platform_s PUBLIC NRF_SECURE_UART_INSTANCE=${NRF_SECURE_UART_INSTANCE} @@ -206,18 +216,52 @@ target_sources(tfm_spm tfm_hal_platform_common.c faults.c target_cfg.c + $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_54l.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_53_91.c> + secure_peripherals_defs.c ) +# Determine the startup file based on SOC variant +if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54l15dk_nrf54l1[05]_cpuapp")) + # nrf54l10 and nrf54l15 share the same startup file + set(startup_file "startup_nrf54lx.c") +elseif((NRF_SOC_VARIANT MATCHES "^nrf54lm20a?$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lm20dk_nrf54lm20a?_cpuapp")) + # nrf54lm20 has its own startup file + set(startup_file "startup_nrf54lm.c") +elseif((NRF_SOC_VARIANT MATCHES "^nrf54lv10a?$") OR + (TFM_PLATFORM MATCHES "nordic_nrf/nrf54lv10dk_nrf54lv10a?_cpuapp")) + # nrf54lv10 has its own startup file + set(startup_file "startup_nrf54lv.c") +else() + # Default to the original startup file for other targets + set(startup_file "startup_${target}.c") +endif() + target_sources(tfm_s PRIVATE - $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_${target}.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/${startup_file}> ) +if(HAS_RRAMC) + target_sources(tfm_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_nrf54l_common.c> + ) +endif() + if(BL2) target_sources(bl2 PRIVATE - $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_${target}.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/${startup_file}> ) + if(HAS_RRAMC) + target_sources(bl2 + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/startup_nrf54l_common.c> + ) + endif() endif() if(NRF_APPROTECT) @@ -244,7 +288,7 @@ install(FILES ${PROJECT_BINARY_DIR}/config_nordic_nrf_spe.cmake ) install(FILES startup.c - startup_${target}.c + ${startup_file} nrfx_glue.c pal_plat_test.c pal_plat_test.h diff --git a/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c new file mode 100644 index 0000000000..9a1aada4d5 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c @@ -0,0 +1,667 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#if TFM_PERIPHERAL_DCNF_SECURE +struct platform_data_t tfm_peripheral_dcnf = { + NRF_DCNF_S_BASE, + NRF_DCNF_S_BASE + (sizeof(NRF_DCNF_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_FPU_SECURE +struct platform_data_t tfm_peripheral_fpu = { + NRF_FPU_S_BASE, + NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_OSCILLATORS_SECURE +struct platform_data_t tfm_peripheral_oscillators = { + NRF_OSCILLATORS_S_BASE, + NRF_OSCILLATORS_S_BASE + (sizeof(NRF_OSCILLATORS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_REGULATORS_SECURE +struct platform_data_t tfm_peripheral_regulators = { + NRF_REGULATORS_S_BASE, + NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_CLOCK_SECURE +struct platform_data_t tfm_peripheral_clock = { + NRF_CLOCK_S_BASE, + NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_POWER_SECURE +struct platform_data_t tfm_peripheral_power = { + NRF_POWER_S_BASE, + NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RESET_SECURE +struct platform_data_t tfm_peripheral_reset = { + NRF_RESET_S_BASE, + NRF_RESET_S_BASE + (sizeof(NRF_RESET_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM0_SECURE +struct platform_data_t tfm_peripheral_spim0 = { + NRF_SPIM0_S_BASE, + NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM00_SECURE +struct platform_data_t tfm_peripheral_spim00 = { + NRF_SPIM00_S_BASE, + NRF_SPIM00_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM20_SECURE +struct platform_data_t tfm_peripheral_spim20 = { + NRF_SPIM20_S_BASE, + NRF_SPIM20_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM21_SECURE +struct platform_data_t tfm_peripheral_spim21 = { + NRF_SPIM21_S_BASE, + NRF_SPIM21_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM22_SECURE +struct platform_data_t tfm_peripheral_spim22 = { + NRF_SPIM22_S_BASE, + NRF_SPIM22_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM23_SECURE +struct platform_data_t tfm_peripheral_spim23 = { + NRF_SPIM23_S_BASE, + NRF_SPIM23_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM30_SECURE +struct platform_data_t tfm_peripheral_spim30 = { + NRF_SPIM30_S_BASE, + NRF_SPIM30_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS0_SECURE +struct platform_data_t tfm_peripheral_spis0 = { + NRF_SPIS0_S_BASE, + NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM0_SECURE +struct platform_data_t tfm_peripheral_twim0 = { + NRF_TWIM0_S_BASE, + NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS0_SECURE +struct platform_data_t tfm_peripheral_twis0 = { + NRF_TWIS0_S_BASE, + NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE0_SECURE +struct platform_data_t tfm_peripheral_uarte0 = { + NRF_UARTE0_S_BASE, + NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM1_SECURE +struct platform_data_t tfm_peripheral_spim1 = { + NRF_SPIM1_S_BASE, + NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS1_SECURE +struct platform_data_t tfm_peripheral_spis1 = { + NRF_SPIS1_S_BASE, + NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM1_SECURE +struct platform_data_t tfm_peripheral_twim1 = { + NRF_TWIM1_S_BASE, + NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS1_SECURE +struct platform_data_t tfm_peripheral_twis1 = { + NRF_TWIS1_S_BASE, + NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE1_SECURE +struct platform_data_t tfm_peripheral_uarte1 = { + NRF_UARTE1_S_BASE, + NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM4_SECURE +struct platform_data_t tfm_peripheral_spim4 = { + NRF_SPIM4_S_BASE, + NRF_SPIM4_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM2_SECURE +struct platform_data_t tfm_peripheral_spim2 = { + NRF_SPIM2_S_BASE, + NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS2_SECURE +struct platform_data_t tfm_peripheral_spis2 = { + NRF_SPIS2_S_BASE, + NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM2_SECURE +struct platform_data_t tfm_peripheral_twim2 = { + NRF_TWIM2_S_BASE, + NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS2_SECURE +struct platform_data_t tfm_peripheral_twis2 = { + NRF_TWIS2_S_BASE, + NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE2_SECURE +struct platform_data_t tfm_peripheral_uarte2 = { + NRF_UARTE2_S_BASE, + NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM3_SECURE +struct platform_data_t tfm_peripheral_spim3 = { + NRF_SPIM3_S_BASE, + NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS3_SECURE +struct platform_data_t tfm_peripheral_spis3 = { + NRF_SPIS3_S_BASE, + NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM3_SECURE +struct platform_data_t tfm_peripheral_twim3 = { + NRF_TWIM3_S_BASE, + NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS3_SECURE +struct platform_data_t tfm_peripheral_twis3 = { + NRF_TWIS3_S_BASE, + NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE3_SECURE +struct platform_data_t tfm_peripheral_uarte3 = { + NRF_UARTE3_S_BASE, + NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE00_SECURE +struct platform_data_t tfm_peripheral_uarte00 = { + NRF_UARTE00_S_BASE, + NRF_UARTE00_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE20_SECURE +struct platform_data_t tfm_peripheral_uarte20 = { + NRF_UARTE20_S_BASE, + NRF_UARTE20_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE21_SECURE +struct platform_data_t tfm_peripheral_uarte21 = { + NRF_UARTE21_S_BASE, + NRF_UARTE21_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE22_SECURE +struct platform_data_t tfm_peripheral_uarte22 = { + NRF_UARTE22_S_BASE, + NRF_UARTE22_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE30_SECURE +struct platform_data_t tfm_peripheral_uarte30 = { + NRF_UARTE30_S_BASE, + NRF_UARTE30_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SAADC_SECURE +struct platform_data_t tfm_peripheral_saadc = { + NRF_SAADC_S_BASE, + NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER0_SECURE +struct platform_data_t tfm_peripheral_timer0 = { + NRF_TIMER0_S_BASE, + NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER00_SECURE +struct platform_data_t tfm_peripheral_timer00 = { + NRF_TIMER00_S_BASE, + NRF_TIMER00_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER10_SECURE +struct platform_data_t tfm_peripheral_timer10 = { + NRF_TIMER10_S_BASE, + NRF_TIMER10_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER20_SECURE +struct platform_data_t tfm_peripheral_timer20 = { + NRF_TIMER20_S_BASE, + NRF_TIMER20_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER21_SECURE +struct platform_data_t tfm_peripheral_timer21 = { + NRF_TIMER21_S_BASE, + NRF_TIMER21_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER22_SECURE +struct platform_data_t tfm_peripheral_timer22 = { + NRF_TIMER22_S_BASE, + NRF_TIMER22_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER23_SECURE +struct platform_data_t tfm_peripheral_timer23 = { + NRF_TIMER23_S_BASE, + NRF_TIMER23_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER24_SECURE +struct platform_data_t tfm_peripheral_timer24 = { + NRF_TIMER24_S_BASE, + NRF_TIMER24_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER1_SECURE +struct platform_data_t tfm_peripheral_timer1 = { + NRF_TIMER1_S_BASE, + NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER2_SECURE +struct platform_data_t tfm_peripheral_timer2 = { + NRF_TIMER2_S_BASE, + NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RTC0_SECURE +struct platform_data_t tfm_peripheral_rtc0 = { + NRF_RTC0_S_BASE, + NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RTC1_SECURE +struct platform_data_t tfm_peripheral_rtc1 = { + NRF_RTC1_S_BASE, + NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_DPPI_SECURE +struct platform_data_t tfm_peripheral_dppi = { + NRF_DPPIC_S_BASE, + NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT_SECURE +struct platform_data_t tfm_peripheral_wdt = { + NRF_WDT_S_BASE, + NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT0_SECURE +struct platform_data_t tfm_peripheral_wdt0 = { + NRF_WDT0_S_BASE, + NRF_WDT0_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT1_SECURE +struct platform_data_t tfm_peripheral_wdt1 = { + NRF_WDT1_S_BASE, + NRF_WDT1_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_COMP_SECURE +struct platform_data_t tfm_peripheral_comp = { + NRF_COMP_S_BASE, + NRF_COMP_S_BASE + (sizeof(NRF_COMP_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_LPCOMP_SECURE +struct platform_data_t tfm_peripheral_lpcomp = { + NRF_LPCOMP_S_BASE, + NRF_LPCOMP_S_BASE + (sizeof(NRF_LPCOMP_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU0_SECURE +struct platform_data_t tfm_peripheral_egu0 = { + NRF_EGU0_S_BASE, + NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU1_SECURE +struct platform_data_t tfm_peripheral_egu1 = { + NRF_EGU1_S_BASE, + NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU2_SECURE +struct platform_data_t tfm_peripheral_egu2 = { + NRF_EGU2_S_BASE, + NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU3_SECURE +struct platform_data_t tfm_peripheral_egu3 = { + NRF_EGU3_S_BASE, + NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU4_SECURE +struct platform_data_t tfm_peripheral_egu4 = { + NRF_EGU4_S_BASE, + NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU5_SECURE +struct platform_data_t tfm_peripheral_egu5 = { + NRF_EGU5_S_BASE, + NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU10_SECURE +struct platform_data_t tfm_peripheral_egu10 = { + NRF_EGU10_S_BASE, + NRF_EGU10_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU20_SECURE +struct platform_data_t tfm_peripheral_egu20 = { + NRF_EGU20_S_BASE, + NRF_EGU20_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM0_SECURE +struct platform_data_t tfm_peripheral_pwm0 = { + NRF_PWM0_S_BASE, + NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM1_SECURE +struct platform_data_t tfm_peripheral_pwm1 = { + NRF_PWM1_S_BASE, + NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM2_SECURE +struct platform_data_t tfm_peripheral_pwm2 = { + NRF_PWM2_S_BASE, + NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM3_SECURE +struct platform_data_t tfm_peripheral_pwm3 = { + NRF_PWM3_S_BASE, + NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM20_SECURE +struct platform_data_t tfm_peripheral_pwm20 = { + NRF_PWM20_S_BASE, + NRF_PWM20_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM21_SECURE +struct platform_data_t tfm_peripheral_pwm21 = { + NRF_PWM21_S_BASE, + NRF_PWM21_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM22_SECURE +struct platform_data_t tfm_peripheral_pwm22 = { + NRF_PWM22_S_BASE, + NRF_PWM22_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PDM0_SECURE +struct platform_data_t tfm_peripheral_pdm0 = { + NRF_PDM0_S_BASE, + NRF_PDM0_S_BASE + (sizeof(NRF_PDM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PDM_SECURE +struct platform_data_t tfm_peripheral_pdm = { + NRF_PDM_S_BASE, + NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_I2S0_SECURE +struct platform_data_t tfm_peripheral_i2s0 = { + NRF_I2S0_S_BASE, + NRF_I2S0_S_BASE + (sizeof(NRF_I2S_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_I2S_SECURE +struct platform_data_t tfm_peripheral_i2s = { + NRF_I2S_S_BASE, + NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_IPC_SECURE +struct platform_data_t tfm_peripheral_ipc = { + NRF_IPC_S_BASE, + NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_FPU_SECURE +struct platform_data_t tfm_peripheral_fpu = { + NRF_FPU_S_BASE, + NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QSPI_SECURE +struct platform_data_t tfm_peripheral_qspi = { + NRF_QSPI_S_BASE, + NRF_QSPI_S_BASE + (sizeof(NRF_QSPI_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_NFCT_SECURE +struct platform_data_t tfm_peripheral_nfct = { + NRF_NFCT_S_BASE, + NRF_NFCT_S_BASE + (sizeof(NRF_NFCT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_MUTEX_SECURE +struct platform_data_t tfm_peripheral_mutex = { + NRF_MUTEX_S_BASE, + NRF_MUTEX_S_BASE + (sizeof(NRF_MUTEX_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QDEC0_SECURE +struct platform_data_t tfm_peripheral_qdec0 = { + NRF_QDEC0_S_BASE, + NRF_QDEC0_S_BASE + (sizeof(NRF_QDEC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QDEC1_SECURE +struct platform_data_t tfm_peripheral_qdec1 = { + NRF_QDEC1_S_BASE, + NRF_QDEC1_S_BASE + (sizeof(NRF_QDEC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_USBD_SECURE +struct platform_data_t tfm_peripheral_usbd = { + NRF_USBD_S_BASE, + NRF_USBD_S_BASE + (sizeof(NRF_USBD_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_USBREG_SECURE +struct platform_data_t tfm_peripheral_usbreg = { + NRF_USBREGULATOR_S_BASE, + NRF_USBREGULATOR_S_BASE + (sizeof(NRF_USBREG_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_NVMC_SECURE +struct platform_data_t tfm_peripheral_nvmc = { + NRF_NVMC_S_BASE, + NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIO0_SECURE +struct platform_data_t tfm_peripheral_gpio0 = { + NRF_P0_S_BASE, + NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIO1_SECURE +struct platform_data_t tfm_peripheral_gpio1 = { + NRF_P1_S_BASE, + NRF_P1_S_BASE + (sizeof(NRF_GPIO_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_VMC_SECURE +struct platform_data_t tfm_peripheral_vmc = { + NRF_VMC_S_BASE, + NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIOTE20_SECURE +struct platform_data_t tfm_peripheral_gpiote20 = { + NRF_GPIOTE20_S_BASE, + NRF_GPIOTE20_S_BASE + (sizeof(NRF_GPIOTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIOTE30_SECURE +struct platform_data_t tfm_peripheral_gpiote30 = { + NRF_GPIOTE30_S_BASE, + NRF_GPIOTE30_S_BASE + (sizeof(NRF_GPIOTE_Type) - 1), +}; +#endif \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/core/startup.h b/platform/ext/target/nordic_nrf/common/core/startup.h index 4b3f738b06..937b495af2 100644 --- a/platform/ext/target/nordic_nrf/common/core/startup.h +++ b/platform/ext/target/nordic_nrf/common/core/startup.h @@ -13,6 +13,9 @@ #ifndef __STARTUP_H__ #define __STARTUP_H__ +#include +#include "cmsis.h" + extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; @@ -24,8 +27,19 @@ typedef void(*VECTOR_TABLE_Type)(void); __NO_RETURN void __PROGRAM_START(void); -#define DEFAULT_IRQ_HANDLER(handler_name) \ -__NO_RETURN void __attribute__((weak, alias("default_tfm_IRQHandler"))) handler_name(void); +#ifdef __cplusplus +extern "C" { +#endif + +__NO_RETURN void default_tfm_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void handler_name(void) __attribute__((weak)); \ +void handler_name(void) { default_tfm_IRQHandler(); } __NO_RETURN void Reset_Handler(void); __NO_RETURN void HardFault_Handler(void); diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.c new file mode 100644 index 0000000000..8301c3199d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file contains common interrupt handlers shared by all nRF54L variants. + * It should be included by the variant-specific startup files. + */ + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +__NO_RETURN __attribute__((naked)) void default_tfm_IRQHandler(void) { + EXCEPTION_INFO(); + + __ASM volatile( + "BL default_irq_handler \n" + "B . \n" + ); +} + +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(SWI00_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI01_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI02_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI03_IRQHandler) +DEFAULT_IRQ_HANDLER(AAR00_CCM00_IRQHandler) +DEFAULT_IRQ_HANDLER(ECB00_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL00_IRQHandler) +DEFAULT_IRQ_HANDLER(RRAMC_IRQHandler) +DEFAULT_IRQ_HANDLER(VPR00_IRQHandler) +DEFAULT_IRQ_HANDLER(CTRLAP_IRQHandler) +DEFAULT_IRQ_HANDLER(CM33SS_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER00_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER10_IRQHandler) +DEFAULT_IRQ_HANDLER(RTC10_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU10_IRQHandler) +DEFAULT_IRQ_HANDLER(AAR10_CCM10_IRQHandler) +DEFAULT_IRQ_HANDLER(ECB10_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_0_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_1_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL20_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL21_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL22_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER21_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER22_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER23_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER24_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM20_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM21_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM22_IRQHandler) +DEFAULT_IRQ_HANDLER(SAADC_IRQHandler) +DEFAULT_IRQ_HANDLER(NFCT_IRQHandler) +DEFAULT_IRQ_HANDLER(TEMP_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE20_1_IRQHandler) +DEFAULT_IRQ_HANDLER(TAMPC_IRQHandler) +DEFAULT_IRQ_HANDLER(I2S20_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC20_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC21_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_0_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_1_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_2_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_3_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL30_IRQHandler) +DEFAULT_IRQ_HANDLER(CLOCK_POWER_IRQHandler) +DEFAULT_IRQ_HANDLER(COMP_LPCOMP_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT30_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT31_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE30_1_IRQHandler) + +#if defined(DOMAIN_NS) || defined(BL2) +DEFAULT_IRQ_HANDLER(MPC00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU10_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU20_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU30_IRQHandler) +DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.h b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.h new file mode 100644 index 0000000000..5266d34a9a --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l_common.h @@ -0,0 +1,82 @@ +/* + * Prototypes for common nRF54L interrupt handlers used in vector tables. + * These are defined as weak defaults in startup_nrf54l_common.c. + */ + +#ifndef STARTUP_NRF54L_COMMON_H +#define STARTUP_NRF54L_COMMON_H + +#include "startup.h" + +/* Core/system exceptions */ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SecureFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +/* Shared nRF54L IRQ handlers */ +void SWI00_IRQHandler(void); +void SWI01_IRQHandler(void); +void SWI02_IRQHandler(void); +void SWI03_IRQHandler(void); +void AAR00_CCM00_IRQHandler(void); +void ECB00_IRQHandler(void); +void SERIAL00_IRQHandler(void); +void RRAMC_IRQHandler(void); +void VPR00_IRQHandler(void); +void CTRLAP_IRQHandler(void); +void CM33SS_IRQHandler(void); +void TIMER00_IRQHandler(void); +void TIMER10_IRQHandler(void); +void RTC10_IRQHandler(void); +void EGU10_IRQHandler(void); +void AAR10_CCM10_IRQHandler(void); +void ECB10_IRQHandler(void); +void RADIO_0_IRQHandler(void); +void RADIO_1_IRQHandler(void); +void SERIAL20_IRQHandler(void); +void SERIAL21_IRQHandler(void); +void SERIAL22_IRQHandler(void); +void EGU20_IRQHandler(void); +void TIMER20_IRQHandler(void); +void TIMER21_IRQHandler(void); +void TIMER22_IRQHandler(void); +void TIMER23_IRQHandler(void); +void TIMER24_IRQHandler(void); +void PWM20_IRQHandler(void); +void PWM21_IRQHandler(void); +void PWM22_IRQHandler(void); +void SAADC_IRQHandler(void); +void NFCT_IRQHandler(void); +void TEMP_IRQHandler(void); +void GPIOTE20_1_IRQHandler(void); +void TAMPC_IRQHandler(void); +void I2S20_IRQHandler(void); +void QDEC20_IRQHandler(void); +void QDEC21_IRQHandler(void); +void GRTC_0_IRQHandler(void); +void GRTC_1_IRQHandler(void); +void GRTC_2_IRQHandler(void); +void GRTC_3_IRQHandler(void); +void SERIAL30_IRQHandler(void); +void CLOCK_POWER_IRQHandler(void); +void COMP_LPCOMP_IRQHandler(void); +void WDT30_IRQHandler(void); +void WDT31_IRQHandler(void); +void GPIOTE30_1_IRQHandler(void); + +/* Conditionally defaulted in common file, but declare always for visibility */ +void MPC00_IRQHandler(void); +void SPU00_IRQHandler(void); +void SPU10_IRQHandler(void); +void SPU20_IRQHandler(void); +void SPU30_IRQHandler(void); +void CRACEN_IRQHandler(void); + +#endif /* STARTUP_NRF54L_COMMON_H */ diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54lm.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lm.c new file mode 100644 index 0000000000..12eb696e5d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lm.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +/* + * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) + * before including cmsis.h because TF-M's linker script + * tfm_common_s.ld assumes the vector table section is called .vectors + * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) + * default to using the name .isr_vector. + */ +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +/* Declarations for common nRF54L interrupt handlers (built separately) */ +#include "startup_nrf54l_common.h" + +/* NRF54LM20A-specific interrupt handlers */ +DEFAULT_IRQ_HANDLER(EGU00_IRQHandler) +DEFAULT_IRQ_HANDLER(USBHS_IRQHandler) +DEFAULT_IRQ_HANDLER(PDM20_IRQHandler) +DEFAULT_IRQ_HANDLER(PDM21_IRQHandler) +DEFAULT_IRQ_HANDLER(TDM_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL23_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL24_IRQHandler) +DEFAULT_IRQ_HANDLER(VREGUSB_IRQHandler) + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + /* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, /* SecureFault_IRQn */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, + /* Device specific interrupt handlers */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SWI00_IRQHandler, + SWI01_IRQHandler, + SWI02_IRQHandler, + SWI03_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU00_IRQHandler, + MPC00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + AAR00_CCM00_IRQHandler, + ECB00_IRQHandler, + VPR00_IRQHandler, + default_tfm_IRQHandler, + RRAMC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CTRLAP_IRQHandler, + default_tfm_IRQHandler, + CM33SS_IRQHandler, + TIMER00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CRACEN_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU10_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TIMER10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + default_tfm_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL20_IRQHandler, + SERIAL21_IRQHandler, + default_tfm_IRQHandler, + EGU20_IRQHandler, + TIMER20_IRQHandler, + TIMER21_IRQHandler, + TIMER22_IRQHandler, + TIMER23_IRQHandler, + TIMER24_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SAADC_IRQHandler, + default_tfm_IRQHandler, + TEMP_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE20_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + QDEC20_IRQHandler, + QDEC21_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + GRTC_3_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TDM_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL23_IRQHandler, + SERIAL24_IRQHandler, + TAMPC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU30_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL30_IRQHandler, + default_tfm_IRQHandler, + COMP_LPCOMP_IRQHandler, + default_tfm_IRQHandler, + WDT30_IRQHandler, + WDT31_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE30_1_IRQHandler, + CLOCK_POWER_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + VREGUSB_IRQHandler, +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54lv.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lv.c new file mode 100644 index 0000000000..e975ff56e8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lv.c @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +/* + * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) + * before including cmsis.h because TF-M's linker script + * tfm_common_s.ld assumes the vector table section is called .vectors + * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) + * default to using the name .isr_vector. + */ +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +/* Declarations for common nRF54L interrupt handlers (built separately) */ +#include "startup_nrf54l_common.h" + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + /* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, /* SecureFault_IRQn */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, + /* Device specific interrupt handlers */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SWI00_IRQHandler, + SWI01_IRQHandler, + SWI02_IRQHandler, + SWI03_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU00_IRQHandler, + MPC00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + AAR00_CCM00_IRQHandler, + ECB00_IRQHandler, + VPR00_IRQHandler, + default_tfm_IRQHandler, + RRAMC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CTRLAP_IRQHandler, + default_tfm_IRQHandler, + CM33SS_IRQHandler, + TIMER00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CRACEN_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU10_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TIMER10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + EGU10_IRQHandler, + default_tfm_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL20_IRQHandler, + SERIAL21_IRQHandler, + default_tfm_IRQHandler, + EGU20_IRQHandler, + TIMER20_IRQHandler, + TIMER21_IRQHandler, + TIMER22_IRQHandler, + TIMER23_IRQHandler, + TIMER24_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SAADC_IRQHandler, + default_tfm_IRQHandler, + TEMP_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE20_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + GRTC_3_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TAMPC_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU30_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL30_IRQHandler, + default_tfm_IRQHandler, + COMP_LPCOMP_IRQHandler, + default_tfm_IRQHandler, + WDT30_IRQHandler, + WDT31_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE30_1_IRQHandler, + CLOCK_POWER_IRQHandler, +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lx.c similarity index 75% rename from platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c rename to platform/ext/target/nordic_nrf/common/core/startup_nrf54lx.c index 5006175b19..e790a29400 100644 --- a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54lx.c @@ -34,84 +34,8 @@ #include "startup.h" #include "exception_info.h" -__NO_RETURN __attribute__((naked)) void default_tfm_IRQHandler(void) { - EXCEPTION_INFO(); - - __ASM volatile( - "BL default_irq_handler \n" - "B . \n" - ); -} - -DEFAULT_IRQ_HANDLER(NMI_Handler) -DEFAULT_IRQ_HANDLER(HardFault_Handler) -DEFAULT_IRQ_HANDLER(MemManage_Handler) -DEFAULT_IRQ_HANDLER(BusFault_Handler) -DEFAULT_IRQ_HANDLER(UsageFault_Handler) -DEFAULT_IRQ_HANDLER(SecureFault_Handler) -DEFAULT_IRQ_HANDLER(SVC_Handler) -DEFAULT_IRQ_HANDLER(DebugMon_Handler) -DEFAULT_IRQ_HANDLER(PendSV_Handler) -DEFAULT_IRQ_HANDLER(SysTick_Handler) - -DEFAULT_IRQ_HANDLER(SWI00_IRQHandler) -DEFAULT_IRQ_HANDLER(SWI01_IRQHandler) -DEFAULT_IRQ_HANDLER(SWI02_IRQHandler) -DEFAULT_IRQ_HANDLER(SWI03_IRQHandler) -DEFAULT_IRQ_HANDLER(AAR00_CCM00_IRQHandler) -DEFAULT_IRQ_HANDLER(ECB00_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL00_IRQHandler) -DEFAULT_IRQ_HANDLER(RRAMC_IRQHandler) -DEFAULT_IRQ_HANDLER(VPR00_IRQHandler) -DEFAULT_IRQ_HANDLER(CTRLAP_IRQHandler) -DEFAULT_IRQ_HANDLER(CM33SS_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER00_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER10_IRQHandler) -DEFAULT_IRQ_HANDLER(RTC10_IRQHandler) -DEFAULT_IRQ_HANDLER(EGU10_IRQHandler) -DEFAULT_IRQ_HANDLER(AAR10_CCM10_IRQHandler) -DEFAULT_IRQ_HANDLER(ECB10_IRQHandler) -DEFAULT_IRQ_HANDLER(RADIO_0_IRQHandler) -DEFAULT_IRQ_HANDLER(RADIO_1_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL20_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL21_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL22_IRQHandler) -DEFAULT_IRQ_HANDLER(EGU20_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER20_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER21_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER22_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER23_IRQHandler) -DEFAULT_IRQ_HANDLER(TIMER24_IRQHandler) -DEFAULT_IRQ_HANDLER(PWM20_IRQHandler) -DEFAULT_IRQ_HANDLER(PWM21_IRQHandler) -DEFAULT_IRQ_HANDLER(PWM22_IRQHandler) -DEFAULT_IRQ_HANDLER(SAADC_IRQHandler) -DEFAULT_IRQ_HANDLER(NFCT_IRQHandler) -DEFAULT_IRQ_HANDLER(TEMP_IRQHandler) -DEFAULT_IRQ_HANDLER(GPIOTE20_1_IRQHandler) -DEFAULT_IRQ_HANDLER(TAMPC_IRQHandler) -DEFAULT_IRQ_HANDLER(I2S20_IRQHandler) -DEFAULT_IRQ_HANDLER(QDEC20_IRQHandler) -DEFAULT_IRQ_HANDLER(QDEC21_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_0_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_1_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_2_IRQHandler) -DEFAULT_IRQ_HANDLER(GRTC_3_IRQHandler) -DEFAULT_IRQ_HANDLER(SERIAL30_IRQHandler) -DEFAULT_IRQ_HANDLER(CLOCK_POWER_IRQHandler) -DEFAULT_IRQ_HANDLER(COMP_LPCOMP_IRQHandler) -DEFAULT_IRQ_HANDLER(WDT30_IRQHandler) -DEFAULT_IRQ_HANDLER(WDT31_IRQHandler) -DEFAULT_IRQ_HANDLER(GPIOTE30_1_IRQHandler) - -#if defined(DOMAIN_NS) || defined(BL2) -DEFAULT_IRQ_HANDLER(MPC00_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU00_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU10_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU20_IRQHandler) -DEFAULT_IRQ_HANDLER(SPU30_IRQHandler) -DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) -#endif +/* Declarations for common nRF54L interrupt handlers (built separately) */ +#include "startup_nrf54l_common.h" #if defined ( __GNUC__ ) #pragma GCC diagnostic push @@ -119,12 +43,12 @@ DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) #endif const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ -/* Exceptions */ + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + /* Exceptions */ Reset_Handler, NMI_Handler, HardFault_Handler, - MemManage_Handler, /* MPU Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ BusFault_Handler, UsageFault_Handler, SecureFault_Handler, @@ -136,7 +60,7 @@ const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { default_tfm_IRQHandler, PendSV_Handler, SysTick_Handler, -/* Device specific interrupt handlers */ + /* Device specific interrupt handlers */ default_tfm_IRQHandler, default_tfm_IRQHandler, default_tfm_IRQHandler, diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.c b/platform/ext/target/nordic_nrf/common/core/target_cfg.c index 75afa398be..ca3d517943 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.c @@ -17,700 +17,9 @@ */ #include "target_cfg.h" #include "region_defs.h" -#include "tfm_plat_defs.h" -#include "tfm_peripherals_config.h" -#include "tfm_plat_provisioning.h" -#include "utilities.h" #include "region.h" -#include "array.h" - -#ifdef __NRF_TFM__ -#include -#endif - -#include #include -#include -#include - -#ifdef RRAMC_PRESENT -#include -#include - -#if CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE > 0 -#define WRITE_BUFFER_SIZE CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE -#else -#define WRITE_BUFFER_SIZE 0 -#endif - -#endif - -#define SPU_ADDRESS_REGION (0x50000000) -#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) -#define GET_SPU_INSTANCE(periph) ((NRF_SPU_Type*)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) - - -#ifdef CACHE_PRESENT -#include -#endif - -#ifdef NVMC_PRESENT -#include -#include -#endif - -#ifdef MPC_PRESENT -#include -#endif - -#ifdef NRF53_SERIES -#define PIN_XL1 0 -#define PIN_XL2 1 -#endif - -#ifdef NRF54L_SERIES -/* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ -#define PIN_XL1 32 -#define PIN_XL2 33 - -/* During TF-M system initialization we invoke a function that comes - * from Zephyr. This function does not have a header file so we - * declare its prototype here. - */ -int nordicsemi_nrf54l_init(void); -#endif - -#if TFM_PERIPHERAL_DCNF_SECURE -struct platform_data_t tfm_peripheral_dcnf = { - NRF_DCNF_S_BASE, - NRF_DCNF_S_BASE + (sizeof(NRF_DCNF_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_FPU_SECURE -struct platform_data_t tfm_peripheral_fpu = { - NRF_FPU_S_BASE, - NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_OSCILLATORS_SECURE -struct platform_data_t tfm_peripheral_oscillators = { - NRF_OSCILLATORS_S_BASE, - NRF_OSCILLATORS_S_BASE + (sizeof(NRF_OSCILLATORS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_REGULATORS_SECURE -struct platform_data_t tfm_peripheral_regulators = { - NRF_REGULATORS_S_BASE, - NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_CLOCK_SECURE -struct platform_data_t tfm_peripheral_clock = { - NRF_CLOCK_S_BASE, - NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_POWER_SECURE -struct platform_data_t tfm_peripheral_power = { - NRF_POWER_S_BASE, - NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RESET_SECURE -struct platform_data_t tfm_peripheral_reset = { - NRF_RESET_S_BASE, - NRF_RESET_S_BASE + (sizeof(NRF_RESET_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM0_SECURE -struct platform_data_t tfm_peripheral_spim0 = { - NRF_SPIM0_S_BASE, - NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM00_SECURE -struct platform_data_t tfm_peripheral_spim00 = { - NRF_SPIM00_S_BASE, - NRF_SPIM00_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM20_SECURE -struct platform_data_t tfm_peripheral_spim20 = { - NRF_SPIM20_S_BASE, - NRF_SPIM20_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM22_SECURE -struct platform_data_t tfm_peripheral_spim21 = { - NRF_SPIM21_S_BASE, - NRF_SPIM21_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM22_SECURE -struct platform_data_t tfm_peripheral_spim22 = { - NRF_SPIM22_S_BASE, - NRF_SPIM22_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM23_SECURE -struct platform_data_t tfm_peripheral_spim23 = { - NRF_SPIM23_S_BASE, - NRF_SPIM23_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM30_SECURE -struct platform_data_t tfm_peripheral_spim30 = { - NRF_SPIM30_S_BASE, - NRF_SPIM30_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS0_SECURE -struct platform_data_t tfm_peripheral_spis0 = { - NRF_SPIS0_S_BASE, - NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM0_SECURE -struct platform_data_t tfm_peripheral_twim0 = { - NRF_TWIM0_S_BASE, - NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS0_SECURE -struct platform_data_t tfm_peripheral_twis0 = { - NRF_TWIS0_S_BASE, - NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE0_SECURE -struct platform_data_t tfm_peripheral_uarte0 = { - NRF_UARTE0_S_BASE, - NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM1_SECURE -struct platform_data_t tfm_peripheral_spim1 = { - NRF_SPIM1_S_BASE, - NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS1_SECURE -struct platform_data_t tfm_peripheral_spis1 = { - NRF_SPIS1_S_BASE, - NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM1_SECURE -struct platform_data_t tfm_peripheral_twim1 = { - NRF_TWIM1_S_BASE, - NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS1_SECURE -struct platform_data_t tfm_peripheral_twis1 = { - NRF_TWIS1_S_BASE, - NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE1_SECURE -struct platform_data_t tfm_peripheral_uarte1 = { - NRF_UARTE1_S_BASE, - NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM4_SECURE -struct platform_data_t tfm_peripheral_spim4 = { - NRF_SPIM4_S_BASE, - NRF_SPIM4_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM2_SECURE -struct platform_data_t tfm_peripheral_spim2 = { - NRF_SPIM2_S_BASE, - NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS2_SECURE -struct platform_data_t tfm_peripheral_spis2 = { - NRF_SPIS2_S_BASE, - NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM2_SECURE -struct platform_data_t tfm_peripheral_twim2 = { - NRF_TWIM2_S_BASE, - NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS2_SECURE -struct platform_data_t tfm_peripheral_twis2 = { - NRF_TWIS2_S_BASE, - NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE2_SECURE -struct platform_data_t tfm_peripheral_uarte2 = { - NRF_UARTE2_S_BASE, - NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM3_SECURE -struct platform_data_t tfm_peripheral_spim3 = { - NRF_SPIM3_S_BASE, - NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS3_SECURE -struct platform_data_t tfm_peripheral_spis3 = { - NRF_SPIS3_S_BASE, - NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM3_SECURE -struct platform_data_t tfm_peripheral_twim3 = { - NRF_TWIM3_S_BASE, - NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS3_SECURE -struct platform_data_t tfm_peripheral_twis3 = { - NRF_TWIS3_S_BASE, - NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE3_SECURE -struct platform_data_t tfm_peripheral_uarte3 = { - NRF_UARTE3_S_BASE, - NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE00_SECURE -struct platform_data_t tfm_peripheral_uarte00 = { - NRF_UARTE00_S_BASE, - NRF_UARTE00_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE20_SECURE -struct platform_data_t tfm_peripheral_uarte20 = { - NRF_UARTE20_S_BASE, - NRF_UARTE20_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE21_SECURE -struct platform_data_t tfm_peripheral_uarte21 = { - NRF_UARTE21_S_BASE, - NRF_UARTE21_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE22_SECURE -struct platform_data_t tfm_peripheral_uarte22 = { - NRF_UARTE22_S_BASE, - NRF_UARTE22_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE30_SECURE -struct platform_data_t tfm_peripheral_uarte30 = { - NRF_UARTE30_S_BASE, - NRF_UARTE30_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SAADC_SECURE -struct platform_data_t tfm_peripheral_saadc = { - NRF_SAADC_S_BASE, - NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER0_SECURE -struct platform_data_t tfm_peripheral_timer0 = { - NRF_TIMER0_S_BASE, - NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER00_SECURE -struct platform_data_t tfm_peripheral_timer00 = { - NRF_TIMER00_S_BASE, - NRF_TIMER00_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER10_SECURE -struct platform_data_t tfm_peripheral_timer10 = { - NRF_TIMER10_S_BASE, - NRF_TIMER10_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER20_SECURE -struct platform_data_t tfm_peripheral_timer20 = { - NRF_TIMER20_S_BASE, - NRF_TIMER20_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER21_SECURE -struct platform_data_t tfm_peripheral_timer21 = { - NRF_TIMER21_S_BASE, - NRF_TIMER21_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER22_SECURE -struct platform_data_t tfm_peripheral_timer22 = { - NRF_TIMER22_S_BASE, - NRF_TIMER22_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER23_SECURE -struct platform_data_t tfm_peripheral_timer23 = { - NRF_TIMER23_S_BASE, - NRF_TIMER23_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER24_SECURE -struct platform_data_t tfm_peripheral_timer24 = { - NRF_TIMER24_S_BASE, - NRF_TIMER24_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER1_SECURE -struct platform_data_t tfm_peripheral_timer1 = { - NRF_TIMER1_S_BASE, - NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER2_SECURE -struct platform_data_t tfm_peripheral_timer2 = { - NRF_TIMER2_S_BASE, - NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RTC0_SECURE -struct platform_data_t tfm_peripheral_rtc0 = { - NRF_RTC0_S_BASE, - NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RTC1_SECURE -struct platform_data_t tfm_peripheral_rtc1 = { - NRF_RTC1_S_BASE, - NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_DPPI_SECURE -struct platform_data_t tfm_peripheral_dppi = { - NRF_DPPIC_S_BASE, - NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT_SECURE -struct platform_data_t tfm_peripheral_wdt = { - NRF_WDT_S_BASE, - NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT0_SECURE -struct platform_data_t tfm_peripheral_wdt0 = { - NRF_WDT0_S_BASE, - NRF_WDT0_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT1_SECURE -struct platform_data_t tfm_peripheral_wdt1 = { - NRF_WDT1_S_BASE, - NRF_WDT1_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_COMP_SECURE -struct platform_data_t tfm_peripheral_comp = { - NRF_COMP_S_BASE, - NRF_COMP_S_BASE + (sizeof(NRF_COMP_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_LPCOMP_SECURE -struct platform_data_t tfm_peripheral_lpcomp = { - NRF_LPCOMP_S_BASE, - NRF_LPCOMP_S_BASE + (sizeof(NRF_LPCOMP_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU0_SECURE -struct platform_data_t tfm_peripheral_egu0 = { - NRF_EGU0_S_BASE, - NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU1_SECURE -struct platform_data_t tfm_peripheral_egu1 = { - NRF_EGU1_S_BASE, - NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU2_SECURE -struct platform_data_t tfm_peripheral_egu2 = { - NRF_EGU2_S_BASE, - NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU3_SECURE -struct platform_data_t tfm_peripheral_egu3 = { - NRF_EGU3_S_BASE, - NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU4_SECURE -struct platform_data_t tfm_peripheral_egu4 = { - NRF_EGU4_S_BASE, - NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU5_SECURE -struct platform_data_t tfm_peripheral_egu5 = { - NRF_EGU5_S_BASE, - NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU10_SECURE -struct platform_data_t tfm_peripheral_egu10 = { - NRF_EGU10_S_BASE, - NRF_EGU10_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU20_SECURE -struct platform_data_t tfm_peripheral_egu20 = { - NRF_EGU20_S_BASE, - NRF_EGU20_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM0_SECURE -struct platform_data_t tfm_peripheral_pwm0 = { - NRF_PWM0_S_BASE, - NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM1_SECURE -struct platform_data_t tfm_peripheral_pwm1 = { - NRF_PWM1_S_BASE, - NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM2_SECURE -struct platform_data_t tfm_peripheral_pwm2 = { - NRF_PWM2_S_BASE, - NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM3_SECURE -struct platform_data_t tfm_peripheral_pwm3 = { - NRF_PWM3_S_BASE, - NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM20_SECURE -struct platform_data_t tfm_peripheral_pwm20 = { - NRF_PWM20_S_BASE, - NRF_PWM20_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM21_SECURE -struct platform_data_t tfm_peripheral_pwm21 = { - NRF_PWM21_S_BASE, - NRF_PWM21_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM22_SECURE -struct platform_data_t tfm_peripheral_pwm22 = { - NRF_PWM22_S_BASE, - NRF_PWM22_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PDM0_SECURE -struct platform_data_t tfm_peripheral_pdm0 = { - NRF_PDM0_S_BASE, - NRF_PDM0_S_BASE + (sizeof(NRF_PDM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PDM_SECURE -struct platform_data_t tfm_peripheral_pdm = { - NRF_PDM_S_BASE, - NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_I2S0_SECURE -struct platform_data_t tfm_peripheral_i2s0 = { - NRF_I2S0_S_BASE, - NRF_I2S0_S_BASE + (sizeof(NRF_I2S_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_I2S_SECURE -struct platform_data_t tfm_peripheral_i2s = { - NRF_I2S_S_BASE, - NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_IPC_SECURE -struct platform_data_t tfm_peripheral_ipc = { - NRF_IPC_S_BASE, - NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_FPU_SECURE -struct platform_data_t tfm_peripheral_fpu = { - NRF_FPU_S_BASE, - NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QSPI_SECURE -struct platform_data_t tfm_peripheral_qspi = { - NRF_QSPI_S_BASE, - NRF_QSPI_S_BASE + (sizeof(NRF_QSPI_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_NFCT_SECURE -struct platform_data_t tfm_peripheral_nfct = { - NRF_NFCT_S_BASE, - NRF_NFCT_S_BASE + (sizeof(NRF_NFCT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_MUTEX_SECURE -struct platform_data_t tfm_peripheral_mutex = { - NRF_MUTEX_S_BASE, - NRF_MUTEX_S_BASE + (sizeof(NRF_MUTEX_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QDEC0_SECURE -struct platform_data_t tfm_peripheral_qdec0 = { - NRF_QDEC0_S_BASE, - NRF_QDEC0_S_BASE + (sizeof(NRF_QDEC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QDEC1_SECURE -struct platform_data_t tfm_peripheral_qdec1 = { - NRF_QDEC1_S_BASE, - NRF_QDEC1_S_BASE + (sizeof(NRF_QDEC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_USBD_SECURE -struct platform_data_t tfm_peripheral_usbd = { - NRF_USBD_S_BASE, - NRF_USBD_S_BASE + (sizeof(NRF_USBD_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_USBREG_SECURE -struct platform_data_t tfm_peripheral_usbreg = { - NRF_USBREGULATOR_S_BASE, - NRF_USBREGULATOR_S_BASE + (sizeof(NRF_USBREG_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_NVMC_SECURE -struct platform_data_t tfm_peripheral_nvmc = { - NRF_NVMC_S_BASE, - NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_GPIO0_SECURE -struct platform_data_t tfm_peripheral_gpio0 = { - NRF_P0_S_BASE, - NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_GPIO1_SECURE -struct platform_data_t tfm_peripheral_gpio1 = { - NRF_P1_S_BASE, - NRF_P1_S_BASE + (sizeof(NRF_GPIO_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_VMC_SECURE -struct platform_data_t tfm_peripheral_vmc = { - NRF_VMC_S_BASE, - NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1), -}; -#endif - #ifdef PSA_API_TEST_IPC struct platform_data_t tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = { @@ -807,784 +116,3 @@ enum tfm_plat_err_t system_reset_cfg(void) return TFM_PLAT_ERR_SUCCESS; } - -enum tfm_plat_err_t init_debug(void) -{ -#if defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT) - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "Debug access controlled by NRF_APPROTECT and NRF_SECURE_APPROTECT." -#endif - -#if defined(NRF_APPROTECT) && !defined(NRF54L_SERIES) - /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot.*/ - if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->APPROTECT, - UICR_APPROTECT_PALL_Protected)) { - nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->APPROTECT, UICR_APPROTECT_PALL_Protected); - } else { - return TFM_PLAT_ERR_SYSTEM_ERR; - } -#endif -#if defined(NRF_SECURE_APPROTECT) && !defined(NRF54L_SERIES) - /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot. */ - if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, - UICR_SECUREAPPROTECT_PALL_Protected)) { - nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, - UICR_SECUREAPPROTECT_PALL_Protected); - } else { - return TFM_PLAT_ERR_SYSTEM_ERR; - } -#endif - -#elif defined(NRF91_SERIES) || defined(NRF54L_SERIES) - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." -#endif - -#elif defined(NRF53_SERIES) - -#if defined(DAUTH_NONE) - /* Disable debugging */ - NRF_CTRLAP->APPROTECT.DISABLE = 0; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; -#elif defined(DAUTH_NS_ONLY) - /* Allow debugging Non-Secure only */ - NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; -#elif defined(DAUTH_FULL) || defined(DAUTH_CHIP_DEFAULT) - /* Allow debugging */ - /* Use the configuration in UICR. */ - NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = NRF_UICR->SECUREAPPROTECT; -#else -#error "No debug authentication setting is provided." -#endif - - /* Lock access to APPROTECT, SECUREAPPROTECT */ - NRF_CTRLAP->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked << - CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk; - NRF_CTRLAP->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked << - CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk; - -#else -#error "Unrecognized platform" - -#endif - - return TFM_PLAT_ERR_SUCCESS; -} - -#define NRF_UARTE_INSTANCE(id) NRF_UARTE ## id -#define NRF_UARTE_INSTANCE_GET(id) NRF_UARTE_INSTANCE(id) - -/*----------------- NVIC interrupt target state to NS configuration ----------*/ -enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) -{ - /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ - for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { - NVIC->ITNS[i] = 0xFFFFFFFF; - } - - /* Make sure that the SPU instance(s) are targeted to S state */ - for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); - } - -#ifdef NRF_CRACEN - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_CRACEN)); -#endif -#ifdef NRF_MPC00 - NVIC_ClearTargetState(MPC00_IRQn); -#endif - -#ifdef SECURE_UART1 - /* IRQ for the selected secure UART has to target S state */ - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); -#endif - - return TFM_PLAT_ERR_SUCCESS; -} - -/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ -enum tfm_plat_err_t nvic_interrupt_enable(void) -{ - /* SPU interrupt enabling */ - spu_enable_interrupts(); - - for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { - NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); - NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); - } - -#ifdef MPC_PRESENT - mpc_clear_events(); - /* MPC interrupt enabling */ - mpc_enable_interrupts(); - - NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); - NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); -#endif - - /* The CRACEN driver configures the NVIC for CRACEN and is - * therefore omitted here. - */ - - return TFM_PLAT_ERR_SUCCESS; -} - -/*------------------- SAU/IDAU configuration functions -----------------------*/ - -void sau_and_idau_cfg(void) -{ - /* - * SAU and IDAU configuration is very different between old - * (53/91) and new (54++) platforms. New platforms have a proper SAU - * and IDAU, whereas old platforms do not. - */ -#ifdef NRF54L_SERIES - /* - * This SAU configuration aligns with ARM's RSS implementation of - * sau_and_idau_cfg when possible. - */ - - /* Enables SAU */ - TZ_SAU_Enable(); - - /* Configures SAU regions to be non-secure */ - - /* Note that this SAU configuration assumes that there is only one - * secure NVM partition and one non-secure NVM partition. Meaning, - * memory_regions.non_secure_partition_limit is at the end of - * NVM. - */ - - /* Configure the end of NVM, and the FICR, to be non-secure using - a single region. Note that the FICR is placed after the - non-secure NVM and before the UICR.*/ - SAU->RNR = 0; - SAU->RBAR = (memory_regions.non_secure_partition_base - & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (NRF_UICR_S_BASE & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; - - /* Leave SAU region 1 disabled until we find a use for it */ - - /* Configures veneers region to be non-secure callable */ - SAU->RNR = 2; - SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) - | SAU_RLAR_ENABLE_Msk | SAU_RLAR_NSC_Msk; - - /* Configures SAU region 3 to cover both the end of SRAM and - * regions above it as shown in the "Example memory map" in the - * "Product Specification" */ - SAU->RNR = 3; - SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); - SAU->RLAR = (0xFFFFFFFFul & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; - -#else - /* IDAU (SPU) is always enabled. SAU is non-existent. - * Allow SPU to have precedence over (non-existing) ARMv8-M SAU. - */ - TZ_SAU_Disable(); - SAU->CTRL |= SAU_CTRL_ALLNS_Msk; -#endif -} - -#if NRF_SPU_HAS_MEMORY -enum tfm_plat_err_t spu_init_cfg(void) -{ - /* - * Configure SPU Regions for Non-Secure Code and SRAM (Data) - * Configure SPU for Peripheral Security - * Configure Non-Secure Callable Regions - * Configure Secondary Image Partition - * Configure Non-Secure Storage Partition - */ - - /* Reset Flash and SRAM configuration of regions that are not owned by - * the bootloader(s) to all-Secure. - */ - spu_regions_reset_unlocked_secure(); - - uint32_t perm; - - /* Configure Secure Code to be secure and RX */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - /* Do not permit writes to secure flash */ - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_flash_config(S_CODE_START, S_CODE_LIMIT, SPU_SECURE_ATTR_SECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configure Secure RAM to be secure and RWX */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - /* Permit execute from Secure RAM because otherwise Crypto fails - * to initialize. */ - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_sram_config(S_DATA_START, S_DATA_LIMIT, SPU_SECURE_ATTR_SECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configures SPU Code and Data regions to be non-secure */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_flash_config(memory_regions.non_secure_partition_base, - memory_regions.non_secure_partition_limit, SPU_SECURE_ATTR_NONSECURE, - perm, SPU_LOCK_CONF_LOCKED); - - spu_regions_sram_config(NS_DATA_START, NS_DATA_LIMIT, SPU_SECURE_ATTR_NONSECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configures veneers region to be non-secure callable */ - spu_regions_flash_config_non_secure_callable(memory_regions.veneer_base, - memory_regions.veneer_limit - 1); - -#ifdef NRF_NS_SECONDARY - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - - /* Secondary image partition */ - spu_regions_flash_config(memory_regions.secondary_partition_base, - memory_regions.secondary_partition_limit, SPU_SECURE_ATTR_NONSECURE, - perm, SPU_LOCK_CONF_LOCKED); -#endif /* NRF_NS_SECONDARY */ - -#ifdef NRF_NS_STORAGE_PARTITION_START - /* Configures storage partition to be non-secure */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - - spu_regions_flash_config(memory_regions.non_secure_storage_partition_base, - memory_regions.non_secure_storage_partition_limit, - SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); -#endif /* NRF_NS_STORAGE_PARTITION_START */ - -#ifdef REGION_PCD_SRAM_ADDRESS - /* Netcore needs PCD memory area to be non-secure. */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - if (tfm_plat_provisioning_is_required()) { - perm |= NRF_SPU_MEM_PERM_WRITE; - } - - spu_regions_sram_config(REGION_PCD_SRAM_ADDRESS, REGION_PCD_SRAM_LIMIT, - SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); -#endif - - return TFM_PLAT_ERR_SUCCESS; -} -#endif /* NRF_SPU_HAS_MEMORY */ - - -#ifdef MPC_PRESENT -struct mpc_region_override { - nrf_mpc_override_config_t config; - nrf_owner_t owner_id; - uintptr_t start_address; - size_t endaddr; - uint32_t perm; - uint32_t permmask; - size_t index; -}; - -static void mpc_configure_override(NRF_MPC_Type *mpc, struct mpc_region_override *override) -{ - nrf_mpc_override_startaddr_set(mpc, override->index, override->start_address); - nrf_mpc_override_endaddr_set(mpc, override->index, override->endaddr); - nrf_mpc_override_perm_set(mpc, override->index, override->perm); - nrf_mpc_override_permmask_set(mpc, override->index, override->permmask); -#if defined(NRF_MPC_HAS_OVERRIDE_OWNERID) && NRF_MPC_HAS_OVERRIDE_OWNERID - nrf_mpc_override_ownerid_set(mpc, override->index, override->owner_id); -#endif - nrf_mpc_override_config_set(mpc, override->index, &override->config); -} - -/* - * Configure the override struct with reasonable defaults. This includes: - * - * Use a slave number of 0 to avoid redirecting bus transactions from - * one slave to another. - * - * Lock the override to prevent the code that follows from tampering - * with the configuration. - * - * Enable the override so it takes effect. - * - * Indicate that secdom is not enabled as this driver is not used on - * platforms with secdom. - */ -static void init_mpc_region_override(struct mpc_region_override * override) -{ - *override = (struct mpc_region_override){ - .config = - (nrf_mpc_override_config_t){ - .slave_number = 0, - .lock = true, - .enable = true, - .secdom_enable = false, - .secure_mask = true, - }, - .perm = 0, /* 0 for non-secure */ - .owner_id = 0, - }; - - override->permmask = MPC_OVERRIDE_PERM_SECATTR_Msk; -} - -enum tfm_plat_err_t nrf_mpc_init_cfg(void) -{ - /* On 54l the NRF_MPC00->REGION[]'s are fixed in HW and the - * OVERRIDE indexes (that are useful to us) start at 0 and end - * (inclusive) at 4. - * - * Note that the MPC regions configure all volatile and non-volatile memory as secure, so we only - * need to explicitly OVERRIDE the non-secure addresses to permit non-secure access. - * - * Explicitly configuring memory as secure is not necessary. - * - * The last OVERRIDE in 54L is fixed in HW and exists to prevent - * other bus masters than the KMU from accessing CRACEN protected RAM. - * - * Note that we must take care not to configure an OVERRIDE that - * affects an active bus transaction. - * - * Note that we don't configure the NSC region to be NS because - * from the MPC's perspective it is secure. NSC is only configurable from the SAU. - * - * Note that OVERRIDE[n].MASTERPORT has a reasonable reset value - * so it is left unconfigured. - * - * Note that there are two owners in 54L. KMU with owner ID 1, and everything else with owner ID 0. - */ - - uint32_t index = 0; - /* - * Configure the non-secure partition of the non-volatile - * memory. This MPC region is intended to cover both the - * non-secure partition in the NVM and also the FICR. The FICR - * starts after the NVM and ends just before the UICR. - */ - { - struct mpc_region_override override; - - init_mpc_region_override(&override); - - override.start_address = memory_regions.non_secure_partition_base; - override.endaddr = NRF_UICR_S_BASE; - override.index = index++; - - mpc_configure_override(NRF_MPC00, &override); - } - - /* Configure the non-secure partition of the volatile memory */ - { - struct mpc_region_override override; - - init_mpc_region_override(&override); - - override.start_address = NS_DATA_START; - override.endaddr = 1 + NS_DATA_LIMIT; - override.index = index++; - - mpc_configure_override(NRF_MPC00, &override); - } - - if(index > 4) { - /* Used more overrides than are available */ - tfm_core_panic(); - } - - /* Lock and disable any unused MPC overrides to prevent malicious configuration */ - while(index <= 4) { - struct mpc_region_override override; - - init_mpc_region_override(&override); - - override.config.enable = false; - - override.index = index++; - - mpc_configure_override(NRF_MPC00, &override); - } - - return TFM_PLAT_ERR_SUCCESS; -} - -#endif /* MPC_PRESENT */ - -static void dppi_channel_configuration(void) -{ - /* The SPU HW and corresponding NRFX HAL API have two different - * API's for DPPI security configuration. The defines - * NRF_SPU_HAS_OWNERSHIP and NRF_SPU_HAS_MEMORY identify which of the two API's - * are present. - * - * TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE is configurable, but - * usually defaults to 0, which results in all DPPI channels being - * non-secure. - */ -#if NRF_SPU_HAS_MEMORY - /* There is only one dppi_id */ - uint8_t dppi_id = 0; - nrf_spu_dppi_config_set(NRF_SPU, dppi_id, TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, - SPU_LOCK_CONF_LOCKED); -#else - /* TODO_NRF54L15: Use the nrf_spu_feature API to configure DPPI - channels according to a user-controllable config similar to - TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE. */ -#endif -} - -enum tfm_plat_err_t spu_periph_init_cfg(void) -{ - /* Peripheral configuration */ -#ifdef NRF54L_SERIES - /* Configure features to be non-secure */ - - /* - * Due to MLT-7600, many SPU HW reset values are wrong. The docs - * generally features being non-secure when coming out of HW - * reset, but the HW has a good mix of both. - * - * When configuring NRF_SPU 0 will indicate non-secure and 1 will - * indicate secure. - * - * Most of the chip should be non-secure so to simplify and be - * consistent, we memset the entire memory map of each SPU - * peripheral to 0. - * - * Just after memsetting to 0 we explicitly configure the - * peripherals that should be secure back to secure again. - */ - // TODO: NCSDK-22597: Evaluate if it is safe to memset everything - // in NRF_SPU to 0. - memset(NRF_SPU00, 0, sizeof(NRF_SPU_Type)); - memset(NRF_SPU10, 0, sizeof(NRF_SPU_Type)); - memset(NRF_SPU20, 0, sizeof(NRF_SPU_Type)); - memset(NRF_SPU30, 0, sizeof(NRF_SPU_Type)); - -#if SECURE_UART1 - /* Configure TF-M's UART peripheral to be secure */ -#if NRF_SECURE_UART_INSTANCE == 00 - uint32_t uart_periph_start = tfm_peripheral_uarte00.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 20 - uint32_t uart_periph_start = tfm_peripheral_uarte20.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 21 - uint32_t uart_periph_start = tfm_peripheral_uarte21.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 22 - uint32_t uart_periph_start = tfm_peripheral_uarte22.periph_start; -#elif NRF_SECURE_UART_INSTANCE == 30 - uint32_t uart_periph_start = tfm_peripheral_uarte30.periph_start; -#endif - spu_peripheral_config_secure(uart_periph_start, SPU_LOCK_CONF_LOCKED); -#endif /* SECURE_UART1 */ - - /* Configure the CTRL-AP mailbox interface to be secure as it is used by the secure ADAC service */ - spu_peripheral_config_secure(NRF_CTRLAP_S_BASE, SPU_LOCK_CONF_LOCKED); - - /* Configure NRF_MEMCONF to be secure as it could otherwise be used to corrupt secure RAM. */ - spu_peripheral_config_secure(NRF_MEMCONF_S_BASE, SPU_LOCK_CONF_LOCKED); - - /* Configure trace to be secure, as the security implications of non-secure trace are not understood */ - spu_peripheral_config_secure(NRF_TAD_S_BASE, SPU_LOCK_CONF_LOCKED); - - /* Configure these HW features, which are not in the MDK, to be - * secure, as the security implications of them being non-secure - * are not understood - */ - uint32_t base_addresses[4] = { - 0x50056000, - 0x5008C000, - 0x500E6000, - 0x5010F000 - }; - for(int i = 0; i < 4; i++) { - spu_peripheral_config_secure(base_addresses[i], SPU_LOCK_CONF_LOCKED); - } - - /* Configure NRF_REGULATORS, and NRF_OSCILLATORS to be secure as NRF_REGULATORS.POFCON is needed - * to prevent glitches when the power supply is attacked. - * - * NB: Note that NRF_OSCILLATORS and NRF_REGULATORS have the same base address and must therefore - * have the same security configuration. - */ - spu_peripheral_config_secure(NRF_REGULATORS_S_BASE, SPU_LOCK_CONF_LOCKED); -#else /* NRF54L_SERIES */ -static const uint32_t target_peripherals[] = { - /* The following peripherals share ID: - * - FPU (FPU cannot be configured in NRF91 series, it's always NS) - * - DCNF (On 53, but not 91) - */ -#ifndef NRF91_SERIES - NRF_FPU_S_BASE, -#endif - /* The following peripherals share ID: - * - REGULATORS - * - OSCILLATORS - */ - NRF_REGULATORS_S_BASE, - /* The following peripherals share ID: - * - CLOCK - * - POWER - * - RESET (On 53, but not 91) - */ - NRF_CLOCK_S_BASE, - /* The following peripherals share ID: (referred to as Serial-Box) - * - SPIMx - * - SPISx - * - TWIMx - * - TWISx - * - UARTEx - */ - - /* When UART0 is a secure peripheral we need to leave Serial-Box 0 as Secure. - * The UART Driver will configure it as non-secure when it uninitializes. - */ -#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 0) - NRF_SPIM0_S_BASE, -#endif -#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 1) - /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */ - NRF_SPIM1_S_BASE, -#endif - NRF_SPIM2_S_BASE, - NRF_SPIM3_S_BASE, -#ifdef NRF_SPIM4 - NRF_SPIM4_S_BASE, -#endif - NRF_SAADC_S_BASE, - NRF_TIMER0_S_BASE, - NRF_TIMER1_S_BASE, - NRF_TIMER2_S_BASE, - NRF_RTC0_S_BASE, - NRF_RTC1_S_BASE, - NRF_DPPIC_S_BASE, -#ifndef PSA_API_TEST_IPC -#ifdef NRF_WDT0 - /* WDT0 is used as a secure peripheral in PSA FF tests */ - NRF_WDT0_S_BASE, -#endif -#ifdef NRF_WDT - NRF_WDT_S_BASE, -#endif -#endif /* PSA_API_TEST_IPC */ -#ifdef NRF_WDT1 - NRF_WDT1_S_BASE, -#endif - /* The following peripherals share ID: - * - COMP - * - LPCOMP - */ -#ifdef NRF_COMP - NRF_COMP_S_BASE, -#endif - NRF_EGU0_S_BASE, - NRF_EGU1_S_BASE, - NRF_EGU2_S_BASE, - NRF_EGU3_S_BASE, - NRF_EGU4_S_BASE, -#ifndef PSA_API_TEST_IPC - /* EGU5 is used as a secure peripheral in PSA FF tests */ - NRF_EGU5_S_BASE, -#endif - NRF_PWM0_S_BASE, - NRF_PWM1_S_BASE, - NRF_PWM2_S_BASE, - NRF_PWM3_S_BASE, -#ifdef NRF_PDM - NRF_PDM_S_BASE, -#endif -#ifdef NRF_PDM0 - NRF_PDM0_S_BASE, -#endif -#ifdef NRF_I2S - NRF_I2S_S_BASE, -#endif -#ifdef NRF_I2S0 - NRF_I2S0_S_BASE, -#endif - NRF_IPC_S_BASE, -#ifndef SECURE_QSPI -#ifdef NRF_QSPI - NRF_QSPI_S_BASE, -#endif -#endif -#ifdef NRF_NFCT - NRF_NFCT_S_BASE, -#endif -#ifdef NRF_MUTEX - NRF_MUTEX_S_BASE, -#endif -#ifdef NRF_QDEC0 - NRF_QDEC0_S_BASE, -#endif -#ifdef NRF_QDEC1 - NRF_QDEC1_S_BASE, -#endif -#ifdef NRF_USBD - NRF_USBD_S_BASE, -#endif -#ifdef NRF_USBREGULATOR - NRF_USBREGULATOR_S_BASE, -#endif /* NRF_USBREGULATOR */ - NRF_NVMC_S_BASE, - NRF_P0_S_BASE, -#ifdef NRF_P1 - NRF_P1_S_BASE, -#endif /*NRF_P1 */ -#if defined(NRF91_SERIES) || defined(NRF53_SERIES) - NRF_VMC_S_BASE -#endif -}; - - for (int i = 0; i < ARRAY_SIZE(target_peripherals); i++) { - spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED); - } - -#endif /* NRF54L_SERIES */ - - /* DPPI channel configuration */ - dppi_channel_configuration(); - - /* GPIO pin configuration */ - uint32_t secure_pins[] = { -#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE - TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, -#endif -#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE - TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, -#endif -#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE - TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, -#endif - }; - - /* Note that there are two different API's for SPU configuration */ -#if NRF_SPU_HAS_MEMORY - - for(int port = 0; port < ARRAY_SIZE(secure_pins); port++){ - nrf_spu_gpio_config_set(NRF_SPU, port, secure_pins[port], SPU_LOCK_CONF_LOCKED); - } - -#elif NRF_SPU_HAS_PERIPHERAL_ACCESS - - for(int port = 0; port < ARRAY_SIZE(secure_pins); port++) { - for (int pin = 0; pin < 32; pin++) { - if (secure_pins[port] & (1 << pin)) { - bool enable = true; // secure - - /* - * Unfortunately, NRF_P0 is not configured by NRF_SPU00, etc. - * so it is a bit convoluted to find the SPU instance for port x. - */ - uint32_t gpio_port_addr[2] = { - NRF_P0_S_BASE, - NRF_P1_S_BASE, - }; - - NRF_SPU_Type * spu_instance = spu_instance_from_peripheral_addr(gpio_port_addr[port]); - - nrf_spu_feature_secattr_set(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, port, pin, enable); - nrf_spu_feature_lock_enable(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, port, pin); - } - } - } -#else -#error "Expected either NRF_SPU_HAS_MEMORY or NRF_SPU_HAS_PERIPHERAL_ACCESS to be true" -#endif - - /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal - * oscillator (LFXO) can be used. - * This configuration can be done only from secure code, as otherwise those - * register fields are not accessible. That's why it is placed here. - */ -#ifdef NRF53_SERIES - nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); - nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); -#endif /* NRF53_SERIES */ -#ifdef NRF54L_SERIES - /* NRF54L has a different define */ - nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_GPIO); - nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_GPIO); -#endif - - /* - * 91 has an instruction cache. - * 53 has both instruction cache and a data cache. - * - * 53's instruction cache has an nrfx driver, but 91's cache is - * not supported by nrfx at time of writing. - * - * We enable all caches available here because non-secure cannot - * configure caches. - */ -#if defined(NVMC_FEATURE_CACHE_PRESENT) // From MDK - nrfx_nvmc_icache_enable(); -#elif defined(CACHE_PRESENT) // From MDK - -#ifdef NRF_CACHE - nrf_cache_enable(NRF_CACHE); -#endif -#ifdef NRF_ICACHE - nrf_cache_enable(NRF_ICACHE); -#endif -#ifdef NRF_DCACHE - nrf_cache_enable(NRF_DCACHE); -#endif - -#endif - -#ifdef RRAMC_PRESENT - nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); - - config.mode_write = true; - -#if CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE > 0 - config.preload_timeout_enable = true; - config.preload_timeout = CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE; -#else - config.preload_timeout_enable = false; - config.preload_timeout = 0; -#endif - - /* Don't use an event handler until it's understood whether we - * want it or not - */ - nrfx_rramc_evt_handler_t handler = NULL; - - nrfx_err_t err = nrfx_rramc_init(&config, handler); - if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { - return err; - } -#endif /* RRAMC_PRESENT */ - -#ifdef NRF54L_SERIES - /* SOC configuration from Zephyr's soc.c. */ - int soc_err = nordicsemi_nrf54l_init(); - if (soc_err) { - return soc_err; - } -#endif - -#if NRF_SPU_HAS_MEMORY - /* Enforce that the nRF5340 Network MCU is in the Non-Secure - * domain. Non-secure is the HW reset value for the network core - * so configuring this should not be necessary, but we want to - * make sure that the bootloader has not accidentally configured - * it to be secure. Additionally we lock the register to make sure - * it doesn't get changed by accident. - */ - nrf_spu_extdomain_set(NRF_SPU, 0, false, true); -#endif - - return TFM_PLAT_ERR_SUCCESS; -} diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.h b/platform/ext/target/nordic_nrf/common/core/target_cfg.h index 1b3072582c..dd767b3865 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.h +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.h @@ -35,6 +35,9 @@ #include "tfm_plat_defs.h" #include "region_defs.h" +#define NRF_UARTE_INSTANCE(id) NRF_UARTE##id +#define NRF_UARTE_INSTANCE_GET(id) NRF_UARTE_INSTANCE(id) + #ifndef NRF_SECURE_UART_INSTANCE #define TFM_DRIVER_STDIO Driver_USART1 #elif NRF_SECURE_UART_INSTANCE == 0 diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c new file mode 100644 index 0000000000..c94181a475 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include +#include +#include +#include +#include + +#define SPU_ADDRESS_REGION (0x50000000) +#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) +#define GET_SPU_INSTANCE(periph) \ + ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) + +#ifdef NRF53_SERIES +#include +#define PIN_XL1 0 +#define PIN_XL2 1 +#endif + +extern const struct memory_region_limits memory_regions; + +static inline enum tfm_plat_err_t configure_approtect_nvmc(void) +{ +#if defined(NRF_APPROTECT) + /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot.*/ + if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected)) { + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected); + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +#endif +#if defined(NRF_SECURE_APPROTECT) + /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot. */ + if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected)) { + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected); + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +#if defined(NRF53_SERIES) + +static inline enum tfm_plat_err_t configure_approtect_registers(void) +{ +#if defined(DAUTH_NONE) + /* Disable debugging */ + NRF_CTRLAP->APPROTECT.DISABLE = 0; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; +#elif defined(DAUTH_NS_ONLY) + /* Allow debugging Non-Secure only */ + NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; +#elif defined(DAUTH_FULL) || defined(DAUTH_CHIP_DEFAULT) + /* Allow debugging */ + /* Use the configuration in UICR. */ + NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = NRF_UICR->SECUREAPPROTECT; +#else +#error "No debug authentication setting is provided." +#endif + + /* Lock access to APPROTECT, SECUREAPPROTECT */ + NRF_CTRLAP->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked + << CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk; + NRF_CTRLAP->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked + << CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk; + + return TFM_PLAT_ERR_SUCCESS; +} +#endif + +enum tfm_plat_err_t init_debug(void) +{ + +#if (defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT)) && !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access controlled by NRF_APPROTECT and NRF_SECURE_APPROTECT." +#elif defined(NRF91_SERIES) && !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access on the nRF91 series can only be configured by programming the corresponding registers in UICR." +#endif + +#if defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT) + return configure_approtect_nvmc(); +#elif defined(NRF53_SERIES) + return configure_approtect_registers(); +#endif +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ + +void sau_and_idau_cfg(void) +{ + /* IDAU (SPU) is always enabled. SAU is non-existent. + * Allow SPU to have precedence over (non-existing) ARMv8-M SAU. + */ + TZ_SAU_Disable(); + SAU->CTRL |= SAU_CTRL_ALLNS_Msk; +} + +enum tfm_plat_err_t spu_init_cfg(void) +{ + /* + * Configure SPU Regions for Non-Secure Code and SRAM (Data) + * Configure SPU for Peripheral Security + * Configure Non-Secure Callable Regions + * Configure Secondary Image Partition + * Configure Non-Secure Storage Partition + */ + + /* Reset Flash and SRAM configuration of regions that are not owned by + * the bootloader(s) to all-Secure. + */ + spu_regions_reset_unlocked_secure(); + + uint32_t perm; + + /* Configure Secure Code to be secure and RX */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + /* Do not permit writes to secure flash */ + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_flash_config(S_CODE_START, S_CODE_LIMIT, SPU_SECURE_ATTR_SECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configure Secure RAM to be secure and RWX */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + /* Permit execute from Secure RAM because otherwise Crypto fails + * to initialize. */ + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_sram_config(S_DATA_START, S_DATA_LIMIT, SPU_SECURE_ATTR_SECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configures SPU Code and Data regions to be non-secure */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_flash_config(memory_regions.non_secure_partition_base, + memory_regions.non_secure_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); + + spu_regions_sram_config(NS_DATA_START, NS_DATA_LIMIT, SPU_SECURE_ATTR_NONSECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configures veneers region to be non-secure callable */ + spu_regions_flash_config_non_secure_callable(memory_regions.veneer_base, + memory_regions.veneer_limit - 1); + +#ifdef NRF_NS_SECONDARY + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + + /* Secondary image partition */ + spu_regions_flash_config(memory_regions.secondary_partition_base, + memory_regions.secondary_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* NRF_NS_SECONDARY */ + +#ifdef NRF_NS_STORAGE_PARTITION_START + /* Configures storage partition to be non-secure */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + + spu_regions_flash_config(memory_regions.non_secure_storage_partition_base, + memory_regions.non_secure_storage_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* NRF_NS_STORAGE_PARTITION_START */ + +#ifdef REGION_PCD_SRAM_ADDRESS + enum tfm_plat_err_t err; + bool provisioning_required; + /* Netcore needs PCD memory area to be non-secure. */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + + err = tfm_plat_provisioning_is_required(&provisioning_required); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + if (provisioning_required) { + perm |= NRF_SPU_MEM_PERM_WRITE; + } + + spu_regions_sram_config(REGION_PCD_SRAM_ADDRESS, REGION_PCD_SRAM_LIMIT, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* REGION_PCD_SRAM_ADDRESS */ + + return TFM_PLAT_ERR_SUCCESS; +} + +static void dppi_channel_configuration(void) +{ + /* The SPU HW and corresponding NRFX HAL API have two different + * API's for DPPI security configuration. The defines + * NRF_SPU_HAS_OWNERSHIP and NRF_SPU_HAS_MEMORY identify which of the two API's + * are present. + * + * TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE is configurable, but + * usually defaults to 0, which results in all DPPI channels being + * non-secure. + */ + /* There is only one dppi_id */ + uint8_t dppi_id = 0; + nrf_spu_dppi_config_set(NRF_SPU, dppi_id, TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, + SPU_LOCK_CONF_LOCKED); +} + +static void cache_configuration(void) +{ + /* + * 91 has an instruction cache. + * 53 has both instruction cache and a data cache. + * + * 53's instruction cache has an nrfx driver, but 91's cache is + * not supported by nrfx at time of writing. + * + * We enable all caches available here because non-secure cannot + * configure caches. + */ +#if defined(NVMC_FEATURE_CACHE_PRESENT) // From MDK + nrfx_nvmc_icache_enable(); +#endif +#if defined(CACHE_PRESENT) // From MDK + nrf_cache_enable(NRF_CACHE); +#endif +} + +static void gpio_configuration(void) +{ + /* GPIO pin configuration */ + uint32_t secure_pins[] = { +#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, +#endif + }; + + /* Note that there are two different API's for SPU configuration */ + + for (int port = 0; port < ARRAY_SIZE(secure_pins); port++) { + nrf_spu_gpio_config_set(NRF_SPU, port, secure_pins[port], SPU_LOCK_CONF_LOCKED); + } + + /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal + * oscillator (LFXO) can be used. + * This configuration can be done only from secure code, as otherwise those + * register fields are not accessible. That's why it is placed here. + */ +#ifdef NRF53_SERIES + nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); + nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); +#endif /* NRF53_SERIES */ +} + +static void peripheral_configuration(void) +{ + /* Peripheral configuration */ + static const uint32_t target_peripherals[] = { + /* The following peripherals share ID: + * - FPU (FPU cannot be configured in NRF91 series, it's always NS) + * - DCNF (On 53, but not 91) + */ +#ifndef NRF91_SERIES + NRF_FPU_S_BASE, +#endif + /* The following peripherals share ID: + * - REGULATORS + * - OSCILLATORS + */ + NRF_REGULATORS_S_BASE, + /* The following peripherals share ID: + * - CLOCK + * - POWER + * - RESET (On 53, but not 91) + */ + NRF_CLOCK_S_BASE, + /* The following peripherals share ID: (referred to as Serial-Box) + * - SPIMx + * - SPISx + * - TWIMx + * - TWISx + * - UARTEx + */ + + /* When UART0 is a secure peripheral we need to leave Serial-Box 0 as Secure. + * The UART Driver will configure it as non-secure when it uninitializes. + */ +#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 0) + NRF_SPIM0_S_BASE, +#endif +#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 1) + /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */ + NRF_SPIM1_S_BASE, +#endif + NRF_SPIM2_S_BASE, + NRF_SPIM3_S_BASE, +#ifdef NRF_SPIM4 + NRF_SPIM4_S_BASE, +#endif + NRF_SAADC_S_BASE, + NRF_TIMER0_S_BASE, + NRF_TIMER1_S_BASE, + NRF_TIMER2_S_BASE, + NRF_RTC0_S_BASE, + NRF_RTC1_S_BASE, + NRF_DPPIC_S_BASE, +#ifndef PSA_API_TEST_IPC +#ifdef NRF_WDT0 + /* WDT0 is used as a secure peripheral in PSA FF tests */ + NRF_WDT0_S_BASE, +#endif +#ifdef NRF_WDT + NRF_WDT_S_BASE, +#endif +#endif /* PSA_API_TEST_IPC */ +#ifdef NRF_WDT1 + NRF_WDT1_S_BASE, +#endif + /* The following peripherals share ID: + * - COMP + * - LPCOMP + */ +#ifdef NRF_COMP + NRF_COMP_S_BASE, +#endif + NRF_EGU0_S_BASE, + NRF_EGU1_S_BASE, + NRF_EGU2_S_BASE, + NRF_EGU3_S_BASE, + NRF_EGU4_S_BASE, +#ifndef PSA_API_TEST_IPC + /* EGU5 is used as a secure peripheral in PSA FF tests */ + NRF_EGU5_S_BASE, +#endif + NRF_PWM0_S_BASE, + NRF_PWM1_S_BASE, + NRF_PWM2_S_BASE, + NRF_PWM3_S_BASE, +#ifdef NRF_PDM + NRF_PDM_S_BASE, +#endif +#ifdef NRF_PDM0 + NRF_PDM0_S_BASE, +#endif +#ifdef NRF_I2S + NRF_I2S_S_BASE, +#endif +#ifdef NRF_I2S0 + NRF_I2S0_S_BASE, +#endif + NRF_IPC_S_BASE, +#ifndef SECURE_QSPI +#ifdef NRF_QSPI + NRF_QSPI_S_BASE, +#endif +#endif +#ifdef NRF_NFCT + NRF_NFCT_S_BASE, +#endif +#ifdef NRF_MUTEX + NRF_MUTEX_S_BASE, +#endif +#ifdef NRF_QDEC0 + NRF_QDEC0_S_BASE, +#endif +#ifdef NRF_QDEC1 + NRF_QDEC1_S_BASE, +#endif +#ifdef NRF_USBD + NRF_USBD_S_BASE, +#endif +#ifdef NRF_USBREGULATOR + NRF_USBREGULATOR_S_BASE, +#endif /* NRF_USBREGULATOR */ + NRF_NVMC_S_BASE, + NRF_P0_S_BASE, +#ifdef NRF_P1 + NRF_P1_S_BASE, +#endif /*NRF_P1 */ + NRF_VMC_S_BASE + }; + + for (int i = 0; i < ARRAY_SIZE(target_peripherals); i++) { + spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED); + } +} + +enum tfm_plat_err_t spu_periph_init_cfg(void) +{ + + /* The default peripheral configuration sets most of the peripherals with split-security + * as non-secure by default. The peripherals explicitly configured as secure + * will be configured as secure later in the tfm_hal_bind_boundary function. + */ + peripheral_configuration(); + dppi_channel_configuration(); + gpio_configuration(); + cache_configuration(); + +#ifdef NRF53_SERIES + /* Enforce that the nRF5340 Network MCU is in the Non-Secure + * domain. Non-secure is the HW reset value for the network core + * so configuring this should not be necessary, but we want to + * make sure that the bootloader has not accidentally configured + * it to be secure. Additionally we lock the register to make sure + * it doesn't get changed by accident. + */ + nrf_spu_extdomain_set(NRF_SPU, 0, false, true); +#endif /* NRF53_SERIES */ + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ + for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that the SPU instance(s) are targeted to S state */ + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + +#ifdef SECURE_UART1 + /* IRQ for the selected secure UART has to target S state */ + NVIC_ClearTargetState( + NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + /* SPU interrupt enabling */ + spu_enable_interrupts(); + + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c new file mode 100644 index 0000000000..1f148e044a --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c @@ -0,0 +1,536 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include + +#if CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE > 0 +#define WRITE_BUFFER_SIZE CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE +#else +#define WRITE_BUFFER_SIZE 0 +#endif + +#if !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." +#endif + +#define SPU_ADDRESS_REGION (0x50000000) +#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) +#define GET_SPU_INSTANCE(periph) \ + ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) + +#if defined(NRF54LV10A_ENGA_XXAA) +/* On nRF54LV10A XL1 and XL2 are(P1.13) and XL2(P1.14) */ +#define PIN_XL1 45 +#define PIN_XL2 46 +#elif defined(NRF54LM20A_ENGA_XXAA) +/* On nRF54LM20A XL1 and XL2 are(P1.13) and XL2(P1.14) */ +#define PIN_XL1 45 +#define PIN_XL2 46 +#else +/* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ +#define PIN_XL1 32 +#define PIN_XL2 33 +#endif /* SOC_NRF54LV10A_ENGA || SOC_NRF54LM20A_ENGA */ + +/* During TF-M system initialization we invoke a function that comes + * from Zephyr. This function does not have a header file so we + * declare its prototype here. + */ +int nordicsemi_nrf54l_init(void); + +extern const struct memory_region_limits memory_regions; + +struct mpc_region_override { + nrf_mpc_override_config_t config; + nrf_owner_t owner_id; + uintptr_t start_address; + size_t endaddr; + uint32_t perm; + uint32_t permmask; + size_t index; +}; + +static void mpc_configure_override(NRF_MPC_Type *mpc, struct mpc_region_override *override) +{ + nrf_mpc_override_startaddr_set(mpc, override->index, override->start_address); + nrf_mpc_override_endaddr_set(mpc, override->index, override->endaddr); + nrf_mpc_override_perm_set(mpc, override->index, override->perm); + nrf_mpc_override_permmask_set(mpc, override->index, override->permmask); +#if defined(NRF_MPC_HAS_OVERRIDE_OWNERID) && NRF_MPC_HAS_OVERRIDE_OWNERID + nrf_mpc_override_ownerid_set(mpc, override->index, override->owner_id); +#endif + nrf_mpc_override_config_set(mpc, override->index, &override->config); +} + +/* + * Configure the override struct with reasonable defaults. This includes: + * + * Use a slave number of 0 to avoid redirecting bus transactions from + * one slave to another. + * + * Lock the override to prevent the code that follows from tampering + * with the configuration. + * + * Enable the override so it takes effect. + * + * Indicate that secdom is not enabled as this driver is not used on + * platforms with secdom. + */ +static void init_mpc_region_override(struct mpc_region_override *override) +{ + *override = (struct mpc_region_override){ + .config = + (nrf_mpc_override_config_t){ + .slave_number = 0, + .lock = true, + .enable = true, + .secdom_enable = false, + .secure_mask = true, + }, + .perm = 0, /* 0 for non-secure */ + .owner_id = 0, + }; + + override->permmask = MPC_OVERRIDE_PERM_SECATTR_Msk; +} + +static nrfx_err_t rramc_configuration(void) +{ + nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); + + config.mode_write = true; + +#if CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE > 0 + config.preload_timeout_enable = true; + config.preload_timeout = CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE; +#else + config.preload_timeout_enable = false; + config.preload_timeout = 0; +#endif + + /* Don't use an event handler until it's understood whether we + * want it or not + */ + nrfx_rramc_evt_handler_t handler = NULL; + + nrfx_err_t err = nrfx_rramc_init(&config, handler); + if (err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + return err; + } + + return NRFX_SUCCESS; +} + +enum tfm_plat_err_t init_debug(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ + +void sau_and_idau_cfg(void) +{ + /* + * This SAU configuration aligns with ARM's RSS implementation of + * sau_and_idau_cfg when possible. + */ + + /* Enables SAU */ + TZ_SAU_Enable(); + + /* Configures SAU regions to be non-secure */ + + /* Note that this SAU configuration assumes that there is only one + * secure NVM partition and one non-secure NVM partition. Meaning, + * memory_regions.non_secure_partition_limit is at the end of + * NVM. + */ + + /* Configure the end of NVM, and the FICR, to be non-secure using + a single region. Note that the FICR is placed after the + non-secure NVM and before the UICR.*/ + SAU->RNR = 0; + SAU->RBAR = (memory_regions.non_secure_partition_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (NRF_UICR_S_BASE & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Leave SAU region 1 disabled until we find a use for it */ + + /* Configures veneers region to be non-secure callable */ + SAU->RNR = 2; + SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk | + SAU_RLAR_NSC_Msk; + + /* Configures SAU region 3 to cover both the end of SRAM and + * regions above it as shown in the "Example memory map" in the + * "Product Specification" */ + SAU->RNR = 3; + SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (0xFFFFFFFFul & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; +} + +enum tfm_plat_err_t nrf_mpc_init_cfg(void) +{ + /* On 54l the NRF_MPC00->REGION[]'s are fixed in HW and the + * OVERRIDE indexes (that are useful to us) start at 0 and end + * (inclusive) at 4. + * + * Note that the MPC regions configure all volatile and non-volatile memory as secure, so we + * only need to explicitly OVERRIDE the non-secure addresses to permit non-secure access. + * + * Explicitly configuring memory as secure is not necessary. + * + * The last OVERRIDE in 54L is fixed in HW and exists to prevent + * other bus masters than the KMU from accessing CRACEN protected RAM. + * + * Note that we must take care not to configure an OVERRIDE that + * affects an active bus transaction. + * + * Note that we don't configure the NSC region to be NS because + * from the MPC's perspective it is secure. NSC is only configurable from the SAU. + * + * Note that OVERRIDE[n].MASTERPORT has a reasonable reset value + * so it is left unconfigured. + * + * Note that there are two owners in 54L. KMU with owner ID 1, and everything else with + * owner ID 0. + */ + + uint32_t index = 0; + /* + * Configure the non-secure partition of the non-volatile + * memory. This MPC region is intended to cover both the + * non-secure partition in the NVM and also the FICR. The FICR + * starts after the NVM and ends just before the UICR. + */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = memory_regions.non_secure_partition_base; + override.endaddr = NRF_UICR_S_BASE; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + /* Configure the non-secure partition of the volatile memory */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = NS_DATA_START; + override.endaddr = 1 + NS_DATA_LIMIT; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + if (index > 4) { + /* Used more overrides than are available */ + tfm_core_panic(); + } + + /* Lock and disable any unused MPC overrides to prevent malicious configuration */ + while (index <= 4) { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.config.enable = false; + + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + return TFM_PLAT_ERR_SUCCESS; +} + +void peripheral_configuration(void) +{ +#if SECURE_UART1 + /* Configure TF-M's UART peripheral to be secure */ + uint32_t uart_periph_start; +#if NRF_SECURE_UART_INSTANCE == 00 + uart_periph_start = tfm_peripheral_uarte00.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 20 + uart_periph_start = tfm_peripheral_uarte20.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 21 + uart_periph_start = tfm_peripheral_uarte21.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 22 + uart_periph_start = tfm_peripheral_uarte22.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 30 + uart_periph_start = tfm_peripheral_uarte30.periph_start; +#else +#error "Unsupported NRF_SECURE_UART_INSTANCE for nrf54l series. Supported instances: 00, 20, 21, 22, 30" +#endif + spu_peripheral_config_secure(uart_periph_start, SPU_LOCK_CONF_LOCKED); +#endif /* SECURE_UART1 */ + + /* Configure the CTRL-AP mailbox interface to be secure as it is used by the secure ADAC + * service */ + spu_peripheral_config_secure(NRF_CTRLAP_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure NRF_MEMCONF to be secure as it could otherwise be used to corrupt secure RAM. + */ + spu_peripheral_config_secure(NRF_MEMCONF_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure trace to be secure, as the security implications of non-secure trace are not + * understood */ + spu_peripheral_config_secure(NRF_TAD_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure these HW features, which are not in the MDK, to be + * secure, as the security implications of them being non-secure + * are not understood + */ + uint32_t base_addresses[4] = {0x50056000, 0x5008C000, 0x500E6000, 0x5010F000}; + for (int i = 0; i < 4; i++) { + spu_peripheral_config_secure(base_addresses[i], SPU_LOCK_CONF_LOCKED); + } + + /* Configure NRF_REGULATORS, and NRF_OSCILLATORS to be secure as NRF_REGULATORS.POFCON is + * needed to prevent glitches when the power supply is attacked. + * + * NB: Note that NRF_OSCILLATORS and NRF_REGULATORS have the same base address and must + * therefore have the same security configuration. + */ + spu_peripheral_config_secure(NRF_REGULATORS_S_BASE, SPU_LOCK_CONF_LOCKED); +} + +static void gpiote_channel_configuration(void) +{ + /* Configure GPIOTE channels to be secure */ + uint32_t secure_gpiote_channels[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + uint32_t gpiote_instances[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + NRF_GPIOTE20_S_BASE, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + NRF_GPIOTE30_S_BASE, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + /* Configure the SPU GPIOTE registers. Each GPIOTE can fire 2 interrupts for + * each available channel. If a channel is configured as secure both of the + * interrupts will only available in secure mode so a single configuration + * should suffice. + */ + for (int i = 0; i < ARRAY_SIZE(gpiote_instances) - 1; i++) { + + NRF_SPU_Type *spu_instance = spu_instance_from_peripheral_addr(gpiote_instances[i]); + for (int channel = 0; channel < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT; channel++) { + if (secure_gpiote_channels[i] & (1 << channel)) { + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, channel); + + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, channel); + } + } + } +} + +static void gpio_configuration(void) +{ + /* GPIO pin configuration */ + uint32_t secure_pins[] = { +#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, +#endif + }; + + for (int port = 0; port < ARRAY_SIZE(secure_pins); port++) { + for (int pin = 0; pin < 32; pin++) { + if (secure_pins[port] & (1 << pin)) { + bool enable = true; // secure + + /* + * Unfortunately, NRF_P0 is not configured by NRF_SPU00, etc. + * so it is a bit convoluted to find the SPU instance for port x. + */ + uint32_t gpio_port_addr[2] = { + NRF_P0_S_BASE, + NRF_P1_S_BASE, + }; + + NRF_SPU_Type *spu_instance = + spu_instance_from_peripheral_addr(gpio_port_addr[port]); + + nrf_spu_feature_secattr_set(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin, enable); + nrf_spu_feature_lock_enable(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin); + } + } + } + + + /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal + * oscillator (LFXO) can be used. + * This configuration can be done only from secure code, as otherwise those + * register fields are not accessible. That's why it is placed here. + */ + nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_GPIO); + nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_GPIO); +} + +enum tfm_plat_err_t spu_periph_init_cfg(void) +{ + /* Peripheral configuration */ + /* Configure features to be non-secure */ + + /* + * Due to MLT-7600, many SPU HW reset values are wrong. The docs + * generally features being non-secure when coming out of HW + * reset, but the HW has a good mix of both. + * + * When configuring NRF_SPU 0 will indicate non-secure and 1 will + * indicate secure. + * + * Most of the chip should be non-secure so to simplify and be + * consistent, we memset the entire memory map of each SPU + * peripheral to 0. + * + * Just after memsetting to 0 we explicitly configure the + * peripherals that should be secure back to secure again. + */ + // TODO: Evaluate if it is safe to memset everything + // in NRF_SPU to 0. + memset(NRF_SPU00, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU10, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU20, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU30, 0, sizeof(NRF_SPU_Type)); + + peripheral_configuration(); + + /* TODO_NRF54L15: Use the nrf_spu_feature API to configure DPPI + channels according to a user-controllable config similar to + TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE. */ + + gpiote_channel_configuration(); + gpio_configuration(); + + nrf_cache_enable(NRF_ICACHE); + + nrfx_err_t nrfx_err = rramc_configuration(); + if (nrfx_err != NRFX_SUCCESS) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* SOC configuration from Zephyr's soc.c. */ + int soc_err = nordicsemi_nrf54l_init(); + if (soc_err) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ + for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + /* Make sure that the SPU instance(s) are targeted to S state */ + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_CRACEN)); + NVIC_ClearTargetState(MPC00_IRQn); + +#ifdef SECURE_UART1 + /* IRQ for the selected secure UART has to target S state */ + NVIC_ClearTargetState( + NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); +#endif + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + /* SPU interrupt enabling */ + spu_enable_interrupts(); + + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + mpc_clear_events(); + /* MPC interrupt enabling */ + mpc_enable_interrupts(); + + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + + /* The CRACEN driver configures the NVIC for CRACEN and is + * therefore omitted here. + */ + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake index e35ee17ebc..12281f1ff6 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake @@ -8,7 +8,5 @@ include(${PLATFORM_PATH}/common/core/config.cmake) -set(SECURE_UART30 ON CACHE BOOL "Enable secure UART" FORCE) set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) -set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c index b3bca1bfc8..1dff3596c7 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c @@ -192,6 +192,21 @@ enum tfm_hal_status_t tfm_spim00_irq_init(void *p_pt, } #endif +#if TFM_PERIPHERAL_SPIM21_SECURE +static struct irq_t spim21_irq = {0}; + +void SPIM21_IRQHandler(void) +{ + spm_handle_interrupt(spim21_irq.p_pt, spim21_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim21_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim21_irq, TFM_SPIM21_IRQ, p_pt, p_ildi); +} +#endif + #if TFM_PERIPHERAL_SPIM22_SECURE static struct irq_t spim22_irq = {0}; diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake index 2222734d24..da98d7efda 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake @@ -8,3 +8,4 @@ include(${PLATFORM_PATH}/common/nrf54l/config.cmake) +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h index 79112d5bac..a9ae3c4500 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h @@ -97,7 +97,12 @@ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) /* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #ifdef PSA_API_TEST_IPC /* Firmware Framework test suites */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake index 2222734d24..da98d7efda 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake @@ -8,3 +8,4 @@ include(${PLATFORM_PATH}/common/nrf54l/config.cmake) +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h index 79112d5bac..a9ae3c4500 100644 --- a/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h @@ -97,7 +97,12 @@ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) /* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #ifdef PSA_API_TEST_IPC /* Firmware Framework test suites */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt new file mode 100644 index 0000000000..485f1859b7 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/CMakeLists.txt @@ -0,0 +1,52 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + ../nrf54l +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ../nrf54l/nrf54l_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake + ns/CMakeLists.txt + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lm20a +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lm20a +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake new file mode 100644 index 0000000000..ebc2bbbb8c --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/config.cmake @@ -0,0 +1,12 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) + +# Override UART instance for nRF54LM20A - it uses UART30, not UART20 +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54lm20a/cpuarch.cmake new file mode 100644 index 0000000000..67d963b80c --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF54LM20A_ENGA_XXAA + NRF54L_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt new file mode 100644 index 0000000000..6e8396c35d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h new file mode 100644 index 0000000000..65ab9951ca --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/flash_layout.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF54LM20A Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (512 KB) + * 0x0008_0000 Protected Storage Area (16 KB) + * 0x0008_4000 Internal Trusted Storage Area (16 KB) + * 0x0008_8000 OTP / NV counters area (8 KB) + * 0x0008_A000 Non-secure image primary (1356 KB) + * 0x001F_2000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF54LM20A has 2036 kB of non volatile memory (RRAM) but the last 96kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0x1E5000) /* 1940 kB since the last 96kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF54LM20A has 512 kB of volatile memory (SRAM) but the last 96kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00068000) /* 416 kB since the last 96kB are reserved for FLPR */ + +#define FLASH_S_PARTITION_SIZE (0x80000) /* S partition: 512 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x153000) /* NS partition: 1356 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h new file mode 100644 index 0000000000..51a8a30e78 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/partition/region_defs.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x4D0) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lm20a/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lm20a/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..f4cc1937f4 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lm20a/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf54lm20a") diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt new file mode 100644 index 0000000000..9f470348a1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/CMakeLists.txt @@ -0,0 +1,52 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + ../nrf54l +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ../nrf54l/nrf54l_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake + ns/CMakeLists.txt + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lv10a +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54lv10a +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake new file mode 100644 index 0000000000..088d9a5d95 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/config.cmake @@ -0,0 +1,11 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) + +set(NRF_SECURE_UART_INSTANCE 20 CACHE STRING "The UART instance number to use for secure UART" FORCE) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54lv10a/cpuarch.cmake new file mode 100644 index 0000000000..3124118308 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF54LV10A_ENGA_XXAA + NRF54L_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt new file mode 100644 index 0000000000..6e8396c35d --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/flash_layout.h new file mode 100644 index 0000000000..cb0fd77770 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/flash_layout.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF54LV10A Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (384 KB) + * 0x0006_0000 Protected Storage Area (16 KB) + * 0x0006_4000 Internal Trusted Storage Area (16 KB) + * 0x0006_8000 OTP / NV counters area (8 KB) + * 0x0006_A000 Non-secure image primary (504 KB) + * 0x000E_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF54LV10A has 1012 kB of non volatile memory (RRAM) but the last 62kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0xF0000) /* 960 kB since the last 62kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF54LV10A has 192 kB of volatile memory (SRAM) but the last 48kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00024000) /* 144 kB since the last 48kB are reserved for FLPR */ + +#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x7E000) /* NS partition: 504 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h new file mode 100644 index 0000000000..a9ae3c4500 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/partition/region_defs.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x47C) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54lv10a/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf54lv10a/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..5258730b3e --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54lv10a/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf54lv10a") diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h index 6159c19f4b..1059d56478 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h @@ -13,7 +13,9 @@ extern "C" { #endif #ifdef SECURE_UART1 -#if NRF_SECURE_UART_INSTANCE == 30 +#if NRF_SECURE_UART_INSTANCE == 20 +#define TFM_PERIPHERAL_UARTE20_SECURE 1 +#elif NRF_SECURE_UART_INSTANCE == 30 #define TFM_PERIPHERAL_UARTE30_SECURE 1 #endif #endif diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h index 6159c19f4b..1059d56478 100644 --- a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h @@ -13,7 +13,9 @@ extern "C" { #endif #ifdef SECURE_UART1 -#if NRF_SECURE_UART_INSTANCE == 30 +#if NRF_SECURE_UART_INSTANCE == 20 +#define TFM_PERIPHERAL_UARTE20_SECURE 1 +#elif NRF_SECURE_UART_INSTANCE == 30 #define TFM_PERIPHERAL_UARTE30_SECURE 1 #endif #endif diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/CMakeLists.txt new file mode 100644 index 0000000000..9e87f0eac1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/CMakeLists.txt @@ -0,0 +1,60 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf54lm20a nrf54lm20a) + +target_include_directories(platform_region_defs + BEFORE INTERFACE + ../common/nrf54lm20a/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf54lm20a/partition + services/include +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/RTE_Device.h new file mode 100644 index 0000000000..3cba0224c8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART20 1 + +#define RTE_USART20_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 36),\ + NRF_PSEL(UART_RX, 0, 37),\ + NRF_PSEL(UART_RTS, 0, 38),\ + NRF_PSEL(UART_CTS, 0, 39),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 0),\ + NRF_PSEL(UART_RX, 0, 1),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake new file mode 100644 index 0000000000..e3c56921db --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf54lm20a/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake new file mode 100644 index 0000000000..721521cc08 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf54lm20a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/device_cfg.h new file mode 100644 index 0000000000..22ddb39ce1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 0000000000..23b1f06587 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +add_compile_definitions(NRF_CONFIG_CPU_FREQ_MHZ=128) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54lm20a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 0000000000..9ff8f6c37c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..6af19cd935 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54lm20a/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 0000000000..619f1f92cf --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_hal_platform.c new file mode 100644 index 0000000000..5f682a8253 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_peripherals_config.h new file mode 100644 index 0000000000..2fce36f8de --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lm20dk_nrf54lm20a_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + + +/* Explicitly configure UART20 as non-secure for NS world */ +#define TFM_PERIPHERAL_UARTE20_SECURE 0 + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#if defined(NRF54L_SERIES) + #include +#else + #error "Unknown device." +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/CMakeLists.txt new file mode 100644 index 0000000000..b23de56b74 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/CMakeLists.txt @@ -0,0 +1,60 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf54lv10a nrf54lv10a) + +target_include_directories(platform_region_defs + INTERFACE + ../common/nrf54lv10a/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf54lv10a/partition + services/include +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/RTE_Device.h new file mode 100644 index 0000000000..3cba0224c8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART20 1 + +#define RTE_USART20_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 36),\ + NRF_PSEL(UART_RX, 0, 37),\ + NRF_PSEL(UART_RTS, 0, 38),\ + NRF_PSEL(UART_CTS, 0, 39),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 0),\ + NRF_PSEL(UART_RX, 0, 1),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake new file mode 100644 index 0000000000..5d91d95708 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf54lv10a/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake new file mode 100644 index 0000000000..9f1545d534 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf54lv10a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/device_cfg.h new file mode 100644 index 0000000000..22ddb39ce1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 0000000000..58b5f3ac47 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +add_compile_definitions(NRF_CONFIG_CPU_FREQ_MHZ=128) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54lv10a/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 0000000000..0847daa215 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 0000000000..9ff8f6c37c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 0000000000..8e4ebb23a1 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54lv10a/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 0000000000..619f1f92cf --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_hal_platform.c new file mode 100644 index 0000000000..5f682a8253 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h new file mode 100644 index 0000000000..82ab7ad3b3 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54lv10dk_nrf54lv10a_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#if defined(NRF54L_SERIES) + #include +#else + #error "Unknown device." +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */