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Mathieu Choplainkartben
Mathieu Choplain
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kartben
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dts: arm: st: stm32wb: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
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‎dts/arm/st/wb/stm32wb.dtsi‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@
145145
compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller";
146146
reg = <0x58004000 0x400>;
147147
interrupts = <4 0>;
148-
clocks = <&rcc STM32_CLOCK(AHB3, 25U)>;
148+
clocks = <&rcc STM32_CLOCK(AHB3, 25)>;
149149

150150
#address-cells = <1>;
151151
#size-cells = <1>;
@@ -197,31 +197,31 @@
197197
gpio-controller;
198198
#gpio-cells = <2>;
199199
reg = <0x48000000 0x400>;
200-
clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
200+
clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
201201
};
202202

203203
gpiob: gpio@48000400 {
204204
compatible = "st,stm32-gpio";
205205
gpio-controller;
206206
#gpio-cells = <2>;
207207
reg = <0x48000400 0x400>;
208-
clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
208+
clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
209209
};
210210

211211
gpioc: gpio@48000800 {
212212
compatible = "st,stm32-gpio";
213213
gpio-controller;
214214
#gpio-cells = <2>;
215215
reg = <0x48000800 0x400>;
216-
clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
216+
clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
217217
};
218218

219219
gpiod: gpio@48000c00 {
220220
compatible = "st,stm32-gpio";
221221
gpio-controller;
222222
#gpio-cells = <2>;
223223
reg = <0x48000c00 0x400>;
224-
clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
224+
clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
225225
};
226226

227227
gpioe: gpio@48001000 {
@@ -230,7 +230,7 @@
230230
#gpio-cells = <2>;
231231
ngpios = <5>;
232232
reg = <0x48001000 0x400>;
233-
clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
233+
clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
234234
};
235235

236236
gpioh: gpio@48001c00 {
@@ -239,22 +239,22 @@
239239
#gpio-cells = <2>;
240240
ngpios = <4>;
241241
reg = <0x48001c00 0x400>;
242-
clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
242+
clocks = <&rcc STM32_CLOCK(AHB2, 7)>;
243243
};
244244
};
245245

246246
wwdg: watchdog@40002c00 {
247247
compatible = "st,stm32-window-watchdog";
248248
reg = <0x40002C00 0x400>;
249-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
249+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
250250
interrupts = <0 7>;
251251
status = "disabled";
252252
};
253253

254254
usart1: serial@40013800 {
255255
compatible = "st,stm32-usart", "st,stm32-uart";
256256
reg = <0x40013800 0x400>;
257-
clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
257+
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
258258
resets = <&rctl STM32_RESET(APB2, 14U)>;
259259
interrupts = <36 0>;
260260
status = "disabled";
@@ -266,7 +266,7 @@
266266
#address-cells = <1>;
267267
#size-cells = <0>;
268268
reg = <0x40005400 0x400>;
269-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
269+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
270270
interrupts = <30 0>, <31 0>;
271271
interrupt-names = "event", "error";
272272
status = "disabled";
@@ -278,7 +278,7 @@
278278
#address-cells = <1>;
279279
#size-cells = <0>;
280280
reg = <0x40005c00 0x400>;
281-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
281+
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
282282
interrupts = <32 0>, <33 0>;
283283
interrupt-names = "event", "error";
284284
status = "disabled";
@@ -288,7 +288,7 @@
288288
compatible = "st,stm32-rtc";
289289
reg = <0x40002800 0x400>;
290290
interrupts = <41 0>;
291-
clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
291+
clocks = <&rcc STM32_CLOCK(APB1, 10)>;
292292
prescaler = <32768>;
293293
alarms-count = <2>;
294294
alrm-exti-line = <17>;
@@ -307,7 +307,7 @@
307307
#size-cells = <0>;
308308
reg = <0x40013000 0x400>;
309309
interrupts = <34 5>;
310-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
310+
clocks = <&rcc STM32_CLOCK(APB2, 12)>;
311311
status = "disabled";
312312
};
313313

@@ -317,14 +317,14 @@
317317
#size-cells = <0>;
318318
reg = <0x40003800 0x400>;
319319
interrupts = <35 5>;
320-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
320+
clocks = <&rcc STM32_CLOCK(APB1, 14)>;
321321
status = "disabled";
322322
};
323323

324324
lpuart1: serial@40008000 {
325325
compatible = "st,stm32-lpuart", "st,stm32-uart";
326326
reg = <0x40008000 0x400>;
327-
clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
327+
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
328328
resets = <&rctl STM32_RESET(APB1H, 0U)>;
329329
interrupts = <37 0>;
330330
status = "disabled";
@@ -420,7 +420,7 @@
420420
adc1: adc@50040000 {
421421
compatible = "st,stm32-adc";
422422
reg = <0x50040000 0x400>;
423-
clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
423+
clocks = <&rcc STM32_CLOCK(AHB2, 13)>;
424424
interrupts = <18 0>;
425425
status = "disabled";
426426
#io-channel-cells = <1>;
@@ -441,7 +441,7 @@
441441

442442
lptim1: timers@40007c00 {
443443
compatible = "st,stm32-lptim";
444-
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
444+
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
445445
#address-cells = <1>;
446446
#size-cells = <0>;
447447
reg = <0x40007c00 0x400>;
@@ -455,7 +455,7 @@
455455
#dma-cells = <3>;
456456
reg = <0x40020000 0x400>;
457457
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
458-
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
458+
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
459459
dma-requests = <7>;
460460
dma-offset = <0>;
461461
status = "disabled";
@@ -466,7 +466,7 @@
466466
#dma-cells = <3>;
467467
reg = <0x40020400 0x400>;
468468
interrupts = <55 0 56 0 57 0 58 0 59 0 60 0 61 0>;
469-
clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
469+
clocks = <&rcc STM32_CLOCK(AHB1, 1)>;
470470
dma-requests = <7>;
471471
dma-offset = <7>;
472472
status = "disabled";
@@ -477,7 +477,7 @@
477477
#dma-cells = <3>;
478478
reg = <0x40020800 0x400>;
479479
interrupts = <62 0>;
480-
clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
480+
clocks = <&rcc STM32_CLOCK(AHB1, 2)>;
481481
dma-channels = <14>;
482482
dma-generators = <4>;
483483
dma-requests= <36>;
@@ -493,7 +493,7 @@
493493
ram-size = <1024>;
494494
maximum-speed = "full-speed";
495495
phys = <&usb_fs_phy>;
496-
clocks = <&rcc STM32_CLOCK(APB1, 26U)>,
496+
clocks = <&rcc STM32_CLOCK(APB1, 26)>,
497497
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
498498
status = "disabled";
499499
};
@@ -504,22 +504,22 @@
504504
#size-cells = <0>;
505505
reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>;
506506
interrupts = <0x32 0x0>;
507-
clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
507+
clocks = <&rcc STM32_CLOCK(AHB3, 8)>;
508508
status = "disabled";
509509
};
510510

511511
rng: rng@58001000 {
512512
compatible = "st,stm32-rng";
513513
reg = <0x58001000 0x400>;
514514
interrupts = <53 0>;
515-
clocks = <&rcc STM32_CLOCK(AHB3, 18U)>;
515+
clocks = <&rcc STM32_CLOCK(AHB3, 18)>;
516516
status = "disabled";
517517
};
518518

519519
aes1: aes@50060000 {
520520
compatible = "st,stm32-aes";
521521
reg = <0x50060000 0x400>;
522-
clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
522+
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
523523
resets = <&rctl STM32_RESET(AHB2, 16U)>;
524524
interrupts = <51 0>;
525525
status = "disabled";
@@ -582,7 +582,7 @@
582582

583583
ble_rf: ble_rf {
584584
compatible = "st,stm32wb-rf";
585-
clocks = <&rcc STM32_CLOCK(AHB3, 20U)>,
585+
clocks = <&rcc STM32_CLOCK(AHB3, 20)>,
586586
<&rcc STM32_SRC_LSE RFWKP_SEL(1)>;
587587
};
588588

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