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Mathieu Choplainkartben
Mathieu Choplain
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kartben
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dts: arm: st: stm32h7rs: remove U suffix from "clocks" in DTSI
PR 79683 added unnecessary U suffix to constants in DTSI. This bloats the files for no reason and is starting to spread as people use the DTSI for reference in other places, and so copy this bad pattern. Remove the useless U suffixes in DTSI files for this series. Signed-off-by: Mathieu Choplain <[email protected]>
1 parent 0722161 commit 221b378

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‎dts/arm/st/h7rs/stm32h7rs.dtsi‎

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@
180180
compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller";
181181
reg = <0x52002000 0x400>;
182182
interrupts = <8 0>;
183-
clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
183+
clocks = <&rcc STM32_CLOCK(AHB3, 8)>;
184184

185185
#address-cells = <1>;
186186
#size-cells = <1>;
@@ -239,150 +239,150 @@
239239
gpio-controller;
240240
#gpio-cells = <2>;
241241
reg = <0x58020000 0x400>;
242-
clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
242+
clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
243243
};
244244

245245
gpiob: gpio@58020400 {
246246
compatible = "st,stm32-gpio";
247247
gpio-controller;
248248
#gpio-cells = <2>;
249249
reg = <0x58020400 0x400>;
250-
clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
250+
clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
251251
};
252252

253253
gpioc: gpio@58020800 {
254254
compatible = "st,stm32-gpio";
255255
gpio-controller;
256256
#gpio-cells = <2>;
257257
reg = <0x58020800 0x400>;
258-
clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
258+
clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
259259
};
260260

261261
gpiod: gpio@58020C00 {
262262
compatible = "st,stm32-gpio";
263263
gpio-controller;
264264
#gpio-cells = <2>;
265265
reg = <0x58020C00 0x400>;
266-
clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
266+
clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
267267
};
268268

269269
gpioe: gpio@58021000 {
270270
compatible = "st,stm32-gpio";
271271
gpio-controller;
272272
#gpio-cells = <2>;
273273
reg = <0x58021000 0x400>;
274-
clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
274+
clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
275275
};
276276

277277
gpiof: gpio@58021400 {
278278
compatible = "st,stm32-gpio";
279279
gpio-controller;
280280
#gpio-cells = <2>;
281281
reg = <0x58021400 0x400>;
282-
clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
282+
clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
283283
};
284284

285285
gpiog: gpio@58021800 {
286286
compatible = "st,stm32-gpio";
287287
gpio-controller;
288288
#gpio-cells = <2>;
289289
reg = <0x58021800 0x400>;
290-
clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
290+
clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
291291
};
292292

293293
gpioh: gpio@58021c00 {
294294
compatible = "st,stm32-gpio";
295295
gpio-controller;
296296
#gpio-cells = <2>;
297297
reg = <0x58021c00 0x400>;
298-
clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
298+
clocks = <&rcc STM32_CLOCK(AHB4, 7)>;
299299
};
300300

301301
gpiom: gpio@58023000 {
302302
compatible = "st,stm32-gpio";
303303
gpio-controller;
304304
#gpio-cells = <2>;
305305
reg = <0x58023000 0x400>;
306-
clocks = <&rcc STM32_CLOCK(AHB4, 12U)>;
306+
clocks = <&rcc STM32_CLOCK(AHB4, 12)>;
307307
};
308308

309309
gpion: gpio@58023400 {
310310
compatible = "st,stm32-gpio";
311311
gpio-controller;
312312
#gpio-cells = <2>;
313313
reg = <0x58023400 0x400>;
314-
clocks = <&rcc STM32_CLOCK(AHB4, 13U)>;
314+
clocks = <&rcc STM32_CLOCK(AHB4, 13)>;
315315
};
316316

317317
gpioo: gpio@58023800 {
318318
compatible = "st,stm32-gpio";
319319
gpio-controller;
320320
#gpio-cells = <2>;
321321
reg = <0x58023800 0x400>;
322-
clocks = <&rcc STM32_CLOCK(AHB4, 14U)>;
322+
clocks = <&rcc STM32_CLOCK(AHB4, 14)>;
323323
};
324324

325325
gpiop: gpio@58023c00 {
326326
compatible = "st,stm32-gpio";
327327
gpio-controller;
328328
#gpio-cells = <2>;
329329
reg = <0x58023c00 0x400>;
330-
clocks = <&rcc STM32_CLOCK(AHB4, 15U)>;
330+
clocks = <&rcc STM32_CLOCK(AHB4, 15)>;
331331
};
332332
};
333333

334334
usart1: serial@42001000 {
335335
compatible = "st,stm32-usart", "st,stm32-uart";
336336
reg = <0x42001000 0x400>;
337-
clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
337+
clocks = <&rcc STM32_CLOCK(APB2, 4)>;
338338
resets = <&rctl STM32_RESET(APB2, 4U)>;
339339
interrupts = <82 0>;
340340
status = "disabled";
341341
};
342342
usart2: serial@40004400 {
343343
compatible = "st,stm32-usart", "st,stm32-uart";
344344
reg = <0x40004400 0x400>;
345-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
345+
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
346346
resets = <&rctl STM32_RESET(APB1L, 17U)>;
347347
interrupts = <83 0>;
348348
status = "disabled";
349349
};
350350
usart3: serial@40004800 {
351351
compatible = "st,stm32-usart", "st,stm32-uart";
352352
reg = <0x40004800 0x400>;
353-
clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
353+
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
354354
resets = <&rctl STM32_RESET(APB1L, 18U)>;
355355
interrupts = <84 0>;
356356
status = "disabled";
357357
};
358358
uart4: serial@40004c00 {
359359
compatible ="st,stm32-uart";
360360
reg = <0x40004c00 0x400>;
361-
clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
361+
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
362362
resets = <&rctl STM32_RESET(APB1L, 19U)>;
363363
interrupts = <85 0>;
364364
status = "disabled";
365365
};
366366
uart5: serial@40005000 {
367367
compatible = "st,stm32-uart";
368368
reg = <0x40005000 0x400>;
369-
clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
369+
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
370370
resets = <&rctl STM32_RESET(APB1L, 20U)>;
371371
interrupts = <86 0>;
372372
status = "disabled";
373373
};
374374
uart7: serial@40007800 {
375375
compatible = "st,stm32-uart";
376376
reg = <0x40007800 0x400>;
377-
clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
377+
clocks = <&rcc STM32_CLOCK(APB1, 30)>;
378378
resets = <&rctl STM32_RESET(APB1L, 30U)>;
379379
interrupts = <87 0>;
380380
status = "disabled";
381381
};
382382
uart8: serial@40007c00 {
383383
compatible = "st,stm32-uart";
384384
reg = <0x40007c00 0x400>;
385-
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
385+
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
386386
resets = <&rctl STM32_RESET(APB1L, 31U)>;
387387
interrupts = <88 0>;
388388
status = "disabled";
@@ -391,7 +391,7 @@
391391
lpuart1: serial@58000c00 {
392392
compatible = "st,stm32-lpuart", "st,stm32-uart";
393393
reg = <0x58000c00 0x400>;
394-
clocks = <&rcc STM32_CLOCK(APB4, 3U)>;
394+
clocks = <&rcc STM32_CLOCK(APB4, 3)>;
395395
resets = <&rctl STM32_RESET(APB4, 3U)>;
396396
interrupts = <131 0>;
397397
status = "disabled";
@@ -403,7 +403,7 @@
403403
#address-cells = <1>;
404404
#size-cells = <0>;
405405
reg = <0x40005400 0x400>;
406-
clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
406+
clocks = <&rcc STM32_CLOCK(APB1, 21)>;
407407
interrupts = <76 0>, <77 0>;
408408
interrupt-names = "event", "error";
409409
status = "disabled";
@@ -415,7 +415,7 @@
415415
#address-cells = <1>;
416416
#size-cells = <0>;
417417
reg = <0x40005800 0x400>;
418-
clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
418+
clocks = <&rcc STM32_CLOCK(APB1, 22)>;
419419
interrupts = <78 0>, <79 0>;
420420
interrupt-names = "event", "error";
421421
status = "disabled";
@@ -427,7 +427,7 @@
427427
#address-cells = <1>;
428428
#size-cells = <0>;
429429
reg = <0x40005c00 0x400>;
430-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
430+
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
431431
interrupts = <80 0>, <81 0>;
432432
interrupt-names = "event", "error";
433433
status = "disabled";
@@ -438,7 +438,7 @@
438438
#address-cells = <1>;
439439
#size-cells = <0>;
440440
reg = <0x42003000 0x400>;
441-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
441+
clocks = <&rcc STM32_CLOCK(APB2, 12)>,
442442
<&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
443443
interrupts = <58 0>;
444444
status = "disabled";
@@ -449,7 +449,7 @@
449449
#address-cells = <1>;
450450
#size-cells = <0>;
451451
reg = <0x40003800 0x400>;
452-
clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
452+
clocks = <&rcc STM32_CLOCK(APB1, 14)>,
453453
<&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
454454
interrupts = <59 0>;
455455
status = "disabled";
@@ -460,7 +460,7 @@
460460
#address-cells = <1>;
461461
#size-cells = <0>;
462462
reg = <0x40003c00 0x400>;
463-
clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
463+
clocks = <&rcc STM32_CLOCK(APB1, 15)>,
464464
<&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
465465
interrupts = <60 0>;
466466
status = "disabled";
@@ -471,7 +471,7 @@
471471
#address-cells = <1>;
472472
#size-cells = <0>;
473473
reg = <0x42003400 0x400>;
474-
clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
474+
clocks = <&rcc STM32_CLOCK(APB2, 13)>;
475475
interrupts = <61 0>;
476476
status = "disabled";
477477
};
@@ -481,7 +481,7 @@
481481
#address-cells = <1>;
482482
#size-cells = <0>;
483483
reg = <0x42005000 0x400>;
484-
clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
484+
clocks = <&rcc STM32_CLOCK(APB2, 20)>;
485485
interrupts = <62 0>;
486486
status = "disabled";
487487
};
@@ -491,7 +491,7 @@
491491
#address-cells = <1>;
492492
#size-cells = <0>;
493493
reg = <0x40013000 0x400>;
494-
clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
494+
clocks = <&rcc STM32_CLOCK(APB2, 12)>,
495495
<&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
496496
interrupts = <35 3>;
497497
status = "disabled";
@@ -502,7 +502,7 @@
502502
reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
503503
interrupts = <105 0>;
504504
clock-names = "xspix";
505-
clocks = <&rcc STM32_CLOCK(AHB5, 5U)>;
505+
clocks = <&rcc STM32_CLOCK(AHB5, 5)>;
506506
#address-cells = <1>;
507507
#size-cells = <0>;
508508
status = "disabled";
@@ -513,7 +513,7 @@
513513
reg = <0x5200a000 0x1000>, <0x70000000 DT_SIZE_M(256)>;
514514
interrupts = <106 0>;
515515
clock-names = "xspix";
516-
clocks = <&rcc STM32_CLOCK(AHB5, 12U)>;
516+
clocks = <&rcc STM32_CLOCK(AHB5, 12)>;
517517
#address-cells = <1>;
518518
#size-cells = <0>;
519519
status = "disabled";
@@ -529,7 +529,7 @@
529529
wwdg: wwdg1: watchdog@40002c00 {
530530
compatible = "st,stm32-window-watchdog";
531531
reg = <0x40002c00 0x1000>;
532-
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
532+
clocks = <&rcc STM32_CLOCK(APB1, 11)>;
533533
interrupts = <4 7>;
534534
status = "disabled";
535535
};
@@ -766,7 +766,7 @@
766766

767767
lptim1: timers@40002400 {
768768
compatible = "st,stm32-lptim";
769-
clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
769+
clocks = <&rcc STM32_CLOCK(APB1, 9)>;
770770
#address-cells = <1>;
771771
#size-cells = <0>;
772772
reg = <0x40002400 0x400>;
@@ -778,7 +778,7 @@
778778
adc1: adc@40022000 {
779779
compatible = "st,stm32-adc";
780780
reg = <0x40022000 0x400>;
781-
clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
781+
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
782782
interrupts = <38 0>;
783783
status = "disabled";
784784
#io-channel-cells = <1>;
@@ -794,7 +794,7 @@
794794
adc2: adc@40022100 {
795795
compatible = "st,stm32-adc";
796796
reg = <0x40022100 0x400>;
797-
clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
797+
clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
798798
interrupts = <38 0>;
799799
status = "disabled";
800800
#io-channel-cells = <1>;
@@ -810,7 +810,7 @@
810810
rng: rng@48020000 {
811811
compatible = "st,stm32-rng";
812812
reg = <0x48020000 0x400>;
813-
clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
813+
clocks = <&rcc STM32_CLOCK(AHB3, 0)>;
814814
interrupts = <37 0>;
815815
status = "disabled";
816816
};
@@ -824,7 +824,7 @@
824824
ram-size = <1280>;
825825
maximum-speed = "full-speed";
826826
phys = <&otgfs_phy>;
827-
clocks = <&rcc STM32_CLOCK(AHB1, 27U)>,
827+
clocks = <&rcc STM32_CLOCK(AHB1, 27)>,
828828
<&rcc STM32_SRC_HSI48 OTGFS_SEL(0)>;
829829
status = "disabled";
830830
};

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