dts: arm: microchip: add pinctrl dts node and bindings for Port G1 IP

Add pinctrl dts node for PIC32CM JH family devices and
update binding file for Microchip Pinctrl Port G1 IP

Signed-off-by: Mohamed Azhar <[email protected]>

Author: AzharMCHP

dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi

@@ -38,12 +38,19 @@
 			compatible = "mmio-sram";
 		};
 
-		porta: gpio@41000000 {
-			compatible = "microchip,port-g1-gpio";
-			reg = <0x41000000 0x80>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			#microchip,pin-cells = <2>;
+		pinctrl: pinctrl@41000000 {
+			compatible = "microchip,port-g1-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x41000000 0x41000000 0x180>;
+
+			porta: gpio@41000000 {
+				compatible = "microchip,port-g1-gpio";
+				reg = <0x41000000 0x80>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				#microchip,pin-cells = <2>;
+			};
 		};
 	};
 };

dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_100.dtsi

@@ -8,22 +8,20 @@
 
 #include <microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi>
 
-/ {
-	soc {
-		portb: gpio@41000080 {
-			compatible = "microchip,port-g1-gpio";
-			reg = <0x41000080 0x80>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			#microchip,pin-cells = <2>;
-		};
+&pinctrl {
+	portb: gpio@41000080 {
+		compatible = "microchip,port-g1-gpio";
+		reg = <0x41000080 0x80>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		#microchip,pin-cells = <2>;
+	};
 
-		portc: gpio@41000100 {
-			compatible = "microchip,port-g1-gpio";
-			reg = <0x41000100 0x80>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			#microchip,pin-cells = <2>;
-		};
+	portc: gpio@41000100 {
+		compatible = "microchip,port-g1-gpio";
+		reg = <0x41000100 0x80>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		#microchip,pin-cells = <2>;
 	};
 };

dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_48.dtsi

@@ -8,14 +8,12 @@
 
 #include <microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi>
 
-/ {
-	soc {
-		portb: gpio@41000080 {
-			compatible = "microchip,port-g1-gpio";
-			reg = <0x41000080 0x80>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			#microchip,pin-cells = <2>;
-		};
+&pinctrl {
+	portb: gpio@41000080 {
+		compatible = "microchip,port-g1-gpio";
+		reg = <0x41000080 0x80>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		#microchip,pin-cells = <2>;
 	};
 };

dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_64.dtsi

@@ -8,14 +8,12 @@
 
 #include <microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi>
 
-/ {
-	soc {
-		portb: gpio@41000080 {
-			compatible = "microchip,port-g1-gpio";
-			reg = <0x41000080 0x80>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			#microchip,pin-cells = <2>;
-		};
+&pinctrl {
+	portb: gpio@41000080 {
+		compatible = "microchip,port-g1-gpio";
+		reg = <0x41000080 0x80>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		#microchip,pin-cells = <2>;
 	};
 };

dts/bindings/pinctrl/microchip,port-g1-pinctrl.yaml

@@ -13,6 +13,7 @@ description: |
 
   Group g1 PORT PINCTRL driver supports following hardware peripherals:
     - module name="PORT" id="U2210" version="2.2.0"
+    - module name="PORT" id="U2210" version="3.1.0"
 
   The node has the 'pinctrl' node label set in your SoC's devicetree, so you can
   modify it like this:
@@ -112,7 +113,7 @@ child-binding:
         description: |
           An array of pins sharing the same group properties. The pins should
           be defined using pre-defined macros or, alternatively, using the
-          SAM_PINMUX utility macros depending on the pinmux model used by the
+          MCHP_PINMUX utility macros depending on the pinmux model used by the
           SoC series.
       drive-strength:
         enum: