devicetree: format SoC-level files in dts/arm

Applying dts-linter results for SoC-level files in

dts/arm

Signed-off-by: Kyle Micallef Bonnici <[email protected]>

Author: kylebonnici

dts/arm/armv6-m.dtsi

@@ -10,7 +10,7 @@
 		interrupt-parent = <&nvic>;
 		ranges;
 
-		nvic: interrupt-controller@e000e100  {
+		nvic: interrupt-controller@e000e100 {
 			#address-cells = <1>;
 			compatible = "arm,v6m-nvic";
 			reg = <0xe000e100 0xc00>;

dts/arm/armv7-m.dtsi

@@ -10,7 +10,7 @@
 		interrupt-parent = <&nvic>;
 		ranges;
 
-		nvic: interrupt-controller@e000e100  {
+		nvic: interrupt-controller@e000e100 {
 			#address-cells = <1>;
 			compatible = "arm,v7m-nvic";
 			reg = <0xe000e100 0xc00>;

dts/arm/armv8-m.dtsi

@@ -10,7 +10,7 @@
 		interrupt-parent = <&nvic>;
 		ranges;
 
-		nvic: interrupt-controller@e000e100  {
+		nvic: interrupt-controller@e000e100 {
 			#address-cells = <1>;
 			compatible = "arm,v8m-nvic";
 			reg = <0xe000e100 0xc00>;

dts/arm/armv8.1-m.dtsi

@@ -14,7 +14,7 @@
 		interrupt-parent = <&nvic>;
 		ranges;
 
-		nvic: interrupt-controller@e000e100  {
+		nvic: interrupt-controller@e000e100 {
 			#address-cells = <1>;
 			compatible = "arm,v8.1m-nvic";
 			reg = <0xe000e100 0xc00>;

dts/arm/cortex_r8_virt.dtsi

@@ -13,51 +13,58 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-r8f";
 			reg = <0>;
 		};
 	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges;
-		interrupt-parent = < &gic >;
+		interrupt-parent = <&gic>;
+
 		flash0: flash@c0000000 {
 			compatible = "soc-nv-flash";
-			reg = < 0xc0000000 0x2000000 >;
+			reg = <0xc0000000 0x2000000>;
 		};
+
 		sram0: memory@0 {
 			compatible = "mmio-sram";
-			reg = < 0x0 0x4000000 >;
+			reg = <0x0 0x4000000>;
 		};
+
 		uart0: uart@ff000000 {
 			compatible = "xlnx,xuartps";
-			reg = < 0xff000000 0x4c >;
+			reg = <0xff000000 0x4c>;
 			status = "disabled";
 			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL
-					IRQ_DEFAULT_PRIORITY>;
+				      IRQ_DEFAULT_PRIORITY>;
 			interrupt-names = "irq_0";
 		};
+
 		ttc0: timer@ff110000 {
 			compatible = "xlnx,ttcps";
 			status = "okay";
-			interrupts = < 0x0 0x24 0x2 0xa0 >,
-				< 0x0 0x25 0x2 0xa0 >,
-				< 0x0 0x26 0x2 0xa0 >;
+			interrupts = <0x0 0x24 0x2 0xa0>,
+				     <0x0 0x25 0x2 0xa0>,
+				     <0x0 0x26 0x2 0xa0>;
 			interrupt-names = "irq_0", "irq_1", "irq_2";
-			reg = < 0xff110000 0x1000 >;
-			clock-frequency = < 5000000 >;
+			reg = <0xff110000 0x1000>;
+			clock-frequency = <5000000>;
 		};
+
 		gic: interrupt-controller@f9000000 {
 			compatible = "arm,gic-v1", "arm,gic";
-			reg = < 0xf9000000 0x1000 >, < 0xf9001000 0x100 >;
+			reg = <0xf9000000 0x1000>, <0xf9001000 0x100>;
 			interrupt-controller;
-			#interrupt-cells = < 0x4 >;
+			#interrupt-cells = <0x4>;
 			status = "okay";
-			phandle = < 0x1 >;
+			phandle = <0x1>;
 		};
 	};
 };