soc: sensry: fix irq enable/disable

kartben · kartben · commit 4cac6583f735 · 2025-06-13T11:12:55.000+02:00
SET/CLR registers are write-only so trying to
read/modify/write is inefficient &amp; illegal

Signed-off-by: Benjamin Cabé &lt;benjamin@zephyrproject.org&gt;
diff --git a/soc/sensry/ganymed/sy1xx/common/soc.c b/soc/sensry/ganymed/sy1xx/common/soc.c
@@ -25,6 +25,7 @@ LOG_MODULE_REGISTER(soc);
 #define SY1XX_ARCHI_ITC_ACK_SET_OFFSET    0x1c
 #define SY1XX_ARCHI_ITC_ACK_CLR_OFFSET    0x20
 #define SY1XX_ARCHI_ITC_FIFO_OFFSET       0x24
+#define SY1XX_ARCHI_ITC_IRQ_MASK          0x1f
 
 void sys_arch_reboot(int type)
 {
@@ -51,17 +52,13 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags)
 
 void soc_enable_irq(uint32_t idx)
 {
-	uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);
-
-	sys_write32(current | (1 << (idx & 0x1f)),
+	sys_write32(BIT(idx & SY1XX_ARCHI_ITC_IRQ_MASK),
 		    SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);
 }
 
 void soc_disable_irq(uint32_t idx)
 {
-	uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);
-
-	sys_write32(current & (~(1 << (idx & 0x1f))),
+	sys_write32(BIT(idx & SY1XX_ARCHI_ITC_IRQ_MASK),
 		    SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);
 }
 

Original file line number	Diff line number	Diff line change
`@@ -25,6 +25,7 @@ LOG_MODULE_REGISTER(soc);`
`25`	`25`	`#define SY1XX_ARCHI_ITC_ACK_SET_OFFSET 0x1c`
`26`	`26`	`#define SY1XX_ARCHI_ITC_ACK_CLR_OFFSET 0x20`
`27`	`27`	`#define SY1XX_ARCHI_ITC_FIFO_OFFSET 0x24`
	`28`	`+#define SY1XX_ARCHI_ITC_IRQ_MASK 0x1f`
`28`	`29`
`29`	`30`	`void sys_arch_reboot(int type)`
`30`	`31`	`{`
`@@ -51,17 +52,13 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags)`
`51`	`52`
`52`	`53`	`void soc_enable_irq(uint32_t idx)`
`53`	`54`	`{`
`54`		`- uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);`
`55`		`-`
`56`		`- sys_write32(current \| (1 << (idx & 0x1f)),`
	`55`	`+ sys_write32(BIT(idx & SY1XX_ARCHI_ITC_IRQ_MASK),`
`57`	`56`	`SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);`
`58`	`57`	`}`
`59`	`58`
`60`	`59`	`void soc_disable_irq(uint32_t idx)`
`61`	`60`	`{`
`62`		`- uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);`
`63`		`-`
`64`		`- sys_write32(current & (~(1 << (idx & 0x1f))),`
	`61`	`+ sys_write32(BIT(idx & SY1XX_ARCHI_ITC_IRQ_MASK),`
`65`	`62`	`SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);`
`66`	`63`	`}`
`67`	`64`