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kylebonnicinashif
kylebonnici
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nashif
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devicetree: format files in dts/riscv/sifive
Applying dts-linter results for files in dts/riscv/sifive Signed-off-by: Kyle Micallef Bonnici <[email protected]>
1 parent 2a120b5 commit 8019bce

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3 files changed

+76
-38
lines changed

3 files changed

+76
-38
lines changed

‎dts/riscv/sifive/riscv32-fe310.dtsi‎

Lines changed: 37 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#size-cells = <1>;
1010
compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
1111
model = "SiFive,FE310G-0002-Z0";
12+
1213
clocks {
1314
coreclk: core-clk {
1415
#clock-cells = <0>;
@@ -23,15 +24,18 @@
2324
clock-div = <1>;
2425
};
2526
};
27+
2628
cpus {
2729
#address-cells = <1>;
2830
#size-cells = <0>;
31+
2932
cpu: cpu@0 {
3033
compatible = "sifive,e31", "riscv";
3134
device_type = "cpu";
3235
reg = <0>;
3336
riscv,isa = "rv32imac_zicsr_zifencei";
3437
status = "okay";
38+
3539
hlic: interrupt-controller {
3640
compatible = "riscv,cpu-intc";
3741
#address-cells = <0>;
@@ -40,65 +44,74 @@
4044
};
4145
};
4246
};
47+
4348
soc {
4449
#address-cells = <1>;
4550
#size-cells = <1>;
4651
compatible = "sifive,FE310G-0002-Z0-soc", "fe310-soc",
47-
"sifive-soc", "simple-bus";
52+
"sifive-soc", "simple-bus";
4853
ranges;
54+
4955
wdog0: wdog@10000000 {
5056
compatible = "sifive,wdt";
5157
interrupt-parent = <&plic>;
5258
interrupts = <1 1>;
5359
reg = <0x10000000 0x40>;
5460
reg-names = "control";
5561
};
62+
5663
aon: aon@10000040 {
5764
compatible = "sifive,aon0";
5865
interrupt-parent = <&plic>;
5966
interrupts = <2 1>;
6067
reg = <0x10000040 0x9c0>;
6168
reg-names = "control";
6269
};
70+
6371
clint: clint@2000000 {
6472
compatible = "sifive,clint0";
6573
interrupts-extended = <&hlic 3 &hlic 7>;
6674
reg = <0x2000000 0x10000>;
6775
};
76+
6877
mtimer: timer@200bff8 {
6978
compatible = "riscv,machine-timer";
7079
interrupts-extended = <&hlic 7>;
7180
reg = <0x200bff8 0x8 0x2004000 0x8>;
7281
reg-names = "mtime", "mtimecmp";
7382
};
83+
7484
debug: debug-controller@0 {
7585
compatible = "sifive,debug-013", "riscv,debug-013";
7686
interrupts-extended = <&hlic 65535>;
7787
reg = <0x0 0x1000>;
7888
reg-names = "control";
7989
};
90+
8091
dtim: dtim@80000000 {
8192
compatible = "sifive,dtim0";
8293
reg = <0x80000000 0x4000>;
8394
reg-names = "mem";
8495
};
96+
8597
error-device@3000 {
8698
compatible = "sifive,error0";
8799
reg = <0x3000 0x1000>;
88100
reg-names = "mem";
89101
};
102+
90103
gpio0: gpio@10012000 {
91104
compatible = "sifive,gpio0";
92105
gpio-controller;
93106
interrupt-parent = <&plic>;
94107
interrupts = <8 1>, <9 1>, <10 1>, <11 1>,
95-
<12 1>, <13 1>, <14 1>, <15 1>,
96-
<16 1>, <17 1>, <18 1>, <19 1>,
97-
<20 1>, <21 1>, <22 1>, <23 1>,
98-
<24 1>, <25 1>, <26 1>, <27 1>,
99-
<28 1>, <29 1>, <30 1>, <31 1>,
100-
<32 1>, <33 1>, <34 1>, <35 1>,
101-
<36 1>, <37 1>, <38 1>, <39 1>;
108+
<12 1>, <13 1>, <14 1>, <15 1>,
109+
<16 1>, <17 1>, <18 1>, <19 1>,
110+
<20 1>, <21 1>, <22 1>, <23 1>,
111+
<24 1>, <25 1>, <26 1>, <27 1>,
112+
<28 1>, <29 1>, <30 1>, <31 1>,
113+
<32 1>, <33 1>, <34 1>, <35 1>,
114+
<36 1>, <37 1>, <38 1>, <39 1>;
102115
reg = <0x10012000 0x1000>;
103116
reg-names = "control";
104117
status = "disabled";
@@ -113,6 +126,7 @@
113126
reg = <0x10012038 0x8>;
114127
};
115128
};
129+
116130
i2c0: i2c@10016000 {
117131
compatible = "sifive,i2c0";
118132
interrupt-parent = <&plic>;
@@ -123,6 +137,7 @@
123137
#address-cells = <1>;
124138
#size-cells = <0>;
125139
};
140+
126141
plic: interrupt-controller@c000000 {
127142
compatible = "sifive,plic-1.0.0";
128143
#address-cells = <0>;
@@ -133,21 +148,25 @@
133148
riscv,max-priority = <7>;
134149
riscv,ndev = <52>;
135150
};
151+
136152
itim: itim@8000000 {
137153
compatible = "sifive,itim0";
138154
reg = <0x8000000 0x2000>;
139155
reg-names = "mem";
140156
};
157+
141158
otp: otp@10010000 {
142159
compatible = "sifive,otp0";
143160
reg = <0x10010000 0x1000 0x20000 0x2000>;
144161
reg-names = "control", "mem";
145162
};
163+
146164
prci: prci@10008000 {
147165
compatible = "sifive,freedome300prci0";
148166
reg = <0x10008000 0x1000>;
149167
reg-names = "control";
150168
};
169+
151170
pwm0: pwm@10015000 {
152171
compatible = "sifive,pwm0";
153172
interrupt-parent = <&plic>;
@@ -158,6 +177,7 @@
158177
sifive,compare-width = <8>;
159178
#pwm-cells = <2>;
160179
};
180+
161181
pwm1: pwm@10025000 {
162182
compatible = "sifive,pwm0";
163183
interrupt-parent = <&plic>;
@@ -168,6 +188,7 @@
168188
sifive,compare-width = <16>;
169189
#pwm-cells = <2>;
170190
};
191+
171192
pwm2: pwm@10035000 {
172193
compatible = "sifive,pwm0";
173194
interrupt-parent = <&plic>;
@@ -178,16 +199,19 @@
178199
sifive,compare-width = <16>;
179200
#pwm-cells = <2>;
180201
};
202+
181203
modeselect: rom@1000 {
182204
compatible = "sifive,modeselect0";
183205
reg = <0x1000 0x1000>;
184206
reg-names = "mem";
185207
};
208+
186209
maskrom: rom@10000 {
187210
compatible = "sifive,maskrom0";
188211
reg = <0x10000 0x2000>;
189212
reg-names = "mem";
190213
};
214+
191215
uart0: serial@10013000 {
192216
compatible = "sifive,uart0";
193217
interrupt-parent = <&plic>;
@@ -196,6 +220,7 @@
196220
reg-names = "control";
197221
status = "disabled";
198222
};
223+
199224
uart1: serial@10023000 {
200225
compatible = "sifive,uart0";
201226
interrupt-parent = <&plic>;
@@ -204,6 +229,7 @@
204229
reg-names = "control";
205230
status = "disabled";
206231
};
232+
207233
spi0: spi@10014000 {
208234
compatible = "sifive,spi0";
209235
interrupt-parent = <&plic>;
@@ -214,6 +240,7 @@
214240
#address-cells = <1>;
215241
#size-cells = <0>;
216242
};
243+
217244
spi1: spi@10024000 {
218245
compatible = "sifive,spi0";
219246
interrupt-parent = <&plic>;
@@ -224,6 +251,7 @@
224251
#address-cells = <1>;
225252
#size-cells = <0>;
226253
};
254+
227255
spi2: spi@10034000 {
228256
compatible = "sifive,spi0";
229257
interrupt-parent = <&plic>;
@@ -234,6 +262,7 @@
234262
#address-cells = <1>;
235263
#size-cells = <0>;
236264
};
265+
237266
teststatus: teststatus@4000 {
238267
compatible = "sifive,test0";
239268
reg = <0x4000 0x1000>;

‎dts/riscv/sifive/riscv64-fu540.dtsi‎

Lines changed: 22 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
i-cache-line-size = <0x4000>;
3939
reg = <0x0>;
4040
riscv,isa = "rv64imac_zicsr_zifencei";
41+
4142
hlic0: interrupt-controller {
4243
compatible = "riscv,cpu-intc";
4344
#address-cells = <0>;
@@ -54,6 +55,7 @@
5455
d-cache-line-size = <0x8000>;
5556
reg = <0x1>;
5657
riscv,isa = "rv64gc";
58+
5759
hlic1: interrupt-controller {
5860
compatible = "riscv,cpu-intc";
5961
#address-cells = <0>;
@@ -71,6 +73,7 @@
7173
d-cache-line-size = <0x8000>;
7274
reg = <0x2>;
7375
riscv,isa = "rv64gc";
76+
7477
hlic2: interrupt-controller {
7578
compatible = "riscv,cpu-intc";
7679
#address-cells = <0>;
@@ -88,6 +91,7 @@
8891
d-cache-line-size = <0x8000>;
8992
reg = <0x3>;
9093
riscv,isa = "rv64gc";
94+
9195
hlic3: interrupt-controller {
9296
compatible = "riscv,cpu-intc";
9397
#address-cells = <0>;
@@ -105,6 +109,7 @@
105109
d-cache-line-size = <0x8000>;
106110
reg = <0x4>;
107111
riscv,isa = "rv64gc";
112+
108113
hlic4: interrupt-controller {
109114
compatible = "riscv,cpu-intc";
110115
#address-cells = <0>;
@@ -168,27 +173,26 @@
168173
reg-names = "mem";
169174
};
170175

171-
172176
clint: clint@2000000 {
173177
compatible = "sifive,clint0";
174178
interrupts-extended = <&hlic0 3 &hlic0 7
175-
&hlic1 3 &hlic1 7
176-
&hlic2 3 &hlic2 7
177-
&hlic3 3 &hlic3 7
178-
&hlic4 3 &hlic4 7>;
179+
&hlic1 3 &hlic1 7
180+
&hlic2 3 &hlic2 7
181+
&hlic3 3 &hlic3 7
182+
&hlic4 3 &hlic4 7>;
179183
interrupt-names = "soft0", "timer0", "soft1", "timer1",
180-
"soft2", "timer2", "soft3", "timer3",
181-
"soft4", "timer4";
184+
"soft2", "timer2", "soft3", "timer3",
185+
"soft4", "timer4";
182186
reg = <0x2000000 0x10000>;
183187
};
184188

185189
mtimer: timer@200bff8 {
186190
compatible = "riscv,machine-timer";
187191
interrupts-extended = <&hlic0 7
188-
&hlic1 7
189-
&hlic2 7
190-
&hlic3 7
191-
&hlic4 7>;
192+
&hlic1 7
193+
&hlic2 7
194+
&hlic3 7
195+
&hlic4 7>;
192196
reg = <0x200bff8 0x8 0x2004000 0x8>;
193197
reg-names = "mtime", "mtimecmp";
194198
};
@@ -205,10 +209,10 @@
205209
#address-cells = <1>;
206210
interrupt-controller;
207211
interrupts-extended = <&hlic0 11
208-
&hlic1 11 &hlic1 9
209-
&hlic2 11 &hlic2 9
210-
&hlic3 11 &hlic3 9
211-
&hlic4 11 &hlic4 9>;
212+
&hlic1 11 &hlic1 9
213+
&hlic2 11 &hlic2 9
214+
&hlic3 11 &hlic3 9
215+
&hlic4 11 &hlic4 9>;
212216
reg = <0x0c000000 0x04000000>;
213217
riscv,max-priority = <7>;
214218
riscv,ndev = <52>;
@@ -271,9 +275,9 @@
271275
ngpios = <16>;
272276
interrupt-parent = <&plic>;
273277
interrupts = <7 1>, <8 1>, <9 1>, <10 1>,
274-
<11 1>, <12 1>, <13 1>, <14 1>,
275-
<15 1>, <16 1>, <17 1>, <18 1>,
276-
<19 1>, <20 1>, <21 1>, <22 1>;
278+
<11 1>, <12 1>, <13 1>, <14 1>,
279+
<15 1>, <16 1>, <17 1>, <18 1>,
280+
<19 1>, <20 1>, <21 1>, <22 1>;
277281
reg = <0x10060000 0x1000>;
278282
reg-names = "control";
279283
status = "disabled";

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