arch: cache: set default of line size

set default of line size to the
value from the devicetree.

Signed-off-by: Fin Maaß <[email protected]>

Author: maass-hamburg

arch/Kconfig

@@ -1123,11 +1123,11 @@ config DCACHE_LINE_SIZE_DETECT
 config DCACHE_LINE_SIZE
 	int "d-cache line size"
 	depends on !DCACHE_LINE_SIZE_DETECT
+	default $(dt_node_int_prop_int,/cpus/cpu@0,d-cache-line-size) \
+		  if $(dt_node_has_prop,/cpus/cpu@0,d-cache-line-size)
 	default 0
 	help
-	  Size in bytes of a CPU d-cache line. If this is set to 0 the value is
-	  obtained from the 'd-cache-line-size' DT property instead if present.
-
+	  Size in bytes of a CPU d-cache line.
 
 	  Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT.
 
@@ -1149,10 +1149,11 @@ config ICACHE_LINE_SIZE_DETECT
 config ICACHE_LINE_SIZE
 	int "i-cache line size"
 	depends on !ICACHE_LINE_SIZE_DETECT
+	default $(dt_node_int_prop_int,/cpus/cpu@0,i-cache-line-size) \
+		  if $(dt_node_has_prop,/cpus/cpu@0,i-cache-line-size)
 	default 0
 	help
-	  Size in bytes of a CPU i-cache line. If this is set to 0 the value is
-	  obtained from the 'i-cache-line-size' DT property instead if present.
+	  Size in bytes of a CPU i-cache line.
 
 	  Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT.
 

drivers/cache/cache_andes.c

@@ -534,9 +534,6 @@ static int andes_cache_init(void)
 		}
 #elif (CONFIG_ICACHE_LINE_SIZE != 0)
 		cache_cfg.instr_line_size = CONFIG_ICACHE_LINE_SIZE;
-#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size)
-		cache_cfg.instr_line_size =
-			DT_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size);
 #else
 		LOG_ERR("Please specific the i-cache-line-size "
 			"CPU0 property of the DT");
@@ -558,9 +555,6 @@ static int andes_cache_init(void)
 		}
 #elif (CONFIG_DCACHE_LINE_SIZE != 0)
 		cache_cfg.data_line_size = CONFIG_DCACHE_LINE_SIZE;
-#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size)
-		cache_cfg.data_line_size =
-			DT_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size);
 #else
 		LOG_ERR("Please specific the d-cache-line-size "
 			"CPU0 property of the DT");

include/zephyr/cache.h

@@ -35,15 +35,6 @@ extern "C" {
  * @{
  */
 
-/**
- * @cond INTERNAL_HIDDEN
- *
- */
-
-#define _CPU DT_PATH(cpus, cpu_0)
-
-/** @endcond */
-
 /**
  * @brief Enable the d-cache
  *
@@ -398,7 +389,6 @@ static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t
  *
  * - At run-time when @kconfig{CONFIG_DCACHE_LINE_SIZE_DETECT} is set.
  * - At compile time using the value set in @kconfig{CONFIG_DCACHE_LINE_SIZE}.
- * - At compile time using the `d-cache-line-size` CPU0 property of the DT.
  * - 0 otherwise
  *
  * @retval size Size of the d-cache line.
@@ -408,10 +398,10 @@ static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
 {
 #ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
 	return cache_data_line_size_get();
-#elif (CONFIG_DCACHE_LINE_SIZE != 0)
+#elif defined(CONFIG_DCACHE_LINE_SIZE)
 	return CONFIG_DCACHE_LINE_SIZE;
 #else
-	return DT_PROP_OR(_CPU, d_cache_line_size, 0);
+	return 0;
 #endif
 }
 
@@ -425,7 +415,6 @@ static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
  *
  * - At run-time when @kconfig{CONFIG_ICACHE_LINE_SIZE_DETECT} is set.
  * - At compile time using the value set in @kconfig{CONFIG_ICACHE_LINE_SIZE}.
- * - At compile time using the `i-cache-line-size` CPU0 property of the DT.
  * - 0 otherwise
  *
  * @retval size Size of the d-cache line.
@@ -435,10 +424,10 @@ static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
 {
 #ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
 	return cache_instr_line_size_get();
-#elif (CONFIG_ICACHE_LINE_SIZE != 0)
+#elif defined(CONFIG_ICACHE_LINE_SIZE)
 	return CONFIG_ICACHE_LINE_SIZE;
 #else
-	return DT_PROP_OR(_CPU, i_cache_line_size, 0);
+	return 0;
 #endif
 }
 

include/zephyr/sys/spsc_pbuf.h

@@ -40,10 +40,10 @@ extern "C" {
 
 /**@} */
 
-#if CONFIG_DCACHE_LINE_SIZE != 0
+#ifdef CONFIG_DCACHE_LINE_SIZE
 #define Z_SPSC_PBUF_LOCAL_DCACHE_LINE CONFIG_DCACHE_LINE_SIZE
 #else
-#define Z_SPSC_PBUF_LOCAL_DCACHE_LINE DT_PROP_OR(CPU, d_cache_line_size, 0)
+#define Z_SPSC_PBUF_LOCAL_DCACHE_LINE 0
 #endif
 
 #ifndef CONFIG_SPSC_PBUF_REMOTE_DCACHE_LINE

tests/drivers/spi/spi_loopback/src/spi.c

@@ -74,8 +74,6 @@ const struct gpio_dt_spec mosi_pin = GPIO_DT_SPEC_GET_OR(DT_PATH(zephyr_user), m
 #define __NOCACHE
 #if CONFIG_DCACHE_LINE_SIZE != 0
 #define __BUF_ALIGN	__aligned(CONFIG_DCACHE_LINE_SIZE)
-#else
-#define __BUF_ALIGN	__aligned(DT_PROP_OR(DT_PATH(cpus, cpu_0), d_cache_line_size, 32))
 #endif
 #endif /* CONFIG_NOCACHE_MEMORY */