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lucien-nxpjhedberg
lucien-nxp
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jhedberg
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boards: nxp: add frdm_mcxe247 board support
- support XIP way to boot - add board doc and picture - enable cases below: hello_world/blinky/button/ philosophers/synchronization/ gpio_basic_api/uart_async_api Signed-off-by: Lucien Zhao <[email protected]>
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‎boards/nxp/frdm_mcxe247/CMakeLists.txt‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_library()
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zephyr_library_sources(board.c)

‎boards/nxp/frdm_mcxe247/Kconfig‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_FRDM_MCXE247
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select BOARD_EARLY_INIT_HOOK

‎boards/nxp/frdm_mcxe247/Kconfig.frdm_mcxe247‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_FRDM_MCXE247
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select SOC_MCXE247
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select SOC_PART_NUMBER_MCXE247VLQ

‎boards/nxp/frdm_mcxe247/board.c‎

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/*
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* Copyright 2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <fsl_clock.h>
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#include <soc.h>
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define ASSERT_WITHIN_RANGE(val, min, max, str) \
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BUILD_ASSERT(val >= min && val <= max, str)
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#define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \
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BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 4 || \
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val == 8 || val == 16 || val == 2 || val == 64, str)
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#define kSCG_AsyncClkDivBy0 kSCG_AsyncClkDisable
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#define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val)
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#define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val)
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#define SCG_CLOCK_NODE(name) DT_CHILD(DT_INST(0, nxp_kinetis_scg), name)
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#define SCG_CLOCK_DIV(name) DT_PROP(SCG_CLOCK_NODE(name), clock_div)
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#define SCG_CLOCK_MULT(name) DT_PROP(SCG_CLOCK_NODE(name), clock_mult)
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/* System Clock configuration */
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ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(slow_clk), 2, 8,
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"Invalid SCG slow clock divider value");
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ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(bus_clk), 1, 16,
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"Invalid SCG bus clock divider value");
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ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 16,
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"Invalid SCG core clock divider value");
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/*******************************************************************************
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* Variables
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******************************************************************************/
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static const scg_sys_clk_config_t scg_sys_clk_config = {
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.divSlow = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(slow_clk)),
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.divBus = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(bus_clk)),
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.divCore = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(core_clk)),
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#if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sosc_clk))
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.src = kSCG_SysClkSrcSysOsc,
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#elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sirc_clk))
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.src = kSCG_SysClkSrcSirc,
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#elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
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.src = kSCG_SysClkSrcFirc,
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#elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(spll_clk))
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.src = kSCG_SysClkSrcSysPll,
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#else
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#error Invalid SCG core clock source
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#endif
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};
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#if DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk))
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/* System Oscillator (SOSC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv1_clk),
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"Invalid SCG SOSC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv2_clk),
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"Invalid SCG SOSC divider 2 value");
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static const scg_sosc_config_t scg_sosc_config = {
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.freq = DT_PROP(SCG_CLOCK_NODE(sosc_clk), clock_frequency),
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.monitorMode = kSCG_SysOscMonitorDisable,
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.enableMode = kSCG_SysOscEnable,
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.div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv1_clk)),
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.div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv2_clk)),
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.workMode = DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_mode)
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};
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#endif /* DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk)) */
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/* Slow Internal Reference Clock (SIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(sircdiv1_clk),
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"Invalid SCG SIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(sircdiv2_clk),
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"Invalid SCG SIRC divider 2 value");
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static const scg_sirc_config_t scg_sirc_config = {
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.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,
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.div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv1_clk)),
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.div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv2_clk)),
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#if MHZ(8) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
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.range = kSCG_SircRangeHigh
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#else
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#error Invalid SCG SIRC clock frequency
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#endif
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};
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/* Fast Internal Reference Clock (FIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(fircdiv1_clk),
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"Invalid SCG FIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(fircdiv2_clk),
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"Invalid SCG FIRC divider 2 value");
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static const scg_firc_config_t scg_firc_config = {
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.enableMode = kSCG_FircEnable,
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.div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv1_clk)),
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.div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv2_clk)),
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#if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
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.range = kSCG_FircRange48M,
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#else
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#error Invalid SCG FIRC clock frequency
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#endif
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.trimConfig = NULL
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};
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/* System Phase-Locked Loop (SPLL) configuration */
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ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(spll_clk), 2, 2,
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"Invalid SCG SPLL fixed divider value");
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(splldiv1_clk),
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"Invalid SCG SPLL divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(splldiv2_clk),
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"Invalid SCG SPLL divider 2 value");
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ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(pll), 1, 8,
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"Invalid SCG PLL pre divider value");
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ASSERT_WITHIN_RANGE(SCG_CLOCK_MULT(pll), 16, 47,
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"Invalid SCG PLL multiplier value");
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#if (DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk)) && \
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DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(spll_clk)))
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static const scg_spll_config_t scg_spll_config = {
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.enableMode = kSCG_SysPllEnable,
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.monitorMode = kSCG_SysPllMonitorDisable,
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.div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(splldiv1_clk)),
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.div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(splldiv2_clk)),
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#if !DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(pll)), SCG_CLOCK_NODE(sosc_clk))
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#error Invalid SCG PLL clock source
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#endif
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.prediv = (SCG_CLOCK_DIV(pll) - 1U),
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.mult = (SCG_CLOCK_MULT(pll) - 16U)
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};
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#endif
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__weak void clock_init(void)
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{
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scg_sys_clk_config_t current;
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const scg_sys_clk_config_t scg_sys_clk_config_safe = {
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.divSlow = kSCG_SysClkDivBy4,
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.divBus = kSCG_SysClkDivBy1,
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.divCore = kSCG_SysClkDivBy1,
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.src = kSCG_SysClkSrcSirc
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};
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#if DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk))
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/* Optionally initialize system oscillator */
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CLOCK_InitSysOsc(&scg_sosc_config);
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CLOCK_SetXtal0Freq(scg_sosc_config.freq);
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#endif
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/* Configure SIRC */
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CLOCK_InitSirc(&scg_sirc_config);
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/* Temporary switch to safe SIRC in order to configure FIRC */
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CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config_safe);
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do {
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CLOCK_GetCurSysClkConfig(&current);
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} while (current.src != scg_sys_clk_config_safe.src);
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CLOCK_InitFirc(&scg_firc_config);
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#if (DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk)) && \
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DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(spll_clk)))
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/* Configure System PLL only if system oscilator is initialized */
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/* as the oscillator is the only SPLL clock source.*/
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CLOCK_InitSysPll(&scg_spll_config);
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#endif
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/* Only RUN mode supported for now */
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CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config);
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do {
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CLOCK_GetCurSysClkConfig(&current);
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} while (current.src != scg_sys_clk_config.src);
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
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CLOCK_SetIpSrc(kCLOCK_Lpuart0,
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DT_CLOCKS_CELL(DT_NODELABEL(lpuart0), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
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CLOCK_SetIpSrc(kCLOCK_Lpuart1,
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DT_CLOCKS_CELL(DT_NODELABEL(lpuart1), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
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CLOCK_SetIpSrc(kCLOCK_Lpuart2,
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DT_CLOCKS_CELL(DT_NODELABEL(lpuart2), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0))
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CLOCK_SetIpSrc(kCLOCK_Lpi2c0,
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DT_CLOCKS_CELL(DT_NODELABEL(lpi2c0), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1))
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CLOCK_SetIpSrc(kCLOCK_Lpi2c1,
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DT_CLOCKS_CELL(DT_NODELABEL(lpi2c1), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0))
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CLOCK_SetIpSrc(kCLOCK_Lpspi0,
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DT_CLOCKS_CELL(DT_NODELABEL(lpspi0), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1))
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CLOCK_SetIpSrc(kCLOCK_Lpspi1,
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DT_CLOCKS_CELL(DT_NODELABEL(lpspi1), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi2))
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CLOCK_SetIpSrc(kCLOCK_Lpspi2,
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DT_CLOCKS_CELL(DT_NODELABEL(lpspi2), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc0))
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CLOCK_SetIpSrc(kCLOCK_Adc0
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DT_CLOCKS_CELL(DT_NODELABEL(adc0), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc1))
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CLOCK_SetIpSrc(kCLOCK_Adc1,
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DT_CLOCKS_CELL(DT_NODELABEL(adc1), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm0))
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CLOCK_SetIpSrc(kCLOCK_Ftm0,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm0), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm1))
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CLOCK_SetIpSrc(kCLOCK_Ftm1,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm1), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm2))
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CLOCK_SetIpSrc(kCLOCK_Ftm2,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm2), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm3))
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CLOCK_SetIpSrc(kCLOCK_Ftm3,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm3), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm4))
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CLOCK_SetIpSrc(kCLOCK_Ftm4,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm4), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm5))
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CLOCK_SetIpSrc(kCLOCK_Ftm5,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm5), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm6))
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CLOCK_SetIpSrc(kCLOCK_Ftm6,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm6), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm7))
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CLOCK_SetIpSrc(kCLOCK_Ftm7,
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DT_CLOCKS_CELL(DT_NODELABEL(ftm7), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ewm0))
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CLOCK_SetIpSrc(kCLOCK_Ewm0,
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DT_CLOCKS_CELL(DT_NODELABEL(ewm0), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio0))
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CLOCK_SetIpSrc(kCLOCK_Flexio0,
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DT_CLOCKS_CELL(DT_NODELABEL(flexio0), ip_source));
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet_ptp_clock))
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CLOCK_SetIpSrc(kCLOCK_Enet,
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DT_CLOCKS_CELL(DT_NODELABEL(enet_ptp_clock), ip_source));
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#endif
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}
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void board_early_init_hook(void)
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{
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#if !defined(CONFIG_ARM_MPU)
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uint32_t temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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#if !defined(CONFIG_ARM_MPU)
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/*
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* Disable memory protection and clear slave port errors.
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* MCXE24x does not implement the optional ARMv7-M memory
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* protection unit (MPU), specified by the architecture (PMSAv7), in the
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* Cortex-M4 core. Instead, the processor includes its own MPU module.
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*/
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temp_reg = SYSMPU->CESR;
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temp_reg &= ~SYSMPU_CESR_VLD_MASK;
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temp_reg |= SYSMPU_CESR_SPERR_MASK;
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SYSMPU->CESR = temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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clock_init();
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}

‎boards/nxp/frdm_mcxe247/board.cmake‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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board_runner_args(linkserver "--device=MCXE247:FRDM-MCXE247")
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board_runner_args(jlink "--device=MCXE247")
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include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/nxp/frdm_mcxe247/board.yml‎

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board:
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name: frdm_mcxe247
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full_name: FRDM-MCXE247
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vendor: nxp
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socs:
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- name: mcxe247

‎boards/nxp/frdm_mcxe247/doc/frdm_mcxe247.webp‎

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