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drivers: counter: Add support for cc23x0 LGPT
Add support for LGPT0, LGPT1, LGPT2 and LGPT3 to cc23x0 SoC. Signed-off-by: Stoyan Bogdanov <[email protected]>
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‎drivers/counter/CMakeLists.txt

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@@ -60,3 +60,4 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912 counter_realtek_
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zephyr_library_sources_ifdef(CONFIG_COUNTER_NEORV32_GPTMR counter_neorv32_gptmr.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_WUT_MAX32 counter_max32_wut.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_CC23X0_RTC counter_cc23x0_rtc.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_CC23X0_LGPT counter_cc23x0_lgpt.c)

‎drivers/counter/Kconfig

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@@ -118,4 +118,6 @@ source "drivers/counter/Kconfig.max32_wut"
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source "drivers/counter/Kconfig.cc23x0_rtc"
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source "drivers/counter/Kconfig.cc23x0_lgpt"
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endif # COUNTER

‎drivers/counter/Kconfig.cc23x0_lgpt

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# Copyright (c) 2024 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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config COUNTER_CC23X0_LGPT
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bool "CC23x0 Counter driver based on the LGPT Timer"
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default y
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depends on DT_HAS_TI_CC23X0_LGPT_ENABLED
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help
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Enable counter driver based on LGPT timer for cc23x0

‎drivers/counter/counter_cc23x0_lgpt.c

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/*
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_lgpt
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#include <zephyr/device.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/logging/log.h>
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#include <driverlib/clkctl.h>
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#include <inc/hw_lgpt.h>
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#include <inc/hw_lgpt1.h>
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#include <inc/hw_lgpt3.h>
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#include <inc/hw_types.h>
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#include <inc/hw_evtsvt.h>
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#include <inc/hw_memmap.h>
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LOG_MODULE_REGISTER(counter_cc23x0_lgpt, CONFIG_COUNTER_LOG_LEVEL);
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static void counter_cc23x0_lgpt_isr(const struct device *dev);
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struct counter_cc23x0_lgpt_config {
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struct counter_config_info counter_info;
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uint32_t base;
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uint32_t prescale;
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};
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struct counter_cc23x0_lgpt_data {
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struct counter_alarm_cfg alarm_cfg[3];
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struct counter_top_cfg target_cfg;
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};
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static int counter_cc23x0_lgpt_get_value(const struct device *dev, uint32_t *ticks)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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*ticks = HWREG(config->base + LGPT_O_CNTR);
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return 0;
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}
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static void counter_cc23x0_lgpt_isr(const struct device *dev)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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const struct counter_cc23x0_lgpt_data *data = dev->data;
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uint32_t reg_ris = HWREG(config->base + LGPT_O_RIS);
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uint32_t reg_mis = HWREG(config->base + LGPT_O_MIS);
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uint32_t isr = reg_ris & reg_mis;
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HWREG(config->base + LGPT_O_ICLR) |= reg_mis;
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HWREG(config->base + LGPT_O_IMCLR) |= reg_mis;
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LOG_DBG("\nISR -> LGPT[%x] RIS[%x] MIS[%x] ISR[%x]\n", config->base, reg_ris, reg_mis, isr);
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if (isr & LGPT_RIS_TGT) {
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LOG_DBG("LGPT_RIS_TGT\n");
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if (data->target_cfg.callback) {
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data->target_cfg.callback(dev, data->target_cfg.user_data);
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}
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}
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if (isr & LGPT_RIS_ZERO) {
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LOG_DBG("LGPT_RIS_ZERO\n");
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}
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if (isr & LGPT_RIS_DBLTRANS) {
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LOG_DBG("LGPT_RIS_DBLTRANS\n");
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}
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if (isr & LGPT_RIS_CNTRCHNG) {
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LOG_DBG("LGPT_RIS_CNTRCHNG\n");
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}
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if (isr & LGPT_RIS_DIRCHNG) {
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LOG_DBG("LGPT_RIS_DIRCHNG\n");
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}
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if (isr & LGPT_RIS_IDX) {
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LOG_DBG("LGPT_RIS_IDX\n");
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}
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if (isr & LGPT_RIS_FAULT) {
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LOG_DBG("LGPT_RIS_FAULT\n");
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}
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if (isr & LGPT_RIS_C0CC) {
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LOG_DBG("LGPT_RIS_C0CC\n");
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if (data->alarm_cfg[0].callback) {
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data->alarm_cfg[0].callback(dev, 0, HWREG(config->base + LGPT_O_CNTR),
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data->alarm_cfg[0].user_data);
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}
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}
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if (isr & LGPT_RIS_C1CC) {
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LOG_DBG("LGPT_RIS_C1CC\n");
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if (data->alarm_cfg[1].callback) {
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data->alarm_cfg[1].callback(dev, 1, HWREG(config->base + LGPT_O_CNTR),
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data->alarm_cfg[1].user_data);
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}
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}
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if (isr & LGPT_RIS_C2CC) {
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LOG_DBG("LGPT_RIS_C2CC\n");
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if (data->alarm_cfg[2].callback) {
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data->alarm_cfg[2].callback(dev, 2, HWREG(config->base + LGPT_O_CNTR),
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data->alarm_cfg[2].user_data);
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}
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}
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}
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static uint32_t counter_cc23x0_lgpt_get_freq(const struct device *dev)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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return (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) / config->prescale);
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}
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static int counter_cc23x0_lgpt_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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struct counter_cc23x0_lgpt_data *data = dev->data;
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if (alarm_cfg->ticks > config->counter_info.max_top_value) {
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LOG_ERR("Ticks out of range\n");
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return -EINVAL;
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}
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if (chan_id == 0) {
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HWREG(config->base + LGPT_O_IMASK) |= 0x100;
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HWREG(config->base + LGPT_O_C0CC) = alarm_cfg->ticks;
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HWREG(config->base + LGPT_O_C0CFG) = 0x9D;
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} else if (chan_id == 1) {
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HWREG(config->base + LGPT_O_IMASK) |= 0x200;
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HWREG(config->base + LGPT_O_C1CC) = alarm_cfg->ticks;
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HWREG(config->base + LGPT_O_C1CFG) = 0x9D;
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} else if (chan_id == 2) {
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HWREG(config->base + LGPT_O_IMASK) |= 0x400;
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HWREG(config->base + LGPT_O_C2CC) = alarm_cfg->ticks;
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HWREG(config->base + LGPT_O_C2CFG) = 0x9D;
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} else {
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LOG_ERR("Invalid chan ID\n");
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return -ENOTSUP;
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}
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data->alarm_cfg[chan_id].flags = 0;
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data->alarm_cfg[chan_id].ticks = alarm_cfg->ticks;
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data->alarm_cfg[chan_id].callback = alarm_cfg->callback;
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data->alarm_cfg[chan_id].user_data = alarm_cfg->user_data;
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return 0;
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}
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static int counter_cc23x0_lgpt_cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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struct counter_cc23x0_lgpt_data *data = dev->data;
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if (chan_id == 0) {
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HWREG(config->base + LGPT_O_IMCLR) |= 0x100;
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HWREG(config->base + LGPT_O_C0CC) = 0x0;
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HWREG(config->base + LGPT_O_C0CFG) = 0x0;
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} else if (chan_id == 1) {
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HWREG(config->base + LGPT_O_IMCLR) |= 0x200;
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HWREG(config->base + LGPT_O_C1CC) = 0;
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HWREG(config->base + LGPT_O_C1CFG) = 0;
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} else if (chan_id == 2) {
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HWREG(config->base + LGPT_O_IMCLR) |= 0x400;
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HWREG(config->base + LGPT_O_C2CC) = 0;
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HWREG(config->base + LGPT_O_C2CFG) = 0;
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} else {
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LOG_ERR("Invalid chan ID\n");
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return -ENOTSUP;
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}
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data->alarm_cfg[chan_id].flags = 0;
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data->alarm_cfg[chan_id].ticks = 0;
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data->alarm_cfg[chan_id].callback = NULL;
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data->alarm_cfg[chan_id].user_data = NULL;
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return 0;
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}
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static uint32_t counter_cc23x0_lgpt_get_top_value(const struct device *dev)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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return HWREG(config->base + LGPT_O_TGT);
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}
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static int counter_cc23x0_lgpt_set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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struct counter_cc23x0_lgpt_data *data = dev->data;
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int ret = 0;
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/* If not running set new top value */
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if (HWREG(config->base + LGPT_O_STARTCFG) == 0) {
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HWREG(config->base + LGPT_O_TGT) = config->counter_info.max_top_value;
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HWREG(config->base + LGPT_O_IMASK) |= 0x001;
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HWREG(config->base + LGPT_O_TGT) = cfg->ticks;
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data->target_cfg.flags = 0;
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data->target_cfg.ticks = cfg->ticks;
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data->target_cfg.callback = cfg->callback;
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data->target_cfg.user_data = cfg->user_data;
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} else {
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ret = -EBUSY;
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}
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return ret;
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}
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static uint32_t counter_cc23x0_lgpt_get_pending_int(const struct device *dev)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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return HWREG(config->base + LGPT_O_RIS) & HWREG(config->base + LGPT_O_MIS) ? 1 : 0;
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}
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static int counter_cc23x0_lgpt_start(const struct device *dev)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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LOG_DBG("[START] LGPT base[%x]\n", config->base);
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HWREG(config->base + LGPT_O_CTL) = LGPT_CTL_MODE_UP_PER;
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/* Set to 1 to start timer */
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HWREG(config->base + LGPT_O_STARTCFG) = 0x1;
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return 0;
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}
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static int counter_cc23x0_lgpt_stop(const struct device *dev)
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{
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const struct counter_cc23x0_lgpt_config *config = dev->config;
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LOG_DBG("[STOP] LGPT base[%x]\n", config->base);
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/* Set to 0 to stop timer */
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HWREG(config->base + LGPT_O_STARTCFG) = 0x0;
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return 0;
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}
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static const struct counter_driver_api cc23x0_lgpt_api = {
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.start = counter_cc23x0_lgpt_start,
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.stop = counter_cc23x0_lgpt_stop,
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.get_value = counter_cc23x0_lgpt_get_value,
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.set_alarm = counter_cc23x0_lgpt_set_alarm,
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.cancel_alarm = counter_cc23x0_lgpt_cancel_alarm,
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.get_top_value = counter_cc23x0_lgpt_get_top_value,
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.set_top_value = counter_cc23x0_lgpt_set_top_value,
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.get_pending_int = counter_cc23x0_lgpt_get_pending_int,
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.get_freq = counter_cc23x0_lgpt_get_freq,
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};
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#define LGPT_CLK_PRESCALE(pres) ((pres + 1) << 8)
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#define LGPT_CC23X0_INIT_FUNC(inst) \
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static int counter_cc23x0_lgpt_init##inst(const struct device *dev) \
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{ \
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const struct counter_cc23x0_lgpt_config *config = dev->config; \
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\
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CLKCTLEnable(CLKCTL_BASE, CLKCTL_LGPT##inst); \
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\
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IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
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counter_cc23x0_lgpt_isr, DEVICE_DT_INST_GET(inst), 0); \
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\
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irq_enable(DT_INST_IRQN(inst)); \
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\
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HWREG(config->base + LGPT_O_TGT) = config->counter_info.max_top_value; \
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\
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HWREG(config->base + LGPT_O_PRECFG) = LGPT_CLK_PRESCALE(config->prescale); \
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\
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HWREG(EVTSVT_BASE + EVTSVT_O_LGPTSYNCSEL) = EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM0; \
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\
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return 0; \
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}
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#define CC23X0_LGPT_INIT(inst) \
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\
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LGPT_CC23X0_INIT_FUNC(inst); \
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\
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static const struct counter_cc23x0_lgpt_config cc23x0_lgpt_config_##inst = { \
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.counter_info = \
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{ \
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.max_top_value = DT_INST_PROP(inst, max_top_value), \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = 3, \
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}, \
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.base = DT_INST_REG_ADDR(inst), \
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.prescale = DT_INST_PROP(inst, clk_prescale), \
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}; \
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\
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static struct counter_cc23x0_lgpt_data cc23x0_lgpt_data_##inst; \
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\
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DEVICE_DT_INST_DEFINE(inst, &counter_cc23x0_lgpt_init##inst, NULL, \
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&cc23x0_lgpt_data_##inst, &cc23x0_lgpt_config_##inst, POST_KERNEL, \
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CONFIG_COUNTER_INIT_PRIORITY, &cc23x0_lgpt_api);
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DT_INST_FOREACH_STATUS_OKAY(CC23X0_LGPT_INIT);

‎dts/bindings/counter/ti,cc23x0-lgpt.yaml

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# Copyright (c) Copyright (c) 2024 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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description: CC23x0 LGPT counter driver
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properties:
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freq:
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type: int
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description: clock frequency (only used for external clock sources)
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interrupts:
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required: true
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clk-prescale:
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type: int
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required: true
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description: Counter clock prescale
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max-top-value:
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type: int
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required: true
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description: Max allowed value for counter
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compatible: "ti,cc23x0-lgpt"
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include: base.yaml

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