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bogdanovskartben
bogdanovs
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kartben
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drivers: counter: Add support for cc23x0 RTC counter
Add support for cc23x0 RTC driver in counter. RTC is always ON after device boot. Timer is restared only on POR, and is active during STANDBY and ACTIVE power states. Signed-off-by: Stoyan Bogdanov <[email protected]>
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‎drivers/counter/CMakeLists.txt

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@@ -59,3 +59,4 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912_SLWTMR counter_r
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zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912 counter_realtek_rts5912.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_NEORV32_GPTMR counter_neorv32_gptmr.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_WUT_MAX32 counter_max32_wut.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_CC23X0_RTC counter_cc23x0_rtc.c)

‎drivers/counter/Kconfig

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@@ -116,4 +116,6 @@ source "drivers/counter/Kconfig.neorv32"
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source "drivers/counter/Kconfig.max32_wut"
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source "drivers/counter/Kconfig.cc23x0_rtc"
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endif # COUNTER

‎drivers/counter/Kconfig.cc23x0_rtc

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# Copyright (c) 2024 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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config COUNTER_CC23X0_RTC
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bool "CC23x0 Counter driver based on the RTC Timer"
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default y
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depends on DT_HAS_TI_CC23X0_RTC_ENABLED
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help
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Enable counter driver based on RTC timer for cc23x0

‎drivers/counter/counter_cc23x0_rtc.c

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/*
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_rtc
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#include <zephyr/device.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/logging/log.h>
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#include <inc/hw_rtc.h>
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#include <inc/hw_types.h>
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#include <inc/hw_evtsvt.h>
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#include <inc/hw_memmap.h>
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LOG_MODULE_REGISTER(cc23x0_counter_rtc, CONFIG_COUNTER_LOG_LEVEL);
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static void counter_cc23x0_isr(const struct device *dev);
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struct counter_cc23x0_config {
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struct counter_config_info counter_info;
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uint32_t base;
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};
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struct counter_cc23x0_data {
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struct counter_alarm_cfg alarm_cfg0;
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};
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static int counter_cc23x0_get_value(const struct device *dev, uint32_t *ticks)
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{
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/* Resolution is 8us and max timeout ~9.5h */
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const struct counter_cc23x0_config *config = dev->config;
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*ticks = HWREG(config->base + RTC_O_TIME8U);
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return 0;
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}
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static int counter_cc23x0_get_value_64(const struct device *dev, uint64_t *ticks)
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{
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const struct counter_cc23x0_config *config = dev->config;
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/*
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* RTC counter register is 67 bits, only part of the bits are accessible.
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* They are split in two partially overlapping registers:
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* TIME524M [50:19]
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* TIME8U [34:3]
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*/
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uint64_t rtc_time_now =
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((HWREG(config->base + RTC_O_TIME524M) << 16) & 0xFFFFFFF800000000) |
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HWREG(config->base + RTC_O_TIME8U);
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*ticks = rtc_time_now;
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return 0;
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}
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static void counter_cc23x0_isr(const struct device *dev)
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{
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const struct counter_cc23x0_config *config = dev->config;
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struct counter_cc23x0_data *data = dev->data;
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/* Clear RTC interrupt regs */
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HWREG(config->base + RTC_O_ICLR) = 0x3;
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HWREG(config->base + RTC_O_IMCLR) = 0x3;
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uint32_t now = HWREG(config->base + RTC_O_TIME8U);
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if (data->alarm_cfg0.callback) {
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data->alarm_cfg0.callback(dev, 0, now, data->alarm_cfg0.user_data);
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}
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}
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static int counter_cc23x0_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct counter_cc23x0_config *config = dev->config;
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struct counter_cc23x0_data *data = dev->data;
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/* RTC have resolutiuon of 8us */
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if (counter_ticks_to_us(dev, alarm_cfg->ticks) <= 8) {
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return -ENOTSUP;
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}
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uint32_t now = HWREG(config->base + RTC_O_TIME8U);
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/* Calculate next alarm relative to current time in us */
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uint32_t next_alarm = now + (counter_ticks_to_us(dev, alarm_cfg->ticks) / 8);
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HWREG(config->base + RTC_O_CH0CC8U) = next_alarm;
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HWREG(config->base + RTC_O_IMASK) = 0x1;
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HWREG(config->base + RTC_O_ARMSET) = 0x1;
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HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ3SEL) = EVTSVT_CPUIRQ16SEL_PUBID_AON_RTC_COMB;
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), counter_cc23x0_isr,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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data->alarm_cfg0.flags = 0;
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data->alarm_cfg0.ticks = alarm_cfg->ticks;
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data->alarm_cfg0.callback = alarm_cfg->callback;
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data->alarm_cfg0.user_data = alarm_cfg->user_data;
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return 0;
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}
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static int counter_cc23x0_cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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const struct counter_cc23x0_config *config = dev->config;
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/* Unset interrupt source */
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HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ3SEL) = 0x0;
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/* Unarm both channels */
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HWREG(config->base + RTC_O_ARMCLR) = 0x3;
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return 0;
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}
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static int counter_cc23x0_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
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{
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return -ENOTSUP;
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}
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static uint32_t counter_cc23x0_get_pending_int(const struct device *dev)
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{
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const struct counter_cc23x0_config *config = dev->config;
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struct counter_cc23x0_data *data = dev->data;
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/* Check interrupt and mask */
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if (HWREG(config->base + RTC_O_RIS) & HWREG(config->base + RTC_O_MIS)) {
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/* Clear RTC interrupt regs */
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HWREG(config->base + RTC_O_ICLR) = 0x3;
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HWREG(config->base + RTC_O_IMCLR) = 0x3;
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uint32_t now = HWREG(config->base + RTC_O_TIME8U);
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if (data->alarm_cfg0.callback) {
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data->alarm_cfg0.callback(dev, 0, now, data->alarm_cfg0.user_data);
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}
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return 0;
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}
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return -ESRCH;
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}
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static uint32_t counter_cc23x0_get_top_value(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return -ENOTSUP;
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}
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static uint32_t counter_cc23x0_get_freq(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/*
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* From TRM clock for RTC is 24Mhz handled internally
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* which is 1/2 from main 48Mhz clock = 24Mhz
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* Accessible for user resolution is 8us per bit
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* TIME8U [34:3] ~ 9.5h
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*/
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return (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) / 2);
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}
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static int counter_cc23x0_start(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* RTC timer runs after power-on reset */
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return -ENOTSUP;
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}
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static int counter_cc23x0_stop(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* Any reset/sleep mode, except for POR, will not stop or reset the RTC timer */
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return -ENOTSUP;
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}
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static int counter_cc23x0_init(const struct device *dev)
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{
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const struct counter_cc23x0_config *config = dev->config;
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/* Clear interrupt Mask */
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HWREG(config->base + RTC_O_IMCLR) = 0x3;
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/* Clear Interrupt */
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HWREG(config->base + RTC_O_ICLR) = 0x3;
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/* Clear Armed */
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HWREG(config->base + RTC_O_ARMCLR) = 0x3;
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return 0;
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}
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static const struct counter_driver_api rtc_cc23x0_api = {
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.start = counter_cc23x0_start,
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.stop = counter_cc23x0_stop,
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.get_value = counter_cc23x0_get_value,
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.get_value_64 = counter_cc23x0_get_value_64,
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.set_alarm = counter_cc23x0_set_alarm,
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.cancel_alarm = counter_cc23x0_cancel_alarm,
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.get_top_value = counter_cc23x0_get_top_value,
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.set_top_value = counter_cc23x0_set_top_value,
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.get_pending_int = counter_cc23x0_get_pending_int,
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.get_freq = counter_cc23x0_get_freq,
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};
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#define CC23X0_INIT(inst) \
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static const struct counter_cc23x0_config cc23x0_config_##inst = { \
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.counter_info = \
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{ \
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.max_top_value = UINT32_MAX, \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = 1, \
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}, \
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.base = DT_INST_REG_ADDR(inst), \
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}; \
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\
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static struct counter_cc23x0_data cc23x0_data_##inst; \
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\
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DEVICE_DT_INST_DEFINE(0, &counter_cc23x0_init, NULL, &cc23x0_data_##inst, \
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&cc23x0_config_##inst, POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \
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&rtc_cc23x0_api);
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DT_INST_FOREACH_STATUS_OKAY(CC23X0_INIT)

‎dts/bindings/counter/ti,cc23x0-rtc.yaml

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# Copyright (c) 2024 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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description: |
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CC23x0 RTC counter driver
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Any reset/sleep mode, except for the power-up reset, will not
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stop or reset the RTC Timer. This behavior may be handy when
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supporting applications that need to keep a timing baseline on
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such situations.
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There is also no need to enable the RTC Timer node, it starts
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running from power-up.
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compatible: "ti,cc23x0-rtc"
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include: base.yaml

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