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drivers: serial: sf32lb: add basic driver
Just basic driver with poll-in/out capability. Signed-off-by: Gerard Marull-Paretas <[email protected]>
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‎drivers/serial/CMakeLists.txt‎

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@@ -87,6 +87,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_SAM uart_sam.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SAM0 uart_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SCI_RA uart_renesas_ra_sci.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SEDI uart_sedi.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SF32LB uart_sf32lb.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SI32_USART uart_si32_usart.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SIFIVE uart_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SILABS_EUSART uart_silabs_eusart.c)

‎drivers/serial/Kconfig‎

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@@ -225,6 +225,7 @@ rsource "Kconfig.rv32m1_lpuart"
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rsource "Kconfig.rzt2m"
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rsource "Kconfig.sam0"
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rsource "Kconfig.sedi"
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rsource "Kconfig.sf32lb"
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rsource "Kconfig.si32"
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rsource "Kconfig.sifive"
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rsource "Kconfig.silabs_eusart"

‎drivers/serial/Kconfig.sf32lb‎

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# Copyright (c) Core Devices LLC
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# SPDX-License-Identifier: Apache-2.0
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config UART_SF32LB
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bool "SiFli SF32LB UART driver"
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default y
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depends on DT_HAS_SIFLI_SF32LB_USART_ENABLED
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select SERIAL_HAS_DRIVER
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select PINCTRL
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select CLOCK_CONTROL
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help
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This option enables the SiFli SF32LB UART driver.

‎drivers/serial/uart_sf32lb.c‎

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/*
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* Copyright (c) Core Devices LLC
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifli_sf32lb_usart
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control/sf32lb.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/uart.h>
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#include <register.h>
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#define UART_CR1 offsetof(USART_TypeDef, CR1)
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#define UART_CR2 offsetof(USART_TypeDef, CR2)
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#define UART_CR3 offsetof(USART_TypeDef, CR3)
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#define UART_BRR offsetof(USART_TypeDef, BRR)
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#define UART_ISR offsetof(USART_TypeDef, ISR)
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#define UART_ICR offsetof(USART_TypeDef, ICR)
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#define UART_RDR offsetof(USART_TypeDef, RDR)
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#define UART_TDR offsetof(USART_TypeDef, TDR)
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#define UART_MISCR offsetof(USART_TypeDef, MISCR)
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#define UART_CR1_M_6B FIELD_PREP(USART_CR1_M_Msk, 0U)
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#define UART_CR1_M_7B FIELD_PREP(USART_CR1_M_Msk, 1U)
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#define UART_CR1_M_8B FIELD_PREP(USART_CR1_M_Msk, 2U)
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#define UART_CR1_M_9B FIELD_PREP(USART_CR1_M_Msk, 3U)
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#define UART_CR2_STOP_1B FIELD_PREP(USART_CR2_STOP_Msk, 0U)
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#define UART_CR2_STOP_2B FIELD_PREP(USART_CR2_STOP_Msk, 1U)
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/* minimal BRR: INT=1, FRAC=0 (0x10) */
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#define UART_BRR_MIN 0x10U
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struct uart_sf32lb_config {
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uintptr_t base;
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const struct pinctrl_dev_config *pcfg;
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struct sf32lb_clock_dt_spec clock;
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struct uart_config uart_cfg;
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};
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static int uart_sf32lb_configure(const struct device *dev, const struct uart_config *cfg)
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{
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const struct uart_sf32lb_config *config = dev->config;
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enum uart_config_data_bits data_bits = cfg->data_bits;
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uint32_t cr1, cr2, cr3, brr, miscr;
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/* CR1: disable USART */
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cr1 = sys_read32(config->base + UART_CR1);
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cr1 &= ~USART_CR1_UE;
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sys_write32(cr1, config->base + UART_CR1);
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/* CR1: data bits, parity, oversampling */
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cr1 &= ~(USART_CR1_M_Msk | USART_CR1_PCE_Msk | USART_CR1_PS_Msk | USART_CR1_OVER8_Msk);
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/* data bits include parity bit */
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if (cfg->parity != UART_CFG_PARITY_NONE) {
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data_bits++;
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if (data_bits > UART_CFG_DATA_BITS_9) {
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return -ENOTSUP;
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}
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}
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switch (data_bits) {
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case UART_CFG_DATA_BITS_6:
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cr1 |= UART_CR1_M_6B;
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break;
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case UART_CFG_DATA_BITS_7:
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cr1 |= UART_CR1_M_7B;
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break;
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case UART_CFG_DATA_BITS_8:
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cr1 |= UART_CR1_M_8B;
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break;
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case UART_CFG_DATA_BITS_9:
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cr1 |= UART_CR1_M_9B;
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break;
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default:
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return -ENOTSUP;
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}
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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break;
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case UART_CFG_PARITY_ODD:
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cr1 |= (USART_CR1_PCE | USART_CR1_PS);
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break;
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case UART_CFG_PARITY_EVEN:
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cr1 |= USART_CR1_PCE;
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break;
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default:
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return -ENOTSUP;
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}
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sys_write32(cr1, config->base + UART_CR1);
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/* CR2: stop bits */
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cr2 = sys_read32(config->base + UART_CR2);
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cr2 &= ~USART_CR2_STOP_Msk;
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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cr2 |= UART_CR2_STOP_1B;
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break;
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case UART_CFG_STOP_BITS_2:
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cr2 |= UART_CR2_STOP_2B;
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break;
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default:
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return -ENOTSUP;
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}
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sys_write32(cr2, config->base + UART_CR2);
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/* CR3: flow control */
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cr3 = sys_read32(config->base + UART_CR3);
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cr3 &= ~(USART_CR3_RTSE_Msk | USART_CR3_CTSE_Msk);
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switch (cfg->flow_ctrl) {
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case UART_CFG_FLOW_CTRL_NONE:
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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cr3 |= (USART_CR3_RTSE_Msk | USART_CR3_CTSE_Msk);
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break;
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default:
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return -ENOTSUP;
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}
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sys_write32(cr3, config->base + UART_CR3);
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/* enable USART */
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cr1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
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sys_write32(cr1, config->base + UART_CR1);
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/* BRR: baudrate */
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miscr = sys_read32(config->base + UART_MISCR);
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miscr &= ~USART_MISCR_SMPLINI_Msk;
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brr = 48000000UL / config->uart_cfg.baudrate;
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if (brr < UART_BRR_MIN) {
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cr1 |= USART_CR1_OVER8;
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sys_write32(cr1, config->base + UART_CR1);
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/* recalculate brr with reduced oversampling */
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brr = (48000000UL * 2U) / config->uart_cfg.baudrate;
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miscr |= FIELD_PREP(USART_MISCR_SMPLINI_Msk, 2U);
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} else {
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miscr |= FIELD_PREP(USART_MISCR_SMPLINI_Msk, 6U);
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}
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sys_write32(miscr, config->base + UART_MISCR);
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sys_write32(brr, config->base + UART_BRR);
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return 0;
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}
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static int uart_sf32lb_poll_in(const struct device *dev, uint8_t *c)
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{
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const struct uart_sf32lb_config *config = dev->config;
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if ((sys_read32(config->base + UART_ISR) & USART_ISR_RXNE) != 0U) {
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*c = sys_read32(config->base + UART_RDR) & 0xFFU;
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return 0;
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}
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return -1;
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}
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static void uart_sf32lb_poll_out(const struct device *dev, uint8_t c)
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{
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const struct uart_sf32lb_config *config = dev->config;
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sys_write32(USART_ISR_TC, config->base + UART_ICR);
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sys_write8(c, config->base + UART_TDR);
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while ((sys_read32(config->base + UART_ISR) & USART_ISR_TC) == 0U) {
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}
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}
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static const struct uart_driver_api uart_sf32lb_api = {
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.poll_in = uart_sf32lb_poll_in,
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.poll_out = uart_sf32lb_poll_out,
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};
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static int uart_sf32lb_init(const struct device *dev)
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{
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const struct uart_sf32lb_config *config = dev->config;
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int ret;
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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if (config->clock.dev != NULL) {
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if (!sf3232lb_clock_is_ready_dt(&config->clock)) {
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return -ENODEV;
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}
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ret = sf32lb_clock_control_on_dt(&config->clock);
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if (ret < 0) {
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return ret;
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}
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}
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ret = uart_sf32lb_configure(dev, &config->uart_cfg);
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if (ret < 0) {
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return ret;
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}
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return 0;
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}
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#define SF32LB_UART_DEFINE(index) \
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PINCTRL_DT_INST_DEFINE(index); \
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\
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static const struct uart_sf32lb_config uart_sf32lb_cfg_##index = { \
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.base = DT_INST_REG_ADDR(index), \
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.clock = SF32LB_CLOCK_DT_INST_SPEC_GET_OR(index, {}), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
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.uart_cfg = \
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{ \
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.baudrate = DT_INST_PROP(index, current_speed), \
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.parity = \
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DT_INST_ENUM_IDX_OR(index, parity, UART_CFG_PARITY_NONE), \
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.stop_bits = DT_INST_ENUM_IDX_OR(index, stop_bits, \
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UART_CFG_STOP_BITS_1), \
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.data_bits = DT_INST_ENUM_IDX_OR(index, data_bits, \
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UART_CFG_DATA_BITS_8), \
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.flow_ctrl = DT_INST_PROP(index, hw_flow_control) \
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? UART_CFG_FLOW_CTRL_RTS_CTS \
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: UART_CFG_FLOW_CTRL_NONE, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(index, uart_sf32lb_init, NULL, NULL, &uart_sf32lb_cfg_##index, \
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PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_sf32lb_api);
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DT_INST_FOREACH_STATUS_OKAY(SF32LB_UART_DEFINE)

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