soc: esp32: Update IRQ config for shared allocator

Update IRQ handling related files to unify interrupt controller
between Xtensa and RISCV devices.

Signed-off-by: Raffael Rostagno <[email protected]>
Signed-off-by: Sylvio Alves <[email protected]>

Author: Raffael Rostagno

soc/espressif/common/loader.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -252,7 +252,7 @@ void __start(void)
 {
 #ifdef CONFIG_RISCV_GP
 
-	__asm__ __volatile__("la t0, _esp_vector_table\n"
+	__asm__ __volatile__("la t0, _vector_table\n"
 			     "csrw mtvec, t0\n");
 
 	/* Disable normal interrupts. */

soc/espressif/esp32/soc.c

@@ -26,8 +26,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 #if CONFIG_ESP_SPIRAM
 	esp_init_psram();
 
@@ -47,8 +45,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 

soc/espressif/esp32/soc_appcpu.c

@@ -87,8 +87,6 @@ void IRAM_ATTR __appcpu_start(void)
 
 	core_intr_matrix_clear();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 

soc/espressif/esp32c2/CMakeLists.txt

@@ -3,7 +3,6 @@
 zephyr_sources(
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )

soc/espressif/esp32c2/Kconfig.defconfig

@@ -1,12 +1,10 @@
-# ESP32C2 SoC configuration
-
-# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_ESP32C2
 
 config NUM_IRQS
-	default 43
+	default 32
 
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)

soc/espressif/esp32c2/soc.c

@@ -10,7 +10,7 @@
 #include <esp_private/cache_utils.h>
 #include <esp_private/system_internal.h>
 #include <esp_timer.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/kernel_structs.h>
 #include <kernel_internal.h>
 
@@ -24,8 +24,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 
@@ -34,8 +32,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 

soc/espressif/esp32c2/soc_irq.S

@@ -1,4 +1,4 @@
-/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,13 +8,8 @@
 
 /* Exports */
 GTEXT(__soc_handle_irq)
-GTEXT(soc_intr_get_next_source)
 
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	addi sp, sp,-4
-	sw  ra, 0x00(sp)
-	la t1, soc_intr_get_next_source
-	jalr ra, t1, 0
-	lw  ra, 0x00(sp)
-	addi sp, sp, 4
+
+	/* int status clearing is done at ISR */
 	ret

soc/espressif/esp32c2/soc_irq.c

@@ -1,4 +1,4 @@
-/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
 	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
 	 */
 
-	.global  _esp_vector_table
+	.global  _vector_table
 	.section .exception_vectors.text
 	.balign   0x100
-	.type     _esp_vector_table, @function
+	.type     _vector_table, @function
 
-_esp_vector_table:
+_vector_table:
 	.option push
 	.option norvc
 	.rept (32)

soc/espressif/esp32c2/vectors.S

@@ -3,7 +3,6 @@
 zephyr_sources(
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )