include: bindings: clock stm32f4 header reformat code

Apply clang-format to re-format the stm32f4_clock header file

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

include/zephyr/dt-bindings/clock/stm32f4_clock.h

@@ -11,15 +11,15 @@
 /** Domain clocks */
 
 /** Bus clocks */
-#define STM32_CLOCK_BUS_AHB1    0x030
-#define STM32_CLOCK_BUS_AHB2    0x034
-#define STM32_CLOCK_BUS_AHB3    0x038
-#define STM32_CLOCK_BUS_APB1    0x040
-#define STM32_CLOCK_BUS_APB2    0x044
-#define STM32_CLOCK_BUS_APB3    0x0A8
+#define STM32_CLOCK_BUS_AHB1 0x030
+#define STM32_CLOCK_BUS_AHB2 0x034
+#define STM32_CLOCK_BUS_AHB3 0x038
+#define STM32_CLOCK_BUS_APB1 0x040
+#define STM32_CLOCK_BUS_APB2 0x044
+#define STM32_CLOCK_BUS_APB3 0x0A8
 
-#define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
-#define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB3
+#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
+#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
 
 /** Domain clocks */
 /* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */
@@ -31,15 +31,14 @@
 #define STM32_SRC_HSI      (STM32_SRC_LSI + 1)
 #define STM32_SRC_HSE      (STM32_SRC_HSI + 1)
 /** PLL clock outputs */
-#define STM32_SRC_PLL_P		(STM32_SRC_HSE + 1)
-#define STM32_SRC_PLL_Q		(STM32_SRC_PLL_P + 1)
-#define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
+#define STM32_SRC_PLL_P    (STM32_SRC_HSE + 1)
+#define STM32_SRC_PLL_Q    (STM32_SRC_PLL_P + 1)
+#define STM32_SRC_PLL_R    (STM32_SRC_PLL_Q + 1)
 /** I2S sources */
-#define STM32_SRC_PLLI2S_R	(STM32_SRC_PLL_R + 1)
+#define STM32_SRC_PLLI2S_R (STM32_SRC_PLL_R + 1)
 /* I2S_CKIN not supported yet */
 /* #define STM32_SRC_I2S_CKIN	TBD */
 
-
 #define STM32_CLOCK_REG_MASK    0xFFU
 #define STM32_CLOCK_REG_SHIFT   0U
 #define STM32_CLOCK_SHIFT_MASK  0x1FU
@@ -62,25 +61,25 @@
  * @param mask Mask for the RCC_CFGRx field.
  * @param val Clock value (0, 1, ... 7).
  */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
+#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)                                                  \
+	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |                               \
+	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |                         \
+	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |                            \
 	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
 
 /** @brief RCC_CFGRx register offset */
-#define CFGR_REG		0x08
+#define CFGR_REG 0x08
 /** @brief RCC_BDCR register offset */
-#define BDCR_REG		0x70
+#define BDCR_REG 0x70
 
 /** @brief Device domain clocks selection helpers */
 /** CFGR devices */
-#define I2S_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
-#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
-#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
+#define I2S_SEL(val)  STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
+#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
+#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
+#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
+#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)  STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */