drivers: Fix the improper use of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC

Fix the improper use of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for some
STM32WB0 drivers due to the misunderstanding of its definition.

Signed-off-by: Ali Hozhabri <[email protected]>

Author: HoZHel

drivers/adc/adc_stm32wb0.c

@@ -97,8 +97,10 @@ LOG_MODULE_REGISTER(adc_stm32wb0, CONFIG_ADC_LOG_LEVEL);
 #define	ADC_CHANNEL_TYPE_DIFF		(0x02U)	/* Differential */
 #define ADC_CHANNEL_TYPE_INVALID	(0xFFU)	/* Invalid */
 
+#define STM32_HCLK_FREQUENCY DT_PROP(DT_NODELABEL(rcc), clock_frequency)
+
 /** See RM0505 §6.2.1 "System clock details" */
-BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= (8 * 1000 * 1000),
+BUILD_ASSERT(STM32_HCLK_FREQUENCY >= (8 * 1000 * 1000),
 	"STM32WB0: system clock frequency must be at least 8MHz to use ADC");
 
 /**

drivers/clock_control/clock_stm32_ll_wb0.c

@@ -28,6 +28,7 @@
 #define CLOCK_FREQ_64MHZ	(64000000U)
 #define CLOCK_FREQ_32MHZ	(32000000U)
 #define CLOCK_FREQ_16MHZ	(16000000U)
+#define STM32_HCLK_FREQUENCY DT_PROP(DT_NODELABEL(rcc), clock_frequency)
 
 /* Device tree node definitions */
 #define DT_RCC_SLOWCLK_NODE	DT_PHANDLE(STM32_CLOCK_CONTROL_NODE, slow_clock)
@@ -74,11 +75,11 @@ BUILD_ASSERT(!IS_ENABLED(STM32_SYSCLK_SRC_HSE) || STM32_WB0_CLKSYS_PRESCALER !=
 		 * the RC64M generator is imprecise. In this configuration, MR_BLE is broken.
 		 * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI.
 		 */
-		BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_32MHZ,
+		BUILD_ASSERT(STM32_HCLK_FREQUENCY >= CLOCK_FREQ_32MHZ,
 			"System clock frequency must be at least 32MHz to use LSI");
 #	else
 		/* In PLL or Direct HSE mode, the clock is stable, so 16MHz can be used. */
-		BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_16MHZ,
+		BUILD_ASSERT(STM32_HCLK_FREQUENCY >= CLOCK_FREQ_16MHZ,
 			"System clock frequency must be at least 16MHz to use LSI");
 #	endif /* STM32_SYSCLK_SRC_HSI */
 
@@ -711,7 +712,7 @@ int stm32_clock_control_init(const struct device *dev)
 	 *  - 0 wait states otherwise (CLK_SYS <= 32MHz)
 	 */
 	LL_FLASH_SetLatency(
-	(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_32MHZ)
+	(STM32_HCLK_FREQUENCY >= CLOCK_FREQ_32MHZ)
 			? LL_FLASH_LATENCY_1
 			: LL_FLASH_LATENCY_0
 	);
@@ -755,7 +756,7 @@ BUILD_ASSERT(IS_ENABLED(STM32_HSE_ENABLED),
 	LL_RCC_SetRC64MPLLPrescaler(
 		kconfig_to_ll_prescaler(STM32_WB0_CLKSYS_PRESCALER));
 
-	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+	SystemCoreClock = STM32_HCLK_FREQUENCY;
 
 #if defined(STM32_LSI_ENABLED)
 	/* Enable MR_BLE clock for LSI measurement.

drivers/entropy/entropy_stm32.c

@@ -36,6 +36,8 @@
 #define STM32_CONDRST_SUPPORT
 #endif
 
+#define STM32_HCLK_FREQUENCY DT_PROP(DT_NODELABEL(rcc), clock_frequency)
+
 /*
  * This driver need to take into account all STM32 family:
  *  - simple rng without hardware fifo and no DMA.
@@ -84,7 +86,7 @@ BUILD_ASSERT((CONFIG_ENTROPY_STM32_THR_POOL_SIZE &
  *  at least 32 MHz. See also: §6.2.2 "Peripheral clock details".
  */
 BUILD_ASSERT(!IS_ENABLED(CONFIG_SOC_STM32WB09XX) ||
-		CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= (32 * 1000 * 1000),
+		STM32_HCLK_FREQUENCY >= (32 * 1000 * 1000),
 	"STM32WB09: TRNG requires system clock frequency >= 32MHz");
 
 struct entropy_stm32_rng_dev_cfg {

drivers/rtc/rtc_ll_stm32.c

@@ -42,6 +42,8 @@
 
 LOG_MODULE_REGISTER(rtc_stm32, CONFIG_RTC_LOG_LEVEL);
 
+#define STM32_HCLK_FREQUENCY DT_PROP(DT_NODELABEL(rcc), clock_frequency)
+
 #if (defined(CONFIG_SOC_SERIES_STM32L1X) && !defined(RTC_SUBSECOND_SUPPORT)) \
 	|| defined(CONFIG_SOC_SERIES_STM32F2X)
 /* subsecond counting is not supported by some STM32L1x MCUs (Cat.1) & by STM32F2x SoC series */
@@ -358,7 +360,7 @@ static int rtc_stm32_init(const struct device *dev)
 	 * as time base, but SysTick is initialized after the RTC...
 	 */
 	const uint32_t cycles_to_waste =
-		84 * (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / USEC_PER_SEC);
+		84 * (STM32_HCLK_FREQUENCY / USEC_PER_SEC);
 	volatile uint32_t i = cycles_to_waste;
 
 	while (--i > 0) {