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Vge0rgekartben
Vge0rge
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kartben
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boards: nordic: Add initial support for nRF54L10 with TF-M
This adds the nrf54l15dk/nrf54l10/cpuapp/ns board variant to Zephyr. It allows to build applications for this target. This is an initial support for the non secure target which allows building and running tfm_ipc and config_build. This is NOT full support of the non secure target in upstream Zephyr. There are important limitations, such as: - The hardware Crypto accelerator is not supported and thus the non secur target is NOT secure for production applications in upstream Zephyr. - The BL2 is not supported, so no DFU is supported with this support Most of the code changes here are taken from nRF Connect SDK in order to avoid having noups there. Signed-off-by: Georgios Vasilakis <[email protected]>
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‎boards/nordic/nrf54l15dk/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
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# nRF54L15 DK board configuration
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6-
if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
6+
if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
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DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
99

@@ -27,4 +27,4 @@ config NRF_TRUSTZONE_RAM_REGION_SIZE
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This abstraction allows us to configure TrustZone without depending
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on peripheral specific symbols.
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30-
endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
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endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS

‎boards/nordic/nrf54l15dk/Kconfig.defconfig

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@@ -14,7 +14,7 @@ config ROM_START_OFFSET
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endif # BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \
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# BOARD_NRF54L15DK_NRF54L15_CPUAPP
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17-
if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
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if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
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config BT_CTLR
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default BT
@@ -30,4 +30,4 @@ config FLASH_LOAD_SIZE
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config BUILD_WITH_TFM
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default y
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33-
endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
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endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS

‎boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk

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@@ -3,7 +3,7 @@
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config BOARD_NRF54L15DK
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select SOC_NRF54L05_CPUAPP if BOARD_NRF54L15DK_NRF54L05_CPUAPP
6-
select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP
6+
select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
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select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
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select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \
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BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP

‎boards/nordic/nrf54l15dk/board.cmake

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@@ -10,7 +10,7 @@ elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR)
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board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
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endif()
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13-
if(CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS)
13+
if(CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS OR CONFIG_BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS)
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set(TFM_PUBLIC_KEY_FORMAT "full")
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endif()
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‎boards/nordic/nrf54l15dk/board.yml

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@@ -5,6 +5,9 @@ board:
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socs:
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- name: nrf54l05
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- name: nrf54l10
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variants:
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- name: ns
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cpucluster: cpuapp
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- name: nrf54l15
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variants:
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- name: xip

‎boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#define USE_NON_SECURE_ADDRESS_MAP 1
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#include <nordic/nrf54l10_cpuapp.dtsi>
12+
#include "nrf54l_05_10_15_cpuapp_common.dtsi"
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/ {
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compatible = "nordic,nrf54l15dk_nrf54l10-cpuapp";
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model = "Nordic nRF54L15 DK nRF54L10 Application MCU";
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chosen {
19+
zephyr,code-partition = &slot0_ns_partition;
20+
zephyr,sram = &sram0_ns;
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zephyr,entropy = &psa_rng;
22+
};
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/delete-node/ rng;
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psa_rng: psa-rng {
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status = "okay";
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};
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};
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/ {
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/*
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* Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
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* - Lowest 96 kB SRAM allocated to Secure image (sram0_s).
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* - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns).
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*
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* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
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* the FLPR MCU.
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* This static layout needs to be the same with the upstream TF-M layout in the
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* header flash_layout.h of the relevant platform. Any updates in the layout
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* needs to happen both in the flash_layout.h and in this file at the same time.
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*/
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram0_s: image_s@20000000 {
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/* Secure image memory */
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reg = <0x20000000 DT_SIZE_K(72)>;
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};
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sram0_ns: image_ns@20012000 {
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/* Non-Secure image memory */
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reg = <0x20012000 DT_SIZE_K(72)>;
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};
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};
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the
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* last 62kB are reserved for the FLPR MCU.
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*
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* This static layout needs to be the same with the upstream TF-M layout in the
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* header flash_layout.h of the relevant platform. Any updates in the layout
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* needs to happen both in the flash_layout.h and in this file at the same time.
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*/
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slot0_partition: partition@0 {
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label = "image-0";
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reg = <0x0000000 DT_SIZE_K(384)>;
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};
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tfm_ps_partition: partition@60000 {
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label = "tfm-ps";
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reg = <0x00060000 DT_SIZE_K(16)>;
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};
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82+
tfm_its_partition: partition@64000 {
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label = "tfm-its";
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reg = <0x00064000 DT_SIZE_K(16)>;
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};
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tfm_otp_partition: partition@68000 {
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label = "tfm-otp";
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reg = <0x00068000 DT_SIZE_K(8)>;
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};
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slot0_ns_partition: partition@6A000 {
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label = "image-0-nonsecure";
94+
reg = <0x0006A000 DT_SIZE_K(504)>;
95+
};
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storage_partition: partition@E8000 {
98+
label = "storage";
99+
reg = <0x000E8000 DT_SIZE_K(32)>;
100+
};
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};
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};
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&uart30 {
105+
/* Disable so that TF-M can use this UART */
106+
status = "disabled";
107+
};

‎boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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identifier: nrf54l15dk/nrf54l10/cpuapp/ns
5+
name: nRF54l15-DK-nRF54l10-Application-Non-Secure
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type: mcu
7+
arch: arm
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toolchain:
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- gnuarmemb
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- zephyr
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ram: 192
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flash: 1022
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supported:
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- adc
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- gpio
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- i2c
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- spi
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- counter
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- watchdog
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- adc
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- i2s

‎boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns_defconfig

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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4+
CONFIG_ARM_MPU=y
5+
CONFIG_HW_STACK_PROTECTION=y
6+
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
7+
CONFIG_ARM_TRUSTZONE_M=y
8+
9+
# This Board implies building Non-Secure firmware
10+
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
11+
12+
# Don't enable the cache in the non-secure image as it is a
13+
# secure-only peripheral on 54l
14+
CONFIG_CACHE_MANAGEMENT=n
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CONFIG_EXTERNAL_CACHE=n
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17+
CONFIG_UART_CONSOLE=y
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CONFIG_CONSOLE=y
19+
CONFIG_SERIAL=y
20+
CONFIG_GPIO=y
21+
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# Start SYSCOUNTER on driver init
23+
CONFIG_NRF_GRTC_START_SYSCOUNTER=y
24+
25+
# Disable TFM BL2 since it is not supported
26+
CONFIG_TFM_BL2=n
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# Support for silence logging is not supported at the moment
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# Tracked by: NCSDK-31930
30+
CONFIG_TFM_LOG_LEVEL_SILENCE=n
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32+
# The oscillators are configured as secure and cannot be configured
33+
# from the non secure application directly. This needs to be set
34+
# otherwise nrfx will try to configure them, resulting in a bus
35+
# fault.
36+
CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y

‎modules/trusted-firmware-m/Kconfig.tfm

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Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ config TFM_BOARD
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default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf9120" if SOC_NRF9120
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default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP
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default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf54l15_cpuapp" if SOC_NRF54L15_CPUAPP
29+
default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp" if SOC_NRF54L10_CPUAPP
2930
help
3031
The board name used for building TFM. Building with TFM requires that
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TFM has been ported to the given board/SoC.

‎modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/CMakeLists.txt

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#
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# Copyright (c) 2025, Nordic Semiconductor ASA.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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7+
set(NRF_BOARD_SELECTED True)
8+
9+
add_subdirectory(${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/common/nrf54l10 nrf54l10)
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add_subdirectory(.. common)
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install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake
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DESTINATION ${INSTALL_PLATFORM_NS_DIR}
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RENAME cpuarch.cmake)
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install(FILES config.cmake
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DESTINATION ${INSTALL_PLATFORM_NS_DIR})
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install(DIRECTORY ${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests
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DESTINATION ${INSTALL_PLATFORM_NS_DIR}
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)

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