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soc: st: stm32: add stm32n6 series
Add STM32N6 series Signed-off-by: Guillaume Gautier <[email protected]>
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‎soc/st/stm32/soc.yml

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- name: stm32mp1x
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socs:
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- name: stm32mp157cxx
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- name: stm32n6x
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socs:
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- name: stm32n657xx
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- name: stm32u0x
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socs:
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- name: stm32u031xx

‎soc/st/stm32/stm32n6x/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources(
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soc.c
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)
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/st/stm32/stm32n6x/Kconfig

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# ST Microelectronics STM32N6 MCU series
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_STM32N6X
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select ARM
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select CPU_CORTEX_M55
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select ARM_TRUSTZONE_M
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select CPU_CORTEX_M_HAS_DWT
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select HAS_STM32CUBE
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select INIT_ARCH_HW_AT_BOOT
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select SOC_RESET_HOOK
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select TRUSTED_EXECUTION_SECURE

‎soc/st/stm32/stm32n6x/Kconfig.defconfig

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# ST Microelectronics STM32N6 MCU series
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_STM32N6X
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rsource "Kconfig.defconfig.stm32n6*"
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DT_STM32_CPU_CLOCK_PATH := $(dt_nodelabel_path,cpusw)
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DT_STM32_CPU_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_CPU_CLOCK_PATH),clock-frequency)
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# For STM32N6, override the value defined in STM32 Kconfig to use CPU clock frequency
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default "$(DT_STM32_CPU_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,cpusw)"
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endif # SOC_SERIES_STM32N6X

‎soc/st/stm32/stm32n6x/Kconfig.defconfig.stm32n657xx

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# ST Microelectronics STM32N6 MCU series
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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if SOC_STM32N657XX
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config NUM_IRQS
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default 194
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endif # SOC_STM32N657XX

‎soc/st/stm32/stm32n6x/Kconfig.soc

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# ST Microelectronics STM32N6 MCU series
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_STM32N6X
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bool
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select SOC_FAMILY_STM32
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config SOC_SERIES
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default "stm32n6x" if SOC_SERIES_STM32N6X
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config SOC_STM32N657XX
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bool
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select SOC_SERIES_STM32N6X
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config SOC
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default "stm32n657xx" if SOC_STM32N657XX

‎soc/st/stm32/stm32n6x/soc.c

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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32N6 processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/cache.h>
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#include <zephyr/logging/log.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_icache.h>
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#include <cmsis_core.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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extern char _vector_start[];
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void *g_pfnVectors = (void *)_vector_start;
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#if defined(CONFIG_SOC_RESET_HOOK)
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void soc_reset_hook(void)
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{
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/* This is provided by STM32Cube HAL */
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SystemInit();
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}
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#endif
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*
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* @return 0
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*/
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void soc_early_init_hook(void)
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{
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/* Enable caches */
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sys_cache_instr_enable();
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sys_cache_data_enable();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 64 MHz from HSI */
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SystemCoreClock = 64000000;
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/* Enable PWR */
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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/* Enable IOs */
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LL_PWR_EnableVddIO2();
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LL_PWR_EnableVddIO3();
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LL_PWR_EnableVddIO4();
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LL_PWR_EnableVddIO5();
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}

‎soc/st/stm32/stm32n6x/soc.h

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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the STM32N6 family processors.
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*
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*/
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#ifndef _STM32N6_SOC_H_
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#define _STM32N6_SOC_H_
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#ifndef _ASMLANGUAGE
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#include <stm32n6xx.h>
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32N6_SOC_H_ */

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