Skip to content

Commit 02504ea

Browse files
ZhaoQiang-b45475ZhaoQiang-b45475
committed
drivers: adc: add support sar adc driver
Add driver for the SAR ADC Signed-off-by: Qiang Zhao <[email protected]>
1 parent 169b47c commit 02504ea

File tree

5 files changed

+273
-0
lines changed

5 files changed

+273
-0
lines changed

‎drivers/adc/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12 adc_mcux_adc12.c)
1313
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
1414
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR adc_mcux_12b1msps_sar.c)
1515
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_LPADC adc_mcux_lpadc.c)
16+
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_SAR_ADC adc_mcux_sar_adc.c)
1617
zephyr_library_sources_ifdef(CONFIG_ADC_VF610 adc_vf610.c)
1718
zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
1819
zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)

‎drivers/adc/Kconfig.mcux

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,14 @@ config ADC_MCUX_LPADC
3737
help
3838
Enable the MCUX LPADC driver.
3939

40+
config ADC_MCUX_SAR_ADC
41+
bool "MCUX SAR ADC driver"
42+
default y
43+
select ADC_CONFIGURABLE_INPUTS
44+
depends on DT_HAS_NXP_SAR_ADC_ENABLED
45+
help
46+
Enable the MCUX SAR ADC driver.
47+
4048
if ADC_MCUX_12B1MSPS_SAR || ADC_MCUX_LPADC
4149
config ADC_MCUX_ETC
4250
bool "MCUX ADC ETC driver"
@@ -123,3 +131,18 @@ config LPADC_CHANNEL_COUNT
123131

124132

125133
endif # ADC_MCUX_LPADC
134+
135+
if ADC_MCUX_SAR_ADC
136+
137+
config SAR_ADC_CHANNEL_COUNT
138+
int "SAR_ADC channel count"
139+
default 8
140+
range 1 8
141+
help
142+
Amount of hardware command channels to use, reduce to save RAM.
143+
The user can reduce this value if their application uses fewer than
144+
8 ADC channels. This value corresponds to how many of the CMD
145+
registers can be configured within the ADC.
146+
147+
148+
endif # ADC_MCUX_SAR_ADC

‎drivers/adc/adc_mcux_sar_adc.c

Lines changed: 227 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,227 @@
1+
/*
2+
* Copyright 2025 NXP
3+
*
4+
* Based on adc_mcux_sar_adc.c, which is:
5+
* Copyright 2023-2024 NXP
6+
* Copyright (c) 2020 Toby Firth
7+
*
8+
* SPDX-License-Identifier: Apache-2.0
9+
*/
10+
11+
#define DT_DRV_COMPAT nxp_sar_adc
12+
13+
#include <errno.h>
14+
#include <zephyr/drivers/adc.h>
15+
#include <zephyr/sys/util.h>
16+
#include <zephyr/drivers/clock_control.h>
17+
#include <zephyr/drivers/pinctrl.h>
18+
19+
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
20+
#include <zephyr/logging/log.h>
21+
#include <zephyr/irq.h>
22+
#include <fsl_sar_adc.h>
23+
LOG_MODULE_REGISTER(adc_mcux_sar_adc);
24+
25+
#define ADC_CONTEXT_USES_KERNEL_TIMER
26+
#include "adc_context.h"
27+
28+
struct mcux_sar_adc_config {
29+
ADC_Type *base;
30+
void (*irq_config_func)(const struct device *dev);
31+
};
32+
33+
struct mcux_sar_adc_data {
34+
const struct device *dev;
35+
struct adc_context ctx;
36+
uint16_t *buffer;
37+
uint16_t *repeat_buffer;
38+
uint32_t channels;
39+
};
40+
41+
static int mcux_sar_adc_channel_setup(const struct device *dev,
42+
const struct adc_channel_cfg *channel_cfg)
43+
{
44+
/* User may configure maximum number of active channels */
45+
if (channel_cfg->channel_id >= CONFIG_SAR_ADC_CHANNEL_COUNT) {
46+
LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
47+
return -EINVAL;
48+
}
49+
50+
if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
51+
LOG_ERR("Unsupported channel acquisition time");
52+
return -ENOTSUP;
53+
}
54+
55+
if (channel_cfg->gain != ADC_GAIN_1) {
56+
LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
57+
return -ENOTSUP;
58+
}
59+
60+
if (channel_cfg->reference != ADC_REF_INTERNAL) {
61+
LOG_ERR("Unsupported channel reference");
62+
return -ENOTSUP;
63+
}
64+
65+
return 0;
66+
}
67+
68+
static int mcux_sar_adc_start_read(const struct device *dev, const struct adc_sequence *sequence)
69+
{
70+
const struct mcux_sar_adc_config *config = dev->config;
71+
struct mcux_sar_adc_data *data = dev->data;
72+
ADC_Type *base = config->base;
73+
uint8_t channel_id;
74+
75+
if (sequence->resolution != 12) {
76+
LOG_ERR("Unsupported resolution %d", sequence->resolution);
77+
return -ENOTSUP;
78+
}
79+
80+
channel_id = CONFIG_SAR_ADC_CHANNEL_COUNT;
81+
while (channel_id-- > 0) {
82+
if (sequence->channels & BIT(channel_id)) {
83+
ADC_EnableSpecificChannelNormalConv(base, channel_id);
84+
} else {
85+
ADC_DisableSpecificChannelNormalConv(base, channel_id);
86+
}
87+
}
88+
89+
data->buffer = sequence->buffer;
90+
91+
adc_context_start_read(&data->ctx, sequence);
92+
int error = adc_context_wait_for_completion(&data->ctx);
93+
94+
return error;
95+
}
96+
97+
static int mcux_sar_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
98+
struct k_poll_signal *async)
99+
{
100+
struct mcux_sar_adc_data *data = dev->data;
101+
int error;
102+
103+
adc_context_lock(&data->ctx, async ? true : false, async);
104+
error = mcux_sar_adc_start_read(dev, sequence);
105+
adc_context_release(&data->ctx, error);
106+
107+
return error;
108+
}
109+
110+
static int mcux_sar_adc_read(const struct device *dev, const struct adc_sequence *sequence)
111+
{
112+
return mcux_sar_adc_read_async(dev, sequence, NULL);
113+
}
114+
115+
static void adc_context_start_sampling(struct adc_context *ctx)
116+
{
117+
struct mcux_sar_adc_data *data = CONTAINER_OF(ctx, struct mcux_sar_adc_data, ctx);
118+
const struct mcux_sar_adc_config *config = data->dev->config;
119+
ADC_Type *base = config->base;
120+
121+
data->channels = ctx->sequence.channels;
122+
data->repeat_buffer = data->buffer;
123+
124+
ADC_StartConvChain(base, kADC_NormalConvOneShotMode);
125+
}
126+
127+
static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
128+
{
129+
struct mcux_sar_adc_data *data = CONTAINER_OF(ctx, struct mcux_sar_adc_data, ctx);
130+
131+
if (repeat_sampling) {
132+
data->buffer = data->repeat_buffer;
133+
}
134+
}
135+
136+
static void mcux_sar_adc_isr(const struct device *dev)
137+
{
138+
const struct mcux_sar_adc_config *config = dev->config;
139+
struct mcux_sar_adc_data *data = dev->data;
140+
ADC_Type *base = config->base;
141+
adc_conv_result_t conv_result;
142+
uint16_t channel_id;
143+
144+
if (((ADC_GetConvIntStatus(base) & kADC_NormalConvChainEndIntFlag))) {
145+
ADC_ClearConvIntStatus(base, kADC_NormalConvChainEndIntFlag);
146+
}
147+
148+
for (channel_id = 0; channel_id < CONFIG_SAR_ADC_CHANNEL_COUNT; channel_id++) {
149+
if (ADC_GetChannelConvResult(base, &conv_result, channel_id)) {
150+
data->channels &= ~BIT(channel_id);
151+
*(data->buffer++) = conv_result.convData;
152+
if (data->channels == 0) {
153+
adc_context_on_sampling_done(&data->ctx, dev);
154+
}
155+
}
156+
}
157+
}
158+
159+
static int mcux_sar_adc_init(const struct device *dev)
160+
{
161+
const struct mcux_sar_adc_config *config = dev->config;
162+
struct mcux_sar_adc_data *data = dev->data;
163+
ADC_Type *base = config->base;
164+
adc_config_t adc_config;
165+
adc_calibration_config_t calibrationConfig;
166+
167+
ADC_GetDefaultConfig(&adc_config);
168+
ADC_Init(base, &adc_config);
169+
ADC_SetConvMode(base, kADC_NormalConvOneShotMode);
170+
ADC_EnableConvInt(base, (uint32_t)kADC_NormalConvChainEndIntEnable);
171+
172+
/* Do calibration to reduce or eliminate the various error contribution effects. */
173+
calibrationConfig.enableAverage = true;
174+
calibrationConfig.sampleTime = kADC_SampleTime22;
175+
#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG == 1U))
176+
calibrationConfig.averageSampleNumbers = kADC_AverageSampleNumbers32;
177+
#else
178+
calibrationConfig.averageSampleNumbers = kADC_AverageSampleNumbers512;
179+
#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */
180+
181+
if (!(ADC_DoCalibration(base, &calibrationConfig))) {
182+
LOG_WRN("Calibration failed.");
183+
}
184+
185+
config->irq_config_func(dev);
186+
data->dev = dev;
187+
188+
adc_context_unlock_unconditionally(&data->ctx);
189+
190+
return 0;
191+
}
192+
193+
static DEVICE_API(adc, mcux_sar_adc_driver_api) = {
194+
.channel_setup = mcux_sar_adc_channel_setup,
195+
.read = mcux_sar_adc_read,
196+
#ifdef CONFIG_ADC_ASYNC
197+
.read_async = mcux_sar_adc_read_async,
198+
#endif
199+
};
200+
201+
#define SAR_ADC_MCUX_INIT(n) \
202+
\
203+
static void mcux_sar_adc_config_func_##n(const struct device *dev); \
204+
\
205+
static const struct mcux_sar_adc_config mcux_sar_adc_config_##n = { \
206+
.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
207+
.irq_config_func = mcux_sar_adc_config_func_##n, \
208+
}; \
209+
static struct mcux_sar_adc_data mcux_sar_adc_data_##n = { \
210+
ADC_CONTEXT_INIT_TIMER(mcux_sar_adc_data_##n, ctx), \
211+
ADC_CONTEXT_INIT_LOCK(mcux_sar_adc_data_##n, ctx), \
212+
ADC_CONTEXT_INIT_SYNC(mcux_sar_adc_data_##n, ctx), \
213+
}; \
214+
\
215+
DEVICE_DT_INST_DEFINE(n, &mcux_sar_adc_init, NULL, &mcux_sar_adc_data_##n, \
216+
&mcux_sar_adc_config_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
217+
&mcux_sar_adc_driver_api); \
218+
\
219+
static void mcux_sar_adc_config_func_##n(const struct device *dev) \
220+
{ \
221+
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mcux_sar_adc_isr, \
222+
DEVICE_DT_INST_GET(n), 0); \
223+
\
224+
irq_enable(DT_INST_IRQN(n)); \
225+
}
226+
227+
DT_INST_FOREACH_STATUS_OKAY(SAR_ADC_MCUX_INIT)

‎dts/bindings/adc/nxp,sar-adc.yaml

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
# Copyright 2025 NXP
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
description: NXP SAR ADC controller
5+
6+
compatible: "nxp,sar-adc"
7+
8+
include: [adc-controller.yaml]
9+
10+
properties:
11+
reg:
12+
required: true
13+
14+
interrupts:
15+
required: true
16+
17+
"#io-channel-cells":
18+
const: 1
19+
20+
io-channel-cells:
21+
- input

‎modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ endif()
1515
set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 CONFIG_MCUX_COMPONENT_driver.src_2)
1616
set_variable_ifdef(CONFIG_GPIO_MCUX_IGPIO CONFIG_MCUX_COMPONENT_driver.igpio)
1717
set_variable_ifdef(CONFIG_ADC_MCUX_LPADC CONFIG_MCUX_COMPONENT_driver.lpadc)
18+
set_variable_ifdef(CONFIG_ADC_MCUX_SAR_ADC CONFIG_MCUX_COMPONENT_driver.sar_adc)
1819
set_variable_ifdef(CONFIG_COUNTER_MCUX_CTIMER CONFIG_MCUX_COMPONENT_driver.ctimer)
1920
set_variable_ifdef(CONFIG_COUNTER_MCUX_LPC_RTC CONFIG_MCUX_COMPONENT_driver.lpc_rtc)
2021
set_variable_ifdef(CONFIG_GLIKEY_MCUX_GLIKEY CONFIG_MCUX_COMPONENT_driver.glikey)

0 commit comments

Comments
 (0)