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drivers: gpio: Add support for RZ/A3M
Add GPIO driver support for RZ/A3M Signed-off-by: Nhut Nguyen <[email protected]>
1 parent 4eea699 commit 02ed625

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4 files changed

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‎drivers/gpio/gpio_renesas_rz.h

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,8 @@
1414

1515
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \
1616
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \
17-
defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL)
17+
defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL) || \
18+
defined(CONFIG_SOC_SERIES_RZA3M)
1819
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
1920

2021
#if defined(CONFIG_SOC_SERIES_RZG3S)
@@ -39,6 +40,18 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23
3940
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
4041
47, 52, 56, 58, 63, 66, 70, 72, 76};
4142

43+
#elif defined(CONFIG_SOC_SERIES_RZA3M)
44+
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P01)
45+
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM01)
46+
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC01)
47+
#define GPIO_RZ_MAX_PORT_NUM 24
48+
#define GPIO_RZ_TINT_IRQ_OFFSET 476
49+
#define R_INTC R_INTC_IA55
50+
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IA55->TSCR &= ~BIT(tint_num))
51+
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 42,
52+
47, 52, 56, 0, 0, 0, 0, 0, 0, 0,
53+
58, 64, 67, 72};
54+
4255
#elif defined(CONFIG_SOC_SERIES_RZV2H)
4356
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P20)
4457
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM20)

‎dts/arm64/renesas/rz/rza/r9a07g066.dtsi

Lines changed: 256 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,262 @@
5252
compatible = "renesas,rza-pinctrl";
5353
reg = <0x11030000 DT_SIZE_K(64)>;
5454
reg-names = "pinctrl";
55+
56+
gpio: gpio-common {
57+
compatible = "renesas,rz-gpio-int";
58+
interrupts =
59+
<GIC_SPI 444 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
60+
<GIC_SPI 445 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
61+
<GIC_SPI 446 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
62+
<GIC_SPI 447 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
63+
<GIC_SPI 448 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
64+
<GIC_SPI 449 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
65+
<GIC_SPI 450 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
66+
<GIC_SPI 451 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
67+
<GIC_SPI 452 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
68+
<GIC_SPI 453 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
69+
<GIC_SPI 454 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
70+
<GIC_SPI 455 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
71+
<GIC_SPI 456 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
72+
<GIC_SPI 457 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
73+
<GIC_SPI 458 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
74+
<GIC_SPI 459 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
75+
<GIC_SPI 460 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
76+
<GIC_SPI 461 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
77+
<GIC_SPI 462 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
78+
<GIC_SPI 463 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
79+
<GIC_SPI 464 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
80+
<GIC_SPI 465 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
81+
<GIC_SPI 466 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
82+
<GIC_SPI 467 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
83+
<GIC_SPI 468 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
84+
<GIC_SPI 469 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
85+
<GIC_SPI 470 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
86+
<GIC_SPI 471 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
87+
<GIC_SPI 472 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
88+
<GIC_SPI 473 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
89+
<GIC_SPI 474 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
90+
<GIC_SPI 475 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
91+
#address-cells = <1>;
92+
#size-cells = <0>;
93+
status = "disabled";
94+
95+
gpio0: gpio@f00 {
96+
compatible = "renesas,rz-gpio";
97+
gpio-controller;
98+
#gpio-cells = <2>;
99+
ngpios = <4>;
100+
reg = <0xf00>;
101+
status = "disabled";
102+
};
103+
104+
gpio1: gpio@1000 {
105+
compatible = "renesas,rz-gpio";
106+
gpio-controller;
107+
#gpio-cells = <2>;
108+
ngpios = <5>;
109+
reg = <0x1000>;
110+
status = "disabled";
111+
};
112+
113+
gpio2: gpio@1100 {
114+
compatible = "renesas,rz-gpio";
115+
gpio-controller;
116+
#gpio-cells = <2>;
117+
ngpios = <4>;
118+
reg = <0x1100>;
119+
status = "disabled";
120+
};
121+
122+
gpio3: gpio@1200 {
123+
compatible = "renesas,rz-gpio";
124+
gpio-controller;
125+
#gpio-cells = <2>;
126+
ngpios = <4>;
127+
reg = <0x1200>;
128+
status = "disabled";
129+
};
130+
131+
gpio4: gpio@1300 {
132+
compatible = "renesas,rz-gpio";
133+
gpio-controller;
134+
#gpio-cells = <2>;
135+
ngpios = <6>;
136+
reg = <0x1300>;
137+
status = "disabled";
138+
};
139+
140+
gpio5: gpio@1400 {
141+
compatible = "renesas,rz-gpio";
142+
gpio-controller;
143+
#gpio-cells = <2>;
144+
ngpios = <5>;
145+
reg = <0x1400>;
146+
status = "disabled";
147+
};
148+
149+
gpio6: gpio@1500 {
150+
compatible = "renesas,rz-gpio";
151+
gpio-controller;
152+
#gpio-cells = <2>;
153+
ngpios = <5>;
154+
reg = <0x1500>;
155+
status = "disabled";
156+
};
157+
158+
gpio7: gpio@1600 {
159+
compatible = "renesas,rz-gpio";
160+
gpio-controller;
161+
#gpio-cells = <2>;
162+
ngpios = <2>;
163+
reg = <0x1600>;
164+
status = "disabled";
165+
};
166+
167+
gpio8: gpio@1700 {
168+
compatible = "renesas,rz-gpio";
169+
gpio-controller;
170+
#gpio-cells = <2>;
171+
ngpios = <4>;
172+
reg = <0x1700>;
173+
status = "disabled";
174+
};
175+
176+
gpio9: gpio@1800 {
177+
compatible = "renesas,rz-gpio";
178+
gpio-controller;
179+
#gpio-cells = <2>;
180+
ngpios = <5>;
181+
reg = <0x1800>;
182+
status = "disabled";
183+
};
184+
185+
gpio10: gpio@1900 {
186+
compatible = "renesas,rz-gpio";
187+
gpio-controller;
188+
#gpio-cells = <2>;
189+
ngpios = <4>;
190+
reg = <0x1900>;
191+
status = "disabled";
192+
};
193+
194+
gpio11: gpio@1a00 {
195+
compatible = "renesas,rz-gpio";
196+
gpio-controller;
197+
#gpio-cells = <2>;
198+
ngpios = <4>;
199+
reg = <0x1a00>;
200+
status = "disabled";
201+
};
202+
203+
gpio12: gpio@1b00 {
204+
compatible = "renesas,rz-gpio";
205+
gpio-controller;
206+
#gpio-cells = <2>;
207+
ngpios = <2>;
208+
reg = <0x1b00>;
209+
status = "disabled";
210+
};
211+
212+
gpio13: gpio@1c00 {
213+
compatible = "renesas,rz-gpio";
214+
gpio-controller;
215+
#gpio-cells = <2>;
216+
ngpios = <0>;
217+
reg = <0x1c00>;
218+
status = "disabled";
219+
};
220+
221+
gpio14: gpio@1d00 {
222+
compatible = "renesas,rz-gpio";
223+
gpio-controller;
224+
#gpio-cells = <2>;
225+
ngpios = <0>;
226+
reg = <0x1d00>;
227+
status = "disabled";
228+
};
229+
230+
gpio15: gpio@1e00 {
231+
compatible = "renesas,rz-gpio";
232+
gpio-controller;
233+
#gpio-cells = <2>;
234+
ngpios = <0>;
235+
reg = <0x1e00>;
236+
status = "disabled";
237+
};
238+
239+
gpio16: gpio@1f00 {
240+
compatible = "renesas,rz-gpio";
241+
gpio-controller;
242+
#gpio-cells = <2>;
243+
ngpios = <0>;
244+
reg = <0x1f00>;
245+
status = "disabled";
246+
};
247+
248+
gpio17: gpio@2000 {
249+
compatible = "renesas,rz-gpio";
250+
gpio-controller;
251+
#gpio-cells = <2>;
252+
ngpios = <0>;
253+
reg = <0x2000>;
254+
status = "disabled";
255+
};
256+
257+
gpio18: gpio@2100 {
258+
compatible = "renesas,rz-gpio";
259+
gpio-controller;
260+
#gpio-cells = <2>;
261+
ngpios = <0>;
262+
reg = <0x2100>;
263+
status = "disabled";
264+
};
265+
266+
gpio19: gpio@2200 {
267+
compatible = "renesas,rz-gpio";
268+
gpio-controller;
269+
#gpio-cells = <2>;
270+
ngpios = <0>;
271+
reg = <0x2200>;
272+
status = "disabled";
273+
};
274+
275+
gpio20: gpio@0 {
276+
compatible = "renesas,rz-gpio";
277+
gpio-controller;
278+
#gpio-cells = <2>;
279+
ngpios = <6>;
280+
reg = <0x0>;
281+
status = "disabled";
282+
};
283+
284+
gpio21: gpio@100 {
285+
compatible = "renesas,rz-gpio";
286+
gpio-controller;
287+
#gpio-cells = <2>;
288+
ngpios = <3>;
289+
reg = <0x100>;
290+
status = "disabled";
291+
};
292+
293+
gpio22: gpio@300 {
294+
compatible = "renesas,rz-gpio";
295+
gpio-controller;
296+
#gpio-cells = <2>;
297+
ngpios = <5>;
298+
reg = <0x300>;
299+
status = "disabled";
300+
};
301+
302+
gpio23: gpio@400 {
303+
compatible = "renesas,rz-gpio";
304+
gpio-controller;
305+
#gpio-cells = <2>;
306+
ngpios = <2>;
307+
reg = <0x400>;
308+
status = "disabled";
309+
};
310+
};
55311
};
56312

57313
scif0: serial@1004b800 {

‎tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.conf

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
CONFIG_SKIP_PULL_TEST=y

‎tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.overlay

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
/*
2+
* Copyright (c) 2025 Renesas Electronics Corporation
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
/ {
7+
resources {
8+
compatible = "test-gpio-basic-api";
9+
out-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
10+
in-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
11+
};
12+
};
13+
14+
&gpio {
15+
status = "okay";
16+
};
17+
18+
&gpio5 {
19+
status = "okay";
20+
};
21+
22+
&gpio8 {
23+
status = "okay";
24+
};

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