10
10
#include <zephyr/dt-bindings/input/input-event-codes.h>
11
11
12
12
/ {
13
- model = "Witte Technology STM32H753ZI Linum board";
14
13
compatible = "witte,linum";
14
+ model = "Witte Technology STM32H753ZI Linum board";
15
15
16
16
chosen {
17
+ zephyr,canbus = &fdcan1;
18
+ zephyr,code-partition = &slot0_partition;
17
19
zephyr,console = &usart1;
20
+ zephyr,dtcm = &dtcm;
21
+ zephyr,flash = &flash0;
18
22
zephyr,shell-uart = &usart1;
19
23
zephyr,sram = &sram0;
20
- zephyr,flash = &flash0;
21
- zephyr,dtcm = &dtcm;
22
- zephyr,code-partition = &slot0_partition;
23
- zephyr,canbus = &fdcan1;
24
24
};
25
25
26
26
sdram1: sdram@c0000000 {
27
27
compatible = "zephyr,memory-region", "mmio-sram";
28
- device_type = "memory";
29
28
reg = <0xc0000000 DT_SIZE_M(8)>;
30
- zephyr,memory-region = "SDRAM1 ";
29
+ device_type = "memory ";
31
30
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
31
+ zephyr,memory-region = "SDRAM1";
32
32
};
33
33
34
34
leds: leds {
108
108
};
109
109
110
110
&pll {
111
+ clocks = <&clk_hse>;
111
112
div-m = <5>;
112
- mul-n = <192>;
113
113
div-p = <2>;
114
114
div-q = <4>;
115
115
div-r = <4>;
116
- clocks = <&clk_hse >;
116
+ mul-n = <192 >;
117
117
status = "okay";
118
118
};
119
119
120
120
&pll2 {
121
+ clocks = <&clk_hse>;
121
122
div-m = <2>;
122
- mul-n = <48>;
123
123
div-p = <8>;
124
124
div-q = <40>;
125
125
div-r = <3>;
126
- clocks = <&clk_hse >;
126
+ mul-n = <48 >;
127
127
status = "okay";
128
128
};
129
129
130
130
&rcc {
131
- clocks = <&pll>;
132
131
clock-frequency = <DT_FREQ_M(480)>;
132
+ clocks = <&pll>;
133
133
d1cpre = <1>;
134
- hpre = <2>;
135
134
d1ppre = <2>;
136
135
d2ppre1 = <2>;
137
136
d2ppre2 = <2>;
138
137
d3ppre = <2>;
138
+ hpre = <2>;
139
139
};
140
140
141
141
&usart1 {
142
+ current-speed = <115200>;
142
143
pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
143
144
pinctrl-names = "default";
144
- current-speed = <115200>;
145
145
status = "okay";
146
146
};
147
147
148
148
&usart2 {
149
+ current-speed = <115200>;
149
150
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
150
151
pinctrl-names = "default";
151
- current-speed = <115200>;
152
152
status = "okay";
153
153
};
154
154
155
155
&usart3 {
156
+ current-speed = <115200>;
156
157
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
157
158
pinctrl-names = "default";
158
- current-speed = <115200>;
159
159
status = "okay";
160
160
};
161
161
162
162
&uart4 {
163
+ current-speed = <115200>;
163
164
pinctrl-0 = <&uart4_tx_pb9 &uart4_rx_pb8>;
164
165
pinctrl-names = "default";
165
- current-speed = <115200>;
166
166
status = "okay";
167
167
};
168
168
169
169
&usart6 {
170
+ current-speed = <115200>;
170
171
pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
171
172
pinctrl-names = "default";
172
- current-speed = <115200>;
173
173
status = "okay";
174
174
};
175
175
@@ -186,20 +186,20 @@ zephyr_udc0: &usbotg_fs {
186
186
};
187
187
188
188
&i2c3 {
189
+ clock-frequency = <I2C_BITRATE_FAST>;
189
190
pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
190
191
pinctrl-names = "default";
191
192
status = "okay";
192
- clock-frequency = <I2C_BITRATE_FAST>;
193
193
};
194
194
195
195
&timers12 {
196
196
st,prescaler = <10000>;
197
197
status = "okay";
198
198
199
199
pwm12: pwm {
200
- status = "okay";
201
200
pinctrl-0 = <&tim12_ch1_pb14>;
202
201
pinctrl-names = "default";
202
+ status = "okay";
203
203
};
204
204
};
205
205
@@ -232,7 +232,8 @@ zephyr_udc0: &usbotg_fs {
232
232
};
233
233
234
234
&mac {
235
- status = "okay";
235
+ phy-connection-type = "rmii";
236
+ phy-handle = <ð_phy>;
236
237
pinctrl-0 = <ð_rxd0_pc4
237
238
ð_rxd1_pc5
238
239
ð_ref_clk_pa1
@@ -241,14 +242,13 @@ zephyr_udc0: &usbotg_fs {
241
242
ð_txd0_pg13
242
243
ð_txd1_pg14>;
243
244
pinctrl-names = "default";
244
- phy-connection-type = "rmii";
245
- phy-handle = <ð_phy>;
245
+ status = "okay";
246
246
};
247
247
248
248
&mdio {
249
- status = "okay";
250
249
pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
251
250
pinctrl-names = "default";
251
+ status = "okay";
252
252
253
253
eth_phy: ethernet-phy@0 {
254
254
compatible = "microchip,ksz8081";
@@ -258,10 +258,10 @@ zephyr_udc0: &usbotg_fs {
258
258
};
259
259
260
260
&spi1 {
261
- status = "okay" ;
261
+ cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)> ;
262
262
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
263
263
pinctrl-names = "default";
264
- cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)> ;
264
+ status = "okay" ;
265
265
};
266
266
267
267
&fmc {
@@ -280,11 +280,11 @@ zephyr_udc0: &usbotg_fs {
280
280
status = "okay";
281
281
282
282
sdram {
283
- status = "okay";
284
- power-up-delay = <100>;
285
- num-auto-refresh = <8>;
286
283
mode-register = <0x220>;
284
+ num-auto-refresh = <8>;
285
+ power-up-delay = <100>;
287
286
refresh-rate = <0x603>;
287
+ status = "okay";
288
288
289
289
bank@1 {
290
290
reg = <1>;
@@ -302,6 +302,16 @@ zephyr_udc0: &usbotg_fs {
302
302
};
303
303
304
304
<dc {
305
+ clocks = <&rcc STM32_CLOCK(APB3, 3)>,
306
+ <&rcc STM32_SRC_PLL3_R NO_SEL>;
307
+ def-back-color-blue = <0xFF>;
308
+ def-back-color-green = <0xFF>;
309
+ def-back-color-red = <0xFF>;
310
+
311
+ disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
312
+
313
+ ext-sdram = <&sdram1>;
314
+ height = <272>;
305
315
pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_pj2
306
316
<dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6
307
317
<dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10
@@ -310,47 +320,36 @@ zephyr_udc0: &usbotg_fs {
310
320
<dc_b4_pk3 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6
311
321
<dc_de_pk7 <dc_clk_pi14 <dc_hsync_pi10 <dc_vsync_pi9>;
312
322
pinctrl-names = "default";
313
-
314
- disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
315
-
316
- ext-sdram = <&sdram1>;
317
- status = "okay";
318
-
319
- clocks = <&rcc STM32_CLOCK(APB3, 3)>,
320
- <&rcc STM32_SRC_PLL3_R NO_SEL>;
323
+ pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
321
324
322
325
width = <480>;
323
- height = <272>;
324
- pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
326
+ status = "okay";
325
327
326
328
display-timings {
327
329
compatible = "zephyr,panel-timing";
328
330
de-active = <1>;
329
- pixelclk-active = <0>;
331
+ hback-porch = <43>;
332
+ hfront-porch = <8>;
330
333
hsync-active = <0>;
331
- vsync-active = <0>;
332
334
hsync-len = <1>;
333
- vsync-len = <10>;
334
- hback-porch = <43>;
335
+ pixelclk-active = <0>;
335
336
vback-porch = <12>;
336
- hfront-porch = <8>;
337
337
vfront-porch = <4>;
338
+ vsync-active = <0>;
339
+ vsync-len = <10>;
338
340
};
339
- def-back-color-red = <0xFF>;
340
- def-back-color-green = <0xFF>;
341
- def-back-color-blue = <0xFF>;
342
341
};
343
342
344
343
&sdmmc1 {
344
+ cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>;
345
+ disk-name = "SD";
345
346
pinctrl-0 = <&sdmmc1_d0_pc8
346
347
&sdmmc1_d1_pc9
347
348
&sdmmc1_d2_pc10
348
349
&sdmmc1_d3_pc11
349
350
&sdmmc1_ck_pc12
350
351
&sdmmc1_cmd_pd2>;
351
352
pinctrl-names = "default";
352
- cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>;
353
- disk-name = "SD";
354
353
status = "okay";
355
354
356
355
disk {
@@ -366,33 +365,33 @@ zephyr_udc0: &usbotg_fs {
366
365
367
366
/* 128KB for bootloader */
368
367
boot_partition: partition@0 {
369
- label = "mcuboot";
370
368
reg = <0x00000000 DT_SIZE_K(128)>;
369
+ label = "mcuboot";
371
370
read-only;
372
371
};
373
372
374
373
/* storage: 128KB for settings */
375
374
storage_partition: partition@20000 {
376
- label = "storage";
377
375
reg = <0x00020000 DT_SIZE_K(128)>;
376
+ label = "storage";
378
377
};
379
378
380
379
/* application image slot: 256KB */
381
380
slot0_partition: partition@40000 {
382
- label = "image-0";
383
381
reg = <0x00040000 DT_SIZE_K(256)>;
382
+ label = "image-0";
384
383
};
385
384
386
385
/* backup slot: 256KB */
387
386
slot1_partition: partition@80000 {
388
- label = "image-1";
389
387
reg = <0x00080000 DT_SIZE_K(256)>;
388
+ label = "image-1";
390
389
};
391
390
392
391
/* swap slot: 128KB */
393
392
scratch_partition: partition@c0000 {
394
- label = "image-scratch";
395
393
reg = <0x000c0000 DT_SIZE_K(128)>;
394
+ label = "image-scratch";
396
395
};
397
396
};
398
397
};
0 commit comments