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devicetree: format files in boards/witte
Applying dts-linter results for format files in boards/witte Signed-off-by: Kyle Micallef Bonnici <[email protected]>
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boards/witte/linum/linum.dts

Lines changed: 53 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -10,25 +10,25 @@
1010
#include <zephyr/dt-bindings/input/input-event-codes.h>
1111

1212
/ {
13-
model = "Witte Technology STM32H753ZI Linum board";
1413
compatible = "witte,linum";
14+
model = "Witte Technology STM32H753ZI Linum board";
1515

1616
chosen {
17+
zephyr,canbus = &fdcan1;
18+
zephyr,code-partition = &slot0_partition;
1719
zephyr,console = &usart1;
20+
zephyr,dtcm = &dtcm;
21+
zephyr,flash = &flash0;
1822
zephyr,shell-uart = &usart1;
1923
zephyr,sram = &sram0;
20-
zephyr,flash = &flash0;
21-
zephyr,dtcm = &dtcm;
22-
zephyr,code-partition = &slot0_partition;
23-
zephyr,canbus = &fdcan1;
2424
};
2525

2626
sdram1: sdram@c0000000 {
2727
compatible = "zephyr,memory-region", "mmio-sram";
28-
device_type = "memory";
2928
reg = <0xc0000000 DT_SIZE_M(8)>;
30-
zephyr,memory-region = "SDRAM1";
29+
device_type = "memory";
3130
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
31+
zephyr,memory-region = "SDRAM1";
3232
};
3333

3434
leds: leds {
@@ -108,68 +108,68 @@
108108
};
109109

110110
&pll {
111+
clocks = <&clk_hse>;
111112
div-m = <5>;
112-
mul-n = <192>;
113113
div-p = <2>;
114114
div-q = <4>;
115115
div-r = <4>;
116-
clocks = <&clk_hse>;
116+
mul-n = <192>;
117117
status = "okay";
118118
};
119119

120120
&pll2 {
121+
clocks = <&clk_hse>;
121122
div-m = <2>;
122-
mul-n = <48>;
123123
div-p = <8>;
124124
div-q = <40>;
125125
div-r = <3>;
126-
clocks = <&clk_hse>;
126+
mul-n = <48>;
127127
status = "okay";
128128
};
129129

130130
&rcc {
131-
clocks = <&pll>;
132131
clock-frequency = <DT_FREQ_M(480)>;
132+
clocks = <&pll>;
133133
d1cpre = <1>;
134-
hpre = <2>;
135134
d1ppre = <2>;
136135
d2ppre1 = <2>;
137136
d2ppre2 = <2>;
138137
d3ppre = <2>;
138+
hpre = <2>;
139139
};
140140

141141
&usart1 {
142+
current-speed = <115200>;
142143
pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
143144
pinctrl-names = "default";
144-
current-speed = <115200>;
145145
status = "okay";
146146
};
147147

148148
&usart2 {
149+
current-speed = <115200>;
149150
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
150151
pinctrl-names = "default";
151-
current-speed = <115200>;
152152
status = "okay";
153153
};
154154

155155
&usart3 {
156+
current-speed = <115200>;
156157
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
157158
pinctrl-names = "default";
158-
current-speed = <115200>;
159159
status = "okay";
160160
};
161161

162162
&uart4 {
163+
current-speed = <115200>;
163164
pinctrl-0 = <&uart4_tx_pb9 &uart4_rx_pb8>;
164165
pinctrl-names = "default";
165-
current-speed = <115200>;
166166
status = "okay";
167167
};
168168

169169
&usart6 {
170+
current-speed = <115200>;
170171
pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
171172
pinctrl-names = "default";
172-
current-speed = <115200>;
173173
status = "okay";
174174
};
175175

@@ -186,20 +186,20 @@ zephyr_udc0: &usbotg_fs {
186186
};
187187

188188
&i2c3 {
189+
clock-frequency = <I2C_BITRATE_FAST>;
189190
pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
190191
pinctrl-names = "default";
191192
status = "okay";
192-
clock-frequency = <I2C_BITRATE_FAST>;
193193
};
194194

195195
&timers12 {
196196
st,prescaler = <10000>;
197197
status = "okay";
198198

199199
pwm12: pwm {
200-
status = "okay";
201200
pinctrl-0 = <&tim12_ch1_pb14>;
202201
pinctrl-names = "default";
202+
status = "okay";
203203
};
204204
};
205205

@@ -232,7 +232,8 @@ zephyr_udc0: &usbotg_fs {
232232
};
233233

234234
&mac {
235-
status = "okay";
235+
phy-connection-type = "rmii";
236+
phy-handle = <&eth_phy>;
236237
pinctrl-0 = <&eth_rxd0_pc4
237238
&eth_rxd1_pc5
238239
&eth_ref_clk_pa1
@@ -241,14 +242,13 @@ zephyr_udc0: &usbotg_fs {
241242
&eth_txd0_pg13
242243
&eth_txd1_pg14>;
243244
pinctrl-names = "default";
244-
phy-connection-type = "rmii";
245-
phy-handle = <&eth_phy>;
245+
status = "okay";
246246
};
247247

248248
&mdio {
249-
status = "okay";
250249
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
251250
pinctrl-names = "default";
251+
status = "okay";
252252

253253
eth_phy: ethernet-phy@0 {
254254
compatible = "microchip,ksz8081";
@@ -258,10 +258,10 @@ zephyr_udc0: &usbotg_fs {
258258
};
259259

260260
&spi1 {
261-
status = "okay";
261+
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
262262
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
263263
pinctrl-names = "default";
264-
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
264+
status = "okay";
265265
};
266266

267267
&fmc {
@@ -280,11 +280,11 @@ zephyr_udc0: &usbotg_fs {
280280
status = "okay";
281281

282282
sdram {
283-
status = "okay";
284-
power-up-delay = <100>;
285-
num-auto-refresh = <8>;
286283
mode-register = <0x220>;
284+
num-auto-refresh = <8>;
285+
power-up-delay = <100>;
287286
refresh-rate = <0x603>;
287+
status = "okay";
288288

289289
bank@1 {
290290
reg = <1>;
@@ -302,6 +302,16 @@ zephyr_udc0: &usbotg_fs {
302302
};
303303

304304
&ltdc {
305+
clocks = <&rcc STM32_CLOCK(APB3, 3)>,
306+
<&rcc STM32_SRC_PLL3_R NO_SEL>;
307+
def-back-color-blue = <0xFF>;
308+
def-back-color-green = <0xFF>;
309+
def-back-color-red = <0xFF>;
310+
311+
disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
312+
313+
ext-sdram = <&sdram1>;
314+
height = <272>;
305315
pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
306316
&ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
307317
&ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
@@ -310,47 +320,36 @@ zephyr_udc0: &usbotg_fs {
310320
&ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
311321
&ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
312322
pinctrl-names = "default";
313-
314-
disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
315-
316-
ext-sdram = <&sdram1>;
317-
status = "okay";
318-
319-
clocks = <&rcc STM32_CLOCK(APB3, 3)>,
320-
<&rcc STM32_SRC_PLL3_R NO_SEL>;
323+
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
321324

322325
width = <480>;
323-
height = <272>;
324-
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
326+
status = "okay";
325327

326328
display-timings {
327329
compatible = "zephyr,panel-timing";
328330
de-active = <1>;
329-
pixelclk-active = <0>;
331+
hback-porch = <43>;
332+
hfront-porch = <8>;
330333
hsync-active = <0>;
331-
vsync-active = <0>;
332334
hsync-len = <1>;
333-
vsync-len = <10>;
334-
hback-porch = <43>;
335+
pixelclk-active = <0>;
335336
vback-porch = <12>;
336-
hfront-porch = <8>;
337337
vfront-porch = <4>;
338+
vsync-active = <0>;
339+
vsync-len = <10>;
338340
};
339-
def-back-color-red = <0xFF>;
340-
def-back-color-green = <0xFF>;
341-
def-back-color-blue = <0xFF>;
342341
};
343342

344343
&sdmmc1 {
344+
cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>;
345+
disk-name = "SD";
345346
pinctrl-0 = <&sdmmc1_d0_pc8
346347
&sdmmc1_d1_pc9
347348
&sdmmc1_d2_pc10
348349
&sdmmc1_d3_pc11
349350
&sdmmc1_ck_pc12
350351
&sdmmc1_cmd_pd2>;
351352
pinctrl-names = "default";
352-
cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>;
353-
disk-name = "SD";
354353
status = "okay";
355354

356355
disk {
@@ -366,33 +365,33 @@ zephyr_udc0: &usbotg_fs {
366365

367366
/* 128KB for bootloader */
368367
boot_partition: partition@0 {
369-
label = "mcuboot";
370368
reg = <0x00000000 DT_SIZE_K(128)>;
369+
label = "mcuboot";
371370
read-only;
372371
};
373372

374373
/* storage: 128KB for settings */
375374
storage_partition: partition@20000 {
376-
label = "storage";
377375
reg = <0x00020000 DT_SIZE_K(128)>;
376+
label = "storage";
378377
};
379378

380379
/* application image slot: 256KB */
381380
slot0_partition: partition@40000 {
382-
label = "image-0";
383381
reg = <0x00040000 DT_SIZE_K(256)>;
382+
label = "image-0";
384383
};
385384

386385
/* backup slot: 256KB */
387386
slot1_partition: partition@80000 {
388-
label = "image-1";
389387
reg = <0x00080000 DT_SIZE_K(256)>;
388+
label = "image-1";
390389
};
391390

392391
/* swap slot: 128KB */
393392
scratch_partition: partition@c0000 {
394-
label = "image-scratch";
395393
reg = <0x000c0000 DT_SIZE_K(128)>;
394+
label = "image-scratch";
396395
};
397396
};
398397
};

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