|
149 | 149 | status = "okay";
|
150 | 150 | };
|
151 | 151 |
|
| 152 | + counter0: counter@40008200 { |
| 153 | + compatible = "ambiq,counter"; |
| 154 | + reg = <0x40008200 0x20>; |
| 155 | + interrupts = <67 0>; |
| 156 | + clock-frequency = <DT_FREQ_M(6)>; |
| 157 | + clk-source = <1>; |
| 158 | + status = "disabled"; |
| 159 | + }; |
| 160 | + |
| 161 | + counter1: counter@40008220 { |
| 162 | + compatible = "ambiq,counter"; |
| 163 | + reg = <0x40008220 0x20>; |
| 164 | + interrupts = <68 0>; |
| 165 | + clock-frequency = <DT_FREQ_M(6)>; |
| 166 | + clk-source = <1>; |
| 167 | + status = "disabled"; |
| 168 | + }; |
| 169 | + |
| 170 | + counter2: counter@40008240 { |
| 171 | + compatible = "ambiq,counter"; |
| 172 | + reg = <0x40008240 0x20>; |
| 173 | + interrupts = <69 0>; |
| 174 | + clock-frequency = <DT_FREQ_M(6)>; |
| 175 | + clk-source = <1>; |
| 176 | + status = "disabled"; |
| 177 | + }; |
| 178 | + |
| 179 | + counter3: counter@40008260 { |
| 180 | + compatible = "ambiq,counter"; |
| 181 | + reg = <0x40008260 0x20>; |
| 182 | + interrupts = <70 0>; |
| 183 | + clock-frequency = <DT_FREQ_M(6)>; |
| 184 | + clk-source = <1>; |
| 185 | + status = "disabled"; |
| 186 | + }; |
| 187 | + |
| 188 | + counter4: counter@40008280 { |
| 189 | + compatible = "ambiq,counter"; |
| 190 | + reg = <0x40008280 0x20>; |
| 191 | + interrupts = <71 0>; |
| 192 | + clock-frequency = <DT_FREQ_M(6)>; |
| 193 | + clk-source = <1>; |
| 194 | + status = "disabled"; |
| 195 | + }; |
| 196 | + |
| 197 | + counter5: counter@400082a0 { |
| 198 | + compatible = "ambiq,counter"; |
| 199 | + reg = <0x400082a0 0x20>; |
| 200 | + interrupts = <72 0>; |
| 201 | + clock-frequency = <DT_FREQ_M(6)>; |
| 202 | + clk-source = <1>; |
| 203 | + status = "disabled"; |
| 204 | + }; |
| 205 | + |
| 206 | + counter6: counter@400082c0 { |
| 207 | + compatible = "ambiq,counter"; |
| 208 | + reg = <0x400082c0 0x20>; |
| 209 | + interrupts = <73 0>; |
| 210 | + clock-frequency = <DT_FREQ_M(6)>; |
| 211 | + clk-source = <1>; |
| 212 | + status = "disabled"; |
| 213 | + }; |
| 214 | + |
| 215 | + counter7: counter@400082e0 { |
| 216 | + compatible = "ambiq,counter"; |
| 217 | + reg = <0x400082e0 0x20>; |
| 218 | + interrupts = <74 0>; |
| 219 | + clock-frequency = <DT_FREQ_M(6)>; |
| 220 | + clk-source = <1>; |
| 221 | + status = "disabled"; |
| 222 | + }; |
| 223 | + |
| 224 | + counter8: counter@40008300 { |
| 225 | + compatible = "ambiq,counter"; |
| 226 | + reg = <0x40008300 0x20>; |
| 227 | + interrupts = <75 0>; |
| 228 | + clock-frequency = <DT_FREQ_M(6)>; |
| 229 | + clk-source = <1>; |
| 230 | + status = "disabled"; |
| 231 | + }; |
| 232 | + |
| 233 | + counter9: counter@40008320 { |
| 234 | + compatible = "ambiq,counter"; |
| 235 | + reg = <0x40008320 0x20>; |
| 236 | + interrupts = <76 0>; |
| 237 | + clock-frequency = <DT_FREQ_M(6)>; |
| 238 | + clk-source = <1>; |
| 239 | + status = "disabled"; |
| 240 | + }; |
| 241 | + |
| 242 | + counter10: counter@40008340 { |
| 243 | + compatible = "ambiq,counter"; |
| 244 | + reg = <0x40008340 0x20>; |
| 245 | + interrupts = <77 0>; |
| 246 | + clock-frequency = <DT_FREQ_M(6)>; |
| 247 | + clk-source = <1>; |
| 248 | + status = "disabled"; |
| 249 | + }; |
| 250 | + |
| 251 | + counter11: counter@40008360 { |
| 252 | + compatible = "ambiq,counter"; |
| 253 | + reg = <0x40008360 0x20>; |
| 254 | + interrupts = <78 0>; |
| 255 | + clock-frequency = <DT_FREQ_M(6)>; |
| 256 | + clk-source = <1>; |
| 257 | + status = "disabled"; |
| 258 | + }; |
| 259 | + |
| 260 | + counter12: counter@40008380 { |
| 261 | + compatible = "ambiq,counter"; |
| 262 | + reg = <0x40008380 0x20>; |
| 263 | + interrupts = <79 0>; |
| 264 | + clock-frequency = <DT_FREQ_M(6)>; |
| 265 | + clk-source = <1>; |
| 266 | + status = "disabled"; |
| 267 | + }; |
| 268 | + |
| 269 | + counter13: counter@400083a0 { |
| 270 | + compatible = "ambiq,counter"; |
| 271 | + reg = <0x400083a0 0x20>; |
| 272 | + interrupts = <80 0>; |
| 273 | + clock-frequency = <DT_FREQ_M(6)>; |
| 274 | + clk-source = <1>; |
| 275 | + status = "disabled"; |
| 276 | + }; |
| 277 | + |
152 | 278 | rtc0: rtc@RTC_BASE_NAME {
|
153 | 279 | compatible = "ambiq,rtc";
|
154 | 280 | reg = <RTC_REG_BASE RTC_REG_SIZE>;
|
|
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