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drivers: pinctrl: Add pinctrl driver for Renesas RA series
To avoid complicating the initial code for supporting the SoC, I have implemented only the bare minimum for now. Signed-off-by: TOKITA Hiroshi <[email protected]>
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‎drivers/pinctrl/CMakeLists.txt‎

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@@ -35,3 +35,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RA pinctrl_ra.c)

‎drivers/pinctrl/Kconfig‎

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@@ -64,5 +64,6 @@ source "drivers/pinctrl/Kconfig.emsdp"
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source "drivers/pinctrl/Kconfig.ti_cc32xx"
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source "drivers/pinctrl/Kconfig.numaker"
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source "drivers/pinctrl/Kconfig.eos_s3"
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source "drivers/pinctrl/Kconfig.ra"
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endif # PINCTRL

‎drivers/pinctrl/Kconfig.ra‎

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# Copyright (c) 2023 TOKITA Hiroshi <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_RA
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bool "Renesas RA series pin controller driver"
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default y
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depends on DT_HAS_RENESAS_RA_PINCTRL_ENABLED
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help
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Enable Renesas RA series pin controller driver.

‎drivers/pinctrl/pinctrl_ra.c‎

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/*
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* Copyright (c) 2023 TOKITA Hiroshi <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <string.h>
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#define DT_DRV_COMPAT renesas_ra_pinctrl
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#define PORT_NUM 15
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#define PIN_NUM 16
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enum {
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PWPR_PFSWE_POS = 6,
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PWPR_B0WI_POS = 7,
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};
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static inline uint32_t pinctrl_ra_read_PmnFPS(size_t port, size_t pin)
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{
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return sys_read32(DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4);
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}
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static inline void pinctrl_ra_write_PmnFPS(size_t port, size_t pin, uint32_t value)
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{
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sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4);
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}
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static inline uint32_t pinctrl_ra_read_PMISC_PWPR(size_t port, size_t pin)
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{
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return sys_read32(DT_INST_REG_ADDR_BY_NAME(0, pmisc_pwpr));
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}
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static inline void pinctrl_ra_write_PMISC_PWPR(uint32_t value)
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{
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sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, pmisc_pwpr));
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}
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static void pinctrl_ra_configure_pfs(const pinctrl_soc_pin_t *pinc)
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{
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pinctrl_soc_pin_t pincfg;
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memcpy(&pincfg, pinc, sizeof(pinctrl_soc_pin_t));
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pincfg.pin = 0;
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pincfg.port = 0;
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/* Clear PMR bits before configuring */
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if ((pincfg.config & PmnPFS_PMR_POS)) {
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uint32_t val = pinctrl_ra_read_PmnFPS(pinc->port, pinc->pin);
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pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, val & ~(BIT(PmnPFS_PMR_POS)));
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pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config & ~PmnPFS_PMR_POS);
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}
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pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config);
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}
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int pinctrl_ra_query_config(uint32_t port, uint32_t pin, struct pinctrl_ra_pin *const pincfg)
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{
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if (port >= PORT_NUM || pin >= PIN_NUM) {
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return -EINVAL;
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}
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pincfg->config = pinctrl_ra_read_PmnFPS(port, pin);
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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pinctrl_ra_write_PMISC_PWPR(0);
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pinctrl_ra_write_PMISC_PWPR(BIT(PWPR_PFSWE_POS));
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for (int i = 0; i < pin_cnt; i++) {
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pinctrl_ra_configure_pfs(&pins[i]);
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}
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pinctrl_ra_write_PMISC_PWPR(0);
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pinctrl_ra_write_PMISC_PWPR(BIT(PWPR_B0WI_POS));
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return 0;
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}

‎dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi‎

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* SPDX-License-Identifier: Apache-2.0
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*/
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#define RA_SOC_PINS 64
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#define RA_SOC_HAS_MSTPCRE 1
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#define RA_SOC_MSTPD5_CHANNELS 1
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#include <zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h>
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#include <renesas/ra/ra4-cm4-common.dtsi>

‎dts/arm/renesas/ra/ra-cm4-common.dtsi‎

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reg = <0x40100000 DT_SIZE_K(8)>;
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};
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};
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pinctrl: pinctrl@40040800 {
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compatible = "renesas,ra-pinctrl";
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reg = <0x40040800 0x500 0x40040d03 0x1>;
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reg-names = "pfs", "pmisc_pwpr";
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status = "okay";
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};
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};
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};
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‎dts/bindings/pinctrl/renesas,ra-pinctrl.yaml‎

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# Copyright (c) 2023 TOKITA Hiroshi <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Renesas RA series pin controller
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compatible: "renesas,ra-pinctrl"
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include: base.yaml
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child-binding:
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description: |
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Definitions for a pinctrl state.
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child-binding:
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include:
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- name: pincfg-node.yaml
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properties:
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pinmux:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. Each
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element of the array is an integer constructed from the
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pin number and the alternative function of the pin.

‎include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r7fa4m1xxxxxx.h‎

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‎include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h‎

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/*
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* Copyright (c) 2023 TOKITA Hiroshi <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_COMMON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_COMMON_H_
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#define PORT4_POS 29
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#define PORT4_MASK 0x1
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#define PSEL_POS 24
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#define PSEL_MASK 0x5
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#define PORT_POS 21
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#define PORT_MASK 0x3
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#define PIN_POS 17
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#define PIN_MASK 0xF
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#define OPT_POS 0
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#define OPT_MASK 0x1B000
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#define RA_PINCFG_GPIO 0x00000
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#define RA_PINCFG_FUNC 0x10000
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#define RA_PINCFG_ANALOG 0x08000
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#define RA_PINCFG(port, pin, psel, opt) \
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((((psel)&PSEL_MASK) << PSEL_POS) | (((pin)&PIN_MASK) << PIN_POS) | \
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(((port)&PORT_MASK) << PORT_POS) | ((((port) >> 3) & PORT4_MASK) << PORT4_POS) | \
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(((opt)&OPT_MASK) << OPT_POS))
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#if RA_SOC_PINS >= 40
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#define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
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#endif
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#if RA_SOC_PINS >= 48
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#define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
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#endif
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#if RA_SOC_PINS >= 64
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#define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
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#endif
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#if RA_SOC_PINS >= 100
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#define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
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#endif
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#endif

‎soc/arm/renesas_ra/common/pinctrl_ra.h‎

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/*
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* Copyright (c) 2023 TOKITA Hiroshi <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_PINCTRL_SOC_H_
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enum {
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PmnPFS_PODR_POS,
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PmnPFS_PIDR_POS,
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PmnPFS_PDR_POS,
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PmnPFS_RSV3_POS,
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PmnPFS_PCR_POS,
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PmnPFS_RSV5_POS,
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PmnPFS_NCODR_POS,
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PmnPFS_RSV7_POS,
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PmnPFS_RSV8_POS,
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PmnPFS_RSV9_POS,
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PmnPFS_DSCR_POS,
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PmnPFS_DSCR1_POS,
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PmnPFS_EOR_POS,
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PmnPFS_EOF_POS,
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PmnPFS_ISEL_POS,
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PmnPFS_ASEL_POS,
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PmnPFS_PMR_POS,
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};
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struct pinctrl_ra_pin {
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union {
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uint32_t config;
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struct {
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uint8_t PODR: 1;
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uint8_t PIDR: 1;
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uint8_t PDR: 1;
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uint8_t RESERVED3: 1;
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uint8_t PCR: 1;
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uint8_t RESERVED5: 1;
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uint8_t NCODR: 1;
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uint8_t RESERVED7: 1;
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uint8_t RESERVED8: 1;
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uint8_t RESERVED9: 1;
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uint8_t DSCR: 2;
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uint8_t EOFR: 2;
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uint8_t ISEL: 1;
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uint8_t ASEL: 1;
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uint8_t PMR: 1;
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uint8_t RESERVED17: 7;
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uint8_t PSEL: 5;
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uint8_t RESERVED29: 3;
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};
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/* Using RESERVED fields for store pin and port info. */
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struct {
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uint32_t UNUSED0: 17;
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uint8_t pin: 4;
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uint8_t port: 3;
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uint32_t UNUSED24: 5;
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uint8_t port4: 3;
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};
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};
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};
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typedef struct pinctrl_ra_pin pinctrl_soc_pin_t;
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extern int pinctrl_ra_query_config(uint32_t port, uint32_t pin,
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struct pinctrl_ra_pin *const pincfg);
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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{ \
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.config = DT_PROP_BY_IDX(node_id, prop, idx), \
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},
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{ \
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DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT) \
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}
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#endif /* ZEPHYR_SOC_ARM_RENESAS_RA_RA6E1_PINCTRL_SOC_H_ */

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