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lines changed Original file line number Diff line number Diff line change 6
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/* AHB clocks must respect the minimum ratio AHB / DCMI_PIXCLK of 2.5 (AN5020 - Rev 3).
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* The OV2640 PCLK is around 72 MHz for QQVGA resolution (160x120) with MCO1_SEL_HSI48
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- * and MCO1_PRE_DIV_4 .
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+ * and MCO_PRE_DIV_4 .
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*/
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&rcc {
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clocks = <&pll>;
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d3ppre = <2>;
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};
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- /* See reference manual (RM0433 Rev 8) page 390:
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- * 100: HSI48 clock selected (hsi48_ck)
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- */
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- #define MCO1_SEL_HSI48 4
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-
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- /* See reference manual (RM0433 Rev 8) page 391:
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- * 0100: division by 4
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- */
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- #define MCO1_PRE_DIV_4 4
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-
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&mco1 {
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status = "okay";
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clocks = <&rcc STM32_SRC_HSI48 MCO1_SEL(MCO1_SEL_HSI48)>;
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- prescaler = <MCO1_PRE(MCO1_PRE_DIV_4 )>;
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+ prescaler = <MCO1_PRE(MCO_PRE_DIV_4 )>;
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pinctrl-0 = <&rcc_mco_1_pa8>;
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pinctrl-names = "default";
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};
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