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djiatsaf-stnashif
djiatsaf-st
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dts: arm: st: add reset control for display peripheral
add reset control registers information (on RCC_BUS_RSTR LTDCRST bit) for display peripheral reset. Signed-off-by: Fabrice DJIATSA <[email protected]>
1 parent af57912 commit 07cdeba

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11 files changed

+15
-2
lines changed

11 files changed

+15
-2
lines changed

‎dts/arm/st/f4/stm32f429.dtsi‎

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@@ -25,6 +25,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
28+
resets = <&rctl STM32_RESET(APB2, 26U)>;
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status = "disabled";
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};
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‎dts/arm/st/f7/stm32f746.dtsi‎

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@@ -17,6 +17,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_err";
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
20+
resets = <&rctl STM32_RESET(APB2, 26U)>;
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status = "disabled";
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};
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};

‎dts/arm/st/f7/stm32f767.dtsi‎

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@@ -18,6 +18,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_err";
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
21+
resets = <&rctl STM32_RESET(APB2, 26U)>;
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status = "disabled";
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};
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};

‎dts/arm/st/h7/stm32h723.dtsi‎

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@@ -88,6 +88,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
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resets = <&rctl STM32_RESET(APB3, 4U)>;
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status = "disabled";
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};
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‎dts/arm/st/h7/stm32h743.dtsi‎

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@@ -49,6 +49,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
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resets = <&rctl STM32_RESET(APB3, 4U)>;
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status = "disabled";
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};
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‎dts/arm/st/h7/stm32h745.dtsi‎

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@@ -42,6 +42,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
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resets = <&rctl STM32_RESET(APB3, 4U)>;
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status = "disabled";
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};
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‎dts/arm/st/h7/stm32h750.dtsi‎

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@@ -49,6 +49,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
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resets = <&rctl STM32_RESET(APB3, 4U)>;
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status = "disabled";
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};
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‎dts/arm/st/h7/stm32h7a3.dtsi‎

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@@ -52,6 +52,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
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resets = <&rctl STM32_RESET(APB3, 4U)>;
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status = "disabled";
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};
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‎dts/arm/st/l4/stm32l4r9.dtsi‎

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@@ -17,7 +17,8 @@
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reg = <0x40016800 0x200>;
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interrupts = <91 0>, <92 0>;
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interrupt-names = "ltdc", "ltdc_er";
20-
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x40000000>;
20+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
21+
resets = <&rctl STM32_RESET(APB2, 26U)>;
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status = "disabled";
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};
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};

‎dts/arm/st/mp1/stm32mp157.dtsi‎

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@@ -395,6 +395,7 @@
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000001>;
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resets = <&rctl STM32_RESET(APB4, 26U)>;
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status = "disabled";
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};
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};

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