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soc: renesas: ra: Add RA2A1 SoC support
Add Support for Renesas RA2A1 SoC. Signed-off-by: TOKITA Hiroshi <[email protected]>
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‎dts/arm/renesas/ra/ra2/r7fa2a1ab3cfm.dtsi‎

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/*
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra2/r7fa2a1xh.dtsi>
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/ {
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soc {
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flash-controller@407e0000 {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x00000000 DT_SIZE_K(256)>;
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};
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flash1: flash@40100000 {
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compatible = "soc-nv-flash";
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reg = <0x40100000 DT_SIZE_K(8)>;
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi‎

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/*
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra2/ra2xx.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/delete-node/ &sci2;
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/delete-node/ &sci3;
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/delete-node/ &ioport6;
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/delete-node/ &ioport7;
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/delete-node/ &ioport8;
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
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};
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(12)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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sdadcclk: sdadcclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra2/ra2xx.dtsi‎

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/*
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m23";
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reg = <0>;
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};
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};
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soc {
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system: system@4001e000 {
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compatible = "renesas,ra-system";
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reg = <0x4001e000 0x1000>;
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status = "okay";
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};
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ioport0: gpio@40040000 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040000 0x20>;
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port = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport1: gpio@40040020 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040020 0x20>;
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port = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport2: gpio@40040040 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040040 0x20>;
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port = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport3: gpio@40040060 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040060 0x20>;
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port = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport4: gpio@40040080 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040080 0x20>;
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port = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport5: gpio@400400a0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400400a0 0x20>;
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port = <5>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport6: gpio@400400c0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400400c0 0x20>;
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port = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport7: gpio@400400e0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400400e0 0x20>;
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port = <7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport8: gpio@40040100 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040100 0x20>;
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port = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport9: gpio@40040120 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40040120 0x20>;
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port = <9>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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pinctrl: pin-controller@40040800 {
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compatible = "renesas,ra-pinctrl-pfs";
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reg = <0x40040800 0x3c0>;
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status = "okay";
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};
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sci0: sci@40070000 {
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compatible = "renesas,ra-sci";
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interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070000 0x20>;
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clocks = <&pclkb MSTPB 31>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <0>;
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status = "disabled";
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};
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};
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sci1: sci@40070020 {
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compatible = "renesas,ra-sci";
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interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070020 0x20>;
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clocks = <&pclkb MSTPB 30>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <1>;
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status = "disabled";
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};
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};
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sci2: sci@40070040 {
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compatible = "renesas,ra-sci";
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interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070040 0x20>;
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clocks = <&pclkb MSTPB 29>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <2>;
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status = "disabled";
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};
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};
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sci3: sci@40070060 {
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compatible = "renesas,ra-sci";
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interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070060 0x20>;
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clocks = <&pclkb MSTPB 28>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <3>;
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status = "disabled";
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};
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};
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sci9: sci@40070120 {
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compatible = "renesas,ra-sci";
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interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40070120 0x20>;
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clocks = <&pclkb MSTPB 22>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <9>;
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status = "disabled";
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};
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};
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flash-controller@407e0000 {
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reg = <0x407e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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id_code: id_code@1010018 {
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compatible = "zephyr,memory-region";
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reg = <0x01010018 0x20>;
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zephyr,memory-region = "ID_CODE";
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};

‎include/zephyr/dt-bindings/clock/ra_clock.h‎

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#define RA_LCD_CLOCK_DIV_6 3
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#define RA_LCD_CLOCK_DIV_8 4
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/* SDADC clock divider options. */
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#define RA_SDADC_CLOCK_DIV_1 0
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#define RA_SDADC_CLOCK_DIV_2 1
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#define RA_SDADC_CLOCK_DIV_3 2
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#define RA_SDADC_CLOCK_DIV_4 3
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#define RA_SDADC_CLOCK_DIV_5 4
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#define RA_SDADC_CLOCK_DIV_6 5
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#define RA_SDADC_CLOCK_DIV_8 6
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#define RA_SDADC_CLOCK_DIV_12 7
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#define RA_SDADC_CLOCK_DIV_16 8
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#define MSTPA 0x40203000
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#define MSTPB 0x40203004
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#define MSTPC 0x40203008

‎soc/renesas/ra/ra2a1/CMakeLists.txt‎

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# Copyright (c) 2024 TOKITA Hiroshi
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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zephyr_linker_sources(DATA_SECTIONS data_sections.ld)
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zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
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zephyr_linker_sources(ROM_START rom_start.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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