@@ -519,18 +519,43 @@ static int adxl345_init(const struct device *dev)
519519#define ADXL345_CFG_IRQ (inst )
520520#endif /* CONFIG_ADXL345_TRIGGER */
521521
522- #define ADXL345_RTIO_DEFINE (inst ) \
523- SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \
524- SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \
525- SPI_MODE_CPOL | SPI_MODE_CPHA, 0U); \
526- RTIO_DEFINE(adxl345_rtio_ctx_##inst, 64, 64);
522+ #define ADXL345_RTIO_SPI_DEFINE (inst ) \
523+ COND_CODE_1(CONFIG_SPI_RTIO, \
524+ (SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \
525+ SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \
526+ SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \
527+ ())
528+
529+ #define ADXL345_RTIO_I2C_DEFINE (inst ) \
530+ COND_CODE_1(CONFIG_I2C_RTIO, \
531+ (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \
532+ ())
533+
534+ /* Conditionally set the RTIO size based on the presence of SPI/I2C
535+ * lines 541 - 542.
536+ * The sizes of sqe and cqe pools are increased due to the amount of
537+ * multibyte reads needed for watermark using 31 samples
538+ * (adx345_stram - line 203), using smaller amounts of samples
539+ * to trigger an interrupt can decrease the pool sizes.
540+ */
541+ #define ADXL345_RTIO_DEFINE (inst ) \
542+ /* Conditionally include SPI and/or I2C parts based on their presence */ \
543+ COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
544+ (ADXL345_RTIO_SPI_DEFINE(inst)), \
545+ ()) \
546+ COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \
547+ (ADXL345_RTIO_I2C_DEFINE(inst)), \
548+ ()) \
549+ COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, spi_dt_spec) && \
550+ DT_INST_NODE_HAS_PROP(inst, i2c_dt_spec), \
551+ (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 128, 128);), \
552+ (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 64, 64);)) \
527553
528554#define ADXL345_CONFIG (inst ) \
529555 .odr = DT_INST_PROP(inst, odr), \
530556 .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \
531557 .fifo_config.fifo_trigger = ADXL345_INT2, \
532558 .fifo_config.fifo_samples = SAMPLE_NUM, \
533- .op_mode = TRUE, \
534559 .odr = ADXL345_RATE_25HZ, \
535560
536561#define ADXL345_CONFIG_SPI (inst ) \
@@ -543,6 +568,7 @@ static int adxl345_init(const struct device *dev)
543568 0)}, \
544569 .bus_is_ready = adxl345_bus_is_ready_spi, \
545570 .reg_access = adxl345_reg_access_spi, \
571+ .bus_type = ADXL345_BUS_SPI, \
546572 ADXL345_CONFIG(inst) \
547573 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
548574 (ADXL345_CFG_IRQ(inst)), ()) \
@@ -553,13 +579,17 @@ static int adxl345_init(const struct device *dev)
553579 .bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \
554580 .bus_is_ready = adxl345_bus_is_ready_i2c, \
555581 .reg_access = adxl345_reg_access_i2c, \
582+ .bus_type = ADXL345_BUS_I2C, \
583+ ADXL345_CONFIG(inst) \
584+ COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
585+ (ADXL345_CFG_IRQ(inst)), ()) \
556586 }
557587
558588#define ADXL345_DEFINE (inst ) \
559589 IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \
560- static struct adxl345_dev_data adxl345_data_##inst = { \
561- IF_ENABLED(CONFIG_ADXL345_STREAM , (.rtio_ctx = &adxl345_rtio_ctx_##inst, \
562- .iodev = &adxl345_iodev_##inst,)) \
590+ static struct adxl345_dev_data adxl345_data_##inst = { \
591+ COND_CODE_1(adxl345_iodev_##inst , (.rtio_ctx = &adxl345_rtio_ctx_##inst, \
592+ .iodev = &adxl345_iodev_##inst,), () ) \
563593 }; \
564594 static const struct adxl345_dev_config adxl345_config_##inst = \
565595 COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \
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