boards/tests: dma: enable dma for S32Z270

Enable dma boards/test for S32Z270.

The non-cacheable memory used for DMA tests (chan_blen_transfer and
loop_transfer) is split from the system SRAM.

Signed-off-by: Ha Duong Quang <[email protected]>

Author: haduongquang

boards/nxp/s32z2xxdc2/doc/index.rst

@@ -59,6 +59,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | LPI2C     | on-chip    | i2c                                 |
 +-----------+------------+-------------------------------------+
+| EDMA      | on-chip    | dma                                 |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
@@ -163,6 +165,12 @@ ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instan
 .. note::
    All channels of an instance only run on 1 group channel at the same time.
 
+EDMA
+====
+
+The EDMA modules feature four EDMA3 instances: Instance 0 with 32 channels,
+and instances 1, 4, and 5, each with 16 channels.
+
 Programming and Debugging
 *************************
 

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml

@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml

@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml

@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml

@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp

tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.conf

@@ -0,0 +1,4 @@
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=16
+CONFIG_CODE_DATA_RELOCATION=y
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAMNOCACHE"

tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	soc {
+		sram_nocache: memory@31870000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x31870000 DT_SIZE_K(64)>;
+			zephyr,memory-region = "SRAMNOCACHE";
+			zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>;
+		};
+	};
+};
+
+&sram0 {
+	compatible = "mmio-sram";
+	reg = <0x31780000 DT_SIZE_K(960)>;
+};
+
+&edma0 {
+	status = "okay";
+};
+
+tst_dma0: &edma0 { };

tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.conf

@@ -0,0 +1,4 @@
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=15
+CONFIG_CODE_DATA_RELOCATION=y
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAMNOCACHE"

tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	soc {
+		sram_nocache: memory@35870000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x35870000 DT_SIZE_K(64)>;
+			zephyr,memory-region = "SRAMNOCACHE";
+			zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>;
+		};
+	};
+};
+
+&sram1 {
+	compatible = "mmio-sram";
+	reg = <0x35780000 DT_SIZE_K(960)>;
+};
+
+&edma5 {
+	status = "okay";
+};
+
+tst_dma0: &edma5 { };

tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay

@@ -0,0 +1,11 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&edma0 {
+	status = "okay";
+};
+
+dma0: &edma0 { };