dts: arm: nxp_imx93_m33: add ADC node

Add ADC node on imx93 core m33

Signed-off-by: Qiang Zhao <[email protected]>

Author: ZhaoQiang-b45475

boards/nxp/imx93_evk/doc/index.rst

@@ -55,6 +55,11 @@ TPM2 is enabled for PWM for M33 core. Signals can be observerd with
 oscilloscope or logic analyzer.
 Connect J1005-3 and J1005-7(GND) to Oscilloscope or logic analyzer
 
+ADC
+---
+
+sar_adc1 is enabled for M33 core. Pins ADC_IN0/1/2/3 are connected to J1003-1/3/5/7
+
 Devices
 ========
 System Clock

boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -69,6 +69,10 @@
 	pinctrl-names = "default";
 };
 
+&sar_adc1 {
+	status = "okay";
+};
+
 &gpio1 {
 	status = "okay";
 };

boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml

@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: imx93_evk/mimx9352/m33
@@ -14,4 +14,5 @@ supported:
   - gpio
   - uart
   - pwm
+  - adc
 vendor: nxp

dts/arm/nxp/nxp_imx93_m33.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -156,6 +156,15 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		sar_adc1: adc@44530000 {
+			compatible = "nxp,sar-adc";
+			reg = <0x44530000 DT_SIZE_K(64)>;
+			interrupts = <219 0>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+			clocks = <&ccm IMX_CCM_SAR_ADC1_CLK 0x0 0>;
+		};
 	};
 };