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73 | 73 | #define IP1SR5(shift, func) IPnSR(1, 5, shift, func)
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74 | 74 | #define IP2SR5(shift, func) IPnSR(2, 5, shift, func)
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75 | 75 | #define IP3SR5(shift, func) IPnSR(3, 5, shift, func)
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| 76 | +#define IP0SR6(shift, func) IPnSR(0, 6, shift, func) |
| 77 | +#define IP1SR6(shift, func) IPnSR(1, 6, shift, func) |
| 78 | +#define IP2SR6(shift, func) IPnSR(2, 6, shift, func) |
| 79 | +#define IP3SR6(shift, func) IPnSR(3, 6, shift, func) |
| 80 | +#define IP0SR7(shift, func) IPnSR(0, 7, shift, func) |
| 81 | +#define IP1SR7(shift, func) IPnSR(1, 7, shift, func) |
| 82 | +#define IP2SR7(shift, func) IPnSR(2, 7, shift, func) |
| 83 | +#define IP3SR7(shift, func) IPnSR(3, 7, shift, func) |
76 | 84 |
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77 | 85 | #define PIN_VOLTAGE_NONE 0
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78 | 86 | #define PIN_VOLTAGE_1P8V 1
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