soc: st: stm32: h7rsx: Disable core power and VOS config for XiP

Disables setting the SystemCoreClock variable to 64MHz (reset default),
the configuration of the core supply LL_PWR_ConfigSupply(...) and
switch to VOLTAGE_SCALE1 (VOS1) during soc_early_init_hook() when
CONFIG_STM32_APP_IN_EXT_FLASH is set.

Signed-off-by: Thomas Decker <[email protected]>

Author: TD-JBL

soc/st/stm32/stm32h7rsx/soc.c

@@ -31,6 +31,8 @@ void soc_early_init_hook(void)
 	sys_cache_instr_enable();
 	sys_cache_data_enable();
 
+#if !defined(CONFIG_STM32_APP_IN_EXT_FLASH)
+
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 64 MHz from HSI */
 	SystemCoreClock = 64000000;
@@ -59,6 +61,8 @@ void soc_early_init_hook(void)
 	while (LL_PWR_IsActiveFlag_VOSRDY() == 0) {
 	}
 
+#endif /* defined(CONFIG_STM32_APP_IN_EXT_FLASH) */
+
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioo), okay) || DT_NODE_HAS_STATUS(DT_NODELABEL(gpiop), okay)
 	LL_PWR_EnableXSPIM1(); /* Required for powering GPIO O and P */
 #endif /* gpioo || gpio p */