Skip to content

Commit 0ace35c

Browse files
author
Raffael Rostagno
committed
drivers: clock_control: Refactor for ESP32C6
Added support for C6 to allow CPU clock config Signed-off-by: Raffael Rostagno <[email protected]>
1 parent 73c3c1e commit 0ace35c

File tree

7 files changed

+133
-87
lines changed

7 files changed

+133
-87
lines changed

‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,6 @@
3737
};
3838
};
3939

40-
&cpu0 {
41-
clock-frequency = <ESP32_CLK_CPU_160M>;
42-
};
43-
4440
&uart0 {
4541
status = "okay";
4642
current-speed = <115200>;

‎drivers/clock_control/clock_control_esp32.c‎

Lines changed: 94 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,15 @@
3232
#define DT_CPU_COMPAT espressif_riscv
3333
#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
3434
#include <esp32c3/rom/rtc.h>
35+
#elif CONFIG_SOC_SERIES_ESP32C6
36+
#define DT_CPU_COMPAT espressif_riscv
37+
#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
38+
#include <soc/lp_clkrst_reg.h>
39+
#include <soc/regi2c_dig_reg.h>
40+
#include <regi2c_ctrl.h>
41+
#include <esp32c6/rom/rtc.h>
42+
#include <soc/dport_access.h>
43+
#include <hal/clk_tree_ll.h>
3544
#endif /* CONFIG_SOC_SERIES_ESP32xx */
3645

3746
#include <zephyr/drivers/clock_control.h>
@@ -68,6 +77,49 @@ static bool reset_reason_is_cpu_reset(void)
6877
return false;
6978
}
7079

80+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
81+
static void esp32_clock_perip_init(void)
82+
{
83+
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
84+
85+
if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) &&
86+
(rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT)) {
87+
88+
periph_ll_disable_clk_set_rst(PERIPH_UART1_MODULE);
89+
periph_ll_disable_clk_set_rst(PERIPH_I2C0_MODULE);
90+
periph_ll_disable_clk_set_rst(PERIPH_RMT_MODULE);
91+
periph_ll_disable_clk_set_rst(PERIPH_LEDC_MODULE);
92+
periph_ll_disable_clk_set_rst(PERIPH_TIMG1_MODULE);
93+
periph_ll_disable_clk_set_rst(PERIPH_TWAI0_MODULE);
94+
periph_ll_disable_clk_set_rst(PERIPH_TWAI1_MODULE);
95+
periph_ll_disable_clk_set_rst(PERIPH_I2S1_MODULE);
96+
periph_ll_disable_clk_set_rst(PERIPH_PCNT_MODULE);
97+
periph_ll_disable_clk_set_rst(PERIPH_ETM_MODULE);
98+
periph_ll_disable_clk_set_rst(PERIPH_MCPWM0_MODULE);
99+
periph_ll_disable_clk_set_rst(PERIPH_PARLIO_MODULE);
100+
periph_ll_disable_clk_set_rst(PERIPH_GDMA_MODULE);
101+
periph_ll_disable_clk_set_rst(PERIPH_SPI2_MODULE);
102+
periph_ll_disable_clk_set_rst(PERIPH_TEMPSENSOR_MODULE);
103+
periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE);
104+
periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE);
105+
periph_ll_disable_clk_set_rst(PERIPH_SDIO_SLAVE_MODULE);
106+
periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
107+
periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
108+
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
109+
periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
110+
periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
111+
periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
112+
113+
REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
114+
REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
115+
REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN);
116+
REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
117+
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
118+
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
119+
WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
120+
}
121+
}
122+
#else
71123
static void esp32_clock_perip_init(void)
72124
{
73125
uint32_t common_perip_clk;
@@ -330,6 +382,7 @@ static void esp32_clock_perip_init(void)
330382
periph_module_enable(PERIPH_TIMG0_MODULE);
331383
#endif
332384
}
385+
#endif
333386

334387
static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
335388
clock_control_subsys_t sys)
@@ -389,7 +442,11 @@ static int clock_control_esp32_get_rate(const struct device *dev, clock_control_
389442

390443
static int esp32_select_rtc_slow_clk(uint8_t slow_clk)
391444
{
445+
#if !defined(CONFIG_SOC_SERIES_ESP32C6)
392446
soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
447+
#else
448+
soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk;
449+
#endif
393450
uint32_t cal_val = 0;
394451
/* number of times to repeat 32k XTAL calibration
395452
* before giving up and switching to the internal RC
@@ -424,9 +481,15 @@ static int esp32_select_rtc_slow_clk(uint8_t slow_clk)
424481
return -ENODEV;
425482
}
426483
}
484+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
485+
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
486+
rtc_clk_rc32k_enable(true);
487+
}
488+
#else
427489
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
428490
rtc_clk_8m_enable(true, true);
429491
}
492+
#endif
430493
rtc_clk_slow_src_set(rtc_slow_clk_src);
431494

432495
if (CONFIG_RTC_CLK_CAL_CYCLES > 0) {
@@ -458,30 +521,53 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
458521

459522
esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM);
460523

524+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
525+
rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
526+
527+
REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
528+
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
529+
REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, rtc_clk_cfg.rc32k_dfreq);
530+
#else
461531
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
462532
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
533+
#endif
463534

464-
#if !defined(CONFIG_SOC_SERIES_ESP32)
535+
#if defined(CONFIG_SOC_SERIES_ESP32)
536+
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1);
537+
#elif defined(CONFIG_SOC_SERIES_ESP32C6)
538+
clk_ll_rc_fast_tick_conf();
539+
#else
465540
/* Configure 150k clock division */
466541
rtc_clk_divider_set(rtc_clk_cfg.clk_rtc_clk_div);
467542

468543
/* Configure 8M clock division */
469544
rtc_clk_8m_divider_set(rtc_clk_cfg.clk_8m_clk_div);
470-
#else
471-
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1);
472545
#endif
546+
547+
#if !defined(CONFIG_SOC_SERIES_ESP32C6)
473548
/* Reset (disable) i2c internal bus for all regi2c registers */
474549
regi2c_ctrl_ll_i2c_reset();
475550
/* Enable the internal bus used to configure BBPLL */
476551
regi2c_ctrl_ll_i2c_bbpll_enable();
552+
#endif
553+
477554
#if defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32)
478555
regi2c_ctrl_ll_i2c_apll_enable();
479556
#endif
480557

481558
#if !defined(CONFIG_SOC_SERIES_ESP32S2)
482559
rtc_clk_xtal_freq_update(rtc_clk_cfg.xtal_freq);
483560
#endif
561+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
562+
/* On ESP32C6, MSPI source clock's default HS divider leads to 120MHz,
563+
* which is unusable before calibration. Therefore, before switching
564+
* SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider
565+
* to make it run at 80MHz after the switch. PLL = 480MHz, so divider is 6.
566+
*/
567+
clk_ll_mspi_fast_set_hs_divider(6);
568+
#else
484569
rtc_clk_apb_freq_update(rtc_clk_cfg.xtal_freq * MHZ(1));
570+
#endif
485571

486572
/* Set CPU frequency */
487573
rtc_clk_cpu_freq_get_config(&old_config);
@@ -498,6 +584,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
498584
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * rtc_clk_cfg.cpu_freq_mhz /
499585
old_config.freq_mhz);
500586

587+
#if !defined(CONFIG_SOC_SERIES_ESP32C6)
501588
#if ESP_ROM_UART_CLK_IS_XTAL
502589
uart_clock_src_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1);
503590
#else
@@ -507,6 +594,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
507594
#if !defined(ESP_CONSOLE_UART_NONE)
508595
esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, uart_clock_src_hz,
509596
ESP_CONSOLE_UART_BAUDRATE);
597+
#endif
510598
#endif
511599
return 0;
512600
}
@@ -546,10 +634,10 @@ static int clock_control_esp32_configure(const struct device *dev, clock_control
546634
static int clock_control_esp32_init(const struct device *dev)
547635
{
548636
const struct esp32_clock_config *cfg = dev->config;
549-
struct esp32_clock_data *data = dev->data;
637+
bool ret;
638+
#if !defined(CONFIG_SOC_SERIES_ESP32C6)
550639
soc_reset_reason_t rst_reas;
551640
rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT();
552-
bool ret;
553641

554642
rst_reas = esp_rom_get_reset_reason(0);
555643
#if !defined(CONFIG_SOC_SERIES_ESP32)
@@ -562,6 +650,7 @@ static int clock_control_esp32_init(const struct device *dev)
562650
}
563651
#endif
564652
rtc_init(rtc_cfg);
653+
#endif
565654

566655
ret = esp32_cpu_clock_configure(&cfg->cpu);
567656
if (ret) {

‎dts/riscv/espressif/esp32c6/esp32c6_common.dtsi‎

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66
#include <mem.h>
7+
#include <freq.h>
78
#include <zephyr/dt-bindings/gpio/gpio.h>
89
#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
910
#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
@@ -26,6 +27,9 @@
2627
compatible = "espressif,riscv";
2728
riscv,isa = "rv32imc_zicsr";
2829
reg = <0>;
30+
clock-source = <ESP32_CPU_CLK_SRC_PLL>;
31+
clock-frequency = <DT_FREQ_M(160)>;
32+
xtal-freq = <DT_FREQ_M(40)>;
2933
};
3034
};
3135

@@ -65,17 +69,20 @@
6569
rtc: rtc@600b000 {
6670
compatible = "espressif,esp32-rtc";
6771
reg = <0x600B000 DT_SIZE_K(1)>;
68-
xtal-freq = <ESP32_CLK_XTAL_40M>;
72+
fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
73+
slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
6974
#clock-cells = <1>;
7075
status = "okay";
7176

72-
rtc_timer: rtc_timer {
73-
compatible = "espressif,esp32-rtc-timer";
74-
slow-clk-freq = <ESP32_RTC_SLOW_CLK_FREQ_90K>;
75-
interrupts = <LP_RTC_TIMER_INTR_SOURCE>;
76-
interrupt-parent = <&intc>;
77-
status = "okay";
78-
};
77+
};
78+
79+
rtc_timer: rtc_timer@600b0c00 {
80+
compatible = "espressif,esp32-rtc-timer";
81+
reg = <0x600B0C00 DT_SIZE_K(1)>;
82+
clocks = <&rtc ESP32_MODULE_MAX>;
83+
interrupts = <LP_RTC_TIMER_INTR_SOURCE>;
84+
interrupt-parent = <&intc>;
85+
status = "okay";
7986
};
8087

8188
spi2: spi@60081000 {

‎include/zephyr/drivers/clock_control/esp32_clock_control.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
1616
#elif defined(CONFIG_SOC_SERIES_ESP32C3)
1717
#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
18+
#elif defined(CONFIG_SOC_SERIES_ESP32C6)
19+
#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
1820
#endif /* CONFIG_SOC_SERIES_ESP32xx */
1921

2022
#define ESP32_CLOCK_CONTROL_SUBSYS_CPU 50

‎include/zephyr/dt-bindings/clock/esp32c6_clock.h‎

Lines changed: 22 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -7,27 +7,34 @@
77
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
88
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
99

10-
/* System Clock Source */
11-
#define ESP32_CLK_SRC_XTAL 0U
12-
#define ESP32_CLK_SRC_PLL 1U
13-
#define ESP32_CLK_SRC_RC_FAST 2U
10+
/* Supported CPU clock Sources */
11+
#define ESP32_CPU_CLK_SRC_XTAL 0U
12+
#define ESP32_CPU_CLK_SRC_PLL 1U
13+
#define ESP32_CLK_SRC_RC_FAST 2U
1414

15-
/* Supported CPU Frequencies */
16-
#define ESP32_CLK_CPU_80M 80000000
17-
#define ESP32_CLK_CPU_160M 160000000
15+
/* Supported CPU frequencies */
16+
#define ESP32_CLK_CPU_PLL_80M 80000000
17+
#define ESP32_CLK_CPU_PLL_160M 160000000
18+
#define ESP32_CLK_CPU_RC_FAST_FREQ 17500000
1819

1920
/* Supported XTAL Frequencies */
20-
#define ESP32_CLK_XTAL_32M 32
21-
#define ESP32_CLK_XTAL_40M 40
21+
#define ESP32_CLK_XTAL_32M 32000000
22+
#define ESP32_CLK_XTAL_40M 40000000
2223

23-
/* Supported RTC fast clock frequencies */
24-
#define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U
25-
#define ESP32_RTC_FAST_CLK_FREQ_APPROX ESP32_RTC_FAST_CLK_FREQ_8M
24+
/* Supported RTC fast clock sources */
25+
#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0
26+
#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1
2627

2728
/* Supported RTC slow clock frequencies */
28-
#define ESP32_RTC_SLOW_CLK_FREQ_90K 90000U
29-
#define ESP32_RTC_SLOW_CLK_FREQ_8MD256 (ESP32_RTC_FAST_CLK_FREQ_APPROX / 256)
30-
#define ESP32_RTC_SLOW_CLK_FREQ_32K 32768U
29+
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
30+
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
31+
#define ESP32_RTC_SLOW_CLK_SRC_RC32K 2
32+
#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
33+
34+
/* RTC slow clock frequencies */
35+
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
36+
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
37+
#define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ 32768
3138

3239
/* Modules IDs
3340
* These IDs are actually offsets in CLK and RST Control registers.

‎soc/espressif/esp32c6/Kconfig.rtc‎

Lines changed: 0 additions & 50 deletions
This file was deleted.

‎soc/espressif/esp32c6/soc.c‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,11 +56,6 @@ void IRAM_ATTR __esp_platform_start(void)
5656
wdt_hal_disable(&rtc_wdt_ctx);
5757
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
5858

59-
/* Configures the CPU clock, RTC slow and fast clocks, and performs
60-
* RTC slow clock calibration.
61-
*/
62-
esp_clk_init();
63-
6459
esp_timer_early_init();
6560

6661
#if CONFIG_SOC_FLASH_ESP32

0 commit comments

Comments
 (0)