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soc: espressif: esp32c6: Add LP Core
Add ULP Coprocessor support for ESP32C6. Signed-off-by: Lucas Tamborrino <[email protected]>
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14 files changed

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-66
lines changed

14 files changed

+642
-66
lines changed

‎drivers/clock_control/clock_control_esp32.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,8 @@ static void esp32_clock_perip_init(void)
105105
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
106106

107107
if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) &&
108-
(rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT)) {
108+
(rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) &&
109+
(rst_reason != RESET_REASON_CPU0_JTAG)) {
109110

110111
periph_ll_disable_clk_set_rst(PERIPH_UART1_MODULE);
111112
periph_ll_disable_clk_set_rst(PERIPH_I2C0_MODULE);

‎dts/riscv/espressif/esp32c6/esp32c6_common.dtsi

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,9 +76,15 @@
7676
};
7777

7878
sramlp: memory@50000000 {
79+
#address-cells = <1>;
80+
#size-cells = <1>;
7981
compatible = "zephyr,memory-region", "mmio-sram";
8082
reg = <0x50000000 DT_SIZE_K(16)>;
8183
zephyr,memory-region = "SRAMLP ";
84+
85+
shmlp: memory@0 {
86+
reg = <0x0 0x10>;
87+
};
8288
};
8389

8490
intc: interrupt-controller@60010000 {

‎dts/riscv/espressif/esp32c6/esp32c6_lpcore.dtsi

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
/*
2+
* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include <mem.h>
7+
#include <freq.h>
8+
#include <zephyr/dt-bindings/gpio/gpio.h>
9+
#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
10+
#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
11+
#include <dt-bindings/pinctrl/esp32c6-pinctrl.h>
12+
13+
/ {
14+
#address-cells = <1>;
15+
#size-cells = <1>;
16+
17+
cpus {
18+
#address-cells = <1>;
19+
#size-cells = <0>;
20+
21+
cpu0: cpu@0 {
22+
device_type = "cpu";
23+
compatible = "espressif,riscv";
24+
riscv,isa = "rv32imac_zicsr_zifencei";
25+
reg = <0>;
26+
clock-source = <ESP32_RTC_FAST_CLK_SRC_XTAL_D2>;
27+
clock-frequency = <DT_FREQ_M(20)>;
28+
xtal-freq = <DT_FREQ_M(40)>;
29+
};
30+
};
31+
32+
soc {
33+
#address-cells = <1>;
34+
#size-cells = <1>;
35+
compatible = "simple-bus";
36+
ranges;
37+
38+
sramlp: memory@50000000 {
39+
#address-cells = <1>;
40+
#size-cells = <1>;
41+
compatible = "mmio-sram";
42+
reg = <0x50000000 DT_SIZE_K(16)>;
43+
44+
shmlp: memory@0 {
45+
reg = <0x0 0x10>;
46+
};
47+
};
48+
49+
flash: flash-controller@60002000 {
50+
compatible = "espressif,esp32-flash-controller";
51+
reg = <0x60002000 0x1000>;
52+
#address-cells = <1>;
53+
#size-cells = <1>;
54+
55+
flash0: flash@0 {
56+
compatible = "soc-nv-flash";
57+
erase-block-size = <4096>;
58+
write-block-size = <4>;
59+
/* Flash size is specified in SOC/SIP dtsi */
60+
};
61+
};
62+
};
63+
};

‎dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
/*
2+
* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include "esp32c6_lpcore.dtsi"
8+
9+
/* 4MB flash */
10+
&flash0 {
11+
reg = <0x0 DT_SIZE_M(4)>;
12+
};

‎include/zephyr/dt-bindings/clock/esp32c6_clock.h

Lines changed: 54 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -13,28 +13,28 @@
1313
#define ESP32_CLK_SRC_RC_FAST 2U
1414

1515
/* Supported CPU frequencies */
16-
#define ESP32_CLK_CPU_PLL_80M 80000000
17-
#define ESP32_CLK_CPU_PLL_160M 160000000
16+
#define ESP32_CLK_CPU_PLL_80M 80000000
17+
#define ESP32_CLK_CPU_PLL_160M 160000000
1818
#define ESP32_CLK_CPU_RC_FAST_FREQ 17500000
1919

2020
/* Supported XTAL Frequencies */
21-
#define ESP32_CLK_XTAL_32M 32000000
22-
#define ESP32_CLK_XTAL_40M 40000000
21+
#define ESP32_CLK_XTAL_32M 32000000
22+
#define ESP32_CLK_XTAL_40M 40000000
2323

2424
/* Supported RTC fast clock sources */
2525
#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0
2626
#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1
2727

2828
/* Supported RTC slow clock frequencies */
29-
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
30-
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
31-
#define ESP32_RTC_SLOW_CLK_SRC_RC32K 2
32-
#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
29+
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
30+
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
31+
#define ESP32_RTC_SLOW_CLK_SRC_RC32K 2
32+
#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
3333

3434
/* RTC slow clock frequencies */
35-
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
36-
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
37-
#define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ 32768
35+
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
36+
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
37+
#define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ 32768
3838

3939
/* Modules IDs
4040
* These IDs are actually offsets in CLK and RST Control registers.
@@ -44,44 +44,49 @@
4444
* Basic Modules
4545
* Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
4646
*/
47-
#define ESP32_LEDC_MODULE 0
48-
#define ESP32_UART0_MODULE 1
49-
#define ESP32_UART1_MODULE 2
50-
#define ESP32_USB_MODULE 3
51-
#define ESP32_I2C0_MODULE 4
52-
#define ESP32_I2S1_MODULE 5
53-
#define ESP32_TIMG0_MODULE 6
54-
#define ESP32_TIMG1_MODULE 7
55-
#define ESP32_UHCI0_MODULE 8
56-
#define ESP32_RMT_MODULE 9
57-
#define ESP32_PCNT_MODULE 10
58-
#define ESP32_SPI_MODULE 11
59-
#define ESP32_SPI2_MODULE 12
60-
#define ESP32_TWAI0_MODULE 13
61-
#define ESP32_TWAI1_MODULE 14
62-
#define ESP32_RNG_MODULE 15
63-
#define ESP32_RSA_MODULE 16
64-
#define ESP32_AES_MODULE 17
65-
#define ESP32_SHA_MODULE 18
66-
#define ESP32_ECC_MODULE 19
67-
#define ESP32_HMAC_MODULE 20
68-
#define ESP32_DS_MODULE 21
69-
#define ESP32_SDIO_SLAVE_MODULE 22
70-
#define ESP32_GDMA_MODULE 23
71-
#define ESP32_MCPWM0_MODULE 24
72-
#define ESP32_ETM_MODULE 25
73-
#define ESP32_PARLIO_MODULE 26
74-
#define ESP32_SYSTIMER_MODULE 27
75-
#define ESP32_SARADC_MODULE 28
76-
#define ESP32_TEMPSENSOR_MODULE 29
77-
#define ESP32_REGDMA_MODULE 30
78-
#define ESP32_LP_I2C0_MODULE 31
47+
#define ESP32_LEDC_MODULE 0
48+
#define ESP32_UART0_MODULE 1
49+
#define ESP32_UART1_MODULE 2
50+
#define ESP32_USB_MODULE 3
51+
#define ESP32_I2C0_MODULE 4
52+
#define ESP32_I2S1_MODULE 5
53+
#define ESP32_TIMG0_MODULE 6
54+
#define ESP32_TIMG1_MODULE 7
55+
#define ESP32_UHCI0_MODULE 8
56+
#define ESP32_RMT_MODULE 9
57+
#define ESP32_PCNT_MODULE 10
58+
#define ESP32_SPI_MODULE 11
59+
#define ESP32_SPI2_MODULE 12
60+
#define ESP32_TWAI0_MODULE 13
61+
#define ESP32_TWAI1_MODULE 14
62+
#define ESP32_RNG_MODULE 15
63+
#define ESP32_RSA_MODULE 16
64+
#define ESP32_AES_MODULE 17
65+
#define ESP32_SHA_MODULE 18
66+
#define ESP32_ECC_MODULE 19
67+
#define ESP32_HMAC_MODULE 20
68+
#define ESP32_DS_MODULE 21
69+
#define ESP32_SDIO_SLAVE_MODULE 22
70+
#define ESP32_GDMA_MODULE 23
71+
#define ESP32_MCPWM0_MODULE 24
72+
#define ESP32_ETM_MODULE 25
73+
#define ESP32_PARLIO_MODULE 26
74+
#define ESP32_SYSTIMER_MODULE 27
75+
#define ESP32_SARADC_MODULE 28
76+
#define ESP32_TEMPSENSOR_MODULE 29
77+
#define ESP32_ASSIST_DEBUG_MODULE 30
78+
/* LP peripherals */
79+
#define ESP32_LP_I2C0_MODULE 31
80+
#define ESP32_LP_UART0_MODULE 32
7981
/* Peripherals clock managed by the modem_clock driver must be listed last */
80-
#define ESP32_WIFI_MODULE 32
81-
#define ESP32_BT_MODULE 33
82-
#define ESP32_IEEE802154_MODULE 34
83-
#define ESP32_COEX_MODULE 35
84-
#define ESP32_PHY_MODULE 36
85-
#define ESP32_MODULE_MAX 37
82+
#define ESP32_WIFI_MODULE 33
83+
#define ESP32_BT_MODULE 34
84+
#define ESP32_IEEE802154_MODULE 35
85+
#define ESP32_COEX_MODULE 36
86+
#define ESP32_PHY_MODULE 37
87+
#define ESP32_ANA_I2C_MASTER_MODULE 38
88+
#define ESP32_MODEM_ETM_MODULE 39
89+
#define ESP32_MODEM_ADC_COMMON_FE_MODULE 40
90+
#define ESP32_MODULE_MAX 41
8691

8792
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_ */

‎soc/espressif/Kconfig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,4 +62,6 @@ config RTC_CLK_CAL_CYCLES
6262
If the crystal could not start, it will be switched to internal RC.
6363
endmenu
6464

65+
rsource "Kconfig.ulp"
66+
6567
endif # SOC_FAMILY_ESPRESSIF_ESP32

‎soc/espressif/Kconfig.ulp

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
menu "Ultra Low Power (ULP) Coprocessor"
5+
6+
config ULP_COPROC_ENABLED
7+
bool "Ultra Low Power (ULP) Coprocessor"
8+
help
9+
Enable this feature if you plan to use the ULP Coprocessor.
10+
Once this option is enabled, further ULP co-processor configuration will appear in the menu.
11+
12+
choice ULP_COPROC_TYPE
13+
prompt "ULP Coprocessor type"
14+
depends on ULP_COPROC_ENABLED
15+
default ULP_COPROC_TYPE_LP_CORE if SOC_SERIES_ESP32C6
16+
help
17+
Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
18+
19+
config ULP_COPROC_TYPE_FSM
20+
bool "ULP FSM (Finite State Machine)"
21+
depends on SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
22+
23+
config ULP_COPROC_TYPE_RISCV
24+
bool "ULP RISC-V"
25+
depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
26+
27+
config ULP_COPROC_TYPE_LP_CORE
28+
bool "LP core RISC-V"
29+
depends on SOC_SERIES_ESP32C6
30+
endchoice
31+
32+
menu "ULP RISC-V Settings"
33+
depends on ULP_COPROC_TYPE_RISCV
34+
35+
config ULP_RISCV_INTERRUPT_ENABLE
36+
bool "ULP RISC-V interrupts"
37+
help
38+
Turn on this setting to enabled interrupts on the ULP RISC-V core.
39+
40+
endmenu
41+
42+
menu "ULP Debugging Options"
43+
44+
config ULP_PANIC_OUTPUT_ENABLE
45+
bool "Panic handler outputs to LP UART"
46+
depends on ULP_COPROC_TYPE_LP_CORE
47+
help
48+
Set this option to enable panic handler functionality. If this option is
49+
enabled then the LP Core will output a panic dump over LP UART,
50+
similar to what the main core does. Output depends on LP UART already being
51+
initialized and configured.
52+
Disabling this option will reduce the LP core binary size by not
53+
linking in panic handler functionality.
54+
55+
config ULP_HP_UART_CONSOLE_PRINT
56+
bool "Route lp_core_printf to the console HP-UART"
57+
depends on ULP_COPROC_TYPE_LP_CORE
58+
help
59+
Set this option to route lp_core_printf to the console HP-UART.
60+
This allows you to easily view print outputs from the LP core, without
61+
having to connect to the LP-UART. This option comes with the following
62+
limitations:
63+
64+
1. There is no mutual exclusion between the HP-Core and the LP-Core accessing
65+
the HP-UART, which means that if both cores are logging heavily the output
66+
strings might get mangled together.
67+
2. The HP-UART can only work while the HP-Core is running, which means that
68+
if the HP-Core is in deep sleep, the LP-Core will not be able to print to the
69+
console HP-UART.
70+
71+
Due to these limitations it is only recommended to use this option for easy debugging.
72+
For more serious use-cases you should use the LP-UART.
73+
74+
config ULP_NORESET_UNDER_DEBUG
75+
bool "Avoid resetting LP core when debugger is attached"
76+
depends on ULP_COPROC_TYPE_LP_CORE
77+
default y
78+
help
79+
Enable this feature to avoid resetting LP core in sleep mode when debugger is attached,
80+
otherwise configured HW breakpoints and dcsr.ebreak* bits will be missed.
81+
This is a workaround until it will be fixed in HW.
82+
83+
endmenu
84+
85+
endmenu # Ultra Low Power (ULP) Coprocessor

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