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ethernet: stm32: move v2 eth init back
move v2 eth init back into eth_initialize() Signed-off-by: Fin Maaß <[email protected]>
1 parent 92d82c8 commit 0c4e0e1

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+55
-83
lines changed

1 file changed

+55
-83
lines changed

drivers/ethernet/eth_stm32_hal.c

Lines changed: 55 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -814,6 +814,9 @@ static void generate_mac(uint8_t *mac_addr)
814814

815815
#endif /* NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(0))) */
816816
#endif
817+
818+
LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x", mac_addr[0], mac_addr[1], mac_addr[2],
819+
mac_addr[3], mac_addr[4], mac_addr[5]);
817820
}
818821

819822
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
@@ -946,28 +949,70 @@ static int eth_initialize(const struct device *dev)
946949

947950
heth->Init.MACAddr = dev_data->mac_addr;
948951

949-
#if defined(CONFIG_ETH_STM32_HAL_API_V1)
952+
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
953+
HAL_StatusTypeDef hal_ret = HAL_OK;
954+
955+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
956+
for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
957+
heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
958+
heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
959+
}
960+
#else
961+
heth->Init.TxDesc = dma_tx_desc_tab;
962+
heth->Init.RxDesc = dma_rx_desc_tab;
963+
#endif
964+
heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
965+
966+
hal_ret = HAL_ETH_Init(heth);
967+
if (hal_ret != HAL_OK) {
968+
LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
969+
return -EIO;
970+
}
971+
972+
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
973+
/* Enable timestamping of RX packets. We enable all packets to be
974+
* timestamped to cover both IEEE 1588 and gPTP.
975+
*/
976+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
977+
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
978+
#else
979+
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
980+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
981+
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
982+
983+
/* Tx config init: */
984+
memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
985+
tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
986+
ETH_TX_PACKETS_FEATURES_CRCPAD;
987+
tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
988+
ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
989+
tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
990+
991+
/* prepare tx buffer header */
992+
for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
993+
dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
994+
}
995+
996+
/* Initialize semaphores */
997+
k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
998+
#else /* CONFIG_ETH_STM32_HAL_API_V2 */
950999
ret = eth_stm32_init_v1_api(dev);
9511000
if (ret < 0) {
9521001
LOG_ERR("eth_init_v1_api failed: %d", ret);
9531002
return -EIO;
9541003
}
9551004

956-
/* Initialize semaphores */
957-
k_mutex_init(&dev_data->tx_mutex);
958-
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
959-
9601005
HAL_ETH_DMATxDescListInit(heth, dma_tx_desc_tab,
9611006
&dma_tx_buffer[0][0], ETH_TXBUFNB);
9621007
HAL_ETH_DMARxDescListInit(heth, dma_rx_desc_tab,
9631008
&dma_rx_buffer[0][0], ETH_RXBUFNB);
1009+
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
9641010

965-
#endif /* !CONFIG_ETH_STM32_HAL_API_V1 */
1011+
/* Initialize semaphores */
1012+
k_mutex_init(&dev_data->tx_mutex);
1013+
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
9661014

967-
LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x",
968-
dev_data->mac_addr[0], dev_data->mac_addr[1],
969-
dev_data->mac_addr[2], dev_data->mac_addr[3],
970-
dev_data->mac_addr[4], dev_data->mac_addr[5]);
1015+
setup_mac_filter(heth);
9711016

9721017
return 0;
9731018
}
@@ -1020,68 +1065,6 @@ static void eth_stm32_mcast_filter(const struct device *dev, const struct ethern
10201065

10211066
#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */
10221067

1023-
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
1024-
static int eth_init_api_v2(const struct device *dev)
1025-
{
1026-
HAL_StatusTypeDef hal_ret = HAL_OK;
1027-
struct eth_stm32_hal_dev_data *dev_data = dev->data;
1028-
ETH_HandleTypeDef *heth = &dev_data->heth;
1029-
1030-
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
1031-
for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
1032-
heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
1033-
heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
1034-
}
1035-
#else
1036-
heth->Init.TxDesc = dma_tx_desc_tab;
1037-
heth->Init.RxDesc = dma_rx_desc_tab;
1038-
#endif
1039-
heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
1040-
1041-
hal_ret = HAL_ETH_Init(heth);
1042-
if (hal_ret == HAL_TIMEOUT) {
1043-
/* HAL Init time out. This could be linked to */
1044-
/* a recoverable error. Log the issue and continue */
1045-
/* driver initialisation */
1046-
LOG_ERR("HAL_ETH_Init Timed out");
1047-
} else if (hal_ret != HAL_OK) {
1048-
LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
1049-
return -EINVAL;
1050-
}
1051-
1052-
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
1053-
/* Enable timestamping of RX packets. We enable all packets to be
1054-
* timestamped to cover both IEEE 1588 and gPTP.
1055-
*/
1056-
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
1057-
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
1058-
#else
1059-
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
1060-
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
1061-
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
1062-
1063-
/* Initialize semaphores */
1064-
k_mutex_init(&dev_data->tx_mutex);
1065-
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
1066-
k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
1067-
1068-
/* Tx config init: */
1069-
memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
1070-
tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
1071-
ETH_TX_PACKETS_FEATURES_CRCPAD;
1072-
tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
1073-
ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
1074-
tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
1075-
1076-
/* prepare tx buffer header */
1077-
for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
1078-
dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
1079-
}
1080-
1081-
return 0;
1082-
}
1083-
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
1084-
10851068
static void set_mac_config(const struct device *dev, struct phy_link_state *state)
10861069
{
10871070
struct eth_stm32_hal_dev_data *dev_data = dev->data;
@@ -1180,7 +1163,6 @@ static void eth_iface_init(struct net_if *iface)
11801163
{
11811164
const struct device *dev = net_if_get_device(iface);
11821165
struct eth_stm32_hal_dev_data *dev_data = dev->data;
1183-
ETH_HandleTypeDef *heth = &dev_data->heth;
11841166
bool is_first_init = false;
11851167

11861168
if (dev_data->iface == NULL) {
@@ -1199,16 +1181,6 @@ static void eth_iface_init(struct net_if *iface)
11991181

12001182
ethernet_init(iface);
12011183

1202-
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
1203-
/* This function requires the Ethernet interface to be
1204-
* properly initialized. In auto-negotiation mode, it reads the speed
1205-
* and duplex settings to configure the driver accordingly.
1206-
*/
1207-
eth_init_api_v2(dev);
1208-
#endif
1209-
1210-
setup_mac_filter(heth);
1211-
12121184
net_if_carrier_off(iface);
12131185

12141186
net_lldp_set_lldpdu(iface);

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