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gautierg-stkartben
gautierg-st
authored and
kartben
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drivers: i2c: renaming, formatting and clean up
Rename all functions and macros starting by stm32_i2c_* to i2c_stm32_* to harmonize the driver. Reformat some indents for better alignment. Remove i2c_stm32_get_config function declaration from header since it is not used. Signed-off-by: Guillaume Gautier <[email protected]>
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-288
lines changed

4 files changed

+287
-288
lines changed

‎drivers/i2c/i2c_ll_stm32.c‎

Lines changed: 91 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -20,17 +20,17 @@
2020
#include <errno.h>
2121
#include <zephyr/drivers/i2c.h>
2222
#include <zephyr/drivers/pinctrl.h>
23-
#include "i2c_ll_stm32.h"
23+
#include <zephyr/irq.h>
2424

2525
#ifdef CONFIG_I2C_STM32_BUS_RECOVERY
2626
#include "i2c_bitbang.h"
2727
#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
2828

2929
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
3030
#include <zephyr/logging/log.h>
31-
#include <zephyr/irq.h>
3231
LOG_MODULE_REGISTER(i2c_ll_stm32);
3332

33+
#include "i2c_ll_stm32.h"
3434
#include "i2c-priv.h"
3535

3636
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
@@ -42,9 +42,9 @@ LOG_MODULE_REGISTER(i2c_ll_stm32);
4242
/* This symbol takes the value 1 if one of the device instances */
4343
/* is configured in dts with a domain clock */
4444
#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
45-
#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
45+
#define I2C_STM32_DOMAIN_CLOCK_SUPPORT 1
4646
#else
47-
#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
47+
#define I2C_STM32_DOMAIN_CLOCK_SUPPORT 0
4848
#endif
4949

5050
int i2c_stm32_get_config(const struct device *dev, uint32_t *config)
@@ -90,7 +90,7 @@ int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
9090
uint32_t i2c_clock = 0U;
9191
int ret;
9292

93-
if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
93+
if (IS_ENABLED(I2C_STM32_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
9494
if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[1],
9595
&i2c_clock) < 0) {
9696
LOG_ERR("Failed call clock_control_get_rate(pclken[1])");
@@ -120,7 +120,7 @@ int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
120120
#if defined(I2C_CR1_SMBUS) || defined(I2C_CR1_SMBDEN) || defined(I2C_CR1_SMBHEN)
121121
i2c_stm32_set_smbus_mode(dev, data->mode);
122122
#endif
123-
ret = stm32_i2c_configure_timing(dev, i2c_clock);
123+
ret = i2c_stm32_configure_timing(dev, i2c_clock);
124124

125125
if (data->smbalert_active) {
126126
LL_I2C_Enable(i2c);
@@ -210,7 +210,7 @@ static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
210210
next = current + 1;
211211
next_msg_flags = &(next->flags);
212212
}
213-
ret = stm32_i2c_transaction(dev, *current, next_msg_flags, slave);
213+
ret = i2c_stm32_transaction(dev, *current, next_msg_flags, slave);
214214
if (ret < 0) {
215215
break;
216216
}
@@ -411,7 +411,7 @@ static int i2c_stm32_init(const struct device *dev)
411411

412412
i2c_stm32_activate(dev);
413413

414-
if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
414+
if (IS_ENABLED(I2C_STM32_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
415415
/* Enable I2C clock source */
416416
ret = clock_control_configure(clk,
417417
(clock_control_subsys_t) &cfg->pclken[1],
@@ -543,60 +543,60 @@ void i2c_stm32_smbalert_disable(const struct device *dev)
543543
#ifdef CONFIG_I2C_STM32_INTERRUPT
544544

545545
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
546-
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
546+
#define I2C_STM32_IRQ_CONNECT_AND_ENABLE(index) \
547547
do { \
548548
IRQ_CONNECT(DT_INST_IRQN(index), \
549549
DT_INST_IRQ(index, priority), \
550-
stm32_i2c_combined_isr, \
550+
i2c_stm32_combined_isr, \
551551
DEVICE_DT_INST_GET(index), 0); \
552552
irq_enable(DT_INST_IRQN(index)); \
553553
} while (false)
554554
#else
555-
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
555+
#define I2C_STM32_IRQ_CONNECT_AND_ENABLE(index) \
556556
do { \
557557
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
558558
DT_INST_IRQ_BY_NAME(index, event, priority),\
559-
stm32_i2c_event_isr, \
559+
i2c_stm32_event_isr, \
560560
DEVICE_DT_INST_GET(index), 0); \
561561
irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
562562
\
563563
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
564564
DT_INST_IRQ_BY_NAME(index, error, priority),\
565-
stm32_i2c_error_isr, \
565+
i2c_stm32_error_isr, \
566566
DEVICE_DT_INST_GET(index), 0); \
567567
irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
568568
} while (false)
569569
#endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
570570

571-
#define STM32_I2C_IRQ_HANDLER_DECL(index) \
571+
#define I2C_STM32_IRQ_HANDLER_DECL(index) \
572572
static void i2c_stm32_irq_config_func_##index(const struct device *dev)
573-
#define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
573+
#define I2C_STM32_IRQ_HANDLER_FUNCTION(index) \
574574
.irq_config_func = i2c_stm32_irq_config_func_##index,
575-
#define STM32_I2C_IRQ_HANDLER(index) \
575+
#define I2C_STM32_IRQ_HANDLER(index) \
576576
static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
577577
{ \
578-
STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
578+
I2C_STM32_IRQ_CONNECT_AND_ENABLE(index); \
579579
}
580580
#else
581581

582-
#define STM32_I2C_IRQ_HANDLER_DECL(index)
583-
#define STM32_I2C_IRQ_HANDLER_FUNCTION(index)
584-
#define STM32_I2C_IRQ_HANDLER(index)
582+
#define I2C_STM32_IRQ_HANDLER_DECL(index)
583+
#define I2C_STM32_IRQ_HANDLER_FUNCTION(index)
584+
#define I2C_STM32_IRQ_HANDLER(index)
585585

586586
#endif /* CONFIG_I2C_STM32_INTERRUPT */
587587

588588
#ifdef CONFIG_I2C_STM32_V2_DMA
589589

590-
#define I2C_DMA_INIT(index, dir) \
591-
.dir##_dma = { \
592-
.dev_dma = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir),\
593-
(DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)),\
594-
.dma_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir),\
595-
(DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1)),\
590+
#define I2C_DMA_INIT(index, dir) \
591+
.dir##_dma = { \
592+
.dev_dma = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \
593+
(DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \
594+
.dma_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \
595+
(DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1)), \
596596
},
597597

598598
void i2c_stm32_dma_tx_cb(const struct device *dma_dev, void *user_data,
599-
uint32_t channel, int status)
599+
uint32_t channel, int status)
600600
{
601601
ARG_UNUSED(dma_dev);
602602
ARG_UNUSED(user_data);
@@ -609,7 +609,7 @@ void i2c_stm32_dma_tx_cb(const struct device *dma_dev, void *user_data,
609609
}
610610

611611
void i2c_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data,
612-
uint32_t channel, int status)
612+
uint32_t channel, int status)
613613
{
614614
ARG_UNUSED(dma_dev);
615615
ARG_UNUSED(user_data);
@@ -621,23 +621,23 @@ void i2c_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data,
621621
}
622622
}
623623

624-
#define I2C_DMA_DATA_INIT(index, dir, src, dest) \
625-
.dma_##dir##_cfg = { \
626-
.dma_slot = STM32_DMA_SLOT(index, dir, slot), \
627-
.channel_direction = STM32_DMA_CONFIG_DIRECTION( \
628-
STM32_DMA_CHANNEL_CONFIG(index, dir)),\
629-
.cyclic = STM32_DMA_CONFIG_CYCLIC( \
630-
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
631-
.channel_priority = STM32_DMA_CONFIG_PRIORITY( \
632-
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
633-
.source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE( \
634-
STM32_DMA_CHANNEL_CONFIG(index, dir)),\
635-
.dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE( \
636-
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
637-
.source_burst_length = 1, \
638-
.dest_burst_length = 1, \
639-
.dma_callback = i2c_stm32_dma_##dir##_cb, \
640-
}, \
624+
#define I2C_DMA_DATA_INIT(index, dir, src, dest) \
625+
.dma_##dir##_cfg = { \
626+
.dma_slot = STM32_DMA_SLOT(index, dir, slot), \
627+
.channel_direction = STM32_DMA_CONFIG_DIRECTION( \
628+
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
629+
.cyclic = STM32_DMA_CONFIG_CYCLIC( \
630+
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
631+
.channel_priority = STM32_DMA_CONFIG_PRIORITY( \
632+
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
633+
.source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE( \
634+
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
635+
.dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE( \
636+
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
637+
.source_burst_length = 1, \
638+
.dest_burst_length = 1, \
639+
.dma_callback = i2c_stm32_dma_##dir##_cb, \
640+
}, \
641641

642642
#else
643643

@@ -646,49 +646,49 @@ void i2c_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data,
646646

647647
#endif /* CONFIG_I2C_STM32_V2_DMA */
648648

649-
#define STM32_I2C_INIT(index) \
650-
STM32_I2C_IRQ_HANDLER_DECL(index); \
651-
\
652-
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
653-
(static const uint32_t i2c_timings_##index[] = \
654-
DT_INST_PROP_OR(index, timings, {});)) \
655-
\
656-
PINCTRL_DT_INST_DEFINE(index); \
657-
\
658-
static const struct stm32_pclken pclken_##index[] = \
659-
STM32_DT_INST_CLOCKS(index); \
660-
\
661-
static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
662-
.i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
663-
.pclken = pclken_##index, \
664-
.pclk_len = DT_INST_NUM_CLOCKS(index), \
665-
STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
666-
.bitrate = DT_INST_PROP(index, clock_frequency), \
667-
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
668-
IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \
669-
(.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}),\
670-
.sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),))\
671-
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
672-
(.timings = (const struct i2c_config_timing *) i2c_timings_##index,\
673-
.n_timings = ARRAY_SIZE(i2c_timings_##index),)) \
674-
I2C_DMA_INIT(index, tx) \
675-
I2C_DMA_INIT(index, rx) \
676-
}; \
677-
\
678-
static struct i2c_stm32_data i2c_stm32_dev_data_##index = { \
679-
I2C_DMA_DATA_INIT(index, tx, MEMORY, PERIPHERAL) \
680-
I2C_DMA_DATA_INIT(index, rx, PERIPHERAL, MEMORY) \
681-
}; \
682-
\
683-
PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
684-
\
685-
I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
686-
PM_DEVICE_DT_INST_GET(index), \
687-
&i2c_stm32_dev_data_##index, \
688-
&i2c_stm32_cfg_##index, \
689-
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
690-
&api_funcs); \
691-
\
692-
STM32_I2C_IRQ_HANDLER(index)
693-
694-
DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT)
649+
#define I2C_STM32_INIT(index) \
650+
I2C_STM32_IRQ_HANDLER_DECL(index); \
651+
\
652+
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
653+
(static const uint32_t i2c_timings_##index[] = \
654+
DT_INST_PROP_OR(index, timings, {});)) \
655+
\
656+
PINCTRL_DT_INST_DEFINE(index); \
657+
\
658+
static const struct stm32_pclken pclken_##index[] = \
659+
STM32_DT_INST_CLOCKS(index); \
660+
\
661+
static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
662+
.i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
663+
.pclken = pclken_##index, \
664+
.pclk_len = DT_INST_NUM_CLOCKS(index), \
665+
I2C_STM32_IRQ_HANDLER_FUNCTION(index) \
666+
.bitrate = DT_INST_PROP(index, clock_frequency), \
667+
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
668+
IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \
669+
(.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}), \
670+
.sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),)) \
671+
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
672+
(.timings = (const struct i2c_config_timing *) i2c_timings_##index, \
673+
.n_timings = ARRAY_SIZE(i2c_timings_##index),)) \
674+
I2C_DMA_INIT(index, tx) \
675+
I2C_DMA_INIT(index, rx) \
676+
}; \
677+
\
678+
static struct i2c_stm32_data i2c_stm32_dev_data_##index = { \
679+
I2C_DMA_DATA_INIT(index, tx, MEMORY, PERIPHERAL) \
680+
I2C_DMA_DATA_INIT(index, rx, PERIPHERAL, MEMORY) \
681+
}; \
682+
\
683+
PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
684+
\
685+
I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
686+
PM_DEVICE_DT_INST_GET(index), \
687+
&i2c_stm32_dev_data_##index, \
688+
&i2c_stm32_cfg_##index, \
689+
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
690+
&api_funcs); \
691+
\
692+
I2C_STM32_IRQ_HANDLER(index)
693+
694+
DT_INST_FOREACH_STATUS_OKAY(I2C_STM32_INIT)

‎drivers/i2c/i2c_ll_stm32.h‎

Lines changed: 16 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -66,21 +66,21 @@ struct i2c_stm32_config {
6666
struct i2c_stm32_data {
6767
#ifdef CONFIG_I2C_STM32_INTERRUPT
6868
struct k_sem device_sync_sem;
69-
#endif
69+
#endif /* CONFIG_I2C_STM32_INTERRUPT */
7070
struct k_sem bus_mutex;
7171
uint32_t dev_config;
7272
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
7373
/* Store the current timing structure set by runtime config */
7474
struct i2c_config_timing current_timing;
75-
#endif
75+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2) */
7676
#ifdef CONFIG_I2C_STM32_V1
7777
uint16_t slave_address;
78-
#endif
78+
#endif /* CONFIG_I2C_STM32_V1 */
7979
struct {
8080
#ifdef CONFIG_I2C_STM32_V1
8181
unsigned int is_restart;
8282
unsigned int flags;
83-
#endif
83+
#endif /* CONFIG_I2C_STM32_V1 */
8484
unsigned int is_write;
8585
unsigned int is_arlo;
8686
unsigned int is_nack;
@@ -94,39 +94,38 @@ struct i2c_stm32_data {
9494
struct i2c_target_config *slave_cfg;
9595
#ifdef CONFIG_I2C_STM32_V2
9696
struct i2c_target_config *slave2_cfg;
97-
#endif
97+
#endif /* CONFIG_I2C_STM32_V2 */
9898
bool slave_attached;
99-
#endif
99+
#endif /* CONFIG_I2C_TARGET */
100100
bool is_configured;
101101
bool smbalert_active;
102102
enum i2c_stm32_mode mode;
103103
#ifdef CONFIG_SMBUS_STM32_SMBALERT
104104
i2c_stm32_smbalert_cb_func_t smbalert_cb_func;
105105
const struct device *smbalert_cb_dev;
106-
#endif
106+
#endif /* CONFIG_SMBUS_STM32_SMBALERT */
107107
#ifdef CONFIG_I2C_STM32_V2_DMA
108108
struct dma_config dma_tx_cfg;
109109
struct dma_config dma_rx_cfg;
110110
struct dma_block_config dma_blk_cfg;
111111
#endif /* CONFIG_I2C_STM32_V2_DMA */
112112
};
113113

114-
int stm32_i2c_transaction(const struct device *dev,
115-
struct i2c_msg msg, uint8_t *next_msg_flags,
116-
uint16_t periph);
117-
int stm32_i2c_configure_timing(const struct device *dev, uint32_t clk);
114+
int i2c_stm32_transaction(const struct device *dev,
115+
struct i2c_msg msg, uint8_t *next_msg_flags,
116+
uint16_t periph);
117+
int i2c_stm32_configure_timing(const struct device *dev, uint32_t clk);
118118
int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config);
119-
int i2c_stm32_get_config(const struct device *dev, uint32_t *config);
120119

121-
void stm32_i2c_event_isr(void *arg);
122-
void stm32_i2c_error_isr(void *arg);
120+
void i2c_stm32_event_isr(void *arg);
121+
void i2c_stm32_error_isr(void *arg);
123122
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
124-
void stm32_i2c_combined_isr(void *arg);
125-
#endif
123+
void i2c_stm32_combined_isr(void *arg);
124+
#endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
126125

127126
#ifdef CONFIG_I2C_TARGET
128127
int i2c_stm32_target_register(const struct device *dev, struct i2c_target_config *config);
129128
int i2c_stm32_target_unregister(const struct device *dev, struct i2c_target_config *config);
130-
#endif
129+
#endif /* CONFIG_I2C_TARGET */
131130

132131
#endif /* ZEPHYR_DRIVERS_I2C_I2C_LL_STM32_H_ */

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