xen: dom0: update Xen public headers for running Zephyr as Dom0

Xen public headers are added to Zephyr kernel partially, so we need
to update them for new features implementation.

Further implementation of Xen domains configuration and memory
management requires dedicated Xen public headers inside Zephyr kernel.
It will be used for add Zephyr OS Xen Domain-0 funtionalities.

Update existent and add new required public headers from Xen 4.17.0
release.

Signed-off-by: Dmytro Firsov <[email protected]>

Author: firscity

include/zephyr/xen/public/arch-arm.h

@@ -205,15 +205,138 @@ typedef uint64_t xen_pfn_t;
 #define PRI_xen_pfn PRIx64
 #define PRIu_xen_pfn PRIu64
 
-typedef uint64_t xen_ulong_t;
-#define PRI_xen_ulong PRIx64
-
 /*
  * Maximum number of virtual CPUs in legacy multi-processor guests.
  * Only one. All other VCPUS must use VCPUOP_register_vcpu_info.
  */
 #define XEN_LEGACY_MAX_VCPUS 1
 
+typedef uint64_t xen_ulong_t;
+#define PRI_xen_ulong PRIx64
+
+#ifdef CONFIG_XEN_DOM0
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+/* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */
+# define __DECL_REG(n64, n32) union {          \
+	uint64_t n64;                           \
+	uint32_t n32;                           \
+}
+#else
+/* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */
+#define __DECL_REG(n64, n32)   uint64_t n64
+#endif
+
+struct vcpu_guest_core_regs {
+	/*      Aarch64         Aarch32 */
+	__DECL_REG(x0,          r0_usr);
+	__DECL_REG(x1,          r1_usr);
+	__DECL_REG(x2,          r2_usr);
+	__DECL_REG(x3,          r3_usr);
+	__DECL_REG(x4,          r4_usr);
+	__DECL_REG(x5,          r5_usr);
+	__DECL_REG(x6,          r6_usr);
+	__DECL_REG(x7,          r7_usr);
+	__DECL_REG(x8,          r8_usr);
+	__DECL_REG(x9,          r9_usr);
+	__DECL_REG(x10,         r10_usr);
+	__DECL_REG(x11,         r11_usr);
+	__DECL_REG(x12,         r12_usr);
+
+	__DECL_REG(x13,         sp_usr);
+	__DECL_REG(x14,         lr_usr);
+
+	__DECL_REG(x15,         __unused_sp_hyp);
+
+	__DECL_REG(x16,         lr_irq);
+	__DECL_REG(x17,         sp_irq);
+
+	__DECL_REG(x18,         lr_svc);
+	__DECL_REG(x19,         sp_svc);
+
+	__DECL_REG(x20,         lr_abt);
+	__DECL_REG(x21,         sp_abt);
+
+	__DECL_REG(x22,         lr_und);
+	__DECL_REG(x23,         sp_und);
+
+	__DECL_REG(x24,         r8_fiq);
+	__DECL_REG(x25,         r9_fiq);
+	__DECL_REG(x26,         r10_fiq);
+	__DECL_REG(x27,         r11_fiq);
+	__DECL_REG(x28,         r12_fiq);
+
+	__DECL_REG(x29,         sp_fiq);
+	__DECL_REG(x30,         lr_fiq);
+
+	/* Return address and mode */
+	__DECL_REG(pc64,        pc32);  /* ELR_EL2 */
+	uint32_t cpsr;                  /* SPSR_EL2 */
+
+	union {
+		uint32_t spsr_el1;      /* AArch64 */
+		uint32_t spsr_svc;      /* AArch32 */
+	};
+
+	/* AArch32 guests only */
+	uint32_t spsr_fiq, spsr_irq, spsr_und, spsr_abt;
+
+	/* AArch64 guests only */
+	uint64_t sp_el0;
+	uint64_t sp_el1, elr_el1;
+};
+typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t;
+DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t);
+
+#undef __DECL_REG
+
+struct vcpu_guest_context {
+#define _VGCF_online			0
+#define VGCF_online			(1 << _VGCF_online)
+	uint32_t flags; /* VGCF_* */
+
+	struct vcpu_guest_core_regs user_regs; /* Core CPU registers */
+
+	uint64_t sctlr;
+	uint64_t ttbcr, ttbr0, ttbr1;
+};
+typedef struct vcpu_guest_context vcpu_guest_context_t;
+DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
+
+/*
+ * struct xen_arch_domainconfig's ABI is covered by
+ * XEN_DOMCTL_INTERFACE_VERSION.
+ */
+#define XEN_DOMCTL_CONFIG_GIC_NATIVE	0
+#define XEN_DOMCTL_CONFIG_GIC_V2	1
+#define XEN_DOMCTL_CONFIG_GIC_V3	2
+
+#define XEN_DOMCTL_CONFIG_TEE_NONE	0
+#define XEN_DOMCTL_CONFIG_TEE_OPTEE	1
+
+struct xen_arch_domainconfig {
+	/* IN/OUT */
+	uint8_t gic_version;
+	/* IN */
+	uint16_t tee_type;
+	/* IN */
+	uint32_t nr_spis;
+	/*
+	 * OUT
+	 * Based on the property clock-frequency in the DT timer node.
+	 * The property may be present when the bootloader/firmware doesn't
+	 * set correctly CNTFRQ which hold the timer frequency.
+	 *
+	 * As it's not possible to trap this register, we have to replicate
+	 * the value in the guest DT.
+	 *
+	 * = 0 => property not present
+	 * > 0 => Value of the property
+	 *
+	 */
+	uint32_t clock_frequency;
+};
+#endif /* CONFIG_XEN_DOM0 */
+
 struct arch_vcpu_info {
 };
 typedef struct arch_vcpu_info arch_vcpu_info_t;
@@ -225,4 +348,129 @@ typedef uint64_t xen_callback_t;
 
 #endif /* __ASSEMBLY__ */
 
+#ifdef CONFIG_XEN_DOM0
+
+/* PSR bits (CPSR, SPSR) */
+#define PSR_THUMB			(1 << 5) /* Thumb Mode enable */
+#define PSR_FIQ_MASK			(1 << 6) /* Fast Interrupt mask */
+#define PSR_IRQ_MASK			(1 << 7) /* Interrupt mask */
+#define PSR_ABT_MASK			(1 << 8) /* Asynchronous Abort mask */
+#define PSR_BIG_ENDIAN			(1 << 9) /* arm32: Big Endian Mode */
+#define PSR_DBG_MASK			(1 << 9) /* arm64: Debug Exception mask */
+#define PSR_IT_MASK			(0x0600fc00) /* Thumb If-Then Mask */
+#define PSR_JAZELLE			(1<<24) /* Jazelle Mode */
+
+/* 32 bit modes */
+#define PSR_MODE_USR			0x10
+#define PSR_MODE_FIQ			0x11
+#define PSR_MODE_IRQ			0x12
+#define PSR_MODE_SVC			0x13
+#define PSR_MODE_MON			0x16
+#define PSR_MODE_ABT			0x17
+#define PSR_MODE_HYP			0x1a
+#define PSR_MODE_UND			0x1b
+#define PSR_MODE_SYS			0x1f
+
+/* 64 bit modes */
+#define PSR_MODE_BIT			0x10 /* Set iff AArch32 */
+#define PSR_MODE_EL3h			0x0d
+#define PSR_MODE_EL3t			0x0c
+#define PSR_MODE_EL2h			0x09
+#define PSR_MODE_EL2t			0x08
+#define PSR_MODE_EL1h			0x05
+#define PSR_MODE_EL1t			0x04
+#define PSR_MODE_EL0t			0x00
+
+#define PSR_GUEST32_INIT		(PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
+#define PSR_GUEST64_INIT		(PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
+
+#define SCTLR_GUEST_INIT		xen_mk_ullong(0x00c50078)
+
+/*
+ * Virtual machine platform (memory layout, interrupts)
+ *
+ * These are defined for consistency between the tools and the
+ * hypervisor. Guests must not rely on these hardcoded values but
+ * should instead use the FDT.
+ */
+
+/* Physical Address Space */
+
+/*
+ * vGIC mappings: Only one set of mapping is used by the guest.
+ * Therefore they can overlap.
+ */
+
+/* vGIC v2 mappings */
+#define GUEST_GICD_BASE			xen_mk_ullong(0x03001000)
+#define GUEST_GICD_SIZE			xen_mk_ullong(0x00001000)
+#define GUEST_GICC_BASE			xen_mk_ullong(0x03002000)
+#define GUEST_GICC_SIZE			xen_mk_ullong(0x00002000)
+
+/* vGIC v3 mappings */
+#define GUEST_GICV3_GICD_BASE		xen_mk_ullong(0x03001000)
+#define GUEST_GICV3_GICD_SIZE		xen_mk_ullong(0x00010000)
+
+#define GUEST_GICV3_RDIST_REGIONS	1
+
+#define GUEST_GICV3_GICR0_BASE		xen_mk_ullong(0x03020000) /* vCPU0..127 */
+#define GUEST_GICV3_GICR0_SIZE		xen_mk_ullong(0x01000000)
+
+/* ACPI tables physical address */
+#define GUEST_ACPI_BASE			xen_mk_ullong(0x20000000)
+#define GUEST_ACPI_SIZE			xen_mk_ullong(0x02000000)
+
+/* PL011 mappings */
+#define GUEST_PL011_BASE		xen_mk_ullong(0x22000000)
+#define GUEST_PL011_SIZE		xen_mk_ullong(0x00001000)
+
+/*
+ * 16MB == 4096 pages reserved for guest to use as a region to map its
+ * grant table in.
+ */
+#define GUEST_GNTTAB_BASE		xen_mk_ullong(0x38000000)
+#define GUEST_GNTTAB_SIZE		xen_mk_ullong(0x01000000)
+
+#define GUEST_MAGIC_BASE		xen_mk_ullong(0x39000000)
+#define GUEST_MAGIC_SIZE		xen_mk_ullong(0x01000000)
+
+#define GUEST_RAM_BANKS			2
+
+#define GUEST_RAM0_BASE			xen_mk_ullong(0x40000000) /* 3GB of low RAM @ 1GB */
+#define GUEST_RAM0_SIZE			xen_mk_ullong(0xc0000000)
+
+#define GUEST_RAM1_BASE			xen_mk_ullong(0x0200000000) /* 1016GB of RAM @ 8GB */
+#define GUEST_RAM1_SIZE			xen_mk_ullong(0xfe00000000)
+
+#define GUEST_RAM_BASE			GUEST_RAM0_BASE /* Lowest RAM address */
+/* Largest amount of actual RAM, not including holes */
+#define GUEST_RAM_MAX			(GUEST_RAM0_SIZE + GUEST_RAM1_SIZE)
+/* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */
+#define GUEST_RAM_BANK_BASES		{ GUEST_RAM0_BASE, GUEST_RAM1_BASE }
+#define GUEST_RAM_BANK_SIZES		{ GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }
+
+/* Current supported guest VCPUs */
+#define GUEST_MAX_VCPUS 128
+
+/* Interrupts */
+#define GUEST_TIMER_VIRT_PPI		27
+#define GUEST_TIMER_PHYS_S_PPI		29
+#define GUEST_TIMER_PHYS_NS_PPI		30
+#define GUEST_EVTCHN_PPI		31
+
+#define GUEST_VPL011_SPI		32
+
+/* PSCI functions */
+#define PSCI_cpu_suspend		0
+#define PSCI_cpu_off			1
+#define PSCI_cpu_on			2
+#define PSCI_migrate			3
+
+#endif /* CONFIG_XEN_DOM0 */
+
+#ifndef __ASSEMBLY__
+/* Stub definition of PMU structure */
+typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t;
+#endif /* __ASSEMBLY__ */
+
 #endif /* __XEN_PUBLIC_ARCH_ARM_H__ */