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ethernet: stm32: move v2 eth init back
move v2 eth init back into eth_initialize() Signed-off-by: Fin Maaß <[email protected]>
1 parent 7a6081c commit 0cc6663

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+55
-83
lines changed

1 file changed

+55
-83
lines changed

drivers/ethernet/eth_stm32_hal.c

Lines changed: 55 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -814,6 +814,9 @@ static void generate_mac(uint8_t *mac_addr)
814814

815815
#endif /* NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(0))) */
816816
#endif
817+
818+
LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x", mac_addr[0], mac_addr[1], mac_addr[2],
819+
mac_addr[3], mac_addr[4], mac_addr[5]);
817820
}
818821

819822
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
@@ -945,28 +948,70 @@ static int eth_initialize(const struct device *dev)
945948

946949
heth->Init.MACAddr = dev_data->mac_addr;
947950

948-
#if defined(CONFIG_ETH_STM32_HAL_API_V1)
951+
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
952+
HAL_StatusTypeDef hal_ret = HAL_OK;
953+
954+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
955+
for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
956+
heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
957+
heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
958+
}
959+
#else
960+
heth->Init.TxDesc = dma_tx_desc_tab;
961+
heth->Init.RxDesc = dma_rx_desc_tab;
962+
#endif
963+
heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
964+
965+
hal_ret = HAL_ETH_Init(heth);
966+
if (hal_ret != HAL_OK) {
967+
LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
968+
return -EIO;
969+
}
970+
971+
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
972+
/* Enable timestamping of RX packets. We enable all packets to be
973+
* timestamped to cover both IEEE 1588 and gPTP.
974+
*/
975+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
976+
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
977+
#else
978+
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
979+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
980+
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
981+
982+
/* Tx config init: */
983+
memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
984+
tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
985+
ETH_TX_PACKETS_FEATURES_CRCPAD;
986+
tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
987+
ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
988+
tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
989+
990+
/* prepare tx buffer header */
991+
for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
992+
dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
993+
}
994+
995+
/* Initialize semaphores */
996+
k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
997+
#else /* CONFIG_ETH_STM32_HAL_API_V2 */
949998
ret = eth_stm32_init_v1_api(dev);
950999
if (ret < 0) {
9511000
LOG_ERR("eth_init_v1_api failed: %d", ret);
9521001
return -EIO;
9531002
}
9541003

955-
/* Initialize semaphores */
956-
k_mutex_init(&dev_data->tx_mutex);
957-
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
958-
9591004
HAL_ETH_DMATxDescListInit(heth, dma_tx_desc_tab,
9601005
&dma_tx_buffer[0][0], ETH_TXBUFNB);
9611006
HAL_ETH_DMARxDescListInit(heth, dma_rx_desc_tab,
9621007
&dma_rx_buffer[0][0], ETH_RXBUFNB);
1008+
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
9631009

964-
#endif /* !CONFIG_ETH_STM32_HAL_API_V1 */
1010+
/* Initialize semaphores */
1011+
k_mutex_init(&dev_data->tx_mutex);
1012+
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
9651013

966-
LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x",
967-
dev_data->mac_addr[0], dev_data->mac_addr[1],
968-
dev_data->mac_addr[2], dev_data->mac_addr[3],
969-
dev_data->mac_addr[4], dev_data->mac_addr[5]);
1014+
setup_mac_filter(heth);
9701015

9711016
return 0;
9721017
}
@@ -1019,68 +1064,6 @@ static void eth_stm32_mcast_filter(const struct device *dev, const struct ethern
10191064

10201065
#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */
10211066

1022-
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
1023-
static int eth_init_api_v2(const struct device *dev)
1024-
{
1025-
HAL_StatusTypeDef hal_ret = HAL_OK;
1026-
struct eth_stm32_hal_dev_data *dev_data = dev->data;
1027-
ETH_HandleTypeDef *heth = &dev_data->heth;
1028-
1029-
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
1030-
for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
1031-
heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
1032-
heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
1033-
}
1034-
#else
1035-
heth->Init.TxDesc = dma_tx_desc_tab;
1036-
heth->Init.RxDesc = dma_rx_desc_tab;
1037-
#endif
1038-
heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
1039-
1040-
hal_ret = HAL_ETH_Init(heth);
1041-
if (hal_ret == HAL_TIMEOUT) {
1042-
/* HAL Init time out. This could be linked to */
1043-
/* a recoverable error. Log the issue and continue */
1044-
/* driver initialisation */
1045-
LOG_ERR("HAL_ETH_Init Timed out");
1046-
} else if (hal_ret != HAL_OK) {
1047-
LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
1048-
return -EINVAL;
1049-
}
1050-
1051-
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
1052-
/* Enable timestamping of RX packets. We enable all packets to be
1053-
* timestamped to cover both IEEE 1588 and gPTP.
1054-
*/
1055-
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
1056-
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
1057-
#else
1058-
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
1059-
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
1060-
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
1061-
1062-
/* Initialize semaphores */
1063-
k_mutex_init(&dev_data->tx_mutex);
1064-
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
1065-
k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
1066-
1067-
/* Tx config init: */
1068-
memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
1069-
tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
1070-
ETH_TX_PACKETS_FEATURES_CRCPAD;
1071-
tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
1072-
ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
1073-
tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
1074-
1075-
/* prepare tx buffer header */
1076-
for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
1077-
dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
1078-
}
1079-
1080-
return 0;
1081-
}
1082-
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
1083-
10841067
static void set_mac_config(const struct device *dev, struct phy_link_state *state)
10851068
{
10861069
struct eth_stm32_hal_dev_data *dev_data = dev->data;
@@ -1179,7 +1162,6 @@ static void eth_iface_init(struct net_if *iface)
11791162
{
11801163
const struct device *dev = net_if_get_device(iface);
11811164
struct eth_stm32_hal_dev_data *dev_data = dev->data;
1182-
ETH_HandleTypeDef *heth = &dev_data->heth;
11831165
bool is_first_init = false;
11841166

11851167
if (dev_data->iface == NULL) {
@@ -1198,16 +1180,6 @@ static void eth_iface_init(struct net_if *iface)
11981180

11991181
ethernet_init(iface);
12001182

1201-
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
1202-
/* This function requires the Ethernet interface to be
1203-
* properly initialized. In auto-negotiation mode, it reads the speed
1204-
* and duplex settings to configure the driver accordingly.
1205-
*/
1206-
eth_init_api_v2(dev);
1207-
#endif
1208-
1209-
setup_mac_filter(heth);
1210-
12111183
net_if_carrier_off(iface);
12121184

12131185
net_lldp_set_lldpdu(iface);

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