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boards: xtensa: add M5Stack CoreS3 support
Initial support for M5Statck CoreS3 development board. Signed-off-by: Zhang Xingtao <[email protected]> Co-authored-by: Benjamin Cabé <[email protected]> Co-authored-by: TOKITA Hiroshi <[email protected]>
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‎boards/m5stack/m5stack_cores3/Kconfig‎

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# Copyright (c) 2024 Zhang Xingtao <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_M5STACK_CORES3_ESP32S3_PROCPU
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config HEAP_MEM_POOL_ADD_SIZE_BOARD
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int
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default $(UINT16_MAX) if WIFI && BT
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default 51200 if WIFI
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default 40960 if BT
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default 4096
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endif # BOARD_M5STACK_CORES3_ESP32S3_PROCPU
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if BOARD_M5STACK_CORES3_ESP32S3_APPCPU
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config HEAP_MEM_POOL_ADD_SIZE_BOARD
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int
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default 256
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endif # BOARD_M5STACK_CORES3_ESP32S3_APPCPU

‎boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3‎

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# M5Stack CoreS3 board configuration
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# Copyright (c) 2024 Zhang Xingtao <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_M5STACK_CORES3
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select SOC_ESP32S3
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select SOC_ESP32S3_PROCPU if BOARD_M5STACK_CORES3_ESP32S3_PROCPU
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select SOC_ESP32S3_APPCPU if BOARD_M5STACK_CORES3_ESP32S3_APPCPU

‎boards/m5stack/m5stack_cores3/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
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set(OPENOCD OPENOCD-NOTFOUND)
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endif()
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find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
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include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/m5stack/m5stack_cores3/board.yml‎

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board:
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name: m5stack_cores3
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full_name: CoreS3
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vendor: m5stack
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socs:
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- name: esp32s3

‎boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3.webp‎

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‎boards/m5stack/m5stack_cores3/doc/index.rst‎

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.. _m5stack_cores3:
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M5Stack CoreS3
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##############
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Overview
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********
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M5Stack CoreS3 is an ESP32-based development board from M5Stack. It is the third generation of the M5Stack Core series.
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M5Stack CoreS3 features consist of:
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- ESP32-S3 chip (dual-core Xtensa LX7 processor @240MHz, WIFI, OTG and CDC functions)
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- PSRAM 8MB
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- Flash 16MB
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- LCD ISP 2", 320x240 pixel ILI9342C
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- Capacitive multi touch FT6336U
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- Camera 30W pixel GC0308
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- Speaker 1W AW88298
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- Dual Microphones ES7210 Audio decoder
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- RTC BM8563
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- USB-C
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- SD-Card slot
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- Geomagnetic sensor BMM150
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- Proximity sensor LTR-553ALS-WA
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- 6-Axis IMU BMI270
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- PMIC AXP2101
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- Battery 500mAh 3.7 V
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.. figure:: img/m5stack_cores3.webp
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:align: center
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:alt: M5Stack-CoreS3
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:width: 400 px
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M5Stack CoreS3 module
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Start Application Development
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*****************************
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Before powering up your M5Stack CoreS3, please make sure that the board is in good
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condition with no obvious signs of damage.
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System requirements
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===================
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Prerequisites
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-------------
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Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
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below to retrieve those files.
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.. code-block:: console
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west blobs fetch hal_espressif
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.. note::
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It is recommended running the command above after :file:`west update`.
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Building & Flashing
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-------------------
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Build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: m5stack_cores3/esp32s3/procpu
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:goals: build
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The usual ``flash`` target will work with the ``m5stack_cores3/esp32s3/procpu`` board
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configuration. Here is an example for the :zephyr:code-sample:`hello_world`
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application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: m5stack_cores3/esp32s3/procpu
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:goals: flash
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The baud rate of 921600bps is set by default. If experiencing issues when flashing,
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try using different values by using ``--esp-baud-rate <BAUD>`` option during
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``west flash`` (e.g. ``west flash --esp-baud-rate 115200``).
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You can also open the serial monitor using the following command:
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.. code-block:: shell
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west espressif monitor
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After the board has automatically reset and booted, you should see the following
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message in the monitor:
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.. code-block:: console
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*** Booting Zephyr OS build vx.x.x-xxx-gxxxxxxxxxxxx ***
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Hello World! m5stack_cores3/esp32s3/procpu
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Debugging
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---------
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ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0.
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Download and install OpenOCD from `OpenOCD`_.
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ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary.
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Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_.
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.. _`OpenOCD`: https://github.com/openocd-org/openocd
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.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
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Related Documents
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*****************
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- `M5Stack CoreS3 official docs <http://docs.m5stack.com/en/core/CoreS3>`_
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- `M5Stack CoreS3 schematic <https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/K128%20CoreS3/Sch_M5_CoreS3_v1.0.pdf>`_ (PDF)

‎boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi‎

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/*
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* Copyright (c) 2024 Zhang Xingtao <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
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#include <zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h>
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#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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pinmux = <UART0_TX_GPIO43>;
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output-high;
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};
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group2 {
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pinmux = <UART0_RX_GPIO44>;
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bias-pull-up;
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};
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};
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spim2_default: spim2_default {
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group1 {
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pinmux = <SPIM2_MISO_GPIO35>,
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<SPIM2_SCLK_GPIO36>;
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};
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group2 {
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pinmux = <SPIM2_MOSI_GPIO37>;
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output-low;
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};
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};
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i2c0_default: i2c0_default {
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group1 {
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pinmux = <I2C0_SDA_GPIO12>,
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<I2C0_SCL_GPIO11>;
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bias-pull-up;
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drive-open-drain;
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output-high;
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};
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};
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};

‎boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.dts‎

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/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
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/ {
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model = "M5Stack CoreS3 APPCPU";
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compatible = "espressif,esp32s3";
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chosen {
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zephyr,sram = &sram0;
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zephyr,ipc_shm = &shm0;
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zephyr,ipc = &ipm0;
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};
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};
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&ipm0 {
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status = "okay";
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};
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&trng0 {
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status = "okay";
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};
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&flash0 {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Reserve 60kB for the bootloader */
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boot_partition: partition@1000 {
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label = "mcuboot";
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reg = <0x00001000 0x0000F000>;
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read-only;
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};
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/* Reserve 1024kB for the application in slot 0 */
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x00010000 0x00100000>;
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};
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/* Reserve 1024kB for the application in slot 1 */
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slot1_partition: partition@110000 {
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label = "image-1";
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reg = <0x00110000 0x00100000>;
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};
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/* Reserve 256kB for the scratch partition */
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scratch_partition: partition@210000 {
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label = "image-scratch";
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reg = <0x00210000 0x00040000>;
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};
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storage_partition: partition@250000 {
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label = "storage";
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reg = <0x00250000 0x00006000>;
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};
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};
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};

‎boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.yaml‎

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identifier: m5stack_cores3/esp32s3/appcpu
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name: M5Stack CoreS3 APPCPU
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type: mcu
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arch: xtensa
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toolchain:
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- zephyr
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supported:
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- uart
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testing:
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ignore_tags:
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- net
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- bluetooth
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- flash
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- cpp
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- posix
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- watchdog
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- logging
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- kernel
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- pm
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- gpio
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- crypto
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- eeprom
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- heap
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- cmsis_rtos
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- jwt
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- zdsp
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vendor: m5stack

‎boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig‎

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_MAIN_STACK_SIZE=2048
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CONFIG_CLOCK_CONTROL=y

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