arch: arm: define Cortex-M23, Cortex-M33 CPUs

This commit defines the Kconfig options for
ARM Cortex-M23 and Cortex-M33 CPUs. It also
udpates the generic memory map for M23 and M33
implementations.

Signed-off-by: Ioannis Glaropoulos <[email protected]>

Author: ioannisg

arch/arm/core/cortex_m/Kconfig

@@ -135,6 +135,20 @@ config CPU_CORTEX_M4
 	help
 	  This option signifies the use of a Cortex-M4 CPU
 
+config CPU_CORTEX_M23
+	bool
+	# Omit prompt to signify "hidden" option
+	select ARMV6_M_ARMV8_M_BASELINE
+	help
+	  This option signifies the use of a Cortex-M23 CPU
+
+config CPU_CORTEX_M33
+	bool
+	# Omit prompt to signify "hidden" option
+	select ARMV7_M_ARMV8_M_MAINLINE
+	help
+	  This option signifies the use of a Cortex-M33 CPU
+
 config CPU_CORTEX_M7
 	bool
 	# Omit prompt to signify "hidden" option
@@ -197,7 +211,7 @@ config XIP
 	default y
 endmenu
 
-menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
+menu "ARM Cortex-M0/M0+/M3/M4/M7/M23/M33 options"
     depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE
 
 config GEN_ISR_TABLES

include/arch/arm/cortex_m/cmsis.h

@@ -115,6 +115,10 @@ typedef enum {
 #define __CM4_REV        0
 #elif defined(CONFIG_CPU_CORTEX_M7)
 #define __CM7_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M23)
+#define __CM23_REV       0
+#elif defined(CONFIG_CPU_CORTEX_M33)
+#define __CM33_REV       0
 #else
 #error "Unknown Cortex-M device"
 #endif
@@ -138,6 +142,10 @@ typedef enum {
 #include <core_cm4.h>
 #elif defined(CONFIG_CPU_CORTEX_M7)
 #include <core_cm7.h>
+#elif defined(CONFIG_CPU_CORTEX_M23)
+#include <core_cm23.h>
+#elif defined(CONFIG_CPU_CORTEX_M33)
+#include <core_cm33.h>
 #else
 #error "Unknown Cortex-M device"
 #endif

include/arch/arm/cortex_m/memory_map.h

@@ -64,6 +64,11 @@
 #define _PPB_INT_RSVD_1           0xE0003000
 #define _PPB_INT_SCS              0xE000E000
 #define _PPB_INT_RSVD_2           0xE000F000
+#elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33)
+#define _PPB_INT_RSVD_0           0xE0000000
+#define _PPB_INT_SCS              0xE000E000
+#define _PPB_INT_SCB              0xE000ED00
+#define _PPB_INT_RSVD_1           0xE002E000
 #else
 #error Unknown CPU
 #endif
@@ -72,13 +77,19 @@
 /* 0xe0000000 -> 0xe00fffff: private peripheral bus */
 /* 0xe0040000 -> 0xe00fffff: external [768K] */
 #define _PPB_EXT_BASE_ADDR        0xE0040000
-#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS)
+#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) \
+	|| defined(CONFIG_CPU_CORTEX_M23)
 #elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
 #define _PPB_EXT_TPIU             0xE0040000
 #define _PPB_EXT_ETM              0xE0041000
 #define _PPB_EXT_PPB              0xE0042000
 #define _PPB_EXT_ROM_TABLE        0xE00FF000
 #define _PPB_EXT_END_ADDR         0xE00FFFFF
+#elif defined(CONFIG_CPU_CORTEX_M33)
+#undef  _PPB_EXT_BASE_ADDR
+#define _PPB_EXT_BASE_ADDR        0xE0044000
+#define _PPB_EXT_ROM_TABLE        0xE00FF000
+#define _PPB_EXT_END_ADDR         0xE00FFFFF
 #elif defined(CONFIG_CPU_CORTEX_M7)
 #define _PPB_EXT_BASE_ADDR        0xE0040000
 #define _PPB_EXT_RSVD_TPIU        0xE0040000