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Chenhongrenkartben
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soc: it8xxx2: move gpio-q and elpm initial to early preparation hook
Relocate the initialization of the gpio-q group and the elpm module to early SoC preparation hook. The elpm xlpout signal is connected to the main power rail and is driven by firmware after bootup. Initializing these modules early ensures that the power rail remains stable and does not drop. Signed-off-by: Ren Chen <[email protected]>
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soc/ite/ec/it8xxx2/soc.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -417,6 +417,22 @@ void soc_prep_hook(void)
417417
IT8XXX2_GPIO_GPCRB3 = GPCR_PORT_PIN_MODE_INPUT;
418418
IT8XXX2_GPIO_GPCRB4 = GPCR_PORT_PIN_MODE_INPUT;
419419
#endif
420+
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#ifdef CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
422+
#if DT_HAS_COMPAT_STATUS_OKAY(ite_it8xxx2_power_elpm)
423+
/* drive xlpout high and then enable elpm firmware control mode if
424+
* the elpm node is marked as okay.
425+
*/
426+
sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3) | FIRMWARE_CTRL_OUTPUT_H,
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ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3);
428+
sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3) | FIRMWARE_CTRL_EN,
429+
ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3);
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(ite_it8xxx2_power_elpm) */
431+
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/* set gpio-q group as gpio by default */
433+
sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF5_INPUT_EN) & ~XLPIN_INPUT_ENABLE_MASK,
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ELPM_BASE_ADDR + ELPMF5_INPUT_EN);
435+
#endif /* CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED */
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}
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422438
static int ite_it8xxx2_init(void)
@@ -537,22 +553,6 @@ static int ite_it8xxx2_init(void)
537553
}
538554
#endif /* (SOC_USBPD_ITE_PHY_PORT_COUNT > 0) */
539555

540-
#ifdef CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
541-
#if DT_HAS_COMPAT_STATUS_OKAY(ite_it8xxx2_power_elpm)
542-
/* drive xlpout high and then enable elpm firmware control mode if
543-
* the elpm node is marked as okay.
544-
*/
545-
sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3) | FIRMWARE_CTRL_OUTPUT_H,
546-
ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3);
547-
sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3) | FIRMWARE_CTRL_EN,
548-
ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3);
549-
#endif /* DT_HAS_COMPAT_STATUS_OKAY(ite_it8xxx2_power_elpm) */
550-
551-
/* set gpio-q group as gpio by default */
552-
sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF5_INPUT_EN) & ~XLPIN_INPUT_ENABLE_MASK,
553-
ELPM_BASE_ADDR + ELPMF5_INPUT_EN);
554-
#endif /* CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED */
555-
556556
return 0;
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}
558558
SYS_INIT(ite_it8xxx2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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