|
56 | 56 | }; |
57 | 57 |
|
58 | 58 | &cpu0 { |
59 | | - clock-frequency = <4000000>; |
| 59 | + clock-frequency = <48000000>; |
| 60 | +}; |
| 61 | + |
| 62 | +&clock { |
| 63 | + compatible = "microchip,pic32cm-jh-clock"; |
| 64 | + |
| 65 | + /* If cpu sourced from osc48m, use 3 for CPU frequency above 24Mhz */ |
| 66 | + flash-wait-states = <2>; |
| 67 | + |
| 68 | + xosc: xosc { |
| 69 | + compatible = "microchip,pic32cm-jh-xosc"; |
| 70 | + xosc-frequency = <32000000>; |
| 71 | + xosc-en = <1>; |
| 72 | + xosc-xtal-en = <1>; |
| 73 | + xosc-run-in-standby-en = <1>; |
| 74 | + }; |
| 75 | + |
| 76 | + fdpll: fdpll { |
| 77 | + compatible = "microchip,pic32cm-jh-fdpll"; |
| 78 | + fdpll-xosc-clock-divider = <15>; |
| 79 | + fdpll-divider-ratio-frac = <0>; |
| 80 | + fdpll-divider-ratio-int = <95>; |
| 81 | + fdpll-output-prescalar = "div2"; |
| 82 | + fdpll-src = "xosc"; |
| 83 | + fdpll-run-in-standby-en = <1>; |
| 84 | + fdpll-en = <1>; |
| 85 | + }; |
| 86 | + |
| 87 | + xosc32k: xosc32k { |
| 88 | + compatible = "microchip,pic32cm-jh-xosc32k"; |
| 89 | + xosc32k-32khz-en = <1>; |
| 90 | + xosc32k-xtal-en = <1>; |
| 91 | + xosc32k-startup-time = "122-us"; |
| 92 | + xosc32k-run-in-standby-en = <1>; |
| 93 | + xosc32k-en = <1>; |
| 94 | + }; |
| 95 | + |
| 96 | + osc32k: osc32k { |
| 97 | + compatible = "microchip,pic32cm-jh-osc32k"; |
| 98 | + osc32k-32khz-en = <1>; |
| 99 | + osc32k-startup-time = "183-us"; |
| 100 | + osc32k-run-in-standby-en = <1>; |
| 101 | + osc32k-en = <0>; |
| 102 | + }; |
| 103 | + |
| 104 | + gclkgen: gclkgen { |
| 105 | + compatible = "microchip,pic32cm-jh-gclkgen"; |
| 106 | + |
| 107 | + gclkgen0 { |
| 108 | + subsystem = <CLOCK_MCHP_GCLKGEN_ID_GEN0>; |
| 109 | + gclkgen-div-factor = <1>; |
| 110 | + gclkgen-run-in-standby-en = <1>; |
| 111 | + gclkgen-src = "fdpll"; |
| 112 | + gclkgen-en = <1>; |
| 113 | + }; |
| 114 | + }; |
| 115 | + |
| 116 | + gclkperiph: gclkperiph { |
| 117 | + compatible = "microchip,pic32cm-jh-gclkperiph"; |
| 118 | + #clock-cells = <1>; |
| 119 | + |
| 120 | + sercom2 { |
| 121 | + subsystem = <CLOCK_MCHP_GCLKPERIPH_ID_SERCOM4_CORE>; |
| 122 | + gclkperiph-src = "gclk0"; |
| 123 | + gclkperiph-en = <1>; |
| 124 | + }; |
| 125 | + }; |
60 | 126 | }; |
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