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iandmorrisfabiobaltieri
iandmorris
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soc: renesas: ra: configure option settings memory
An area of flash memory on the RA4M1 MCU is used to store information used to configure the device following a reset. This patch instructs the linker to reserve this memory area and provides kconfig options that are used to populate it (at build time) with the desired device configuration. Signed-off-by: Ian Morris <[email protected]>
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‎soc/renesas/ra/ra4m1/CMakeLists.txt‎

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zephyr_include_directories(.)
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zephyr_library_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY
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soc.c
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)
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zephyr_linker_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY
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ROM_START
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${CMAKE_CURRENT_SOURCE_DIR}/opt_set_mem.ld
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)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra4m1/Kconfig‎

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@@ -9,3 +9,7 @@ config SOC_SERIES_RA4M1
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select DYNAMIC_INTERRUPTS
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select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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select XIP
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config SOC_OPTION_SETTING_MEMORY
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bool "Option Setting Memory"
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default y

‎soc/renesas/ra/ra4m1/opt_set_mem.ld‎

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/*
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* Copyright (c) 2024 Ian Morris
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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. = 0x400;
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FILL(0xFF)
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KEEP(*(.opt_set_mem*))
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. = 0x500;

‎soc/renesas/ra/ra4m1/soc.c‎

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/*
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* Copyright (c) 2024 Ian Morris
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#define HOCO_FREQ DT_PROP(DT_PATH(clocks, hoco), clock_frequency)
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#if HOCO_FREQ == MHZ(24)
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#define OFS1_HOCO_FREQ 0
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#elif HOCO_FREQ == MHZ(32)
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#define OFS1_HOCO_FREQ 2
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#elif HOCO_FREQ == MHZ(48)
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#define OFS1_HOCO_FREQ 4
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#elif HOCO_FREQ == MHZ(64)
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#define OFS1_HOCO_FREQ 5
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#else
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#error "Unsupported HOCO frequency"
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#endif
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struct ofs0_reg {
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uint32_t RSVD1: 1;
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uint32_t IWDTSTRT: 1;
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uint32_t IWDTTOPS: 2;
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uint32_t IWDTCKS: 4;
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uint32_t IWDTRPES: 2;
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uint32_t IWDTRPSS: 2;
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uint32_t IWDTRSTIRQS: 1;
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uint32_t RSVD2: 1;
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uint32_t IWDTSTPCTL: 1;
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uint32_t RSVD3: 2;
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uint32_t WDTSTRT: 1;
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uint32_t WDTTOPS: 2;
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uint32_t WDTCKS: 4;
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uint32_t WDTRPES: 2;
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uint32_t WDTRPSS: 2;
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uint32_t WDTRSTIRQS: 1;
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uint32_t RSVD4: 1;
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uint32_t WDTSTPCTL: 1;
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uint32_t RSVD5: 1;
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};
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struct ofs1_reg {
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uint32_t RSVD1: 2;
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uint32_t LVDAS: 1;
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uint32_t VDSEL1: 3;
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uint32_t RSVD2: 2;
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uint32_t HOCOEN: 1;
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uint32_t RSVD3: 3;
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uint32_t HOCOFRQ1: 3;
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uint32_t RSVD4: 17;
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};
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struct mpu_regs {
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uint32_t SECMPUPCSO;
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uint32_t SECMPUPCEO;
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uint32_t SECMPUPCS1;
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uint32_t SECMPUPCE1;
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uint32_t SECMPUS0;
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uint32_t SECMPUE0;
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uint32_t SECMPUS1;
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uint32_t SECMPUE1;
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uint32_t SECMPUS2;
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uint32_t SECMPUE2;
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uint32_t SECMPUS3;
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uint32_t SECMPUE3;
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uint32_t SECMPUAC;
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};
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struct opt_set_mem {
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struct ofs0_reg ofs0;
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struct ofs1_reg ofs1;
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struct mpu_regs mpu;
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};
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#ifdef CONFIG_SOC_OPTION_SETTING_MEMORY
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const struct opt_set_mem ops __attribute__((section(".opt_set_mem"))) = {
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.ofs0 = {
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/*
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* Initial settings for watchdog timers. Set all fields to 1,
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* disabling watchdog functionality as config options have not
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* yet been implemented.
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*/
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.RSVD1 = 0x1,
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.IWDTSTRT = 0x1, /* Disable independent watchdog timer */
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.IWDTTOPS = 0x3,
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.IWDTCKS = 0xf,
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.IWDTRPES = 0x3,
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.IWDTRPSS = 0x3,
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.IWDTRSTIRQS = 0x1,
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.RSVD2 = 0x1,
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.IWDTSTPCTL = 0x1,
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.RSVD3 = 0x3,
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.WDTSTRT = 0x1, /* Stop watchdog timer following reset */
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.WDTTOPS = 0x3,
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.WDTCKS = 0xf,
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.WDTRPES = 0x3,
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.WDTRPSS = 0x3,
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.WDTRSTIRQS = 0x1,
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.RSVD4 = 0x1,
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.WDTSTPCTL = 0x1,
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.RSVD5 = 0x1,
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},
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.ofs1 = {
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.RSVD1 = 0x3,
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.LVDAS = 0x1, /* Disable voltage monitor 0 following reset */
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.VDSEL1 = 0x3,
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.RSVD2 = 0x3,
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.HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, hoco), okay),
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.RSVD3 = 0x7,
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.HOCOFRQ1 = OFS1_HOCO_FREQ,
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.RSVD4 = 0x1ffff,
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},
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.mpu = {
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/*
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* Initial settings for MPU. Set all areas to maximum values
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* essentially disabling MPU functionality as config options
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* have not yet been implemented.
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*/
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.SECMPUPCSO = 0x00fffffc,
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.SECMPUPCEO = 0x00ffffff,
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.SECMPUPCS1 = 0x00fffffc,
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.SECMPUPCE1 = 0x00ffffff,
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.SECMPUS0 = 0x00fffffc,
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.SECMPUE0 = 0x00ffffff,
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.SECMPUS1 = 0x200ffffc,
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.SECMPUE1 = 0x200fffff,
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.SECMPUS2 = 0x407ffffc,
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.SECMPUE2 = 0x407fffff,
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.SECMPUS3 = 0x40dffffc,
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.SECMPUE3 = 0x40dfffff,
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.SECMPUAC = 0xffffffff,
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}
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};
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#endif

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