dts: arm: st: add basic dts support for adc.

Adding ADC1 dts support to these series of soc, not covering ADC2.

Signed-off-by: Song Qiang <[email protected]>

Author: cybertale

dts/arm/st/f0/stm32f0.dtsi

@@ -287,6 +287,15 @@
 				#pwm-cells = <2>;
 			};
 		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 };
 

dts/arm/st/f1/stm32f1.dtsi

@@ -220,6 +220,15 @@
 				#pwm-cells = <2>;
 			};
 		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 };
 

dts/arm/st/f2/stm32f2.dtsi

@@ -206,6 +206,15 @@
 			status = "disabled";
 			label = "OTGFS";
 		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 
 	otgfs_phy: otgfs_phy {

dts/arm/st/f3/stm32f3.dtsi

@@ -286,6 +286,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@50000000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 
 	usb_fs_phy: usbphy {

dts/arm/st/f4/stm32f4.dtsi

@@ -359,6 +359,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 
 	otgfs_phy: otgfs_phy {

dts/arm/st/f7/stm32f7.dtsi

@@ -575,6 +575,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 
 	otghs_fs_phy: otghs_fs_phy {

dts/arm/st/l0/stm32l0.dtsi

@@ -155,6 +155,15 @@
 			status = "disabled";
 			label = "SPI_1";
 		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 };
 

dts/arm/st/l4/stm32l4.dtsi

@@ -283,6 +283,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@50040000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; //RCC_APB1ENR1_CAN1EN
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_0";
+		};
 	};
 };
 

dts/bindings/iio/adc/st,stm32-adc.yaml

@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2018, Song Qiang <[email protected]>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: ST Microcontroller STM32 Family ADC
+version: 0.1
+
+description: >
+    This is a representation of the STM32 ADC node
+
+inherits:
+    !include adc.yaml
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "st,stm32-adc"
+
+    reg:
+      type: array
+      description: mmio register space
+      generation: define
+      category: required
+
+    clocks:
+      type: array
+      category: required
+      description: Clock gate control information
+      generation: define
+
+    interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+...