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49 | 49 | (((mask) & STM32_DT_CLKSEL_MASK_MASK) << STM32_DT_CLKSEL_MASK_SHIFT) | \ |
50 | 50 | (((val) & STM32_DT_CLKSEL_VAL_MASK) << STM32_DT_CLKSEL_VAL_SHIFT)) |
51 | 51 |
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52 | | -/* STM32_CLOCK_* macros, defined for convenience */ |
53 | | -#define STM32_CLOCK_REG_MASK STM32_DT_CLKSEL_REG_MASK |
54 | | -#define STM32_CLOCK_REG_SHIFT STM32_DT_CLKSEL_REG_SHIFT |
55 | | -#define STM32_CLOCK_SHIFT_MASK STM32_DT_CLKSEL_SHIFT_MASK |
56 | | -#define STM32_CLOCK_SHIFT_SHIFT STM32_DT_CLKSEL_SHIFT_SHIFT |
57 | | -#define STM32_CLOCK_MASK_MASK STM32_DT_CLKSEL_MASK_MASK |
58 | | -#define STM32_CLOCK_MASK_SHIFT STM32_DT_CLKSEL_MASK_SHIFT |
59 | | -#define STM32_CLOCK_VAL_MASK STM32_DT_CLKSEL_VAL_MASK |
60 | | -#define STM32_CLOCK_VAL_SHIFT STM32_DT_CLKSEL_VAL_SHIFT |
61 | | -#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ |
62 | | - STM32_DT_CLOCK_SELECT((val), (mask), (shift), (reg)) |
63 | | - |
64 | | -/* STM32_MCO_CFGR_* macros, defined for convenience */ |
65 | | -#define STM32_MCO_CFGR_REG_MASK STM32_DT_CLKSEL_REG_MASK |
66 | | -#define STM32_MCO_CFGR_REG_SHIFT STM32_DT_CLKSEL_REG_SHIFT |
67 | | -#define STM32_MCO_CFGR_SHIFT_MASK STM32_DT_CLKSEL_SHIFT_MASK |
68 | | -#define STM32_MCO_CFGR_SHIFT_SHIFT STM32_DT_CLKSEL_SHIFT_SHIFT |
69 | | -#define STM32_MCO_CFGR_MASK_MASK STM32_DT_CLKSEL_MASK_MASK |
70 | | -#define STM32_MCO_CFGR_MASK_SHIFT STM32_DT_CLKSEL_MASK_SHIFT |
71 | | -#define STM32_MCO_CFGR_VAL_MASK STM32_DT_CLKSEL_VAL_MASK |
72 | | -#define STM32_MCO_CFGR_VAL_SHIFT STM32_DT_CLKSEL_VAL_SHIFT |
73 | | -#define STM32_MCO_CFGR(val, mask, shift, reg) \ |
74 | | - STM32_DT_CLOCK_SELECT((val), (mask), (shift), (reg)) |
75 | | - |
76 | 52 | /** |
77 | 53 | * Pack RCC clock register offset and bit in two 32-bit values |
78 | 54 | * as expected for the Device Tree `clocks` property on STM32. |
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